High-precision sigma-delta ADC based on fixed code offset and mismatch error shaping technology

Abstract

The invention discloses a high-precision sigma-delta ADC (Analog to Digital Converter) based on a fixed code offset and mismatch error shaping technology. A subtractor is adopted to generate a processing signal of a current period according to an analog signal of the current period and a feedback analog signal of a previous period; filtering the processed signal by using a filter; quantizing the filtered signal into a digital code by adopting an analog-to-digital converter; a fixed code offset logic circuit is adopted to generate a converted thermometer code of the current period according to the high four-bit code of the digital code of the current period, the pointer code of the previous period and a preset fixed code; a mismatch error shaping logic circuit is adopted to generate two low-order digital codes according to the digital code of the current period, and the two low-order digital codes are alternately input into two RDAC units of a digital-to-analog conversion circuit in a continuous period; and a digital-to-analog conversion circuit is adopted to generate a feedback analog signal of the current period according to the converted thermometer code and the low-order digital code of the current period. The problem of dynamic and static mismatch can be solved.

Description

Technical Field

[0001] The invention belongs to the field of circuit technology, and in particular relates to a high-precision sigma-delta ADC based on fixed code offset and mismatch error shaping technology. Background Art

[0002] Continuous-time CT sigma-delta ADCs are widely used as key components in the interface between analog and digital systems due to their high precision, low power consumption and easy driving, and play an important role in applications such as consumer electronics and industrial electronics. Moreover, compared with discrete-time DT sigma-delta ADCs, they do not require additional anti-aliasing filters, and the resistive input impedance is also conducive to the driving of the front-end circuit.

[0003] However, in realizing multi-bit quantized CT sigma-delta ADC with high dynamic range, the static mismatch caused by the mismatch between feedback DACs and the dynamic mismatch caused by the mismatch of rise and fall time of DAC pulse function have a great impact on its linearity. Although in the field of discrete DT sigma-delta ADC, many dynamic component matching technologies can shape the static mismatch, these technologies cannot handle the dynamic mismatch of DAC in continuous time and may even aggravate the distortion. Summary of the invention

[0004] In order to solve the above problems existing in the prior art, the present invention provides a high-precision sigma-delta ADC based on fixed code offset and mismatch error shaping technology.

[0005] The technical problem to be solved by the present invention is achieved through the following technical solutions:

[0006] The present invention provides a high-precision sigma-delta ADC based on fixed code offset and mismatch error shaping technology, comprising:

[0007] A subtractor, used for performing a subtraction operation on an input analog signal of a current cycle and a feedback analog signal of a cycle before the current cycle to obtain a processed signal of the current cycle;

[0008] A feedforward loop filter, used for shaping the quantization noise in the processed signal of the current cycle to obtain a filtered signal;

[0009] A successive approximation analog-to-digital converter, used for quantizing the filtered signal to obtain a digital code of the current cycle;

[0010] A fixed code offset logic circuit, used for generating a converted thermometer code of the current cycle according to the upper four bits of the digital code of the current cycle, the pointer code of the previous cycle and a preset fixed code;

[0011] a mismatch error shaping logic circuit, configured to generate the first low-order digital code and the second low-order digital code based on the digital code of the current cycle, and alternately input the first low-order digital code and the second low-order digital code into the first RDAC unit and the second RDAC unit in the resistance-type digital-to-analog conversion circuit according to the control of an external control signal;

[0012] The resistance-type digital-to-analog conversion circuit is used to generate a feedback analog signal of the current cycle according to the converted thermometer code of the current cycle, the first low-bit digital code and the second low-bit digital code.

[0013] Compared with the prior art, the present invention has the following beneficial effects:

[0014] In the actual continuous-time ADC circuit, the DAC feedback waveform has unequal rising and falling delays corresponding to the digital code from 0 to 1 and from 1 to 0, and the feedback analog mismatch generated by the DAC will be introduced into the loop filter; in the traditional thermometer code and dynamic element matching technology mode, the dynamic mismatch will be related to the signal, and harmonics will be introduced, thereby affecting the linearity of the ADC. In this regard, the present invention generates the converted thermometer code of the current cycle according to the high four-bit code of the digital code of the current cycle, the pointer code of the previous cycle and the preset fixed code, so that the pointer of each cycle moves a fixed number of bits, so that the digital code switched from 0 to 1 is a fixed number, so that the mismatch amount injected into the loop is independent of the signal, thereby achieving the effect of eliminating the correlation between dynamic mismatch and signal. To address the static mismatch problem, the present invention generates the first low-order digital code and the second low-order digital code based on the digital code of the current cycle, and according to the control of an external control signal, alternately inputs the first low-order digital code and the second low-order digital code into the first RDAC unit and the second RDAC unit in the resistive digital-to-analog conversion circuit, thereby injecting the mismatch error of the previous cycle to cancel the error, thereby achieving a mismatch error shaping effect.

[0015] The present invention will be further described in detail below with reference to the accompanying drawings and specific implementation methods. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a flow chart of a high-precision sigma-delta ADC based on fixed code offset and mismatch error shaping technology provided by an embodiment of the present invention;

[0017] Figure 2is a schematic diagram of an exemplary connection relationship between the resistance-type digital-to-analog conversion circuit provided in an embodiment of the present invention and FT Logic and MES Logic;

[0018] Figure 3 is a circuit structure diagram of FT Logic provided by an embodiment of the present invention;

[0019] Figure 4 is a schematic diagram of an exemplary DAC feedback waveform provided by an embodiment of the present invention;

[0020] Figure 5 is a schematic diagram of a circuit structure of an exemplary 4-bit Logarithmic Shifter provided in an embodiment of the present invention;

[0021] Figure 6 is a circuit structure diagram of MES Logic provided by an embodiment of the present invention;

[0022] Figure 7 is a schematic diagram of the structure of each RDAC unit provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0023] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0024] Figure 1 FIG. 1 is a flow chart of a high-precision sigma-delta ADC based on a fixed code offset and mismatch error shaping technology provided by an embodiment of the present invention. Figure 1As shown, the sigma-delta ADC includes: a subtractor, a feedforward loop filter (Cascade of integrators with feedforward loop filter, CIFF LP Filter), a successive approximation register analog-to-digital converter (SAR ADC), a fixed-transition logic (FT Logic), a mismatch error shaping logic (MES Logic) and a resistive digital-to-analog conversion circuit (RDAC). The subtractor is used to subtract the input analog signal VIN of the current cycle from the feedback analog signal of the previous cycle of the current cycle to obtain the processing signal of the current cycle. The feedforward loop filter is used to shape the quantization noise in the processing signal of the current cycle to obtain the filtered signal. The successive approximation analog-to-digital converter is used to quantize the filtered signal to obtain the digital code DOUT of the current cycle. The fixed code offset logic circuit is used to generate the converted thermometer code of the current cycle according to the high four-bit code of the digital code of the current cycle, the pointer code of the previous cycle and the preset fixed code. The mismatch error shaping logic circuit is used to generate the first low-bit digital code and the second low-bit digital code based on the digital code of the current cycle, and according to the control of the external control signal, the first low-bit digital code and the second low-bit digital code are alternately input into the first RDAC unit and the second RDAC unit in the resistance-type digital-to-analog conversion circuit. The resistance-type digital-to-analog conversion circuit is used to generate the feedback analog signal of the current cycle according to the converted thermometer code of the current cycle, the first low-bit digital code and the second low-bit digital code.

[0025] Exemplarily, the resistor digital-to-analog converter circuit may be a non-return-to-zero resistor digital-to-analog converter (NRZ RDAC). The SAR ADC uses an 8-bit SAR ADC. Compared with single-bit quantization, high-bit quantization can achieve a larger dynamic range of the ADC, higher loop linearity and lower op amp slew rate requirements.

[0026] In the present invention, the resistance-type digital-to-analog conversion circuit includes: a first RDAC unit, a second RDAC unit, a third RDAC unit and a second adder. Exemplarily, the first RDAC unit, the second RDAC unit and the third RDAC unit are all 4-bit RDACs. Figure 2FIG. 1 is a schematic diagram showing an exemplary connection relationship between a resistor-type digital-to-analog conversion circuit and FT Logic and MES Logic. Figure 1 and Figure 2 As shown, the outputs of the three 4-bit RDACs are connected to the second adder ( Figure 2 The output of the second adder is connected to the three input terminals of the subtractor ( Figure 1 The output of the subtractor is connected to the input of the CIFF LP Filter; the output of the CIFFLP Filter is connected to the input of the SAR ADC; the output of the SAR ADC is used as the output of the high-precision sigma-delta ADC, and the output of the SAR ADC is also connected to the input of the FT Logic and the MES Logic, so as to input the high four-bit code 4Bit MSB of the digital code 8Bit DATA of the current cycle to the FT Logic, and input the low four-bit code 4Bit LSB of the digital code 8Bit DATA of the current cycle to the MES Logic. The output of the FT Logic is connected to the input of the 4Bit RDAC; the two outputs of the MES Logic are connected to the input of the 4Bit RDAC1 and the 4Bit RDAC2 respectively.

[0027] In the present invention, FT Logic is specifically used to: save the pointer code of the previous cycle, superimpose the pointer code of the previous cycle with the preset fixed code to obtain the pointer code of the current cycle; convert the high four bits of the digital code of the current cycle into the thermometer code of the current cycle; perform logical shift processing on the thermometer code of the current cycle according to the pointer code of the current cycle to obtain the converted thermometer code of the current cycle. Exemplarily, the pointer code and the preset fixed code are both 4-bit binary codes, and the thermometer code is a 15-bit binary code.

[0028] For example, Figure 3 This is a circuit diagram of FT Logic. Figure 3 As shown, FT Logic includes: a pointer addition unit Point ADD, a first D flip-flop DFF, a 4-bit logical shifter (4-bit Loganithmic Shifter) and a binary code thermometer code conversion unit B_T. Figure 3 As shown, the Q end of DFF ( Figure 3 (not shown) is connected to an input terminal of Point ADD, and the D terminal of DFF ( Figure 3 ) is connected to the output terminal of Point ADD, and the clk terminal ( Figure 3 ) is connected to the external first clock signal ( Figure 3 The DFF is used to save the pointer code POINT<3:0> of the previous cycle output by Point ADD to the current cycle and then output it. The other input end of Point ADD is used to access the preset fixed code Fixtransition. The end connected to the D end of DFF is also connected to an input end of the 4-Bit Loganithmic Shifter. DFF is used to superimpose the POINT<3:0> of the previous cycle with the Fix transition to obtain the pointer code POINT<3:0> of the current cycle. The input end of B_T is connected to the output end of the SAR ADC to receive the 4-Bit MSB (i.e. Figure 3 The 4-bit Logarithmic Shifter is used to convert the 4-bit MSB of the current cycle into the thermometer code K<14:0> of the current cycle and output it to the 4-bit Logarithmic Shifter. The other input end of the 4-bit Logarithmic Shifter is connected to the output end of B_T, and the output end is connected to the input end of the 4-bit RDAC in the resistance-type digital-to-analog conversion circuit. The 4-bit Logarithmic Shifter is used to perform a logical shift process on the K<14:0> of the current cycle according to the POINT<3:0> of the current cycle, and obtain the converted thermometer code OUT<14:0> of the current cycle to output it to the 4-bit RDAC.

[0029] like Figure 4 As shown, in the actual continuous-time ADC circuit, the DAC feedback waveform has unequal rising and falling delays corresponding to the digital code from 0 to 1 and from 1 to 0, and the feedback analog mismatch generated by the DAC will be introduced into the loop filter. In the traditional thermometer code and dynamic element matching technology mode, the dynamic mismatch will be related to the signal, which will introduce harmonics and affect the linearity of the ADC. The FT Logic proposed in the present invention moves a fixed number of bits in each cycle pointer. For example, the digital code of the previous cycle is 00_0000_0111_0000, the pointer of this cycle is the 9th bit, and the temperature code of this cycle is 00_0000_0000_1111. Then, after passing through the FT Logic, the digital code output is 00_0001_1110_0000. It can be seen that the digital code switching from 0 to 1 is a fixed number, so that the mismatch amount injected into the loop is independent of the signal, thereby achieving the effect of eliminating the correlation between dynamic mismatch and signal.

[0030] In the present invention, the truth table of B_T is shown in the following Table 1. Referring to Table 1, it can be seen that when the high 4-bit code MSB<3:0> of the digital code of the current cycle is "0000", B_T converts "0000" into a 15-bit thermometer code K<14:0> "000000000000000", when MSB<3:0> is "0001", B_T converts "0001" into a 15-bit thermometer code "0000000000000 01", and when MSB<3:0> is "0010", B_T converts "0010" into a 15-bit thermometer code "0000000000000 11", and so on.

[0031] Table 1

[0032] MSB<3:0 K<14:0> 0000 0000000000000 00 0001 0000000000000 01 0010 0000000000000 11 … … 1110 0111111111111 11 1111 1111111111111 11

[0033] In some embodiments, when the pointer code is a 4-bit binary code and the thermometer code is an m-bit binary code, the 4-Bit Logarithmic Shifter includes 4 groups of logic units. The input of the first group of logic units is the thermometer code of the current cycle, the input of the second group of logic units is the output of the first group of logic units, the input of the third group of logic units is the output of the second group of logic units, the input of the fourth group of logic units is the output of the third group of logic units, and the output of the fourth group of logic units is the converted thermometer code of the current cycle. Each group of logic units includes m two-to-one data selectors, wherein the difference between the two input codes of each two-to-one data selector in the first group of logic units in the m-bit input code of the first group of logic units is 2 3 The difference between the two input codes of each binary data selector in the second group of logic units in the m-bit input code of the second group of logic units is 22, and the difference between the two input codes of each binary data selector in the third group of logic units in the m-bit input code of the third group of logic units is 2 1 , the difference between the two input codes of each two-to-one data selector in the fourth group of logic units in the m-bit input code of the fourth group of logic units is 2 0 The highest bit of the 4-bit binary code is used as the control signal of each binary data selector in the first group of logic units, the second highest bit of the 4-bit binary code is used as the control signal of each binary data selector in the second group of logic units, the second lowest bit of the 4-bit binary code is used as the control signal of each binary data selector in the third group of logic units, and the lowest bit of the 4-bit binary code is used as the control signal of each binary data selector in the fourth group of logic units. For example, Figure 5 The following is a schematic diagram of the circuit structure of a 4-bit Logarithmic Shifter. Figure 5As shown in FIG. 1 , when the pointer code is a 4-bit binary code POINT<3:0> and the thermometer code is an m-bit binary code K<14:0>, the 4-bit Logarithmic Shifter includes 4 groups of logic units, and each group of logic units includes 15 two-to-one data selectors. <3> The control signal for each binary data selector in the first group of logic units, POINT <2> The control signal for each binary data selector in the second group of logic units, POINT <1> The control signal for each binary data selector in the third group of logic units, POINT <0> The control signal of each binary data selector in the fourth group of logic units; the input of the first group of logic units is K<14:0>, and the output is K1<14:0>; the input of the second group of logic units is K1<14:0>, and the output is K2<14:0>; the input of the third group of logic units is K2<14:0>, and the output is K3<14:0>; the input of the fourth group of logic units is K3<14:0>, and the output is OUT<14:0>. The two inputs of the first binary data selector in the first group of logic units are K <0> and K <8> , the two inputs of the second two-to-one data selector are K <1> and K <9> ,…, the two inputs of the 15th two-to-one data selector are K <14> and K <7> ; The two inputs of the first two-to-one data selector in the second group of logic units are K1 <0> and K1 <4> , the two inputs of the second two-to-one data selector are K1 <1> and K1 <5> ,…, the two inputs of the 15th two-to-one data selector are K1 <14> and K1 <3> , and the same goes for the rest.

[0034] In the present invention, MES Logic is specifically used for: saving the lower four bits of the superimposed code of the previous cycle as the first low-order digital code LSB2, superimposing the digital code of the current cycle with the first low-order digital code LSB2 to obtain the superimposed code of the current cycle, and using the lower four bits of the superimposed code of the current cycle as the second low-order digital code LSB1; under the control of the external control signal CLK, in each cycle, the output relationship between the first low-order digital code LSB2 and the second low-order digital code LSB1 and the first RDAC unit and the second RDAC unit is exchanged once, so that the first low-order digital code LSB2 and the second low-order digital code LSB1 are alternately output to the first RDAC unit and the second RDAC unit in consecutive different cycles.

[0035] For example, Figure 6 This is a circuit diagram of MES Logic. Figure 6 As shown, MES Logic includes: a second D flip-flop DFF, a first adder ( Figure 6 The “⊕” in the figure), the chopper switch and the polarity conversion unit. The Q end of the DFF ( Figure 6(not shown) is connected to an input terminal of the first adder and a second input terminal of the chopper switch, and the D terminal of the DFF ( Figure 6 The clk terminal of DFF (not shown) is connected to the output terminal of the first adder and the first input terminal of the chopper switch. Figure 6 ) is connected to an external second clock signal ( Figure 6 (not shown in the figure), DFF is used to save the lower four-bit code LSB2<3:0> of the superimposed code of the previous cycle output by the first adder as the first low-bit digital code to the current cycle, and output the first low-bit digital code LSB2<3:0> to one input end of the first adder and the second input end of the chopping switch respectively. The other input end of the first adder is connected to the output end of the SAR ADC, and the first adder is used to superimpose the digital code DATA<7:0> of the current cycle output by the SAR ADC with the first low-bit digital code LSB2<3:0> to obtain the superimposed code of the current cycle, and output the lower four-bit code in the superimposed code of the current cycle as the second low-bit digital code LSB1<3:0> to the D end of the second D flip-flop and the first input end of the chopping switch. The first output end of the chopping switch is connected to the input end of the first RDAC unit RDAC1, and the second output end is connected to the input end of the polarity conversion unit, and the polarity conversion unit is used to convert the polarity of the input signal. The output end of the polarity conversion unit is connected to the input end of the second RDAC unit RDAC2, and the control end of the chopping switch is connected to the external control signal CLK. The chopping switch is used to exchange the output relationship between the first low-order digital code LSB2<3:0> and the second low-order digital code LSB1<3:0> and RDAC1 and RDAC2 once in each cycle, so as to output the first low-order digital code LSB2<3:0> and the second low-order digital code LSB1<3:0> alternately to RDAC1 and RDAC2 in consecutive different cycles. For example, when LSB2<3:0> is output to RDAC2 and LSB1<3:0> is output to RDAC1 in the previous cycle, then LSB1<3:0> is output to RDAC2 in this cycle, and LSB2<3:0> is output to RDAC1.

[0036] Static mismatch refers to the mismatch between DAC units due to process problems, resulting in a deviation between the designed binary digital domain weight and the actual analog domain weight. Assuming that the mismatch error of this analog weight minus the digital weight is E(n), n is the current cycle, and n-1 represents the previous cycle. This will cause E(n) to be injected when the DAC is used once per cycle, that is, E(n) will be injected when RDAC1 is used once per cycle. RDAC1 (n), using RDAC2 once will inject E RDAC2 (n-1), the number of times the DAC is used is related to the input signal, so E is injected in two adjacent cycles.RDAC2 (n-1), E RDAC1 (n), E RDAC1 (n-1), E RDAC2 (n), thus causing nonlinear harmonic problems. The MES Logic provided by the present invention adds the digital code of the previous cycle and the digital code of this cycle in the digital domain, and outputs the first low-order digital code and the second low-order digital code alternately to RDAC1 and RDAC2 in different consecutive cycles, and injects the mismatch error E(n-1) of the previous cycle by subtracting the two DAC analog domains in the analog domain, and can realize E(n)-E(n-1) in the time domain and E(z)(1-z^(-1)) in the frequency domain. In this way, the mismatch error shaping effect can be achieved, that is, by adjusting V O +E RDAC1 (n)+E RDAC2 (n-1) and V O +E RDAC2 (n)+E RDAC1 (n-1) to achieve error cancellation, V O Represents the ideal analog value of the digital code input to RDAC1 and RDAC2.

[0037] In some embodiments, the first RDAC unit, the second RDAC unit, and the third RDAC unit are all non-return-to-zero code resistance-type digital-to-analog converters with virtual ground characteristics, that is, the resistance-type digital-to-analog conversion circuit composed of the first RDAC unit, the second RDAC unit, the third RDAC unit, and the second adder is a virtual ground resistance-type RDAC network. For example, Figure 7 As shown, each of the three RDAC units includes: two unit resistors R UNIT , four NMOS tubes, two integrating capacitors C1, C2 and an amplifier; wherein one end of the first unit resistor is used to access the first external reference signal VREFP, and the other end is connected to the drain of the first NMOS tube and the drain of the second NMOS tube, the source of the first NMOS tube is connected to the source of the third NMOS tube, the negative input terminal of the amplifier and one end of the first integrating capacitor, the other end of the first integrating capacitor is connected to the positive output terminal of the amplifier, the gate of the third NMOS tube is connected to the gate of the second NMOS tube, the drain of the third NMOS tube is connected to the drain of the fourth NMOS tube and one end of the second unit resistor, the other end of the second unit resistor is used to access the second external reference signal VREFN, the source of the second NMOS tube is connected to the source of the fourth NMOS tube, the positive input terminal of the amplifier and one end of the second integrating capacitor, and the other end of the second integrating capacitor is connected to the negative output terminal of the amplifier. Unit resistors R in different RDAC units UNITThe resistance values ​​are different. When the RDAC unit is the first RDAC unit, the gates of the four NMOS tubes are used to access the converted thermometer code output by FT Logic, so as to control the on and off of the four NMOS tubes using the converted thermometer code output by FT Logic; when the RDAC unit is the second RDAC unit or the second RDAC unit, the gates of the four NMOS tubes are used to access the first low-order digital code and the second low-order digital code output by MES Logic, so as to control the on and off of the four NMOS tubes. The gates of the first NMOS tube and the fourth NMOS tube are both connected to the control signal D, and the gates of the second NMOS tube and the third NMOS tube are both connected to the control signal DB, D is opposite to DB, and D is a binary code in the binary code output by FTLogic or MES Logic. VREFP can be VDD, and VREFN can be the ground terminal. The RDAC unit adopting this structure can utilize the virtual ground characteristic of the amplifier to move the switch to the virtual ground points A and B. At this time, the voltage conducted by the MOS tube is a common mode voltage. The present invention uses NMOS to implement the RDAC function, which can reduce the mismatch in the conduction time, thereby alleviating the inter-symbol interference (ISI) problem caused by the dynamic mismatch between the rising edge and the falling edge of the DAC feedback waveform.

[0038] It should be noted that the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0039] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification.

[0040] In the specification, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality of components. Certain measures are recorded in different embodiments, but this does not mean that these measures cannot be combined to produce good effects.

[0041] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A high-precision sigma-delta ADC based on fixed code offset and mismatch error shaping technology, characterized in that: include: A subtractor, used for performing a subtraction operation on an input analog signal of a current cycle and a feedback analog signal of a cycle before the current cycle to obtain a processed signal of the current cycle; A feedforward loop filter, used for shaping the quantization noise in the processed signal of the current cycle to obtain a filtered signal; A successive approximation analog-to-digital converter, used for quantizing the filtered signal to obtain a digital code of the current cycle; A fixed code offset logic circuit, used for generating a converted thermometer code of the current cycle according to the upper four bits of the digital code of the current cycle, the pointer code of the previous cycle and a preset fixed code; a mismatch error shaping logic circuit, configured to generate the first low-order digital code and the second low-order digital code based on the digital code of the current cycle, and alternately input the first low-order digital code and the second low-order digital code into the first RDAC unit and the second RDAC unit in the resistance-type digital-to-analog conversion circuit according to the control of an external control signal; The resistance-type digital-to-analog conversion circuit is used to generate a feedback analog signal of the current cycle according to the converted thermometer code of the current cycle, the first low-bit digital code and the second low-bit digital code.

2. The high-precision sigma-delta ADC based on fixed code offset and mismatch error shaping technology according to claim 1, characterized in that: The fixed code offset logic circuit is specifically used to: save the pointer code of the previous cycle, superimpose the pointer code of the previous cycle with the preset fixed code to obtain the pointer code of the current cycle; convert the high four bits of the digital code of the current cycle into the thermometer code of the current cycle; and perform logical shift processing on the thermometer code of the current cycle according to the pointer code of the current cycle to obtain the converted thermometer code of the current cycle.

3. The high-precision sigma-delta ADC based on fixed code offset and mismatch error shaping technology according to claim 1, characterized in that: The fixed code offset logic circuit comprises: A first D flip-flop, wherein the Q terminal is connected to an input terminal of the pointer adding unit, the D terminal is connected to the output terminal of the pointer adding unit, and the clk terminal is connected to an external first clock signal, and is used to save the pointer code of the previous cycle output by the pointer adding unit and then output it in the current cycle; The pointer adding unit, another input end of which is used to access the preset fixed code, and one end connected to the D end of the first D flip-flop is also connected to an input end of the 4-bit logic shifter, and is used to superimpose the pointer code of the previous cycle with the preset fixed code to obtain the pointer code of the current cycle; A binary code thermometer code conversion unit, whose input end is connected to the output end of the successive approximation analog-to-digital converter, is used to convert the upper four bits of the digital code of the current cycle into the thermometer code of the current cycle and output it; The 4-bit logic shifter has another input end connected to the output end of the binary code thermometer code conversion unit, and an output end connected to the input end of the third RDAC unit in the resistance-type digital-to-analog conversion circuit, and is used to perform logic shift processing on the thermometer code of the current cycle according to the pointer code of the current cycle to obtain the converted thermometer code of the current cycle.

4. The high-precision sigma-delta ADC based on fixed code offset and mismatch error shaping technology according to claim 3, characterized in that: The pointer code is a 4-bit binary code, and the thermometer code is an m-bit binary code; The 4-bit logic shifter includes 4 groups of logic units, wherein the input of the first group of logic units is the thermometer code of the current cycle, the input of the second group of logic units is the output of the first group of logic units, the input of the third group of logic units is the output of the second group of logic units, the input of the fourth group of logic units is the output of the third group of logic units, and the output of the fourth group of logic units is the converted thermometer code of the current cycle; Each group of logic units includes m two-to-one data selectors, wherein the difference between the two input codes of each two-to-one data selector in the first group of logic units in the m-bit input code of the first group of logic units is 2 3 The difference between the two input codes of each two-to-one data selector in the second group of logic units in the m-bit input code of the second group of logic units is 2 2 The difference between the two input codes of each two-to-one data selector in the third group of logic units in the m-bit input code of the third group of logic units is 2 1 The difference between the two input codes of each two-to-one data selector in the fourth group of logic units in the m-bit input code of the fourth group of logic units is 2 0 ; The highest bit of the 4-bit binary code is used as the control signal of each two-to-one data selector in the first group of logic units, the second highest bit of the 4-bit binary code is used as the control signal of each two-to-one data selector in the second group of logic units, the second lowest bit of the 4-bit binary code is used as the control signal of each two-to-one data selector in the third group of logic units, and the lowest bit of the 4-bit binary code is used as the control signal of each two-to-one data selector in the fourth group of logic units.

5. The high-precision sigma-delta ADC based on fixed code offset and mismatch error shaping technology according to claim 1, characterized in that: The mismatch error shaping logic circuit is specifically used to: save the lower four bits of the superimposed code of the previous cycle as the first low-order digital code, superimpose the digital code of the current cycle with the first low-order digital code to obtain the superimposed code of the current cycle, and use the lower four bits of the superimposed code of the current cycle as the second low-order digital code; under the control of the external control signal, in each cycle, exchange the output relationship between the first low-order digital code and the second low-order digital code and the first RDAC unit and the second RDAC unit, so as to alternately output the first low-order digital code and the second low-order digital code to the first RDAC unit and the second RDAC unit in consecutive different cycles.

6. The high-precision sigma-delta ADC based on fixed code offset and mismatch error shaping technology according to claim 1, characterized in that: The mismatch error shaping logic circuit comprises: a second D flip-flop, wherein the Q end is connected to an input end of the first adder and the second input end of the chopper switch, the D end is connected to the output end of the first adder and the first input end of the chopper switch, and the clk end is connected to an external second clock signal, and is used to save the lower four bits of the superimposed code of the previous cycle output by the first adder as the first low-bit digital code to the current cycle, and output the first low-bit digital code to an input end of the first adder and the second input end of the chopper switch respectively; The first adder, another input end of which is connected to the output end of the successive approximation analog-to-digital converter, is used to superimpose the digital code of the current cycle with the first low-bit digital code to obtain the superimposed code of the current cycle, and output the low four-bit code in the superimposed code of the current cycle as the second low-bit digital code to the D end of the second D flip-flop and the first input end of the chopper switch; The chopper switch has a first output end connected to the input end of the first RDAC unit, and a second output end connected to the input end of the polarity conversion unit; the polarity conversion unit is used to convert the polarity of the input signal; The output end of the polarity conversion unit is connected to the input end of the second RDAC unit, and the control end is connected to the external control signal CLK, so as to exchange the output relationship between the first low-order digital code and the second low-order digital code and the first RDAC unit and the second RDAC unit once in each cycle, so as to output the first low-order digital code and the second low-order digital code alternately to the first RDAC unit and the second RDAC unit in consecutive different cycles.

7. The high-precision sigma-delta ADC based on fixed code offset and mismatch error shaping technology according to claim 1, characterized in that: The resistance-type digital-to-analog conversion circuit comprises: a first RDAC unit, a second RDAC unit, a third RDAC unit and a second adder; The output ends of the first RDAC unit, the second RDAC unit and the third RDAC unit are respectively connected to the three input ends of the second adder, the output end of the second adder is connected to one input end of the subtractor, the other input end of the subtractor is connected to the analog signal of the current cycle, and the output end of the subtractor is connected to the input end of the feedforward loop filter; the output end of the feedforward loop filter is connected to the input end of the successive approximation analog-to-digital converter; the output end of the successive approximation analog-to-digital converter serves as the output end of the high-precision sigma-delta ADC, and the output end is also connected to the input end of the fixed code offset logic circuit and the input end of the mismatch error shaping logic circuit; the output end of the fixed code offset logic circuit is connected to the input end of the third RDAC unit; and the two output ends of the mismatch error shaping logic circuit are respectively connected to the input ends of the first RDAC unit and the RDAC unit.

8. The high-precision sigma-delta ADC based on fixed code offset and mismatch error shaping technology according to claim 7, characterized in that: The first RDAC unit, the second RDAC unit and the third RDAC unit are all non-return-to-zero code resistance type digital-to-analog converters with virtual ground characteristics.

9. The high-precision sigma-delta ADC based on fixed code offset and mismatch error shaping technology according to claim 7 or 8, characterized in that: Each RDAC unit includes: two unit resistors, four NMOS tubes, two integrating capacitors and an amplifier; wherein one end of the first unit resistor is used to connect the first external reference signal V REFP , the other end is connected to the drain of the first NMOS tube and the drain of the second NMOS tube, the source of the first NMOS tube is connected to the source of the third NMOS tube, the negative input terminal of the amplifier and one end of the first integrating capacitor, the other end of the first integrating capacitor is connected to the positive output terminal of the amplifier, the gate of the third NMOS tube is connected to the gate of the second NMOS tube, the drain of the third NMOS tube is connected to the drain of the fourth NMOS tube and one end of the second unit resistor, and the other end of the second unit resistor is used to access the second external reference signal V REFN The source of the second NMOS tube is connected to the source of the fourth NMOS tube, the positive input terminal of the amplifier and one end of the second integrating capacitor, and the other end of the second integrating capacitor is connected to the negative output terminal of the amplifier; the gates of the four NMOS tubes are used to access the signals output by the fixed code offset logic circuit or the mismatch error shaping logic circuit.

10. The high-precision sigma-delta ADC based on fixed code offset and mismatch error shaping technology according to claim 1, characterized in that: The successive approximation analog-to-digital converter is an 8-bit successive approximation analog-to-digital converter, the pointer code, the preset fixed code, the first low-order digital code and the second low-order digital code are all 4-bit binary codes, and the thermometer code is a 15-bit binary code.

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