Ethernet connection information acquisition system and acquisition method

Abstract

The application provides an Ethernet connection information acquisition system and method, wherein the system comprises an FPGA chip and a PHY chip, the FPGA chip comprises a connection information acquisition module and an SMI read-write module, the PHY chip is connected with a host through a network cable, and the SMI read-write module is connected with the connection information acquisition module and the PHY chip; the SMI read-write module is used for converting a read instruction of the connection information acquisition module into an instruction of an smi interface, transmitting the instruction to the PHY chip through two signal lines of mdc and mdio, and sending read data returned by the PHY chip to the connection information acquisition module, so that the connection information acquisition module obtains connection state information and network rate information and outputs the information externally. The Ethernet connection information acquisition system provided by the application can cooperate with multiple PHY chips through the FPGA chip, and is convenient for reading the connection state information and the network rate information of any PHY chip.

Description

Technical Field

[0001] The present disclosure generally relates to the field of network communication technology, and in particular to a system and method for obtaining Ethernet connection information. Background Art

[0002] Before Ethernet data is sent or received, the devices at both ends of the network must first establish a link connection, and then send and receive data based on the Ethernet connection information. The Ethernet connection information usually includes the connection status and network speed.

[0003] The existing technology obtains the connection status and network speed from the PHY chip through the operating system in the CPU. However, the CPU can only obtain the PHY chip connected to it. Generally, a CPU can only connect to one or two PHY chips. For switches with more than a dozen or even dozens of PHY chips, it is impossible to obtain the connection status and network speed of any PHY chip. Summary of the Invention

[0004] In view of the above-mentioned defects or deficiencies in the prior art, it is desired to provide an Ethernet connection information acquisition system and acquisition method to solve the above-mentioned problems.

[0005] In a first aspect, the present application provides an Ethernet connection information acquisition system, comprising an FPGA chip and a PHY chip, wherein the FPGA chip comprises a connection information acquisition module and an SMI read / write module, the PHY chip is connected to a host via a network cable, and the SMI read / write module connects the connection information acquisition module and the PHY chip;

[0006] The SMI read-write module is used to convert the read instructions of the connection information acquisition module into instructions of the SMI interface, and transmit them to the PHY chip through the two signal lines MDC and MDIO, and send the read data returned by the PHY chip to the connection information acquisition module, so that the connection information acquisition module obtains the connection status information and network rate information and outputs them to the outside; the read instruction includes a first read request signal or a second read request signal and an address signal, the first read request signal is used to request the connection status information, the second read request signal is used to request the network rate information, and the address signal is used to indicate the location of the connection status information and network rate information in the PHY chip.

[0007] According to the technical solution provided in the embodiment of the present application, the PHY chip is provided with a connection status register and a network rate register, the connection status register is used to store the connection status information, and the network rate register is used to store the network rate information.

[0008] According to the technical solution provided in the embodiment of the present application, the address signal includes a first address signal or a second address signal, the first address signal is used to indicate the address of the connection status register, and the second address signal is used to indicate the address of the network rate register.

[0009] According to the technical solution provided in the embodiment of the present application, the PHY chip returns a first read data signal according to the first read request signal, and the PHY chip returns a second read data signal according to the second read request signal. The first read data signal is used by the connection information acquisition module to read the connection status information, and the second read data signal is used by the connection information acquisition module to read the network rate information.

[0010] According to the technical solution provided in the embodiment of the present application, the function of the connection information acquisition module is implemented through a state machine.

[0011] A second aspect of the present application provides a method for obtaining Ethernet connection information, based on the Ethernet connection information obtaining system described above, comprising:

[0012] The connection information acquisition module enters a connection state request state after determining that the system is started;

[0013] The connection information acquisition module sends a first read request signal to the SMI read / write module, so that the SMI read / write module forwards the first read request signal to the PHY chip; the connection information acquisition module jumps to the connection status reading state;

[0014] When the connection information acquisition module determines that the connection state is placed in the connection state reading state, the first address signal is sent to the SMI read-write module, so that the PHY chip reads the connection state signal according to the first address signal forwarded by the SMI, and sends a first read completion signal and a first read data signal after the PHY chip completes the reading;

[0015] When the connection information acquisition module receives the first read completion signal and determines that it is at a high level, it jumps to a connection status check state;

[0016] When the connection information acquisition module is in the connection status check state, it determines whether the network is connected according to the first read data signal, and if so, the output connection status is set to a high level, otherwise the output connection status is set to a low level; the connection information acquisition module jumps to the network rate request state;

[0017] When the connection information acquisition module determines that the state is set to the network rate request state, the connection information acquisition module sends a second read request signal to the SMI read / write module, so that the SMI read / write module forwards the second read request signal to the PYH chip; the connection information acquisition module jumps to the network rate reading state;

[0018] When the connection information acquisition module determines that the network rate reading state is set, the second address signal is sent to the SMI read / write module, so that the PHY chip reads the network rate signal according to the second address signal forwarded by the SMI read / write module, and sends a read completion signal and a second read data signal after the PHY chip completes the reading;

[0019] When the connection information acquisition module receives the second read completion signal and determines that it is at a high level, it jumps to a network rate check state;

[0020] When the connection information acquisition module determines that it is in the network rate check state, it obtains the actual network rate according to the second read data signal; the connection information acquisition module jumps to the waiting state, and jumps to the connection state request state after the waiting state lasts for a first preset time.

[0021] According to the technical solution provided in the embodiment of the present application, the connection information acquisition module enters the connection status request state after determining that the system is started, including:

[0022] The connection information acquisition module determines that the system enters an idle state after starting;

[0023] After the connection information acquisition module determines that the idle state is in the first preset time period, the module jumps to the connection state request state.

[0024] Compared with the existing technology, the beneficial effect of the present application is that: the Ethernet connection information acquisition system provided by the present application includes an FPGA chip and a PHY chip, and the FPGA chip includes a connection information acquisition module and an SMI read-write module. The read instruction is sent through the connection information acquisition module and forwarded to the PHY chip through the SMI read-write module, and then the connection status and network rate are obtained from the PHY chip; since the FPGA chip can establish a one-to-many connection with the PHY chip, the present application can obtain the connection status and network rate from any PHY chip through the connection between the FPGA chip and the PHY chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Other features, objects and advantages of the present application will become more apparent upon reading the detailed description of non-limiting embodiments made with reference to the following drawings:

[0026] Figure 1A schematic diagram of the structure of the Ethernet connection information acquisition system provided in Example 1;

[0027] Figure 2 This is a flowchart of the method for obtaining Ethernet connection information provided in Example 2.

[0028] Figure numbers: 1. FPGA chip; 11. Connection information acquisition module; 12. SMI read / write module; 2. PHY chip. DETAILED DESCRIPTION

[0029] The present application will be further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are merely for the purpose of explaining the relevant invention and are not intended to limit the invention. It should also be noted that, for ease of description, only portions relevant to the invention are shown in the accompanying drawings.

[0030] It should be noted that, in the absence of conflict, the embodiments and features of the embodiments in this application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0031] Example 1

[0032] Please refer to Figure 1 The present application provides an Ethernet connection information acquisition system, including an FPGA chip 1 and a PHY chip 2. The FPGA chip 1 includes a connection information acquisition module 11 and an SMI read-write module 12. The PHY chip 2 is connected to a host via a network cable. The SMI read-write module 12 connects the connection information acquisition module 11 and the PHY chip 2.

[0033] The SMI read-write module 12 is used to convert the read instructions of the connection information acquisition module 11 into instructions of the SMI interface, and transmit them to the PHY chip 2 through the two signal lines MDC and MDIO, and send the read data returned by the PHY chip 2 to the connection information acquisition module 11, so that the connection information acquisition module 11 obtains the connection status information and network rate information and outputs them to the outside; the read instruction includes a first read request signal or a second read request signal and an address signal, the first read request signal is used to request the connection status information, the second read request signal is used to request the network rate information, and the address signal is used to indicate the location of the connection status information and the network rate information in the PHY chip 2.

[0034] Specifically, the connection information acquisition module 11 is used to generate a read instruction, wherein the read instruction includes two signals: a 1-bit request read_req and a 5-bit address reg_addr. The 1-bit request includes the first read request signal or the second read request signal, a 5-bit address, and the address signal indicating the position of the PHY chip 2. When it is necessary to obtain the connection status, the connection information acquisition module 11 sends the first read request signal to the SMI read-write module 12. The SMI read-write module 12 converts the first read request signal into an instruction of the SMI interface and transmits it to the PHY chip 2 through the two signal lines mdc and mdio. Then, the connection information acquisition module 11 sends the address signal to the SMI read-write module 12. The SMI read-write module 12 also converts the address signal and sends it to the PHY chip 2. The SMI read-write module 12 obtains the connection status of the corresponding position from the PHY chip 2 and returns the connection status of the corresponding position to the connection information acquisition module 11 through the 16-bit read data read_data.

[0035] When it is necessary to obtain the network rate, the connection information acquisition module 11 sends the second read request signal to the SMI read-write module 12, and the SMI read-write module 12 converts the second read request signal into an instruction of the SMI interface and transmits it to the PHY chip 2 through the two signal lines of MDC and MDIO. Then the connection information acquisition module 11 sends the address signal to the SMI read-write module 12, which is also converted by the SMI read-write module 12 and sent to the PHY chip 2. The SMI read-write module 12 obtains the network rate of the corresponding position from the PHY chip 2, and returns the network rate of the corresponding position to the connection information acquisition module 11 through 16-bit read data read_data.

[0036] In addition to sending read instructions, the connection information acquisition module 11 can also send write instructions to the SMI read and write module. The write instructions include three signals: 1-bit write request write_req, 16-bit write data write_data and 5-bit address reg_addr. Since this application does not involve the relevant content of write instructions, no further details will be given here.

[0037] Furthermore, the PHY chip 2 is provided with a connection status register and a network rate register, wherein the connection status register is used to store the connection status information, and the network rate register is used to store the network rate information.

[0038] Specifically, the connection status information and the network rate information are respectively stored through the connection status register and the network rate register. When the PHY chip 2 receives the corresponding address information, the connection status information and the network rate information are returned from the corresponding registers to the SMI read-write module 2, and sent to the connection information acquisition module 11 through the SMI read-write module.

[0039] Furthermore, the address signal includes a first address signal or a second address signal, the first address signal is used to indicate the address of the connection status register, and the second address signal is used to indicate the address of the network rate register.

[0040] Specifically, the addresses of the connection status register and the network rate register can be accurately located through the first address signal and the second address signal.

[0041] Furthermore, the PHY chip 2 returns a first read data signal according to the first read request signal, and the PHY chip 2 returns a second read data signal according to the second read request signal. The first read data signal is used by the connection information acquisition module 11 to read the connection status information, and the second read data signal is used by the connection information acquisition module 11 to read the network rate information.

[0042] Furthermore, the function of the connection information acquisition module 11 is implemented through a state machine.

[0043] Example 2

[0044] Please refer to Figure 2 This embodiment provides a method for obtaining external network connection information, based on the Ethernet connection information obtaining system as described in Example 1, including:

[0045] S100, the connection information acquisition module 11 determines that the system is started and enters the connection state request state;

[0046] S200: The connection information acquisition module 11 sends a first read request signal to the SMI read / write module 12, so that the SMI read / write module 12 forwards the first read request signal to the PYH chip; the connection information acquisition module 11 jumps to the connection status reading state;

[0047] S300: When the connection information acquisition module 11 determines that the connection state is in the connection state reading state, the first address signal is sent to the SMI read-write module 12, so that the PHY chip 2 reads the connection state signal according to the first address signal forwarded by the SMI read-write module 12, and sends a first read completion signal and a first read data signal after the PHY chip 2 completes the reading;

[0048] S400: When the connection information acquisition module 11 receives the first read completion signal and determines that the signal is at a high level, the module switches to a connection status check state.

[0049] S500: When the connection information acquisition module 11 is in the connection status check state, it determines whether the network is connected according to the first read data signal. If so, the connection status is output to a high level; otherwise, the connection status is output to a low level. The connection information acquisition module 11 jumps to the network rate request state.

[0050] S600: When the connection information acquisition module 11 determines that the state is the network rate request state, the connection information acquisition module 11 sends a second read request signal to the SMI read / write module 12, so that the SMI read / write module 12 forwards the second read request signal to the PYH chip; the connection information acquisition module 11 jumps to the network rate read state;

[0051] S700: When the connection information acquisition module 11 determines that the network rate is in the reading state, the connection information acquisition module 11 sends the second address signal to the SMI read / write module 12, so that the PHY chip 2 reads the network rate signal according to the second address signal forwarded by the SMI read / write module 12, and sends a read completion signal and a second read data signal after the PHY chip 2 completes the reading.

[0052] S800: When the connection information acquisition module 11 receives the second read completion signal and determines that the signal is at a high level, the module switches to a network rate check state.

[0053] S900, when the connection information acquisition module 11 determines to be in the network rate check state, the actual network rate is obtained according to the second read data signal; the connection information acquisition module 11 jumps to the waiting state, and jumps to the connection state request state after the waiting state lasts for a first preset time.

[0054] Specifically, such as Figure 2As shown, after the system is started, the connection information acquisition module 11 enters the connection state request state, in which the connection information acquisition module 11 sends a first read request signal read_req to the SMI read-write module 12 and jumps to the connection state reading state. In the connection state reading state, the connection information acquisition module 11 sends the first address signal reg_addr to the SMI read-write module 12, where the address reg_addr is the connection state register address of the PHY chip 2, and then waits for the first read completion signal done. When the first read completion signal done becomes high, it indicates that the SMI read-write module 12 has returned the first read data signal read_data, and the data of this signal is the connection state value, and jumps to the connection state check state. In the connection state check state, the connection state value is judged. If the value is 1, it indicates that the network has been connected, the connection state link output by the connection information acquisition module 11 is high, and jumps to the network rate request state, otherwise the value is 0, indicating that the network has no connection, the connection state link output by the connection information acquisition module 11 is low, and jumps to the waiting state.

[0055] In the network rate request state, the connection information acquisition module 11 sends a second read request signal read_req to the SMI read-write module 12 and jumps to the network rate reading state. In the network rate reading state, the connection information acquisition module 11 sends the second address signal reg_addr to the SMI read-write module 12, where the address reg_addr is the network rate register address of the PHY chip 2, and then waits for the second read completion signal done. When the second read completion signal done becomes high, it indicates that the SMI read-write module 12 has returned the second read data signal read_data, and the data of this signal is the network rate value, and jumps to the network rate check state. In the network rate check state, the current rate is judged according to the network rate. If the network rate value is 001, it indicates 10M rate, the network rate speed output by the connection information acquisition module 11 is set to 01; if the network rate value is 010, it indicates 100M rate, the network rate speed output by the connection information acquisition module 11 is set to 10; if the network rate value is 100, it indicates 1000M rate, the network rate speed output by the connection information acquisition module 11 is set to 11; and then jumps to the waiting state. In the waiting state, after timing for 1 second, it jumps to the connection state request state.

[0056] Further, the connection information acquisition module 11 judges that after the system is started, the connection state request state includes:

[0057] The connection information acquisition module 11 determines that the system enters an idle state after starting;

[0058] After the connection information acquisition module 11 determines that the idle state is in the first preset time period, it jumps to the connection state request state.

[0059] Specifically, after the system is started, the connection information acquisition module 11 enters the idle state by default, counts for 1 second in the idle state to ensure that the PHY chip 2 is initialized, and jumps to the connection state request state after 1 second.

[0060] The above description is merely a preferred embodiment of the present application and an illustration of the technical principles employed. Those skilled in the art should understand that the scope of the invention herein is not limited to the technical solutions formed by the specific combination of the above-mentioned technical features, but also encompasses other technical solutions formed by any combination of the above-mentioned technical features or their equivalents without departing from the inventive concept. For example, a technical solution formed by replacing the above-mentioned features with (but not limited to) technical features having similar functions disclosed in this application.

Claims

1. An Ethernet connection information acquisition system, characterized in that: The device comprises an FPGA chip (1) and a PHY chip (2), wherein the FPGA chip (1) comprises a connection information acquisition module (11) and an SMI read / write module (12), the PHY chip (2) is connected to a host via a network cable, and the SMI read / write module (12) is connected to the connection information acquisition module (11) and the PHY chip (2); The SMI read / write module (12) is used to convert the read instruction of the connection information acquisition module (11) into an instruction of the SMI interface, and transmit it to the PHY chip (2) through two signal lines, MDC and MDIO, and send the read data returned by the PHY chip (2) to the connection information acquisition module (11), so that the connection information acquisition module (11) obtains the connection status information and the network rate information and outputs them externally; the read instruction includes a first read request signal or a second read request signal and an address signal, the first read request signal is used to request the connection status information, the second read request signal is used to request the network rate information, and the address signal is used to indicate the location of the connection status information and the network rate information in the PHY chip (2).

2. The Ethernet connection information acquisition system according to claim 1, characterized in that: The PHY chip (2) is provided with a connection status register and a network rate register, wherein the connection status register is used to store the connection status information, and the network rate register is used to store the network rate information.

3. The Ethernet connection information acquisition system according to claim 2, characterized in that: The address signal includes a first address signal or a second address signal, the first address signal is used to indicate the address of the connection status register, and the second address signal is used to indicate the address of the network rate register.

4. The Ethernet connection information acquisition system according to claim 3, characterized in that: The PHY chip (2) returns a first read data signal according to the first read request signal, and the PHY chip (2) returns a second read data signal according to the second read request signal, the first read data signal being used by the connection information acquisition module (11) to read the connection status information, and the second read data signal being used by the connection information acquisition module (11) to read the network rate information.

5. The Ethernet connection information acquisition system according to claim 4, characterized in that: The function of the connection information acquisition module (11) is realized through a state machine.

6. A method for obtaining Ethernet connection information, characterized in that: The Ethernet connection information acquisition system according to claim 5 comprises: The connection information acquisition module (11) enters a connection state request state after determining that the system is started; The connection information acquisition module (11) sends a first read request signal to the SMI read / write module (12), so that the SMI read / write module (12) forwards the first read request signal to the PHY chip; the connection information acquisition module (11) jumps to a connection status reading state; When the connection information acquisition module (11) determines that the state is to be placed in the connection state reading state, the first address signal is sent to the SMI read / write module (12), so that the PHY chip (2) reads the connection state signal according to the first address signal forwarded by the SMI read / write module (12), and sends a first read completion signal and a first read data signal after the PHY chip (2) completes the reading; When the connection information acquisition module (11) receives the first reading completion signal and determines that it is at a high level, it jumps to a connection status check state; When the connection information acquisition module (11) is in the connection status check state, it determines whether the network is connected according to the first read data signal, and if so, the output connection status is set to a high level, and if not, the output connection status is set to a low level; the connection information acquisition module (11) jumps to the network rate request state; When the connection information acquisition module (11) determines that the network rate request state is set, the second read request signal is sent to the SMI read / write module (12), so that the SMI read / write module (12) forwards the second read request signal to the PYH chip; the connection information acquisition module (11) jumps to the network rate reading state; When the connection information acquisition module (11) determines that the network rate is in the reading state, the second address signal is sent to the SMI read / write module (12), so that the PHY chip (2) reads the network rate signal according to the second address signal forwarded by the SMI, and sends a read completion signal and a second read data signal after the PHY chip (2) completes the reading; When the connection information acquisition module (11) receives the second read completion signal and determines that it is at a high level, it jumps to a network rate check state; When the connection information acquisition module (11) determines that the network rate is in the check state, the actual network rate is obtained according to the second read data signal; the connection information acquisition module (11) jumps to the waiting state, and jumps to the connection state request state after the waiting state lasts for a first preset time.

7. The method for obtaining Ethernet connection information according to claim 6, wherein: The connection information acquisition module (11) enters a connection state request state after determining that the system is started, including: The connection information acquisition module (11) determines that the system enters an idle state after starting; The connection information acquisition module (11) jumps to the connection state request state after determining that the idle state has lasted for a first preset time.

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