Printed circuit board and method of manufacturing same

Abstract

The invention provides a printed circuit board and a method of manufacturing the same. The printed circuit board includes: a first insulating layer; a first metal layer disposed on an upper side of the first insulating layer; a second metal layer disposed on a lower side of the first insulating layer; and a first via layer penetrating at least a portion of the first insulating layer to connect the first metal layer to the second metal layer. The first via layer has a tapering shape in which a width becomes narrower toward a top of the first insulating layer, and an upper surface of the first metal layer is substantially flat, and a side surface of the first metal layer is a curved surface.

Description

[0001] This application claims the benefit of priority from Korean Patent Application No. 10-2023-0086886 filed on July 5, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0002] The present disclosure relates to a printed circuit board and a method of manufacturing the printed circuit board. Background Art

[0003] Multi-chip packages for data processing that has been growing exponentially due to recent advances in artificial intelligence (AI) technology are being used, and the multi-chip packages include memory chips (such as high bandwidth memory (HBM), processor chips (such as central processing units (CPUs), graphics processing units (GPUs), and logic chips (such as application-specific integrated circuits (ASICs) and field-programmable gate arrays (FPGAs)). In detail, the number of CPU cores and GPU cores in server products has increased rapidly, and it is necessary to respond to chip bumps with finer pitches. Therefore, research is continuing to develop substrates and package structures that can reduce the pitch of bumps to respond to higher density requirements, improve connection reliability, and increase yields. Summary of the invention

[0004] An aspect of the present disclosure is to provide a printed circuit board for mounting electronic components, semiconductor chips, etc., which can realize bumps with fine pitches.

[0005] An aspect of the present disclosure is to provide a printed circuit board that can implement protruding bumps without etching an insulating layer.

[0006] An aspect of the present disclosure is to provide a printed circuit board having improved reliability.

[0007] According to one aspect of the present disclosure, a printed circuit board includes: a first insulating layer; a first metal layer disposed on an upper side of the first insulating layer; a second metal layer disposed on a lower side of the first insulating layer; and a first via layer penetrating at least a portion of the first insulating layer to connect the first metal layer to the second metal layer. The first via layer has a tapered shape in which a width becomes narrower toward a top of the first insulating layer, and an upper surface of the first metal layer is substantially flat, and a side surface of the first metal layer is a curved surface.

[0008] According to one aspect of the present disclosure, a method for manufacturing a printed circuit board includes: forming a first barrier layer on a carrier substrate; forming a second barrier layer on the first barrier layer; forming a first insulating layer on the second barrier layer; forming a first through hole penetrating the first insulating layer; forming a second through hole penetrating the second barrier layer; forming a first metal layer by filling the second through hole; forming a first via layer by filling the first through hole; forming a second metal layer on the first insulating layer; and removing the carrier substrate, the first barrier layer, and the second barrier layer.

[0009] According to one aspect of the present disclosure, a printed circuit board includes: a first insulating layer; a first metal layer, disposed on the upper side of the first insulating layer; a second metal layer, disposed on the lower side of the first insulating layer; and a first via layer, penetrating at least a portion of the first insulating layer to connect the first metal layer to the second metal layer. The first via layer has a tapered shape in which the width becomes narrower toward the first metal layer. The first metal layer, the first via layer, and the second metal layer each include a first metal disposed at a corresponding boundary with the first insulating layer and a second metal disposed on the first metal. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other aspects, features and advantages of the present disclosure will be more clearly understood through the following detailed description in conjunction with the accompanying drawings, in which: Figure 1 is a block diagram schematically illustrating an example of an electronic device system; Figure 2 is a perspective view schematically showing an example of an electronic device; Figure 3 is a cross-sectional view schematically illustrating a printed circuit board according to an example; and Figures 4 to 6 is a cross-sectional view schematically illustrating a method of manufacturing a printed circuit board according to an example. DETAILED DESCRIPTION

[0011] Hereinafter, the present disclosure will be described with reference to the accompanying drawings. For clearer description, the shapes and sizes of elements in the drawings may be exaggerated or reduced.

[0012] Electronic Devices Figure 1 is a block diagram schematically illustrating an example of an electronic device system.

[0013] Reference Figure 1, the electronic device 1000 may house a mainboard 1010 therein. Chip-related components 1020, network-related components 1030, other components 1040, etc. may be physically or electrically connected to the mainboard 1010. These components may be connected to other electronic components to be described below through various signal lines 1090.

[0014] The chip-related components 1020 may include: memory chips, such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., read-only memory (ROM), flash memory), etc.; application processor chips, such as central processing units (e.g., central processing units (CPUs)), graphics processors (e.g., graphics processing units (GPUs)), digital signal processors, cryptographic processors, microprocessors, microcontrollers, etc.; and logic chips, such as analog-to-digital converters (ADCs), application-specific integrated circuits (ASICs), etc. However, the chip-related components 1020 are not limited thereto, but may also include other types of chip-related components. In addition, the chip-related components 1020 may also be combined with each other. The chip-related components 1020 may be in the form of a package including the above-mentioned chips.

[0015] The network-related components 1030 may include components that are compatible with or operate according to protocols such as: Wireless Fidelity (Wi-Fi) (Institute of Electrical and Electronics Engineers (IEEE) 802.11 series, etc.), Worldwide Interoperability for Microwave Access (WiMAX) (IEEE 802.16 series, etc.), IEEE 802.20, Long Term Evolution (LTE), Evolution-Data Optimized (Ev-DO), High Speed ​​Packet Access + (HSPA+), High Speed ​​Downlink Packet Access + (HSDPA+), High Speed ​​Uplink Packet Access + (HSUPA+), Enhanced Data Rates for GSM Evolution (EDGE), Global System for Mobile Communications (GSM), Global Positioning System (GPS), General Packet Radio Service (GPRS), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Enhanced Digital Cordless Telecommunications (DECT), Bluetooth, third generation mobile communication technology (3G) protocols, fourth generation mobile communication technology (4G) protocols, and fifth generation mobile communication technology (5G) protocols, as well as any other wireless protocols and wired protocols specified after the above protocols. However, the network-related component 1030 is not limited thereto, but may also include components compatible with or operating in accordance with various other wireless standards or protocols or wired standards or protocols. In addition, the network-related component 1030 may be combined with the chip-related component 1020 described above.

[0016] Other components 1040 may include high frequency inductors, ferrite inductors, power inductors, ferrite beads, low temperature co-fired ceramic (LTCC) components, electromagnetic interference (EMI) filters, multilayer ceramic capacitors (MLCC), etc. However, other components 1040 are not limited thereto, but may also include passive devices in the form of chip components for various other purposes, etc. In addition, other components 1040 may also be combined with the above-mentioned chip-related components 1020 and / or network-related components 1030.

[0017] Depending on the type of the electronic device 1000, the electronic device 1000 may include other electronic components that are physically or electrically connected to the mainboard 1010 or that are not physically or electrically connected to the mainboard 1010. These other electronic components may include, for example, a camera 1050, an antenna 1060, a display 1070, and a battery 1080, etc. However, these other electronic components are not limited thereto, and may also be an audio codec, a video codec, a power amplifier, a compass, an accelerometer, a gyroscope, a speaker, a mass storage unit (e.g., a hard disk drive), a compact disk (CD) drive, a digital versatile disk (DVD) drive, etc. In addition, depending on the type of the electronic device 1000, the electronic device 1000 may also include other electronic components for various purposes.

[0018] The electronic device 1000 may be a smart phone, a personal digital assistant (PDA), a digital video camera, a digital camera, a network system, a computer, a monitor, a tablet PC, a laptop PC, a netbook PC, a television, a video game console, a smart watch, an automobile component, etc. However, the electronic device 1000 is not limited thereto but may be any other electronic device capable of processing data.

[0019] Figure 2 is a schematic perspective view showing an example of an electronic device.

[0020] Reference Figure 2, the electronic device may be, for example, a smart phone 1100. A mainboard 1110 is housed inside the smart phone 1100, and various components 1120 are physically or electrically connected to the mainboard 1110. In addition, other electronic components (such as a camera module 1130 and / or a speaker 1140) that are physically or electrically connected to the mainboard 1110 or that are not physically or electrically connected to the mainboard 1110 may be housed in the smart phone 1100. Some of the components 1120 may be the above-mentioned chip-related components, for example, a component package 1121, but are not limited thereto. The component package 1121 may be in the form of a printed circuit board on which an electronic component (including an active component and / or a passive component) is surface-mounted. Alternatively, the component package 1121 may be in the form of a printed circuit board in which an electronic component (including an active component and / or a passive component) is embedded. On the other hand, the electronic device need not be limited to the smart phone 1100, and may also be other electronic devices as described above.

[0021] Printed Circuit Board Figure 3 is a cross-sectional view schematically illustrating a printed circuit board according to an example.

[0022] Reference Figure 3 , a printed circuit board according to an example may include: a first insulating layer 111; a first metal layer 121 disposed on an upper side of the first insulating layer 111; a second metal layer 122 disposed on a lower side of the first insulating layer 111; and a first via layer 131 penetrating at least a portion of the first insulating layer 111 to connect the first metal layer 121 and the second metal layer 122 to each other. The first via layer 131 has a tapered shape in which a width becomes narrower toward a top (upper side) of the first insulating layer 111 or the first metal layer 121, an upper surface of the first metal layer 121 is substantially flat, and a side surface of the first metal layer 121 may be a curved surface.

[0023] The first insulating layer 111 may include an insulating material. The insulating material may include a thermosetting resin (such as an epoxy resin), a thermoplastic resin (such as polyimide), or a material prepared by impregnating a thermosetting resin or a thermoplastic resin with an inorganic filler into a core material (such as glass fiber (such as glass fabric exemplified by glass cloth)). The insulating material may be a photosensitive material and / or a non-photosensitive material. For example, the insulating material of the first insulating layer 111 may be an insulating material such as a prepreg (PPG) or a resin-coated copper foil (RCC), but is not limited thereto, and may be an Ajinomoto deposited film (ABF), a photosensitive dielectric (PID), FR-4, bismaleimide triazine (BT), etc. However, the present disclosure is not limited thereto, and other polymer materials having excellent rigidity may be used if necessary.

[0024] The first metal layer 121 may include a metal material. The metal material may be copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), lead (Pb), titanium (Ti), or an alloy thereof. In detail, the metal material may include copper (Cu), but is not limited thereto. The first metal layer 121 may perform various functions according to the design. For example, the first metal layer 121 may be a pad on which electronic components and chips may be mounted, and may include a circuit pattern for performing signal connection with other pads. If the first metal layer 121 requires a high-density fine pitch for mounting semiconductor chips, etc., the gap between the first metal layers 121 may be narrowed, and in the case of mounting electronic components, the gap between the first metal layers 121 may be widened.

[0025] The first metal layer 121 may be formed using any one of a semi-additive process (SAP), a modified semi-additive process (MSAP), a hole sealing (TT) method, and a subtractive method, but is not limited thereto. As will be described later, the first metal layer 121 is formed by filling the second through hole 232 that penetrates the second barrier layer 220, and may be used as a pad and / or a column to reduce the pitch of the bump, thereby mounting a semiconductor chip with a fine pitch. The first metal layer 121 may include an electroless plating layer (e.g., a chemical copper plating layer) as a seed layer and an electrolytic plating layer (e.g., an electrolytic copper plating layer) as a plating layer, but is not limited thereto. A sputtering layer may be formed to replace the chemical copper plating layer as the electroless plating layer. If necessary, copper foil may also be included. The seed layer will be described later.

[0026] The first metal layer 121 may be disposed on the first insulating layer 111. The first metal layer 121 may have a structure protruding from the upper surface of the first insulating layer 111. The first metal layer 121 may include a plurality of first metal layers 121 (or may be referred to as a plurality of patterns) disposed on the same layer. Each of the plurality of first metal layers 121 (or may be referred to as a plurality of patterns) may have substantially the same height.

[0027] Substantially the same is a concept including approximate things, and may include, for example, process errors, positional deviations, and measurement errors that occur during the manufacturing process. As will be described later, since the first metal layer 121 is formed by filling the second through hole 232 that penetrates the second barrier layer 220, a plurality of first metal layers 121 may be uniformly formed. In addition, since the second barrier layer 220 uses a different metal from the first metal layer 121, the first metal layer 121 may be protected during the removal step of the second barrier layer 220, and thus a plurality of first metal layers 121 may be protected. The heights of the first metal layers 121 may be substantially the same.

[0028] The height of the first metal layer 121 can be measured by photographing a cross section cut along the stacking direction of the printed circuit board using a scanning microscope or the like. The height of the first metal layer 121 can be interpreted in the same manner as the thickness of the first metal layer 121, and the thickness of the structure can be interpreted as the distance vertically passing through the structure, but may include measurement errors or errors in the manufacturing process. For example, the height of the first metal layer 121 can be the average of the vertical distances between the upper surface and the lower surface of the first metal layer 121 measured at five arbitrary points relative to one first metal layer 121. The fact that the heights of the plurality of first metal layers 121 may be substantially the same as each other means that the measured heights of each first metal layer 121 may be substantially the same as each other.

[0029] The upper surface of the first metal layer 121 is substantially flat, and the side surface of the first metal layer 121 may be a curved surface. As will be described later in the manufacturing step of the printed circuit board, the first metal layer 121 may be formed by filling the second through hole 232 penetrating the second barrier layer 220. In the operation of forming the second through hole 232, even if the second barrier layer 220 is completely penetrated so that the upper surface and the lower surface of the second barrier layer 220 are connected, the first barrier layer 210 is not removed. The first metal layer 121 may have a substantially flat upper surface. At this time, since the side of the second through hole 232 penetrating the second barrier layer 220 may have a curved shape, the side of the first metal layer 121 may have a curved shape. In detail, if the operation of removing the second barrier layer 220 involves chemical etching, the side of the second through hole 232 penetrating the second barrier layer 220 may have a curved shape.

[0030] The width of the lower surface of the first metal layer 121 may be wider than the width of the upper surface of the first metal layer 121. If the operation of removing the second barrier layer 220 is performed by etching, the upper width of the second through hole 232 penetrating the second barrier layer 220 at the upper surface may be different from the lower width at the lower surface, and the second through hole 232 may be formed to be wider at the lower surface than at the upper surface. In addition, the side surface of the first metal layer 121 may be a curved surface so that the width at the top (ie, the upper width) is the narrowest and the width at the bottom (ie, the lower width) is the widest.

[0031] The width of the first metal layer 121 can be measured by photographing a cross section cut along the stacking direction of the printed circuit board using a scanning microscope or the like. The width of the structure can be interpreted as the distance horizontally passing through the structure, but may include measurement errors or errors in the manufacturing process. For example, the width at the upper surface of the first metal layer 121 may represent the horizontal distance between the two ends of the upper surface relative to one first metal layer 121. This can also be applied to measuring the width of the lower surface of the first metal layer 121. At this time, the fact that the width of the lower surface of the first metal layer 121 is wider than the width of the upper surface of the first metal layer 121 can be understood in the same sense as: the cross-sectional area of ​​the lower surface of the first metal layer 121 is greater than the cross-sectional area of ​​the upper surface of the first metal layer 121.

[0032] The second metal layer 122 may be disposed under the first insulating layer 111. The second metal layer 122 may include a metal material. The metal material may be copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), lead (Pb), titanium (Ti), or an alloy thereof. In detail, the metal material may include copper (Cu), but is not limited thereto. The second metal layer 122 may include the same metal material as the first metal layer 121.

[0033] The second metal layer 122 may perform various functions according to the design of each configuration, and may include a circuit pattern that performs signal connection between the first metal layer 121 and other metal layers, for example, the circuit pattern may include a ground pattern, a power pattern, a signal pattern, etc. In this case, the signal pattern may include various signal patterns (for example, a data signal pattern, etc.) in addition to the ground pattern, the power pattern, etc. These patterns may each include a line pattern, a plane pattern, and / or a pad pattern.

[0034] The second metal layer 122 may be formed using any one of a semi-additive process (SAP), a modified semi-additive process (MSAP), a hole sealing (TT) method, and a subtractive method, but is not limited thereto. The second metal layer 122 may include an electroless plating layer (e.g., a chemical copper plating layer) as a seed layer and an electrolytic plating layer (e.g., an electrolytic copper plating layer) as a plating layer, but is not limited thereto. A sputtering layer may be formed to replace the chemical copper plating layer as the electroless plating layer. If necessary, a copper foil may also be included. The seed layer will be described later.

[0035] The second metal layer 122 may include a plurality of second metal layers 122 disposed on the same layer. The second metal layer 122 may include a plurality of second metal layers 122, and may have the same meaning as the first metal layer 121 may include a plurality of first metal layers 121. Figure 3In order to describe in detail the area of ​​a first metal layer 121 and a second metal layer 122, a first metal layer 121 and a second metal layer 122 are represented as including a one-to-one situation, but the arrangement of the first metal layer 121 and the second metal layer 122 of the printed circuit board according to the example is not limited thereto, and a plurality of first metal layers 121 may be connected through the second metal layer 122, and there may also be portions where the first metal layer 121 and the second metal layer 122 are not connected.

[0036] The first via layer 131 may penetrate at least a portion of the first insulating layer 111 to connect the first metal layer 121 and the second metal layer 122 to each other. The first via layer 131 may have a tapered shape such that the width becomes narrower toward the top of the first insulating layer 111. The width of the upper surface of the first via layer 131 may be narrower than the width of the lower surface of the first metal layer 121. The fact that the first via layer 131 may include a plurality of first via layers 131 may have the same meaning as the fact that the first metal layer 121 may include a plurality of first metal layers 121.

[0037] The first via layer 131 may include micro vias. The micro vias may be filled vias that fill the via holes or conformal vias arranged along the walls of the via holes. The micro vias may be arranged in a stacked and / or staggered manner with other via layers.

[0038] The first via layer 131 may include a metal material. The metal material includes copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof. In detail, the metal material may include copper (Cu), but is not limited thereto. The first via layer 131 may include the metal material included in the first metal layer 121 and the second metal layer 122.

[0039] The first via layer 131 may perform various functions according to the design of the corresponding layer, for example, may include a ground via, a power via, a signal via, etc. In this case, the signal via may include a via for transmitting various signals (for example, a data signal, etc.) in addition to the ground via, the power via, etc.

[0040] The first via layer 131 may be formed by any one of a semi-additive process (SAP), a modified semi-additive process (MSAP), a hole sealing (TT) method, and a subtractive method, but is not limited thereto. Any method that can construct a circuit on a printed circuit board may be used without limitation. The first via layer 131 may include an electroless plating layer (e.g., a chemical copper plating layer) as a seed layer and an electrolytic plating layer (e.g., an electrolytic copper plating layer) as a plating layer, but is not limited thereto. A sputtering layer may be formed to replace the chemical copper plating layer as an electroless plating layer. If necessary, copper foil may also be included. The seed layer will be described later.

[0041] The first metal layer 121, the first via layer 131, and the second metal layer 122 may be formed integrally with each other. Integrally formed may mean that they may be formed simultaneously by one process in one manufacturing step, and may mean that the boundary between the structures may not be clear. For example, the first metal layer 121, the first via layer 131, and the second metal layer 122 may be formed as one body so that no boundary may appear between them. Each of the first metal layer 121, the first via layer 131, and the second metal layer 122 may include a first metal 141 and a second metal 142, and a boundary may appear between the first metal 141 and the second metal 142, but the present disclosure is not limited thereto, and the boundary may not be clear due to post-processing, etc.

[0042] The first metal 141 may be disposed at a boundary between the first metal layer 121 and the first insulating layer 111, may be disposed at a boundary between the first via layer 131 and the first insulating layer 111, and may be disposed at a boundary between the second metal layer 122 and the first insulating layer 111. Each of the first metals 141 may extend along their respective boundaries and may be formed as one body. This is because in the manufacturing stage, the first metal 141 is formed on the inner wall of the first through hole 231 and the inner wall of the second through hole 232, and may be arranged to extend to the lower surface of the first insulating layer 111. The first metal 141 may be used as a seed layer for the second metal 142. The first metal 141 may be formed by performing electroless plating (e.g., chemical copper plating), but is not limited thereto. For example, the electroless plating layer may be formed by sputtering instead of chemical copper plating, and as long as it is a process for forming a seed for plating, it can be used without limitation.

[0043] The second metal 142 may be formed to form the first metal layer 121, the first via layer 131, and the second metal layer 122, and each of the second metals 142 may be formed as one body. This is because during the manufacturing step, the second metal 142 may be formed on the first metal 141 to fill the first through hole 231 and the second through hole 232. The second metal 142 may be provided to contact the first metal 141. The second metal 142 may be formed by performing electrolytic plating (e.g., electrolytic copper plating), but is not limited thereto, and any process that can form a metal layer may be used without limitation.

[0044] As described above, the first metal layer 121, the first via layer 131, and the second metal layer 122 may be integrally formed, and the central axis CA of each of the first metal layer 121, the first via layer 131, and the second metal layer 122 may substantially coincide. The central axis of a particular configuration may refer to the center of a cross section viewed from the top of the particular configuration, and may refer to a virtual line in the stacking direction passing through the center. Alternatively, it may refer to a virtual line in the stacking direction passing through the center of the width of the particular configuration in a cross-sectional view of the printed circuit board cut along the stacking direction. Figure 3As shown in , the central axis of the first metal layer 121, the central axis of the first via layer 131, and the central axis of the second metal layer 122 correspond to a virtual line passing through the center of the width of the structure in a cross-sectional view cut along the stacking direction of the printed circuit board, and the respective central axes (CA) may substantially coincide with each other. The fact that the central axes substantially coincide with each other is a concept including approximate things, and may include, for example, process errors, positional deviations, and measurement errors that occur during the manufacturing process. This means that the central axis of the first metal layer 121, the central axis of the first via layer 131, and the central axis of the second metal layer 122 are substantially the same. This means that the first metal layer 121, the first via layer 131, and the second metal layer 122 can be formed at the same time. For example, because the first metal layer 121, the first via layer 131, and the second metal layer 122 can be formed at the same time, each central axis may substantially coincide with each other. In the case of a general printed circuit board, the via and the pad portion may be formed as one body, but since they are not formed as one body with the pad placed below the via, a so-called eccentricity phenomenon in which the central axis of the pad and the central axis of the via are not aligned may occur. The finer the pad and the via are, the greater the influence of the eccentricity, and even the defect that the pad is not connected to the via may occur. However, since the first metal layer 121, the first via layer 131, and the second metal layer 122 in the printed circuit board according to the example are formed by filling the first through hole 231 penetrating the first insulating layer 111 and the second through hole 232 penetrating the second barrier layer 220 at one time, the eccentricity phenomenon may not occur. Therefore, the printed circuit board according to the example can improve reliability while realizing fine patterns.

[0045] The upper surface of the first insulating layer 111 of the printed circuit board according to the example may be substantially flat. The fact that the upper surface of the first insulating layer 111 may be substantially flat may mean that the printed circuit board according to the example does not separately process the upper surface of the first insulating layer 111. Unlike the case of using a method of removing a portion of the top insulating layer to expose the metal column, the printed circuit board according to the example does not process the first insulating layer 111, which means that the first insulating layer 111 does not have a step, and the upper surface of the first insulating layer 111 may be substantially flat.

[0046] In addition, the surface roughness of the lower surface of the first metal layer 121 may be substantially the same as the surface roughness of the upper surface of the second metal layer 122. When an insulating layer is laminated on a circuit pattern, a surface treatment is generally performed on the upper surface of the circuit pattern to ensure adhesion to the insulating layer. In the printed circuit board according to the example, in the manufacturing stage, the first metal layer 121 and the second metal layer 122 are formed after the first insulating layer 111 is stacked. This is because in the area where the first metal layer 121 and the second metal layer 122 are in contact with the first insulating layer 111, sufficient adhesion can be ensured without performing a surface treatment. For example, since the surface treatment of the metal layer is not performed on the area in contact with the first insulating layer 111, the roughness of the lower surface of the first metal layer 121 and the roughness of the upper surface of the second metal layer 122 may be substantially the same.

[0047] The roughness of the lower surface of the first metal layer 121 can be measured by photographing a cross section cut along the stacking direction of the printed circuit board using a scanning microscope or the like. The roughness can be measured on the cut surface of the first metal layer 121 by a known roughness measurement method (e.g., a center line average calculation method (Ra) or a core point average calculation method (Rz)), but is not limited thereto. Any method that can measure the roughness can be used without limitation. For example, as a non-limiting example, the average position of the lower surface of the first metal layer 121 can be displayed with a virtual line as an average line, and then the average value of the absolute value of the height difference can be measured based on the average line as the surface roughness, or the average value of the height difference between the five points with the highest height and the five points with the lowest height can also be obtained based on the average line as the surface roughness. On the other hand, the roughness measurement method is not limited thereto, and when the measurement method for measuring the roughness of the lower surface of the first metal layer 121 and the measurement method for measuring the roughness of the upper surface of the second metal layer 122 are the same, a more accurate comparison can be made.

[0048] Since the printed circuit board according to the example forms the first metal layer 121 and the second metal layer 122 after forming the first insulating layer 111, each of the first metal layer 121 and the second metal layer 122 may not be buried in the first insulating layer 111. For example, the first metal layer 121 and the second metal layer 122 may each have a structure protruding from the first insulating layer 111, and the first insulating layer 111 may not cover the side surfaces of the first metal layer 121 and the second metal layer 122.

[0049] The printed circuit board according to the example may also include: a second insulating layer 112, which is arranged under the first insulating layer 111 and buries the second metal layer 122; a third metal layer 123, which is arranged on the second insulating layer 112 and / or in the second insulating layer 112; and a second via layer 132, which penetrates at least a portion of the second insulating layer 112 to connect the second metal layer 122 to the third metal layer 123.

[0050] The second insulating layer 112, the third metal layer 123, and the second via layer 132 may correspond to the first insulating layer 111, the second metal layer 122, and the first via layer 131, respectively, and may correspond to a configuration that may be included as a general configuration of a printed circuit board. Descriptions related thereto may be repeated with descriptions of the first insulating layer 111, the second metal layer 122, and the first via layer 131, and thus the repeated descriptions are omitted. In addition, the lower surface from which the second via layer 132 of the second metal layer 122 extends may be spaced apart from the first metal 141.

[0051] The solder resist layer 150 is disposed on the second insulating layer 112 and on the outermost surface of the printed circuit board to protect the printed circuit board from external influences. The solder resist layer 150 can use a known solder resist, and the solder resist layer 150 may include an insulating resin and a filler dispersed in the insulating resin, but may not include glass fiber. The insulating resin may be a photosensitive insulating resin, and the filler may be an inorganic filler and / or an organic filler, but is not limited thereto. If necessary, other polymer materials may be used. The solder resist layer 150 may have an opening, and at least a portion of the third metal layer 123 may be exposed through the opening. The third metal layer 123 exposed through the opening may be connected to a mainboard or other printed circuit boards, and may also be connected to other devices such as semiconductor chips.

[0052] On the other hand, the printed circuit board according to the example is not limited to Figure 3 The configuration shown in , and may also include a general configuration of a printed circuit board, in detail, may include additional configurations that can be used by anyone having ordinary knowledge in the relevant technical field.

[0053] Method for manufacturing printed circuit board Figures 4 to 6 is a cross-sectional view schematically illustrating a method of manufacturing a printed circuit board according to an example.

[0054] Reference Figure 4 , a method of manufacturing a printed circuit board according to an example may include: forming a first barrier layer 210 on a carrier substrate 200 ; forming a second barrier layer 220 on the first barrier layer 210 ; and forming a first insulating layer 111 on the second barrier layer 220 .

[0055] The carrier substrate 200 may include a core 201 and a copper foil 202 formed on one or both sides thereof. The core 201 is used to support the insulating layer and / or the circuit layer when the insulating layer and / or the circuit layer are formed, and may be made of an insulating material or a metal material. The copper foil 202 may be formed of copper, but is not limited thereto. The above-mentioned carrier substrate 200 is an example of a case, and the carrier substrate 200 may be a carrier substrate used by anyone having ordinary knowledge in the relevant technical field. Any object used as a supporting substrate and which may be separated or removed later may be used in the present disclosure without any particular limitation.

[0056] In a process of processing the second barrier layer 220 to be described later, the first barrier layer 210 may be used as an etching stopper for the second barrier layer 220. The first barrier layer 210 may include a metal or an oxide. As a metal material, silver (Ag), aluminum (Al), tin (Sn), gold (Au), lead (Pb), titanium (Ti), or an alloy thereof may be used, and a stainless steel (SUS) metal may be used. The oxide may include aluminum oxide (Al 2 O 3 ), silicon dioxide (SiO 2 ) and the like. If the first barrier layer 210 includes an oxide, the first barrier layer 210 may be formed in the form of a thin film. In detail, the first barrier layer 210 may include silver (Ag) or aluminum oxide (Al 2 O 3 ), but is not limited thereto. Any material different from the copper foil 202 of the carrier substrate 200 and / or the second barrier layer 220 formed later may be used as the material of the first barrier layer 210, and in the operation of processing the second barrier layer 220, the first barrier layer 210 may be used without particular limitation as long as the first barrier layer 210 can perform a stopper function to prevent the second barrier layer 220 from being processed.

[0057] The second barrier layer 220 is a region where the second through hole 232 will be formed in a step to be described later, and may correspond to a layer where the first metal layer 121 will be formed later. The second barrier layer 220 may include a metal material. The metal material may be nickel (Ni), aluminum (Al), tin (Sn), gold (Au), lead (Pb), titanium (Ti), or an alloy thereof. In detail, the second barrier layer 220 may include nickel (Ni), but is not limited thereto. Since the second barrier layer 220 should be separated from the first metal layer 121 later, any material different from the first metal layer 121 may be used as a material of the second barrier layer 220. Any material that is easily separated from the first metal layer 121 may be used without particular limitation.

[0058] Since the description of the first insulating layer 111 overlaps with that described above in the printed circuit board, the description thereof is omitted.

[0059] Reference Figure 5 According to the example, the method of manufacturing a printed circuit board may also include: forming a first through hole 231 penetrating the first insulating layer 111; forming a second through hole 232 penetrating the second barrier layer 220; forming a first metal layer 121 by filling the second through hole 232; forming a first via layer 131 by filling the first through hole 231; and forming a second metal layer 122 on the first insulating layer 111.

[0060] The operation of forming the first through hole 231 penetrating the first insulating layer 111 may be performed by laser drilling, mechanical drilling, etc., but is not limited thereto. Any method that can penetrate the insulating layer may be used without limitation. On the other hand, when laser drilling is performed, CO may be used. 2 Laser or YAG (yttrium aluminum garnet) laser, but the present disclosure is not limited thereto. The first through hole 231 may be formed to be as thick as the first insulating layer 111 to penetrate the first insulating layer 111 between the upper surface and the lower surface of the first insulating layer 111. When the first through hole 231 is formed by drilling, the first through hole 231 may have a tapered shape. In detail, the first through hole 231 may have a tapered shape so that the width at the lower surface of the second barrier layer 220 is the narrowest. Therefore, in the printed circuit board according to the example, the first via layer 131 may have a tapered shape so that the first via layer 131 has the narrowest width at the top of the first insulating layer 111 and has the widest width at the bottom of the first insulating layer 111.

[0061] The operation of forming the second through hole 232 penetrating the second barrier layer 220 may be performed by an etching process, but is not limited thereto. Any method that allows penetration by removing a portion of the metal material of the second barrier layer 220 may be used without limitation. As an etching process, wet etching or dry etching may be used. The second through hole 232 may be formed to be as thick as the second barrier layer 220 to penetrate the second barrier layer 220 between the upper surface and the lower surface of the second barrier layer 220. When the second through hole 232 is formed by wet etching, the side of the second through hole 232 may have a curved shape, and the width of the upper surface of the second through hole 232 may be formed to be narrower than the width of the lower surface of the second through hole 232. This may occur according to the degree of penetration of the etching solution in the wet etching process. Because the first barrier layer 210 exists even if the second through hole 232 completely penetrates the second barrier layer 220, the first metal layer 121 formed later may have a substantially flat upper surface. Since the first through hole 231 is formed first and then the second through hole 232 is formed, and the second through hole 232 is formed by wet etching to achieve isotropy, the central axis of the first through hole 231 and the central axis of the second through hole 232 can basically coincide, and the possibility of eccentricity errors occurring in the first metal layer 121, the first via layer 131 and the second metal layer 122 can be reduced.

[0062] The operation of forming the first metal layer 121, the first via layer 131, and the second metal layer 122 may be performed by forming the first metal 141 along the inner wall of the first through hole 231 and the inner wall of the second through hole 232 and the lower surface of the first insulating layer 111, and forming the second metal 142 on the first metal 141, and then removing a portion of the first metal 141 and a portion of the second metal 142. Since the operation of forming the first metal 141 and the operation of forming the second metal 142 may be performed in one step, the first metal layer 121, the first via layer 131, and the second metal layer 122 may be formed as one body.

[0063] The operation of forming the first metal 141 may be performed by electroless plating, and the first metal 141 may be used as a seed for forming the second metal 142. The operation of forming the second metal 142 may be performed by electrolytic plating using the first metal 141 as a seed. Thereafter, the operation of forming the first metal 141 and the second metal 142 may be completed by removing the remaining portions of the first metal 141 and the second metal 142 except for necessary regions.

[0064] Reference Figure 6 , the method of manufacturing a printed circuit board according to an example may further include: forming a second insulating layer 112 on the first insulating layer 111 to bury the second metal layer 122; forming a second via layer 132 penetrating at least a portion of the second insulating layer 112; forming a third metal layer 123 on the second insulating layer 112; and forming a solder resist layer 150. After forming the first metal layer 121, the first via layer 131, and the second metal layer 122, the printed circuit board may be configured to further include other components, and the number of layers of the second insulating layer 112, the third metal layer 123, and the second via layer 132 may be designed without limitation.

[0065] The method of manufacturing a printed circuit board according to an example may further include removing the carrier substrate 200 , the first barrier layer 210 , and the second barrier layer 220 .

[0066] In the operation of removing the carrier substrate 200, the copper foil 202 may be removed after removing the core 201, or the core 201 and the copper foil 202 may be removed simultaneously. The operation of removing the carrier substrate 200 may be performed using a known process for carrier separation without limitation.

[0067] The operation of removing the first barrier layer 210 may be performed by etching, but is not limited thereto. The operation of removing the first barrier layer 210 may be performed by different processes according to the constituent material of the first barrier layer 210, and any process that can remove the constituent material of the first barrier layer 210 may be used without limitation. Different conditions may be implemented according to the material of the first barrier layer 210. Since the second through hole 232 penetrating the second barrier layer 220 penetrates the second barrier layer 220 between the upper surface and the lower surface of the second barrier layer 220, and the first metal layer 121 is formed by filling the second through hole 232, when the operation of removing the first barrier layer 210 is performed, the upper surface of the first metal layer 121 may be exposed to the outside.

[0068] The operation of removing the second barrier layer 220 may be performed by etching. Since the constituent materials of the first barrier layer 210 and the second barrier layer 220 are different, the removal of the second barrier layer 220 may be performed under conditions different from the removal step of the first barrier layer 210. At this time, since the second barrier layer 220 includes a material different from the first metal layer 121, and the first metal layer 121 remains even if the operation of removing the second barrier layer 220 is performed, a structure in which the first metal layer 121 protrudes from the first insulating layer 111 may be completed.

[0069] Figures 4 to 6 It is shown as being constructed only on the lower surface of the carrier substrate 200. The same process may be performed on the upper surface of the carrier substrate 200 to manufacture a printed circuit board having a symmetrical structure. In this case, two printed circuit boards having the same structure may be manufactured by one carrier substrate 200.

[0070] Furthermore, as described above in the description of the printed circuit board according to the example, the general configuration of the printed circuit board may also be included, and additions or omissions may be freely made if the technical meaning of the present disclosure is not changed.

[0071] As described above, according to the embodiment, a printed circuit board for mounting electronic components, semiconductor chips, etc., which can realize bumps with a fine pitch, can be provided.

[0072] Furthermore, a printed circuit board can be provided which can realize protruding bumps without etching an insulating layer.

[0073] Furthermore, a printed circuit board having improved reliability can be provided.

[0074] In the present disclosure, the shape on the cross section may refer to the cross-sectional shape when the object is cut vertically, or the shape when the object is viewed from a side view. In addition, the shape on the plane may refer to the shape when the object is cut horizontally, or the plane shape when the object is viewed from a top view or a bottom view.

[0075] In the present disclosure, for convenience, "upper side", "top", "upper surface", etc. are used to refer to the direction toward the surface on which the electronic component can be mounted based on the cross section of the drawing, and "lower side", "bottom", "lower surface", etc. are used in the opposite direction. However, this direction is defined for convenience of explanation, and of course, the scope of the patent claims is not particularly limited by the description of this direction.

[0076] In the present disclosure, the meaning of connection is a concept including not only direct connection but also indirect connection through an adhesive layer or the like. In addition, the meaning of electrical connection is a concept including both the case of physical connection and the case of no physical connection. In addition, expressions such as first, second, etc. are used to distinguish one component from another component and do not limit the order and / or importance of the components. In some cases, without departing from the scope of the rights, a first component may be named a second component, and similarly, a second component may be named a first component.

[0077] The expression "example" used in this disclosure does not mean the same example, and is provided to emphasize and explain different unique features. However, the examples presented above do not exclude implementation in combination with features of other examples. For example, even if the content described in an example is not described in another example, it can be understood as an explanation related to another example unless there is an opposite or contradictory explanation in the other example.

[0078] The terms used in the present disclosure are only used to describe examples and are not intended to limit the present disclosure.At this time, unless the context clearly indicates otherwise, a singular expression includes a plural expression.

[0079] While example embodiments have been shown and described above, it will be readily apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the present disclosure as defined by the appended claims.

Claims

1. A printed circuit board, comprising: a first insulating layer; a first metal layer disposed on an upper side of the first insulating layer; a second metal layer disposed on a lower side of the first insulating layer; as well as a first via layer penetrating at least a portion of the first insulating layer to connect the first metal layer to the second metal layer, wherein the first via layer has a tapered shape in which the width becomes narrower toward the top of the first insulating layer, and An upper surface of the first metal layer is substantially flat, and a side surface of the first metal layer is a curved surface.

2. The printed circuit board according to claim 1, wherein: The side surface of the first metal layer is the curved surface so that an upper width of the first metal layer is narrowest and a lower width of the first metal layer is widest.

3. The printed circuit board according to claim 1, wherein: The first metal layer includes a first metal arranged at a boundary between the first metal layer and the first insulating layer, the first via layer includes a first metal arranged at a boundary between the first via layer and the first insulating layer, and the second metal layer includes a first metal arranged at a boundary between the second metal layer and the first insulating layer.

4. The printed circuit board according to claim 3, wherein: The first metal extends along a boundary between the first metal layer and the first insulating layer, a boundary between the first via layer and the first insulating layer, and a boundary between the second metal layer and the first insulating layer and is integrally formed.

5. The printed circuit board according to claim 4, wherein: The first metal layer, the first via layer, and the second metal layer each further include a second metal disposed on the first metal to form the first metal layer, the first via layer, and the second metal layer, and the first metal layer, the first via layer, and the second metal layer are integrally formed.

6. The printed circuit board according to claim 5, wherein: The central axes of the first metal layer, the first via layer, and the second metal layer substantially coincide with each other.

7. The printed circuit board according to claim 1, wherein: The first metal layer includes a plurality of patterns, Wherein, the heights of the plurality of patterns are substantially the same as each other.

8. The printed circuit board according to claim 1, wherein: A width of a lower surface of the first metal layer is wider than a width of an upper surface of the first via layer.

9. The printed circuit board according to claim 1, wherein: The upper surface of the first insulating layer is substantially flat, and The roughness of the lower surface of the first metal layer is substantially the same as the roughness of the upper surface of the second metal layer.

10. The printed circuit board according to any one of claims 1 to 9, further comprising: a second insulating layer, disposed on a lower surface of the first insulating layer and burying the second metal layer; a third metal layer, disposed on the second insulating layer and / or disposed in the second insulating layer; as well as The second via layer penetrates at least a portion of the second insulating layer.

11. A method for manufacturing a printed circuit board, the method comprising: forming a first barrier layer on a carrier substrate; forming a second barrier layer on the first barrier layer; forming a first insulating layer on the second barrier layer; forming a first through hole penetrating the first insulating layer; forming a second through hole penetrating the second barrier layer; forming a first metal layer by filling the second through hole; forming a first via layer by filling the first through hole; forming a second metal layer on the first insulating layer; as well as The carrier substrate, the first barrier layer, and the second barrier layer are removed.

12. The method according to claim 11, wherein: The operation of forming the second through hole penetrating the second barrier layer is performed by penetrating the second barrier layer between an upper surface and a lower surface of the second barrier layer.

13. The method according to claim 11, wherein: The operations of forming the first metal layer, the first via layer, and the second metal layer are performed by forming a first metal along inner walls of the first and second via holes and a lower surface of the first insulating layer and forming a second metal on the first metal.

14. The method according to claim 13, wherein: The operation of forming the first metal is performed by electroless plating, and The operation of forming the second metal is performed by electrolytic plating.

15. The method according to claim 14, wherein: The first metal layer, the first via layer and the second metal layer are integrated.

16. The method according to any one of claims 11 to 15, wherein: The operation of forming the first through hole is performed by a drilling process, and The operation of forming the second through hole is performed through an etching process.

17. A printed circuit board, comprising: a first insulating layer; a first metal layer disposed on an upper side of the first insulating layer; a second metal layer disposed on a lower side of the first insulating layer; as well as a first via layer penetrating at least a portion of the first insulating layer to connect the first metal layer to the second metal layer, wherein the first via layer has a tapered shape with a width becoming narrower toward the first metal layer, and The first metal layer, the first via layer, and the second metal layer each include a first metal disposed at a corresponding boundary with the first insulating layer and a second metal disposed on the first metal.

18. The printed circuit board according to claim 17, wherein: A width of a lower surface of the first metal layer is wider than a width of an upper surface of the first via layer.

19. The printed circuit board according to claim 17 or 18, further comprising: a second insulating layer, disposed on a lower surface of the first insulating layer and burying the second metal layer; a third metal layer, disposed on the second insulating layer and / or disposed in the second insulating layer; as well as The second via layer penetrates at least a portion of the second insulating layer.

20. The printed circuit board according to claim 19, wherein A lower surface of the second metal layer is spaced apart from the first metal, and the second via layer extends from the lower surface of the second metal layer.

Images