Semiconductor device and method of manufacturing the same

Abstract

The application discloses a semiconductor device and a manufacturing method thereof. The semiconductor device comprises a substrate, a plurality of first lower electrodes on the substrate, the plurality of first lower electrodes arranged in an array in a first direction, a second direction and a third direction which are not perpendicular to each other, and an outer contour of each of the first lower electrodes being circular. A plurality of second lower electrodes are on the substrate, and an outer contour of the second lower electrode comprises a main body and three protruding parts. The main body is circular, and the three protruding parts are circular arcs which extend outward from the center of the main body along a fourth direction, a fifth direction and a sixth direction respectively.

Description

Technical Field

[0001] This invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor memory device and a method for manufacturing the same. Background Technology

[0002] With the trend towards miniaturization in various electronic products, the design of semiconductor devices must also meet the requirements of high integration and high density. For dynamic random access memory (DRAM) with a recessed gate structure, it can achieve a longer carrier channel length within the same semiconductor substrate, reducing leakage current caused by capacitor structures. Therefore, under the current mainstream development trend, it has gradually replaced DRAM with only planar gate structures. Generally, DRAM with a recessed gate structure consists of a large number of memory cells clustered into an array area to store information. Each memory cell can be composed of a transistor assembly and a capacitor assembly connected in series to receive voltage information from the word line (WL) and bit line (BL). Due to product demands, the density of memory cells in the array area must continue to increase, resulting in increasing difficulty and complexity in related manufacturing processes and designs. Therefore, existing technologies or structures need further improvement to effectively enhance the performance and reliability of related memory devices. Summary of the Invention

[0003] The present invention provides a semiconductor device including a substrate, a plurality of first lower electrodes located on the substrate, the plurality of first lower electrodes being arranged in an array in a first direction, a second direction and a third direction that are not perpendicular to each other, the outer contour of each first lower electrode being circular, and a plurality of second lower electrodes located on the substrate, the outer contour of each second lower electrode including a body and three protrusions, wherein the body is circular, and the three protrusions are arc-shaped, extending outward from the center of the body along a fourth direction, a fifth direction and a sixth direction, respectively.

[0004] The present invention also provides a semiconductor device, including a substrate, a plurality of first lower electrodes and a second lower electrode located on the substrate, the plurality of first lower electrodes being arranged in an array adjacent to each other, wherein, in a cross-sectional view, each of the first lower electrodes presents an I-shaped profile and each of the second lower electrodes presents a U-shaped profile.

[0005] The present invention also provides a method for fabricating a semiconductor device, comprising the following steps: providing a substrate, forming a support stack layer on the substrate, forming a mask layer on the support stack layer, performing a first patterning step to form a plurality of first grooves in the mask layer, performing a second patterning step to form a plurality of second grooves in the mask layer, wherein, from a top view, each of the second grooves overlaps with a plurality of the first grooves, and the overlapping portion of each of the first grooves and each of the second grooves is defined as a plurality of third grooves, performing an etching step, using the patterned mask layer as a mask, to form a plurality of first capacitor vias and a plurality of second capacitor vias in the support stack layer.

[0006] The present invention is characterized in that, as viewed from the top view, the second capacitor via OP2 is located within the second region A2, and the second lower electrode BE2 of the second capacitor via OP2 surrounds the outer periphery of the first lower electrode BE1 of the plurality of first capacitor vias OP1, and the shape of the second lower electrode BE2 is different from that of the first lower electrode BE1. Because the second region A2 is adjacent to a blank area (i.e., the third region A3) where no components are formed during the manufacturing process, the component density difference between these two regions is significant, making them susceptible to damage to the capacitor structure within the second region A2 due to load effects. The present invention, within the second region A2, fabricates a second capacitor via OP2 with a larger area and a unique shape by overlapping the first groove R1 and the second groove R2. Therefore, compared to the plurality of first capacitor vias OP1 located in the first region A1, the coverage area of ​​the second capacitor via OP2 is larger, and the second capacitor via OP2 is composed of three first capacitor vias OP1 and a central via, resulting in a stable structure that is less susceptible to damage due to load effects. Therefore, the present invention helps to improve the quality of capacitor structures located in edge regions. Attached Figure Description

[0007] The accompanying drawings provide a more detailed understanding of embodiments of the invention and are incorporated herein by reference as a whole. These drawings and descriptions are used to illustrate the principles of some embodiments. It should be noted that all drawings are schematic diagrams, and for illustrative and drafting purposes, relative sizes and proportions have been adjusted. The same symbols represent corresponding or similar features in different embodiments.

[0008] Figures 1 to 7 A schematic diagram illustrating the steps of a method for fabricating a semiconductor device according to a first embodiment of the present invention is shown, wherein... Figures 1 to 7 The upper half of the image is a top view of the semiconductor device, while the lower half is a cross-sectional view of the corresponding semiconductor device.

[0009] Figure 8 Draw Figure 6 A partially enlarged schematic diagram of the steps in the process;

[0010] Figure 9 and Figure 10 Cross-sectional structural schematic diagrams of semiconductor devices according to two other different embodiments of the present invention are shown respectively.

[0011] The reference numerals in the attached figures are explained as follows:

[0012] 100: Substrate

[0013] 110: Support stacking layers

[0014] 111: First Support Layer

[0015] 112: Second support layer

[0016] 113: Third Support Layer

[0017] 114: Fourth Support Layer

[0018] 115: Fifth Support Layer

[0019] 122: Polycrystalline silicon layer

[0020] 124: Oxide layer

[0021] 126: Bottom anti-reflective coating

[0022] 128: Photoresist layer

[0023] 130: Capacitor dielectric layer

[0024] 140: Prominent part

[0025] 142: Main Body

[0026] 200: Range

[0027] 210: Depression (gap)

[0028] 211: Fully Filled Structure

[0029] 212: Partially filled structure

[0030] A1: First Area

[0031] A2: Second Area

[0032] A3: Third Area

[0033] AE1, AE2, AE3, AE4, AE5, AE6, AE7, AE8, AE9, AE10, AE11, AE12: Curved boundary

[0034] BE1: First lower electrode

[0035] BE2: Second lower electrode

[0036] C1: First capacitor structure

[0037] C2: Second capacitor structure

[0038] D1: First Direction

[0039] D2: Second Direction

[0040] D3: Third direction

[0041] D4: Fourth Direction

[0042] D5: Fifth Direction

[0043] D6: Sixth Direction

[0044] O: Center point

[0045] OP1: First capacitor via

[0046] OP2: Second capacitor via

[0047] P: First spacing

[0048] R1: First groove

[0049] R2: Second groove

[0050] R3: Third Groove

[0051] SOP1: First support opening

[0052] SOP2: Second support opening

[0053] SNP: Contact Pad (Storage Node Pad)

[0054] SNISO: Insulating sidewall

[0055] TE: Upper electrode layer

[0056] W1: First dimension

[0057] W2: Second size

[0058] W3: Third Size

[0059] W4: Fourth size Detailed Implementation

[0060] Although this document discusses specific configurations and arrangements, it should be understood that this is for illustrative purposes only. Those skilled in the art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of this disclosure. It will be apparent to those skilled in the art that this disclosure can also be used in a variety of other applications.

[0061] Please refer to Figures 1 to 7 The illustration shows the steps of a method for fabricating a semiconductor device according to the first embodiment of the present invention. Figures 1 to 7 The upper half of the image is a top view of the semiconductor device, while the lower half is a corresponding cross-sectional view. First, Figure 1 The upper half is a top view of the semiconductor device. Figure 1 The lower half is a cross-sectional view obtained along section line I-I'. For example... Figure 1 As shown, a substrate 100 is provided, such as a silicon substrate, a silicon-containing substrate (e.g., SiC, SiGe, etc.), or a silicon-on-insulator (SOI) substrate, or other suitable material layers. At least one shallow trench isolation (STI, not shown) is formed within the substrate 100, and multiple active areas (AA, not shown) are defined within the substrate 100. Furthermore, multiple gates, such as buried gates, can be formed within the substrate 100, where the buried gates can serve as buried word lines (BWL, not shown) of a semiconductor device. Since these structures for forming active areas, shallow trench isolation, and buried gates are well-known in the art, they will not be described in detail here. Figure 1 In this context, substrate 100 represents the structural layer containing the aforementioned elements.

[0062] Additionally, multiple bit lines (not shown, BL) and multiple storage node pads (SNPs) are formed on the substrate 100. Although the bit lines are not specifically shown in the accompanying drawings of this embodiment, those skilled in the art should easily understand that each bit line extends parallel to each other and is electrically isolated from the buried gate located in the substrate 100 by an insulating layer (not shown, for example, containing a silicon oxide-silicon nitride-silicon oxide structure) covering the top surface of the substrate 100, and is electrically connected to the substrate 100 by bit line contacts (not shown, BLC) formed correspondingly below each bit line extending into the active region.

[0063] Adjacent storage node pads (SNPs) are isolated from each other by storage node contact isolation (SCISO) located directly above each buried gate. Thus, the storage node pads (SNPs) are electrically connected to the substrate 100 to receive and transmit voltage signals from the substrate 100 (such as transistor components within the substrate 100). In one embodiment, the storage node pads (SNPs) may be made of low-resistivity metals such as aluminum (Al), titanium (Ti), copper (Cu), or tungsten (W), but are not limited thereto.

[0064] For example Figure 1 As shown, a support stack layer 110 continues to be formed on the substrate 100. In detail, the support stack layer 110 includes, for example, alternating layers of multiple materials. In this embodiment, the support stack layer 110 includes, for example, a first support layer 111 (e.g., silicon nitride or silicon carbonitride), a second support layer 112 (e.g., borosilicate glass (BPSG)), a third support layer 113 (e.g., silicon nitride or silicon carbonitride), a fourth support layer 114 (e.g., silicon oxide), and a fifth support layer 115 (e.g., silicon nitride or silicon carbonitride) stacked sequentially from bottom to top, but is not limited thereto. Preferably, the second support layer 112 and the fourth support layer 114 may have a relatively large thickness, for example, approximately 5 to 10 times the thickness of the nitride layer (e.g., including the first support layer 111, the third support layer 113, or the fifth support layer 115). Thus, the overall thickness of the support layer structure 110 reaches approximately 1600 to 2000 angstroms, but is not limited thereto. Those skilled in the art will understand that the specific number of oxide layers and nitride layers stacked is not limited to this. Figure 1 The number of layers shown is for reference only and can be adjusted to other numbers based on actual needs.

[0065] like Figure 1 As shown, a polysilicon layer 122 serving as a mask layer and an oxide layer 124 are also formed on the support stack layer 110. Among them, in Figure 1 In this process, the oxide layer 124 has undergone a patterning step (e.g., a photolithography process, but not limited to this) to form multiple first grooves R1 located within the oxide layer 124. See also... Figure 1 The upper half of the top view shows a plurality of first grooves R1 arranged in an array on a plane. More specifically, the plurality of first grooves R1 are arranged along a first direction D1, a second direction D2, and a third direction D3, respectively. The first direction D1, the second direction D2, and the third direction D3 are neither parallel nor perpendicular to each other. Preferably, Figure 1The four adjacent first grooves R1 can be arranged in a rhombus shape. That is, the distance from any first groove R1 along the second direction D2 to the adjacent first groove R1 can be equal to the distance from the first groove R1 along the third direction D3 to another adjacent first groove R1, but the present invention is not limited thereto.

[0066] For ease of explanation, let's first... Figure 1 The diagram defines a first region A1, a second region A2, and a third region A3. A first groove R1 is located within both the first and second regions A1 and A2, while the third region A3 does not contain any first groove R1. The second region A2 is located at the edge of the first region A1 and surrounds or encloses it, while the third region A3, in turn, surrounds or encloses the second region A2. In other words, the area near the edge of the array formed by the first grooves R1 is defined as the second region A2, and the area outside the second region A2 that does not contain any first grooves R1 is defined as the third region A3. In this embodiment, the width of the second region A2 approximately includes one to two first grooves R1, but the invention is not limited to this.

[0067] Figure 2 The upper half is a top view of the semiconductor device. Figure 2 The lower half is a cross-sectional view obtained along section line II-II'. For example... Figure 2 As shown, a bottom anti-reflective coating 126 and a photoresist layer 128 are formed covering the polysilicon layer 122 and the patterned oxide layer 124. Then, a photolithography process is performed to pattern the photoresist layer 128, and a plurality of second grooves R2 are formed within the photoresist layer 128. See reference... Figure 2 The top view shows that the second groove R2 is located within the second region A2. The shape of the second groove R2 can be rectangular, circular, polygonal, or other shapes, and the present invention is not limited thereto. Preferably, in this embodiment, the shape of the second groove R2 is circular, because according to the applicant's experiments, the structure of the circular second groove R2 is more stable, which is beneficial to improving the structural strength of the subsequently formed capacitor structure. It is worth noting that, from Figure 2 From the top view, each second groove R2 overlaps with multiple first grooves R1. More specifically, each second groove R2 is located between three adjacent first grooves R1 and overlaps with the three first grooves R1.

[0068] Figure 3 The upper half is a top view of the semiconductor device. Figure 3 The lower half is a cross-sectional view obtained along section line III-III'. (See image below.) Figure 3As shown, the etching step continues, transferring the pattern of the second groove R2 to the underlying material layer. Specifically, the pattern of the second groove R2 is transferred to the underlying oxide layer 124, and excess bottom anti-reflective coating 126 and photoresist layer 128 are removed. As mentioned above, since part of the first groove R1 overlaps with the second groove R2, the overlapping portion of the first groove R1 and the second groove R2 is defined as the third groove R3. That is, at this time, the oxide layer 124 contains multiple first grooves R1 and multiple third grooves R3. From the top view, the third groove R3 is located in the second region A2, that is, at the outer edge of the array formed by the first grooves R1. In addition, the third groove R3 has a special shape, wherein three arc-shaped protrusions extend outward from the center point O of the third groove R3 in three different directions D4, D5, and D6 respectively. Here, directions D4, D5, and D6 are different from the first direction D1, the second direction D2, and the third direction D3 mentioned above. Specifically, the directions from the center point of the second groove R2 toward the center points of the three overlapping first grooves R1 are defined as directions D4, D5, and D6, respectively, but are not limited thereto.

[0069] Figure 4 The upper half is a top view of the semiconductor device. Figure 4 The lower half is a cross-sectional view obtained along section line IV-IV'. For example... Figure 4 As shown, the pattern transfer step continues, such as an etching step, using oxide layer 124 as a mask to transfer the patterns of the first groove R1 and the third groove R3 to the underlying support stack layer 110. For example, using a dry etching process, the fifth support layer 115, the fourth support layer 114, the third support layer 113, the second support layer 112, and the first support layer 111 are sequentially etched through, forming multiple first capacitor vias OP1 and multiple second capacitor vias OP2 within the support stack layer 110. Each first capacitor via OP1 corresponds to the position of the first groove R1, and each second capacitor via OP2 corresponds to the position of the third groove R3. In addition, the bottom of each first capacitor via OP1 exposes one underlying memory node pad SNP, and the area of ​​each second capacitor via OP2 is larger than the area of ​​the first capacitor via OP1, thus the bottom of each second capacitor via OP2 exposes multiple (two or more) underlying memory node pads SNP.

[0070] The positions of the first capacitor via OP1 and the second capacitor via OP2 formed here will form multiple capacitor structures in subsequent steps. The first capacitor vias OP1 are arranged in an array, while the second capacitor via OP2 is located around the array of the first capacitor vias OP1. The shape of the second capacitor via OP2 is the same as the third groove R3 described above, but the second capacitor via OP2 has a larger area than the first capacitor via OP1, thus making the capacitor structure subsequently formed within the second capacitor via OP2 more stable. In this embodiment, the second capacitor via OP2 can protect the first capacitor via OP1 located near its edge.

[0071] Figure 5 The upper half is a top view of the semiconductor device. Figure 5 The lower half is a cross-sectional view obtained along the section line V-V'. For example... Figure 5 As shown, a deposition and etch-back fabrication process is performed to form multiple lower electrodes BE1 within a first capacitor via OP1, and a second lower electrode BE2 within a second capacitor via OP2. In one embodiment, the fabrication process of the first lower electrode BE1 and the second lower electrode BE2 includes, but is not limited to, the following steps: First, an electrode material layer is formed in the first capacitor via OP1 and the second capacitor via OP2, such as a low-resistivity metal material including titanium nitride, aluminum, titanium, copper, or tungsten, preferably including titanium nitride. The electrode material layer may fill each of the first capacitor via OP1 and cover the inner surface and bottom surface of the second capacitor via OP2, but not fill the second capacitor via OP2. Then, the excess electrode material layer located outside the first capacitor via OP1 and the second capacitor via OP2 is removed, forming a first lower electrode BE1 with an I-shaped cross-section in the first capacitor via OP1, and a second lower electrode BE2 with a U-shaped cross-section in the second capacitor via OP2. It is understood that the first lower electrode BE1 and the second lower electrode BE2 have the same material (both are made of electrode material layers). The bottom of the second lower electrode BE2 spans at least two storage node contact pads SNP.

[0072] Additionally, as seen in the top view, as Figure 5 As shown in the upper part, since the first lower electrode BE1 fills all the first capacitor vias OP1, and the first capacitor vias OP1 have a circular outline, the first lower electrode BE1 also has a circular outline. Furthermore, since the second lower electrode BE2 does not fill the second capacitor via OP2, but rather covers the side surface of the second capacitor via OP2, from the top view, a portion of the second capacitor via OP2 remains unfilled by the second lower electrode BE2. The second lower electrode BE2 is shaped to fit within the inner surface of the second capacitor via OP2, and its outer boundary has three arc-shaped protrusions, corresponding to the three apexes of a triangle (see reference for details). Figure 5 (The shape shown).

[0073] Figure 6 The upper half is a top view of the semiconductor device. Figure 6 The lower half is a cross-sectional view obtained along section line VI-VI'. For example... Figure 6 As shown, a wet etching process can then be performed, for example, by introducing an etchant such as tetramethylammonium hydroxide (TMAH) to remove the remaining portion of the fourth support layer 114 and the second support material layer 112. At this point, the first support material layer 111, the third support material layer 113, and the fifth support material layer 115 remain in the support stack layer 110, located between each of the first lower electrode BE1 and / or the second lower electrode BE2, which can serve as a structure to stabilize the lower electrode.

[0074] Furthermore, to further enhance the support effect between the first lower electrode BE1 and / or the second lower electrode BE2, an etching process can be performed after the aforementioned wet etching process to form support openings in the remaining support material layer of the support stack 110 using a mask (not shown). These support openings may include openings between the first lower electrode BE1 and adjacent first lower electrodes BE1, defined as first support openings SOP1, and openings between the first lower electrode BE1 and the second lower electrode BE2, defined as second support openings SOP2. In this embodiment, the shapes of the first support openings SOP1 and the second support openings SOP2 are different; preferably, the area of ​​the first support opening SOP1 is larger than the area of ​​the second support opening SOP2. Furthermore, the first support opening SOP1 is circular or polygonal, and its outer contour extends through multiple adjacent first lower electrodes BE1, partially exposing the sidewalls of the adjacent first lower electrodes BE1. The outer contour of the second support opening SOP2 extends through one first lower electrode BE1 and one adjacent second lower electrode BE2, partially exposing the sidewalls of both first lower electrodes BE1 and second lower electrodes BE2. In subsequent steps, the first support opening SOP1 and the second support opening SOP2 will be filled into the capacitor dielectric layer and the upper electrode layer, serving as a support structure between the electrodes, thus further stabilizing the structure.

[0075] Figure 7 The upper half is a top view of the semiconductor device. Figure 7 The lower half is a cross-sectional view obtained along section line VII-VII'. For example... Figure 7As shown, at least one deposition process is performed to sequentially form a capacitor dielectric layer 130 and an upper electrode layer TE. The capacitor dielectric layer 130 conformally covers the exposed surfaces of the first lower electrode BE1 and the second lower electrode BE2, the fifth support layer 115, and the first support opening SOP1 and the second support opening SOP2. The upper electrode layer TE covers the capacitor dielectric layer 130 and fills the remaining space between the second lower electrode BE2, as well as the first support opening SOP1 and the second support opening SOP2. Parts of the capacitor dielectric layer 130 and the upper electrode layer TE may further be formed in the space between the first support layer 111 and the third support layer 113, and in the space between the third support layer 1163 and the fifth support layer 115, to increase the contact area and improve the capacitance value. In one embodiment, the capacitor dielectric layer 130 includes, for example, a high dielectric constant dielectric material, preferably zirconium oxide-aluminum oxide-zirconia (ZAZ), and the upper electrode layer TE includes, for example, a low-resistivity metal material such as titanium nitride, aluminum, titanium, copper or tungsten, a semiconductor material such as SiGe, or a combination of the above materials, preferably including a multilayer structure of titanium nitride and SiGe, but not limited thereto. It is worth noting that... Figure 7 The upper electrode layer TE covers the entire device surface, but for ease of viewing the structural features of this embodiment from the top view, Figure 7 The top view corresponds to section line VII-VII' in the cross-sectional view. Therefore, the material layers such as the first lower electrode BE1, the second lower electrode BE2, the capacitor dielectric layer 130, and the upper electrode layer TE can be seen from the top view.

[0076] At this step, multiple capacitor structures have been formed. Each capacitor structure consists of a first lower electrode BE1 and / or a second lower electrode BE2, a dielectric layer 130, and an upper electrode layer TE, stacked sequentially. More specifically, the capacitor structure composed of the first lower electrode BE1, the dielectric layer 130, and the upper electrode layer TE can be defined as the first capacitor structure C1, while the capacitor structure composed of the second lower electrode BE2, the dielectric layer 130, and the upper electrode layer TE can be defined as the second capacitor structure C2. The second capacitor structure C2 is located around the array of first capacitor structures C1 and can protect the peripheral structure of the array of first capacitor structures C1. In other words, the second capacitor structure C2 can be regarded as a dummy capacitor structure. The first capacitor structure C1 and the capacitor structure C2 serve as storage nodes (SN) of the semiconductor device, wherein each capacitor can be electrically connected to the transistor assembly (not shown) in the substrate 100 through the storage node pad SNP. Under this configuration, the semiconductor device of this embodiment can form a dynamic random access memory (DRAM) device, which is composed of at least one transistor assembly and at least one first capacitor structure C1 to form the smallest memory cell in the dynamic random access memory array, so as to receive voltage information from bit lines and buried word lines (buried gates).

[0077] Before forming the capacitor structure, a contact plug connection capacitor structure can be formed first. This involves forming an interlayer dielectric layer covering the preceding semiconductor structure, and then forming a contact plug electrical connection capacitor structure made of a conductive material on the interlayer dielectric layer. The contact plugs include materials such as aluminum, titanium, tantalum, tungsten, niobium, molybdenum, and copper, preferably tungsten, but not limited thereto. The above features are well-known in the art and will not be elaborated further here.

[0078] Furthermore, the shapes of the first support opening SOP1 and the second support opening SOP2, as well as the shape of the second lower electrode BE2, are also characteristic. (See reference...) Figure 8 , Figure 8 A partially enlarged top view illustrating the first support opening SOP1, the second support opening SOP2, the first lower electrode BE1, and the second lower electrode BE2 of the semiconductor device of the present invention. Figure 8 For the above Figure 6 A partially enlarged schematic diagram of the steps shown can be referenced. Figure 6 The range 200 includes a first support opening SOP1, a second support opening SOP2, a first lower electrode BE1, and a second lower electrode BE2. For example... Figure 8As shown in the top view, the first support opening SOP1 is located between the three first lower electrodes BE1. Each first lower electrode BE1 has a circular outline. Part of the boundary of the first support opening SOP1 contacts the sidewall of the first lower electrode BE1, while the boundaries of the other first support openings SOP1 that do not contact the sidewall of the first lower electrode BE1 can be roughly connected to form a circle. That is, the boundary of the first support opening SOP1 can be formed by six interconnected arc-shaped boundaries, defined as arc-shaped boundaries AE1, AE2, AE3, AE4, AE5, and AE6. Among them, arc-shaped boundaries AE1, AE3, and AE5 have the same radius of curvature, while arc-shaped boundaries AE2, AE4, and AE6 have the same radius of curvature. In addition, the radius of curvature of arc-shaped boundary AE1 is larger than that of arc-shaped boundary AE2.

[0079] Please continue to refer to this. Figure 8 From the top view, the second support opening SOP2 is located between the first lower electrode BE1 and the second lower electrode BE2. The second lower electrode BE2 may include a main body 142 in the middle and three protrusions 140 on the side. The main body 142 is roughly circular, while the protrusions 140 are arc-shaped. The three protrusions 140 extend outward from the center point O of the main body 142 along the directions D4, D5, and D6, respectively.

[0080] The second support opening SOP2 is located between the first lower electrode BE1 and the second lower electrode BE2. The shape of the second support opening SOP2 may be composed of multiple arc shapes. Taking this embodiment as an example, the boundary of the second support opening SOP2 can be formed by six interconnected arc-shaped boundaries, defined as arc boundaries AE7, AE8, AE9, AE10, AE11, and AE12. Arc boundaries AE7 and AE11 have the same radius of curvature, while arc boundaries AE8, AE10, and AE12 have the same radius of curvature. Furthermore, the radius of curvature of arc boundary AE7 is greater than that of arc boundary AE8, and the radius of curvature of arc boundary AE9 is greater than that of arc boundary AE7, but this is not a limitation. Additionally, the radius of curvature of arc boundary AE7 may be equal to the radius of curvature of arc boundary AE1 of the first support opening SOP1, and the radius of curvature of arc boundary AE8 may be equal to that of arc boundary AE8 of the first support opening SOP1, but this invention is not limited to these limitations.

[0081] The boundaries of the first support opening SOP1 and the second support opening SOP2 are composed of multiple arc-shaped boundaries. According to the applicant's experiments, the shape formed by the arc-shaped boundaries has a more stable structure. Therefore, it is beneficial to improve the support effect of the capacitor structure. However, the present invention is not limited to this, and the shapes of the first support opening SOP1 and the second support opening SOP2 can be adjusted according to requirements.

[0082] In addition, such as Figure 8 As shown, the first lower electrode BE1 has a first dimension (i.e., the diameter of the first lower electrode BE1). The second lower electrode BE2 has a second dimension W2, a third dimension W3, and a fourth dimension W4 in the first direction D1, the second direction D2, and the third direction D3, respectively. The shortest distance between any two first lower electrodes BE1 is defined as a first spacing P. At least one of the second dimension W2, the third dimension W3, and the fourth dimension W4 is not less than twice the sum of the first dimension W1 and the first spacing P. That is, taking the second dimension W2 as an example, the condition W2 ≥ 2W1 + P is satisfied. The same applies to the third dimension W3 and the fourth dimension W4.

[0083] For further details regarding the features of the first lower electrode BE1, the second lower electrode BE2, the first support opening SOP1, and the second support opening SOP2, please refer to [reference needed]. Figure 8 The illustrations are shown but will not be described in detail here. It is worth noting that in other embodiments of the present invention, the size, shape, and arrangement of the components can be adjusted according to actual needs, and the present invention is not limited thereto.

[0084] Figure 9 and Figure 10 Cross-sectional structural schematic diagrams of semiconductor devices according to two other different embodiments of the present invention are shown. Figure 9 and Figure 10 With the above Figure 7 The semiconductor devices of the first embodiment shown are compared to highlight the differences between the embodiments. For simplicity, the following description focuses primarily on the differences between the embodiments, without repeating the similarities. Furthermore, identical elements in the various embodiments of the present invention are designated with the same reference numerals to facilitate comparison between the embodiments. For example... Figure 9 and Figure 10 As shown, when forming the first lower electrode BE1, the process parameters can be adjusted so that the first lower electrode BE1 does not completely fill the first capacitor via OP1, thus leaving a recess 210 in the first lower electrode BE1. The recess 210 may be a void, and subsequently, when forming the capacitor dielectric layer 130, the capacitor dielectric layer 130 may fill the recess 210 to form a fully filled structure 211 (e.g., ...). Figure 9 (as shown), or the capacitor dielectric layer 130 only partially fills the depression 210, forming a partially filled structure 212 (as shown). Figure 10 (as shown), or the capacitor dielectric layer 130 is not filled into the recess 210, but covers the recess 210, so that the recess 210 is retained to form a pore (as shown). Figure 9 (As shown). It is understandable that, with the adjustment of process parameters, first lower electrodes BE1 of different shapes can also be combined with each other, for example, by... Figure 9 and Figure 10The structures are combined with each other. All the above variations are within the scope of this invention.

[0085] Based on the above instructions and diagrams, please refer to... Figures 1-8 The present invention provides a semiconductor device, including a substrate 100, a plurality of first lower electrodes BE1 located on the substrate 100, the plurality of first lower electrodes BE1 arranged in an array on mutually non-perpendicular first directions D1, second directions D2 and third directions D3, the outer contour of each first lower electrode BE1 being circular, and a plurality of second lower electrodes BE2 located on the substrate 100, the outer contour of the second lower electrode BE2 including a body 142 and three protrusions 140, wherein the body 142 is circular, and the three protrusions 142 are arc-shaped, extending outward from the center O of the body 142 along the fourth direction D4, the fifth direction D5 and the sixth direction D6 respectively.

[0086] In some embodiments of the present invention, a plurality of second lower electrodes BE2 surround an array arranged around a first lower electrode.

[0087] In some embodiments of the present invention, a capacitor dielectric layer 130 is further included, located on the first lower electrode BE1 and the second lower electrode BE2, and an upper electrode layer TE is located on the capacitor dielectric layer 130.

[0088] In some embodiments of the present invention, an opening (i.e., a second capacitor via OP2) is also included in each of the second lower electrodes BE2, and the opening OP2 is filled with a capacitor dielectric layer 130 and / or an upper electrode layer TE.

[0089] In some embodiments of the present invention, a recess 210 is further included in at least one first lower electrode BE1. The recess 210 may include a void 210, a void partially filled with a capacitor dielectric layer (i.e., a partially filled structure 212), or a completely filled capacitor dielectric layer (i.e., a completely filled structure 211).

[0090] In some embodiments of the present invention, the first lower electrode BE1 has a first size W1, and the second lower electrode BE2 has a second size W2, a third size W3, and a fourth size W4 in the first direction D1, the second direction D2, and the third direction D3, respectively. The shortest distance between any two first lower electrodes BE1 is defined as a first spacing P, wherein at least one of the second size W2, the third size W3, and the fourth size W4 is not less than twice the sum of the first size W1 and the first spacing P.

[0091] In some embodiments of the present invention, a support layer (support stack layer 110) is further included, surrounding the first lower electrode BE1 and the second lower electrode BE2. The support layer 110 includes a first support opening SOP1 located between the plurality of first lower electrodes BE1 and a second support opening SOP2 located between the first lower electrode BE1 and the second lower electrode BE2.

[0092] In some embodiments of the present invention, the area of ​​the second support opening SOP2 is smaller than the area of ​​the first support opening SOP1.

[0093] In some embodiments of the present invention, the shape of the second support opening SOP2 is different from the shape of the first support opening SOP1.

[0094] In some embodiments of the present invention, the first support opening SOP1 is circular or polygonal, and the outer contour of the first support opening SOP1 extends through a plurality of adjacent first lower electrodes BE1 and partially exposes the sidewalls of the adjacent first lower electrodes BE1.

[0095] In some embodiments of the present invention, the second support opening SOP2 is circular or polygonal, and the outer contour of the second support opening SOP2 extends through at least one first lower electrode BE1 and an adjacent second lower electrode BE2, and partially exposes the sidewalls of the first lower electrode BE1 and the second lower electrode BE2.

[0096] In some embodiments of the invention, the second support opening SOP2 partially exposes the sidewall of the body 142 of the second lower electrode BE2 and the sidewall of at least one protrusion 140.

[0097] In some embodiments of the present invention, the outer contour of the second lower electrode BE2 is composed of three first arcs with a first radius of curvature and three second arcs with a second radius of curvature, wherein the first radius of curvature is smaller than the second radius of curvature.

[0098] Please refer to Figures 1-10 The present invention also provides a semiconductor device, including a substrate 100, a plurality of first lower electrodes BE1 and second lower electrodes BE2 located on the substrate 100, the plurality of first lower electrodes BE1 being arranged in an array adjacent to each other, wherein, from the cross-sectional view, each first lower electrode BE1 presents an I-shaped profile and each second lower electrode BE2 presents a U-shaped profile.

[0099] In some embodiments of the present invention, the second lower electrode BE2 is located on one side of the array formed by the first lower electrodes BE1, as viewed in cross-sectional view.

[0100] In some embodiments of the present invention, a capacitor dielectric layer 130 is further included, located on the first lower electrode BE1 and the second lower electrode BE2, and an upper electrode layer TE is located on the capacitor dielectric layer 130.

[0101] In some embodiments of the present invention, wherein, as viewed in cross-sectional view, a second lower electrode BE2 surrounds an opening OP2, the opening OP2 being filled with a capacitor dielectric layer 130 and / or an upper electrode layer TE.

[0102] In some embodiments of the present invention, as seen in the cross-sectional view, a recess 210 is also included in at least one first lower electrode BE1. The recess 210 may include a void 210, a void partially filled with a capacitor dielectric layer (i.e., a partially filled structure 212), or a completely filled capacitor dielectric layer (i.e., a completely filled structure 211).

[0103] In some embodiments of the present invention, wherein, as viewed in cross-sectional view, the first lower electrode BE1 is in a first direction parallel to the substrate ( Figure 9 The first lower electrode BE1 has a first dimension W1 in the X direction, and the second lower electrode BE2 has a second dimension W2 in the first direction. The shortest distance between any two first lower electrodes BE1 in the first direction is defined as the first spacing P, wherein the second dimension W2 is not less than twice the sum of the first dimension W1 and the first spacing P.

[0104] In some embodiments of the present invention, a plurality of contact pads SNPs are located on the substrate 100, the contact pads SNPs are located between the second lower electrode BE2 and the substrate 100, wherein the second lower electrode BE2 contacts the plurality of contact pads SNPs (the second lower electrode BE2 spans at least two or more contact pads SNPs).

[0105] according to Figures 1 to 7 This invention provides a method for fabricating a semiconductor device, including providing a substrate 100, forming a support stack layer 110 on the substrate 100, forming a mask layer (including a polysilicon layer 122, an oxide layer 124, a bottom anti-reflective coating 126, and a photoresist layer 128) on the support stack layer 110, and performing a first patterning step. Figure 1 As shown), to form multiple first grooves R1 in the mask layer, and perform the second patterning step ( Figure 2 As shown, a plurality of second grooves R2 are formed in the mask layer, wherein each second groove R2 overlaps with a plurality of first grooves R1 as seen from the top view, and the overlapping portion of each first groove R1 and each second groove R2 is defined as a plurality of third grooves R3. An etching step is performed, using the patterned mask layer as a mask, to form a plurality of first capacitor vias OP1 and a plurality of second capacitor vias OP2 in the support stack layer 110.

[0106] In some embodiments of the present invention, each first capacitor through-hole OP1 corresponds to each first groove R1, and each second capacitor through-hole OP2 corresponds to each third groove R3.

[0107] In some embodiments of the present invention, the process further includes filling the lower electrode layer into each of the first capacitor vias OP1 and the second capacitor vias OP2 to form a first lower electrode BE1 and a second lower electrode BE2.

[0108] In some embodiments of the present invention, from the top view, each first capacitor through hole OP1 is circular, and each second capacitor through hole OP2 includes a body 142 and three protrusions 140, wherein the body 142 is circular, and the three protrusions 140 are arc-shaped, respectively distributed on the fourth direction D4, the fifth direction D5 and the sixth direction D6 which are not perpendicular to each other.

[0109] In some embodiments of the present invention, the area of ​​the second capacitor via OP2 is greater than three times the area of ​​the first capacitor via OP1.

[0110] In some embodiments of the present invention, forming a first lower electrode BE1 and a second lower electrode BE2 further includes forming a support opening in the support stack layer 110, including a first support opening SOP1 located between a plurality of first lower electrodes BE1 and a second support opening SOP2 located between a first lower electrode BE1 and a second lower electrode BE2, wherein the area of ​​the first support opening SOP1 is larger than the area of ​​the second support opening SOP2.

[0111] In some embodiments of the present invention, a plurality of contact pads SNPs are formed on the substrate 100, and each first capacitor via OP1 corresponds to one contact pad SNP, while the second capacitor via OP2 corresponds to a plurality of contact pads SNPs.

[0112] The present invention is characterized in that, as viewed from the top view, the second capacitor via OP2 is located within the second region A2, and the second lower electrode BE2 of the second capacitor via OP2 surrounds the outer periphery of the first lower electrode BE1 of the plurality of first capacitor vias OP1, and the shape of the second lower electrode BE2 is different from that of the first lower electrode BE1. Because the second region A2 is adjacent to a blank area (i.e., the third region A3) where no components are formed during the manufacturing process, the component density difference between these two regions is significant, making them susceptible to damage to the capacitor structure within the second region A2 due to load effects. The present invention, within the second region A2, fabricates a second capacitor via OP2 with a larger area and a unique shape by overlapping the first groove R1 and the second groove R2. Therefore, compared to the plurality of first capacitor vias OP1 located in the first region A1, the coverage area of ​​the second capacitor via OP2 is larger, and the second capacitor via OP2 is composed of three first capacitor vias OP1 and a central via, resulting in a stable structure that is less susceptible to damage due to load effects. Therefore, the present invention helps to improve the quality of capacitor structures located in edge regions.

[0113] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A semiconductor device, characterized in that, include: Substrate; Multiple first lower electrodes are located on the substrate, and the multiple first lower electrodes are arranged in an array in a first direction, a second direction and a third direction that are not perpendicular to each other, and the outer contour of each first lower electrode is circular. Multiple second lower electrodes are located on the substrate. The outer contour of the second lower electrode includes a main body and three protrusions, wherein the main body is circular and the three protrusions are arc-shaped, extending outward from the center of the main body along the fourth, fifth and sixth directions, respectively. From the top view, the substrate has a first region and a second region, the second region being located at the edge of the first region and surrounding the first region, the first lower electrode being located within the first region, and the second lower electrode being located within the second region.

2. The semiconductor device according to claim 1, characterized in that, The array formed by the plurality of second lower electrodes surrounding the first lower electrode.

3. The semiconductor device according to claim 1, characterized in that, Also includes: A capacitor dielectric layer is located on the first lower electrode and the second lower electrode; The upper electrode layer is located on the capacitor dielectric layer.

4. The semiconductor device according to claim 3, characterized in that, It also includes an opening located in each of the second lower electrodes, the opening being filled with the capacitor dielectric layer and / or the upper electrode layer.

5. The semiconductor device according to claim 3, characterized in that, It also includes a recess located in at least one of the first lower electrodes, the recess comprising a void, a void partially filled with the capacitor dielectric layer, or a completely filled capacitor dielectric layer.

6. The semiconductor device according to claim 1, characterized in that, The first lower electrode has a first size, and the second lower electrode has a second size, a third size, and a fourth size in the first direction, the second direction, and the third direction, respectively. The shortest distance between any two first lower electrodes is defined as a first spacing, wherein at least one of the second size, the third size, and the fourth size is not less than twice the sum of the first size and the first spacing.

7. The semiconductor device according to claim 1, characterized in that, Also includes: A support layer surrounds the first lower electrode and the second lower electrode, the support layer including a first support opening located between the plurality of first lower electrodes, and a second support opening located between the first lower electrode and the second lower electrode.

8. The semiconductor device according to claim 7, characterized in that, The area of ​​the second support opening is smaller than the area of ​​the first support opening.

9. The semiconductor device according to claim 7, characterized in that, The shape of the second support opening is different from the shape of the first support opening.

10. The semiconductor device according to claim 7, characterized in that, The first support opening is circular or polygonal, and the outer contour of the first support opening extends through the adjacent plurality of first lower electrodes and partially exposes the sidewalls of the adjacent first lower electrodes.

11. The semiconductor device according to claim 7, characterized in that, The second support opening is circular or polygonal, and the outer contour of the second support opening extends through at least one first lower electrode and an adjacent second lower electrode, and partially exposes the sidewalls of the first lower electrode and the second lower electrode.

12. The semiconductor device according to claim 11, characterized in that, The second support opening exposes the sidewall of the body of the second lower electrode and the sidewall of at least one of the protrusions.

13. The semiconductor device according to claim 1, characterized in that, The outer contour of the second lower electrode is composed of three alternating first arcs with a first radius of curvature and three second arcs with a second radius of curvature, wherein the first radius of curvature is smaller than the second radius of curvature.

14. The semiconductor device according to claim 1, characterized in that, The device includes a plurality of contact pads located on the substrate, the contact pads being positioned between the second lower electrode and the substrate, wherein the second lower electrode contacts the plurality of contact pads.

15. The semiconductor device according to claim 14, characterized in that, The contact pad is located between the first lower electrode and the substrate, with one of the first lower electrodes contacting one of the contact pads.

16. The semiconductor device of claim 14 or 15 further comprises a plurality of insulating sidewalls, the plurality of insulating sidewalls being located between the plurality of contact pads and isolating each of the contact pads.

17. A semiconductor device, characterized in that, include: Substrate; A plurality of first lower electrodes and a second lower electrode are located on the substrate, the plurality of first lower electrodes being arranged in an array adjacent to each other, wherein, in cross-sectional view, each first lower electrode presents an I-shaped profile and each second lower electrode presents a U-shaped profile; From the top view, the substrate has a first region and a second region, the second region being located at the edge of the first region and surrounding the first region, the first lower electrode being located within the first region, and the second lower electrode being located within the second region.

18. The semiconductor device according to claim 17, characterized in that, From the cross-sectional view, the second lower electrode is located on one side of the array formed by the first lower electrodes.

19. The semiconductor device according to claim 17, characterized in that, Also includes: A capacitor dielectric layer is located on the first lower electrode and the second lower electrode; The upper electrode layer is located on the capacitor dielectric layer.

20. The semiconductor device according to claim 19, characterized in that, From the cross-sectional view, the second lower electrode surrounds an opening, and the opening is filled with the capacitor dielectric layer and / or the upper electrode layer.

21. The semiconductor device according to claim 19, characterized in that, From the cross-sectional view, it also includes a recess located in at least one of the first lower electrodes, the recess including a void, a void partially filled with the capacitor dielectric layer, or a completely filled capacitor dielectric layer.

22. The semiconductor device according to claim 17, characterized in that, From the cross-sectional view, the first lower electrode has a first dimension in a first direction parallel to the substrate, and the second lower electrode has a second dimension in the first direction. The shortest distance between any two first lower electrodes in the first direction is defined as a first spacing, wherein the second dimension is not less than twice the sum of the first dimension and the first spacing.

23. The semiconductor device according to claim 17, characterized in that, The device includes a plurality of contact pads located on the substrate, the contact pads being positioned between the second lower electrode and the substrate, wherein the second lower electrode contacts the plurality of contact pads.

24. The semiconductor device according to claim 23, characterized in that, The contact pad is located between the first lower electrode and the substrate, with one of the first lower electrodes contacting one of the contact pads.

25. The semiconductor device of claim 23 or 24 further comprises a plurality of insulating sidewalls, the plurality of insulating sidewalls being located between the plurality of contact pads and isolating each of the contact pads.

26. A method for fabricating a semiconductor device, characterized in that, include: A substrate is provided, which, as viewed from the top view, has a first region and a second region; A support stack layer is formed on the substrate; A mask layer is formed on the support stack layer; A first patterning step is performed to form a plurality of first grooves in the mask layer in a first region and a second region, the second region being located at the edge of the first region and surrounding the first region; A second patterning step is performed to form a plurality of second grooves in the mask layer in the second region, wherein each second groove overlaps with a plurality of first grooves as viewed from the top view, and the overlapping portion of each first groove and each second groove is defined as a plurality of third grooves. An etching step is performed, using the patterned mask layer as a mask, to form a plurality of first capacitor vias and a plurality of second capacitor vias in the support stack layer; The process further includes filling the lower electrode layer into each of the first capacitor vias and the second capacitor vias to form a first lower electrode and a second lower electrode.

27. The method for fabricating a semiconductor device according to claim 26, characterized in that, Each of the first capacitor vias corresponds to each of the first grooves, and each of the second capacitor vias corresponds to each of the third grooves.

28. The method for fabricating a semiconductor device according to claim 26, characterized in that, From the top view, each of the first capacitor vias is circular, and each of the second capacitor vias includes a main body and three protrusions, wherein the main body is circular, and the three protrusions are arc-shaped and are respectively distributed in the fourth, fifth and sixth directions that are not perpendicular to each other.

29. The method for fabricating a semiconductor device according to claim 26, characterized in that, The area of ​​the second capacitor via is greater than three times the area of ​​the first capacitor via.

30. The method for fabricating a semiconductor device according to claim 26, characterized in that, The process of forming the first lower electrode and the second lower electrode further includes: A support opening is formed in the support stack layer, including a first support opening located between a plurality of first lower electrodes and a second support opening located between a first lower electrode and a second lower electrode, wherein the area of ​​the first support opening is larger than the area of ​​the second support opening.

31. The method for fabricating a semiconductor device according to claim 26, characterized in that, It further includes forming a plurality of contact pads on the substrate, with each of the first capacitor vias corresponding to one of the contact pads, and each of the second capacitor vias corresponding to a plurality of the contact pads.

32. The method of fabricating a semiconductor device according to claim 31 further includes forming a plurality of insulating sidewalls, the plurality of insulating sidewalls being located between the plurality of contact pads and isolating each of the contact pads.

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