Semiconductor device

Abstract

A semiconductor device includes: a plurality of active patterns respectively extending in a first direction on a substrate; a separation pattern extending in a second direction on the substrate and dividing each of the plurality of active patterns into a first active pattern and a second active pattern, the separation pattern including a first separation pattern and a second separation pattern, the second separation pattern is displaced from the first separation pattern in the first direction to partially overlap the first separation pattern in the second direction; a first dummy gate structure and a second dummy gate structure, the first dummy gate structure and the second dummy gate structure being respectively on a first side and a second side of the separation pattern and respectively extending in a second direction along respective end portions of the first active pattern and the second active pattern; and a plurality of first gate structures and a plurality of second gate structures, the plurality of first gate structures and the plurality of second gate structures crossing portions of the first active pattern and the second active pattern, respectively, and extending in the second direction.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2023-0087758 filed in the Korean Intellectual Property Office on July 6, 2023, the disclosure of which is incorporated herein by reference in its entirety for all purposes. Technical Field

[0003] The inventive concept relates to a semiconductor device. Background Art

[0004] In various semiconductor devices such as logic circuits and memories, active regions such as source and drain regions are connected to metal wirings of the back-end of the line (BEOL) through contact structures. A method is needed that disposes at least some wirings of the BEOL (e.g., power lines) on the back side of a substrate and forms a conductive through structure penetrating the semiconductor substrate for connection to some of the wirings. Summary of the invention

[0005] Some example embodiments of the inventive concepts provide semiconductor devices having improved reliability.

[0006] According to example embodiments, a semiconductor device includes: a substrate having a first surface and a second surface opposite to each other; a plurality of active patterns, the plurality of active patterns respectively extending in a first direction on the first surface of the substrate; a separation pattern, the plurality of active patterns extending in a second direction on the first surface of the substrate, the second direction intersecting the first direction, the separation pattern dividing each of the plurality of active patterns into a first active pattern and a second active pattern, the separation pattern including a first separation pattern and a second separation pattern, the second separation pattern being shifted from the first separation pattern in the first direction to partially overlap with the first separation pattern in the second direction; a first dummy gate structure and a second dummy gate structure, the first dummy gate structure and the second dummy gate structure being respectively located at both sides of the separation pattern, the first dummy gate structure and the second dummy gate structure respectively extending in the second direction along corresponding ends of the first active pattern and the second active pattern; a plurality of first gate structures and a plurality of second dummy gate structures Two-gate structure, multiple first gate structures and multiple second gate structures respectively intersect with the first active pattern and the second active pattern, and the multiple first gate structures and the multiple second gate structures extend in the second direction; source / drain patterns, which are on both sides of each of the multiple first gate structures and the multiple second gate structures and on the first active pattern and the second active pattern; an interlayer insulating layer, which is on the substrate and covers the source / drain pattern; a contact structure, which penetrates the interlayer insulating layer and is connected to at least one of the source / drain patterns; multiple buried conductive structures, multiple buried conductive structures are in the separation pattern and arranged along the second direction, at least one of the multiple buried conductive structures penetrates the interlayer insulating layer and is electrically connected to the contact structure; and multiple conductive penetration structures, multiple conductive penetration structures extend from the second surface of the substrate toward the first surface, and multiple conductive penetration structures are respectively connected to multiple buried conductive structures.

[0007] According to example embodiments, a semiconductor device includes: a plurality of active patterns, the plurality of active patterns respectively extending along a first direction on a substrate; a separation pattern, which extends along a second direction on the substrate, the second direction intersecting the first direction, the separation pattern dividing each of the plurality of active patterns into a first active pattern and a second active pattern, the separation pattern including a plurality of first separation patterns and a plurality of second separation patterns alternating with each other, the plurality of second separation patterns being shifted from the plurality of first separation patterns in the first direction to partially overlap with the plurality of first separation patterns in the second direction; a first dummy gate structure and a second dummy gate structure, the first dummy gate structure and the second dummy gate structure being respectively located at both sides of the separation pattern, the first dummy gate structure and the second dummy gate structure respectively extending in the second direction along corresponding ends of the first active pattern and the second active pattern; a plurality of first gate structures and a plurality of second gate structures, the plurality of first gate structures and the plurality of second gate structures respectively overlapping with the first active pattern; The source pattern and the second active pattern intersect, and the first gate structure and the second gate structure extend in the second direction; a source / drain pattern, which is on both sides of each of the multiple first gate structures and the multiple second gate structures and on the first active pattern and the second active pattern; an interlayer insulating layer, which is on the substrate and covers the source / drain pattern; a contact structure, which penetrates the interlayer insulating layer and is connected to at least one of the source / drain patterns; a plurality of buried conductive structures, the multiple buried conductive structures are in the separation pattern and arranged along the second direction, at least one of the multiple buried conductive structures penetrates the interlayer insulating layer and is electrically connected to the contact structure; a plurality of conductive penetration structures, the multiple conductive penetration structures extend from the lower surface of the substrate toward the upper surface of the substrate, and the multiple conductive penetration structures are respectively connected to the multiple buried conductive structures; and a first interconnect structure, which is on the interlayer insulating layer, and the first interconnect structure includes a first interconnect layer connecting the contact structure with the buried conductive structure.

[0008] According to an example embodiment, a semiconductor device includes: a plurality of active patterns, the plurality of active patterns respectively extending along a first direction on a substrate; a separation pattern, which extends along a second direction on the substrate, the second direction intersecting the first direction, the separation pattern dividing each of the plurality of active patterns into a first active pattern and a second active pattern, the separation pattern including a plurality of first separation patterns and a plurality of second separation patterns alternating with each other in the second direction, the plurality of second separation patterns being shifted from the plurality of first separation patterns in the first direction to partially overlap with the plurality of first separation patterns in the second direction; a first dummy gate structure and a second dummy gate structure, the first dummy gate structure and the second dummy gate structure being respectively located on a first side and a second side of the separation pattern, the first dummy gate structure and the second dummy gate structure respectively extending in the second direction along corresponding ends of the first active pattern and the second active pattern; and a plurality of first gate structures and a plurality of second gate structures, the plurality of first gate structures and the plurality of second gate structures extending in the second direction and respectively intersecting with the first active pattern and the second active pattern, and extending in the second direction. A first dummy gate structure located on a first side of each of the plurality of first separation patterns is connected to a corresponding one of the plurality of first gate structures located on a first side of an adjacent second separation pattern among the plurality of second separation patterns, and a second dummy gate structure located on a second side of each of the plurality of second separation patterns is connected to a corresponding one of the plurality of second gate structures located on a second side of an adjacent first separation pattern among the plurality of first separation patterns. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and other aspects, features and advantages of the present inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 is a plan view showing a semiconductor device according to example embodiments;

[0011] Figure 2A and Figure 2B yes Figure 1 The semiconductor device shown is a cross-sectional view taken along lines I1-I1' and I2-I2' respectively;

[0012] Figure 3A and Figure 3B yes Figure 1 The semiconductor device shown is a cross-sectional view taken along lines II 1-II 1' and II 12-II 1' respectively;

[0013] Figure 4 is a plan view showing a semiconductor device according to example embodiments;

[0014] Figure 5A and Figure 5B yes Figure 4The semiconductor device shown is a cross-sectional view taken along lines I1-I1' and I2-I2' respectively;

[0015] Figure 6 and Figure 7 are plan views respectively illustrating semiconductor devices according to some example embodiments;

[0016] Figure 8 is a plan view showing a semiconductor device according to example embodiments;

[0017] Fig.9A and Fig. 9B yes Figure 8 The semiconductor device is shown as a cross-sectional view taken along lines I1-I1' and I2-I2'; and

[0018] Fig. 10A and Fig. 10B yes Figure 8 The semiconductor device shown is a cross-sectional view taken along lines II 1-II 1′ and II 2 -II 2′, respectively. DETAILED DESCRIPTION

[0019] Hereinafter, some example embodiments will be described with reference to the accompanying drawings.

[0020] Although the terms "same", "equal" or "equivalent" are used in the description of example embodiments, it should be understood that some imprecision may exist. Therefore, when an element or value is referred to as being the same as another element or value, it should be understood that the element or value is the same as the other element or value within a desired manufacturing or operating tolerance range (e.g., ±10%).

[0021] When the term "about" or "substantially" is used in conjunction with a numerical value in this specification, it is intended that the associated numerical value includes manufacturing or operating tolerances around the stated numerical value (e.g.,

[0022] ±10%). In addition, when the words "about" and "substantially" are used in conjunction with geometric shapes, the intention is that the accuracy of the geometric shapes is not required, but the freedom of the shapes is within the scope of the present disclosure. In addition, whether or not a value or shape is modified as "about" or "substantially", it will be understood that these values ​​and shapes should be interpreted as including manufacturing or operating tolerances (e.g., ±10%) around the value or shape.

[0023] Figure 1 is a plan view showing a semiconductor device according to example embodiments, Figure 2A and Figure 2B yes Figure 1 The semiconductor device shown is a cross-sectional view taken along line I1-I1' and line I2-I2', respectively, and Figure 3A and Figure 3B yes Figure 1 The semiconductor devices shown are respectively along lines II 1-II 1'

[0024] and a cross-sectional view taken along lines I I2-I I2'.

[0025] Reference Figure 1 , Figure 2A , Figure 2B , Figure 3A and Figure 3B According to the embodiment, the semiconductor device 100 includes a substrate 101 having a first side and a second side opposite to each other, a plurality of active patterns 105 extending from a first surface (or an active region) of the substrate 101 along a first direction (e.g., a D1 direction), a separation pattern SP extending along a second direction (e.g., a D2 direction) intersecting the first direction (e.g., the D1 direction) and dividing each of the plurality of active patterns 105 into a first active pattern 105A and a second active pattern 105B, and a first dummy gate structure DG1 and a second dummy gate structure DG2 extending in the second direction (e.g., the D2 direction) along ends of the plurality of first active patterns 105A and the second active pattern 105B on both sides of the separation pattern SP.

[0026] In this case, the gate structures GS1 and GS2 refer to “active gate structures” constituting transistors, and the dummy gate structures DG1 and DG2 refer to “passive gate structures” not constituting transistors.

[0027] The semiconductor device 100 according to this embodiment may also include a first gate structure GS1 and a second gate structure GS2 respectively intersecting the first active pattern 105A and the second active pattern 105B and extending in a second direction (for example, direction D2), a source / drain pattern 120 arranged on the first active pattern 105A and the second active pattern 105B on both sides of the first gate structure GS1 and the second gate structure GS2, a first contact structure 180A connected to the source / drain pattern 120, and a second contact structure 180B connected to the first gate structure GS1 and the second gate structure GS2.

[0028] The substrate 101 may include, for example, a semiconductor (such as Si or Ge) or a compound semiconductor (such as SiGe, SiC, GaAs, InAs, or InP). In another example, the substrate 101 may have a silicon-on-insulator (SOI) structure. An active region having a well doped with impurities is disposed on a first side of the substrate 101, and the active pattern 105 may have a protruding fin structure extending along a first direction (e.g., D1 direction) on the active region. However, the inventive concept is not limited thereto, and the active region and the active pattern 105 may be an N-type region for a P-MOS transistor or a P-type region for an N-MOS transistor.

[0029] The device isolation layer 110 may be disposed on the substrate 101 to define an active region including the active pattern 105. For example, the device isolation layer 110 may include silicon oxide or a silicon oxide-based insulating material. The device isolation layer 110 may be a shallow trench isolation (STI) defining the active pattern 105.

[0030] Reference Figure 1 , Figure 2A and Figure 2B , the active pattern 105 extends from the first surface of the substrate 101 in a first direction (e.g., D1 direction) and has a fin-shaped structure protruding from the upper surface of the active area. A plurality of channel layers 130 (or semiconductor patterns) may be arranged on the active pattern 105 to be spaced apart from each other in a third direction (e.g., D3 direction) perpendicular to the first surface of the substrate 101. The active pattern 105 and the plurality of channel layers 130 may be provided as a multi-channel layer of a transistor. In this example embodiment, the plurality of channel layers 130 are shown as three, but the number thereof is not particularly limited. For example, the plurality of channel layers 130 may include silicon (Si), silicon germanium (SiGe), or germanium (Ge). In some example embodiments, the plurality of channel layers 130 may include the same semiconductor as the substrate 101.

[0031] like Figure 1 As shown, the semiconductor device 100 according to this example embodiment may include a plurality of gate structures GS extending in a second direction (e.g., direction D2). As described above, the plurality of gate structures GS may include first gate structures GS1a and GS1b and second gate structures GS2a and GS2b respectively crossing the first active pattern 105A and the second active pattern 105B.

[0032] like Figure 2A and Figure 2BAs shown, the first gate structures GS1a and GS1b and the second gate structures GS2a and GS2b may respectively include a gate spacer 141, a gate insulating film 142 and a gate electrode 145 sequentially disposed between the gate spacers 141, and a gate capping layer 147 disposed on the gate electrode 145. For example, the gate spacer 141 may include an insulating material such as SiOCN, SiON, SiCN or SiN. The gate insulating film 142 may be made of, for example, a silicon oxide layer, a high-κ dielectric layer or a combination thereof. The high-κ dielectric layer may include a material having a higher dielectric constant (e.g., about 10 to 25) than the silicon oxide layer. For example, the high-κ dielectric layer may include a material selected from the group consisting of hafnium oxide, hafnium oxynitride, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide and a combination thereof, but is not limited thereto. The gate electrode 145 may include a conductive material, and may include, for example, a metal nitride (such as titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN)) and / or a metal material (such as aluminum (Al), tungsten (W), or molybdenum (Mo)) or a semiconductor material (such as doped polysilicon). In some example embodiments, the gate electrode 145 may be a multilayer structure including two or more films. In addition, the gate capping layer 147 may include, for example, silicon nitride, silicon oxynitride, silicon carbonitride, or silicon carbon nitride oxide.

[0033] The separation pattern SP may provide two separated cell regions on the substrate 101 by dividing each of the plurality of active patterns 105 into a first active pattern 105A and a second active pattern 105B.

[0034] like Figure 1 As shown, the separation pattern SP adopted in this example embodiment may include a first separation pattern SP1 extending in the second direction (e.g., D2 direction) and a second separation pattern SP2 shifted from the first separation pattern SP1 in the first direction (e.g., D1 direction) to partially overlap the first separation pattern SP1 in the second direction (e.g., D2 direction). In this way, the separation pattern SP adopted in this example embodiment generally extends in the second direction (e.g., D2 direction), but has a pattern (e.g., a portion) partially shifted in the first direction (e.g., D1 direction).

[0035] Reference Figure 2A and Figure 2B, the separation pattern SP employed in this example embodiment includes a first trench TR1 and a second trench TR2, the depth of which is equal to or lower than the depth of the active pattern 105. In this embodiment, each of the first trench TR1 and the second trench TR2 may have a depth corresponding to the depth of the STI defining the active pattern. The first trench TR1 and the second trench TR2 may be shifted relative to each other in a first direction (e.g., D1 direction) to define a first separation pattern SP1 and a second separation pattern SP2, respectively.

[0036] The separation pattern SP employed in this example embodiment may include a portion of the device isolation layer 110 partially filled in each of the first and second trenches TR1 and TR2, and an interlayer insulating layer 160 disposed on the device isolation layer 110. The portion of the device isolation layer 110 filled in the first and second trenches TR1 and TR2 may have the same level as other device isolation layers 110. The interlayer insulating layer 160 has a portion 160a on the first device isolation layer 110a of the separation pattern SP.

[0037] In this example embodiment, the separation pattern SP has a partially shifted pattern, and each of the first and second dummy gate structures DG1 and DG2 located at both sides (ie, the first and second sides) of the separation pattern SP may be disconnected. Figure 1 As shown, the first dummy gate structure DG1 can be disconnected by being divided into a first dummy gate portion DG1a on a first side of the first separation pattern SP1 and a first dummy gate portion DG1b on a first side of the second separation pattern SP2. Similarly, the second dummy gate structure DG2 can be disconnected by being divided into a second dummy gate portion DG2a on a second side of the first separation pattern SP1 and a second dummy gate portion DG2b on a second side of the second separation pattern SP2.

[0038] like Figure 2A and Figure 2B As shown, the first and second dummy gate structures DG1 and DG2 are formed along ends of the first and second active patterns 105A and 105B, respectively, and may therefore have a structurally unstable condition, unlike the first and second gate structures GS1 and GS2.

[0039] Unlike the present exemplary embodiment, when these fragile dummy gate structures are located on both sides of the separation pattern and extend without displacement (e.g., excluding a portion displaced from another portion), their structural fragility may increase due to their relatively long length. Therefore, bending and tilting defects may easily occur in the relatively long dummy gate structure.

[0040] However, as described above, the first dummy gate structure DG1 and the second dummy gate structure DG2 employed in this exemplary embodiment are disconnected by shifting the separation pattern SP (e.g., by shifting one of the first separation pattern SP1 and the second separation pattern SP2 from the other of the first separation pattern SP1 and the second separation pattern SP2), and the lengths of the first dummy gate structure DG1 and the second dummy gate structure DG2 in the second direction (e.g., direction D2) can be shortened. Therefore, structural defects such as the above-mentioned tilting defects can be significantly alleviated.

[0041] The length of the first separation pattern SP1 and the second separation pattern SP2 in the second direction (e.g., D2 direction) may correspond to an integer multiple of the cell height CH. In this case, the cell height CH may be defined as (or may be equal to) the length of each logic cell in the second direction (e.g., D2 direction). In this case, the "logic cell" may include a first active area and a second active area (e.g., 2 active patterns adjacent in the second direction) arranged in the second direction (e.g., D2 direction) between an upper boundary and a lower boundary (boundaries with other cells arranged in the second direction), respectively. In this case, the cell height CH may be defined as the distance between the upper boundary and the lower boundary of the logic cell.

[0042] In order to effectively reduce the tilt defect, the length of each of the first separation pattern SP1 and the second separation pattern SP2 in the second direction (e.g., D2 direction) may be designed to have a maximum of 2 to 4 unit heights CH (e.g., 2 CH). In some example embodiments, the length of each of the first separation pattern SP1 and the second separation pattern SP2 in the second direction (e.g., D2 direction) may be 1 μm or less (e.g., 900 nm or less).

[0043] The first gate structures GS1a and GS1b and the first dummy gate portions DG1a and DG1b may be arranged at a constant pitch P0 (hereinafter referred to as "gate pitch") in a first direction (e.g., D1 direction). Similarly, the second gate structures GS2a and GS2b and the second dummy gate portions DG2a and DG2b may be arranged at the same pitch P0 in a first direction (e.g., D1 direction).

[0044] The separation pattern SP may have a width corresponding to an integer multiple of the gate pitch P0. In this embodiment, the width P1 of each of the first separation pattern SP1 and the second separation pattern SP2 may be twice the gate pitch P0. The first separation pattern SP1 and the second separation pattern SP2 have the same width. In some example embodiments, the first separation pattern SP1 and the second separation pattern SP2 may have different widths.

[0045] The distance d of the second separation pattern SP2 shifted from the first separation pattern SP1 to the first direction (e.g., D1 direction) may be an integer multiple of the gate pitch P0. In this example embodiment, the shift distance d may be a distance corresponding to (e.g., may be equal to) the gate pitch P0. In some example embodiments, the shift distance d may be less than the width P1 of the separation pattern SP.

[0046] The separation pattern SP may have a connection separation pattern SP', which is set to a region shifted between the first separation pattern SP1 and the second separation pattern SP2. The connection separation pattern SP' may have a width overlapping each of the first separation pattern SP1 and the second separation pattern SP2 in the second direction (for example, the D2 direction) between the first separation pattern SP1 and the second separation pattern SP2, and the connection separation pattern SP' may have a width P2 greater than each width P1 of the first separation pattern and the second separation pattern.

[0047] In this example embodiment, Figure 1 As shown, the width P2 of the connection separation pattern SP' may have a width defined by the spacing between the first dummy gate portion DG1a on the first side of the first separation pattern SP1 and the second dummy gate portion DG2b on the second side of the second separation pattern SP2 (e.g., having a width equal to the spacing). For example, the width P2 of the connection separation pattern SP' may be three times the gate spacing P0. The length of the connection separation pattern SP' in the second direction (e.g., D2 direction) may be an integer multiple of the cell height CH. In this example embodiment, the length of the connection separation pattern SP' in the second direction (e.g., D2 direction) may be one cell height CH.

[0048] As described above, the first dummy gate structure DG1 and the second dummy gate structure DG2 employed in this exemplary embodiment are disconnected by the displacement of the separation pattern SP, and may have a shortened length in the second direction (e.g., D2 direction). In this embodiment, the dummy gate portions DG1b and DG2a on both sides of the separation pattern SP are disconnected, or in the plurality of gate structures GS1 and GS2, the gate structures GS1b and GS2a may be connected to the separation pattern SP.

[0049] Reference Figure 1 , Figure 2A and Figure 2B, the second dummy gate portion DG2a on the second side of the first separation pattern SP1 is cut off by the shifted separation pattern portion (e.g., the connecting separation pattern SP'), and the first dummy gate portion DG1b on the first side of the second separation pattern SP2 is cut off by the shifted separation pattern portion (e.g., the connecting separation pattern SP'). On the other hand, the first dummy gate portion DG1a on the first side of the first separation pattern SP1 extends in the second direction (e.g., the D2 direction) and serves as the first gate structure GS1b, and the second dummy gate portion DG2b on the second side of the second separation pattern SP2 extends in the second direction (e.g., the D2 direction) and serves as the second gate structure GS2a.

[0050] The semiconductor device 100 according to this example embodiment is arranged according to the separation pattern SP, and includes a power transmission structure for supplying power to each logic unit from the back side of the substrate 101. The power transmission structure adopted in this example embodiment includes a buried conductive structure 150 arranged in the second direction (e.g., D2 direction) in the separation pattern SP, and a conductive through structure 170 extending from the second side toward the first side of the substrate 101 and connected to the buried conductive structure 150.

[0051] In this example embodiment, Figure 2A and Figure 2B As shown, the buried conductive structure 150 extends to the first side of the substrate 101 , and the conductive through structures 170 may penetrate the substrate 101 and contact bottom surfaces of the buried conductive structures 150 at the first side of the substrate 101 , respectively.

[0052] Each of the conductive through structures 170 receives power from a backside power line PL2 (or a second power line or PL) located at the second side of the substrate 101. Power may be supplied to the source / drain pattern 120 of each logic cell through the buried conductive structure 150. In this example embodiment, the buried conductive structure 150 may be electrically connected to the source / drain pattern 120 through a frontside power line PM (or a first power line or PM1) of the first interconnect structure 210.

[0053] Reference Figure 1 In this example embodiment, the buried conductive structure 150 and the conductive through structure 170 may be arranged in the separation pattern SP at a pitch corresponding to the cell height CH of the logic cell (e.g., a pitch equal to the cell height CH). Thus, in this example embodiment, the buried conductive structure 150 and the conductive through structure 170 are disposed at the upper and lower boundaries of each logic cell and may serve as a power transmission structure for each logic cell.

[0054] The buried conductive structure 150 may include a first buried conductive structure arranged in the second direction (e.g., D2 direction) in the first separation pattern SP1, and a second buried conductive structure arranged in the second direction (e.g., D2 direction) in the second separation pattern SP2. Similar to the displacement of the first separation pattern SP1 and the second separation pattern SP2, the arrangement of the second buried conductive structure may be displaced from the arrangement of the first buried conductive structure in the first direction (e.g., D1 direction) by a distance d corresponding to the gate pitch P0.

[0055] In this example embodiment, the buried conductive structure 150 between the first separation pattern SP1 and the second separation pattern SP2 may be provided as a power transmission structure that supplies power to the cells of the connection separation pattern SP' that overlap in the first direction (e.g., D1 direction). In this case, the length of the connection separation pattern SP' in the second direction (e.g., D2 direction) may be defined by the spacing of adjacent buried conductive structures 150 between the first separation pattern SP1 and the second separation pattern SP2 (e.g., may be equal to the spacing of adjacent buried conductive structures 150 between the first separation pattern SP1 and the second separation pattern SP2).

[0056] The buried conductive structure 150 may include a first conductive material 155 .

[0057] The first conductive barrier 152 surrounds the bottom surface and the side surface of the first conductive material 155. In this example embodiment, the buried conductive structure 150 may further include a first insulating liner 151 surrounding the first conductive barrier 152. The conductive through structure 170 may include a second conductive material 175, a second insulating liner 171 disposed between the substrate 101 and the second conductive barrier 172 surrounding the bottom surface and the side surface of the second conductive material 175.

[0058] For example, the first conductive material 155 and the second conductive material 175 may include Cu, Co, Mo, Ru, W, or alloys thereof. In some example embodiments, the first conductive material 155 and the second conductive material 175 may include different conductive materials. For example, the first conductive material 155 may include W or Mo, and the second conductive material 175 may include Cu. For example, the first conductive barrier 152 and the second conductive barrier 172 may include Ta, TaN, Mn, MnN, WN, Ti, TiN, or a combination thereof. For example, the first insulating liner 151 and the second insulating liner 171 may include SiO 2 , SiN, SiCN, SiC, SiCOH, SiON, Al 2 O 3 , AlN or a combination thereof.

[0059] In this example embodiment, the first dummy gate structure DG1 and the second dummy gate structure DG2 located on both sides of the separation pattern SP may also have a structure similar to the gate structure GS. Each of the first dummy gate structure DG1 and the second dummy gate structure DG2 may include a gate spacer 141, a gate insulating film 142, a gate electrode 145, and a gate capping layer 147. However, as described above, the first dummy gate structure DG1 and the second dummy gate structure DG2 are located at the ends of the first active pattern 105A and the second active pattern 105B, and as described above, Figure 2A and Figure 2B As shown, some regions of the first and second dummy gate structures DG1 and DG2 may extend to the device isolation layer 110 along the cross-sections of the first and second active patterns 105A and 105B.

[0060] In this way, the first dummy gate structure DG1 and the second dummy gate structure DG2 have an asymmetric structure along the ends of the first active pattern 105A and the second active pattern 105B, and therefore, are structurally unstable compared to the first gate structure GS1 and the second gate structure GS2, and in order to reduce the tilting defect caused thereby, by using the shift of the separation pattern SP adopted in this example embodiment, the length of the first dummy gate structure DG1 and the second dummy gate structure DG2 in the second direction (for example, the D2 direction) can be shortened, and therefore, structural defects such as tilting defects can be significantly reduced.

[0061] The source / drain pattern 120 may be disposed on regions of the first active pattern 105A and the second active pattern 105B located on both sides of the first gate structure GS1 and the second gate structure GS2. The source / drain pattern 120 may be connected to both ends of the plurality of channel layers 130 in a first direction (e.g., D1 direction), respectively. The gate electrode 145 may have a portion 145' extending in a second direction (e.g., D2 direction) to surround the plurality of channel layers 130 and intersect with the first active pattern 105A and the second active pattern 105B. The gate insulating film 142 may also have a portion 142' extending between the plurality of channel layers 130 and the gate electrode portion 145'. In this way, the semiconductor device 100 according to this example embodiment may construct a gate-all-around field effect transistor.

[0062] The source / drain pattern 120 may include an epitaxial pattern provided by selective epitaxial growth (SEG) from the recessed surfaces of the first active pattern 105A and the second active pattern 105B and the side surfaces of the plurality of channel layers 130 located on both sides of the first gate structure GS1 and the second gate structure GS2. The source / drain pattern 120 is also referred to as a raised source / drain (RSD). For example, the source / drain pattern 120 may be Si, SiGe, or Ge, and may have an N-type or P-type conductivity type. When forming the P-type source / drain pattern 120, regrowth using SiGe is performed, and, for example, boron (B), indium (In), gallium (Ga), boron trifluoride (BF 3 ) etc. as P-type impurities. When the N-type source / drain pattern 120 is formed of silicon (Si), phosphorus (P), nitrogen (N), arsenic (As), antimony (Sb), etc., may be doped as N-type impurities. During the growth process, the source / drain pattern 120 may have different shapes along a crystallographically stable plane. For example, the source / drain pattern 120 may have a pentagonal cross-section (in the case of the P-type), and may have a hexagonal or polygonal cross-section whose angles are gentle (in the case of the N-type).

[0063] The semiconductor device 100 according to this example embodiment may include an interlayer insulating layer 160 disposed on the device isolation layer 110. The interlayer insulating layer 160 may be disposed around the source / drain pattern 120 and the first gate structure GS1 and the second gate structure GS2. For example, the interlayer insulating layer 160 may be a flowable oxide (FOX), east-burning silazane (TOSZ), undoped silica glass (USG), borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), plasma-enhanced tetraethyl orthosilicate (PETEOS), fluorosilicate glass (FSG), high-density plasma (HDP) oxide, plasma-enhanced oxide (PEOX), flowable CVD (FCVD) oxide, or a combination thereof. The interlayer insulating layer 160 may be formed using a chemical vapor deposition (CVD) process, a flowable CVD process, or a spin coating process. The semiconductor device 100 according to this example embodiment may further include an intermediate insulating layer 191 covering the first gate structure GS1 and the second gate structure GS2 on the interlayer insulating layer 160. The intermediate insulating layer 191 may include an insulating material similar to that of the interlayer insulating layer 160 .

[0064] like Figure 2A and Figure 2B as well as Figure 3A and Figure 3BAs shown, the first contact structure 180A and the second contact structure 180B penetrate the interlayer insulating layer 160 and the intermediate insulating layer 191, and can be connected to the source / drain pattern 120 and the gate electrode 145, respectively. Each of the first contact structure 180A and the second contact structure 180B may include a conductive barrier 182 and a contact plug 185. For example, the contact plug 185 may include Cu, Co, Mo, Ru, W, or an alloy thereof. In addition, the conductive barrier 182 may include Ta, TaN, Mn, MnN, WN, Ti, TiN, or a combination thereof. In this embodiment, each of the first contact structures 180A may include a metal silicide film 183 formed on the source / drain pattern 120 to improve contact resistance.

[0065] In this example embodiment, the first interconnect structure 210 may include a plurality of (e.g., two) first insulating layers 211, and first metal lines M1 and first metal vias V1a, V1b, and V1c formed on the first insulating layers 211. For example, the first interconnect layer including the first metal lines M1 and the first metal vias V1a, V1b, and V1c may be formed by a dual damascene process.

[0066] At least one of the first contact structures 180A may be connected to the first metal line M1 through a metal via V1b. As described above, the first metal line M1 may be connected to the buried conductive structure 150 through a metal via V1a and may be provided as a first power line PM.

[0067] The insulating protection film 197 may be disposed on the second surface of the substrate 101. The insulating protection film 197 may be provided to surround the contact region of the conductive through structure 170 protruding from the second surface of the substrate 101. The second interconnect structure 220 is disposed on the insulating protection film 197. The second interconnect structure 220 may include a second insulating layer 221 and a second metal line M2 formed on the second insulating layer 221. The second metal line M2 may include a second power line PL connected to the conductive through structure 170. The insulating protection film 197 and the first insulating layer 211 and the second insulating layer 221 may include different insulating materials. For example, the insulating protection film 197 may include AlN or SiN, and the first insulating layer 211 and the second insulating layer 221 may include SiO 2 .

[0068] According to the above-described example embodiments, by shifting a portion of the separation pattern SP in which the power transmission structure including the buried conductive structure 150 and the conductive through structure 170 is arranged in a first direction (e.g., D1 direction) by an integer multiple (e.g., 1 times) of the gate pitch P0, and by shortening the lengths of the first dummy gate structure DG1 and the second dummy gate structure DG2 adjacent to the separation pattern SP, the structural fragility (e.g., tilting risk) thereof can be reduced.

[0069] Figure 4 is a plan view showing a semiconductor device according to example embodiments, and Figure 5A and Figure 5B yes Figure 4 The semiconductor device shown is a cross-sectional view taken along lines I1 - I1 ′ and I2 - I2 ′, respectively.

[0070] The semiconductor device 100A according to this example embodiment may be understood as having the same structure as the semiconductor device 100A except that the separation pattern SP has a zigzag pattern, the buried conductive structure 150 has a structure penetrating the substrate 101, and the second power line PL of the second interconnect structure 220 is directly connected to the buried conductive structure 150 while omitting the conductive through structure 170. Figures 1 to 3B In addition, unless otherwise specified, the components of this example embodiment may refer to the components of the semiconductor device 100 shown in FIG. Figures 1 to 3B The description of the same or similar components of the semiconductor device 100 shown in FIG. 1 should be understood.

[0071] The separation pattern SP adopted in this embodiment has a zigzag pattern. Figure 4 , similar to the previous example embodiment, in addition to the first separation pattern SP1 and the second separation pattern SP2 shifted in the first direction (e.g., D1 direction), the separation pattern SP may further include a third separation pattern SP3 connected to the second separation pattern SP2 in the second direction (e.g., D2 direction). The third separation pattern SP3 is shifted in the first direction (e.g., D1 direction) so that a portion of the third separation pattern SP3 overlaps with the second separation pattern SP2, and the width in the first direction (e.g., D1 direction) may be the same as the width of the first separation pattern SP1 in the first direction (e.g., D1 direction). Figure 4 As shown, the first separation pattern SP1 and the third separation pattern SP3 may be substantially completely overlapped in the second direction (eg, direction D2).

[0072] The second separation pattern SP2 is shifted from the first separation pattern SP1 in the forward direction of the first direction (e.g., D1 direction) by a distance d corresponding to the gate pitch P0, and the third separation pattern SP3 is shifted from the second separation pattern SP2 in the backward direction of the first direction (e.g., D1 direction) by a distance d corresponding to the gate pitch P0.

[0073] In this manner, the first and second dummy gate structures DG1 and DG2 located at both sides (ie, the first and second sides) of the zigzag-shifted separation pattern SP are disconnected and each may have a shortened length corresponding to the shift period.

[0074] Reference Figure 4, the first dummy gate structure DG1 may be disconnected by being divided into a first dummy gate portion DG1a on a first side of the first separation pattern SP1, a first dummy gate portion DG1b on a first side of the second separation pattern SP2, and a first dummy gate portion DG1a' on a first side of the third separation pattern SP3. Similarly, the second dummy gate structure DG2 may be disconnected by being divided into a second dummy gate portion DG2a on a second side of the first separation pattern SP1, a second dummy gate portion DG2b on a second side of the second separation pattern SP2, and a second dummy gate portion DG2a' on a second side of the third separation pattern SP3.

[0075] like Figure 5A and Figure 5B As shown, the first dummy gate structure DG1 and the second dummy gate structure DG2 are formed along the ends of the first active pattern 105A and the second active pattern 105B, respectively, and may therefore have a structurally unstable condition, which is different from the first gate structure GS1 and the second gate structure GS2. In this example embodiment, the first dummy gate structure DG1 and the second dummy gate structure DG2 are disconnected by a zigzag separation pattern SP to have a shortened length, and structural defects such as tilt defects can be significantly alleviated. In this example embodiment, the disconnected dummy gate structures may have different lengths. For example, the length L2 of the second dummy gate portion DG2b of the second separation pattern SP2 may be greater than the length L1 of the first dummy gate portion DG1b. In each dummy gate portion (DG1a, DG1b, DG1a', DG2a, DG2b, DG2a'), the length in the second direction (e.g., D2 direction) may be designed to be up to 2 to 6 unit heights CH (e.g., 3 CH or 5 CH). In some example embodiments, the length of each of the dummy gate portions DG1a, DG1b, DG1a', DG2a, DG2b, and DG2a' may be 1 μm or less (eg, 900 nm or less).

[0076] The power transmission structure employed in this example embodiment may also have a different structure from that of the previous example embodiments.

[0077] Similar to the previous example embodiment, the buried conductive structure 150 is arranged along the second direction within the separation pattern, and similar to the shift of the first separation pattern to the third separation pattern SP1, SP2 and SP3, the arrangement of the buried conductive structure 150 may also be shifted along the first direction (e.g., D1 direction). In this example embodiment, unlike the previous example embodiment, the conductive penetration structure 170 is omitted, and the second power line PL of the second interconnect structure 220 may be directly connected to the buried conductive structure 150. The second power line PL may have a track structure extending in one direction.

[0078] In some example embodiments, a portion of the substrate 101 other than the first active pattern 105A and the second active pattern 105B may be removed. For example, a portion of the substrate 101 may be removed using a polishing process until the lower surfaces of the first active pattern 105A and the second active pattern 105B and the lower surface of the device isolation layer 110 are exposed, and the second interconnect structure 220 may be directly formed on the removed surface. In this case, the buried conductive structure 150 may be connected to the second power line PL through the interlayer insulating layer 160 and the device isolation layer 110 as well as the substrate 101.

[0079] The partial shift of the separation pattern employed in this exemplary embodiment may be implemented to have various patterns. For example, the width of the separation pattern may be adjusted (see Figure 6 ), and the separation pattern may be shifted two or more times in the same first direction (eg, forward direction) (see Figure 7 ).

[0080] Reference Figure 6 , except that the separation pattern SP has a width greater than that of the separation pattern of the previous example embodiment, the semiconductor device 100B according to this example embodiment may be understood to have the same Figures 1 to 3B In addition, unless otherwise specified, the components of this example embodiment may refer to those of the semiconductor device 100 shown in FIG. Figures 1 to 3B The description of the same or similar components of the semiconductor device 100 shown in FIG. 1 should be understood.

[0081] The separation pattern SP adopted in this example embodiment may have a width Pa greater than that of the separation pattern of the previous example embodiment. In this example embodiment, the width Pa of each of the first separation pattern SP1 and the second separation pattern SP2 may be three times the gate pitch P0. The first separation pattern SP1 and the second separation pattern SP2 have the same width. In this example embodiment, the distance of the second separation pattern SP2 shifted from the first separation pattern SP1 to the first direction (e.g., D1 direction) may correspond to the gate pitch P0, and may be appropriately adjusted within a range smaller than the width Pa of the first separation pattern SP1 and the second separation pattern SP2. For example, in this example embodiment, the second separation pattern SP2 may be shifted by twice the gate pitch.

[0082] The separation pattern SP may have a connection separation pattern SP' which is set to a region shifted between the first separation pattern SP1 and the second separation pattern SP2. The connection separation pattern SP' may have a width overlapping each of the first separation pattern SP1 and the second separation pattern SP2 in a second direction (e.g., D2 direction) between the first separation pattern SP1 and the second separation pattern SP2. The connection separation pattern SP' may have a width Pb greater than the respective widths Pa of the first separation pattern and the second separation pattern. For example, the width Pb of the connection separation pattern SP' may have a length obtained by adding the shift distance d to the width Pa of the first separation pattern SP1 and the second separation pattern SP2.

[0083] Reference Figure 7 , except that the semiconductor device 100C has the separation patterns SP shifted in a different manner, the semiconductor device 100C according to this example embodiment may be understood as having the same Figures 1 to 3B In addition, unless otherwise specified, the components of this example embodiment may refer to those of the semiconductor device 100 shown in FIG. Figures 1 to 3B The description of the same or similar components of the semiconductor device 100 shown in FIG. 1 should be understood.

[0084] The separation pattern SP employed in this exemplary embodiment includes Figure 4 The first to third separation patterns SP1, SP2, SP3 are similar to the separation pattern SP shown in FIG. 1 and have patterns shifted in different ways. The second separation pattern SP2 is shifted from the first separation pattern SP1 in a forward direction in a first direction (e.g., D1 direction) by a distance d corresponding to the gate pitch P0, and the third separation pattern SP3 can be shifted from the second separation pattern SP2 in the same forward direction in the first direction (e.g., D1 direction) by a distance d corresponding to the gate pitch P0.

[0085] Also in this example embodiment, the first and second dummy gate structures DG1 and DG2 located at both sides (ie, the first and second sides) of the separation pattern SP may be disconnected and have a shortened length corresponding to the shift period.

[0086] Reference Figure 7, the first dummy gate structure DG1 may be disconnected by being divided into a first dummy gate portion DG1a on a first side of the first separation pattern SP1, a first dummy gate portion DG1b on a first side of the second separation pattern SP2, and a first dummy gate portion DG1c on a first side of the third separation pattern SP3. Similarly, the second dummy gate structure DG2 may be disconnected by being divided into a second dummy gate portion DG2a on a second side of the first separation pattern SP1, a second dummy gate portion DG2b on a second side of the second separation pattern SP2, and a second dummy gate portion DG2c on a second side of the third separation pattern SP3.

[0087] Therefore, the first dummy gate structure DG1 and the second dummy gate structure DG2 are disconnected to have a shortened length, thereby significantly reducing structural defects such as tilt defects. Each dummy gate portion (DG1a, DG1b, DG1c, DG2a, DG2b, DG2c) may be designed to have a length of up to 2 to 6 unit heights CH (e.g., 2 CH) in the second direction (e.g., D2 direction). In some example embodiments, the length of each dummy gate portion DG1a, DG1b, DG1c, DG2a, DG2b, and DG2c may be 1 μm or less (e.g., 900 nm or less).

[0088] According to the above embodiments, the lengths of the first and second dummy gate structures DG1 and DG2 adjacent to the separation pattern SP are shortened by adopting the separation pattern SP shifted in various ways, and thus, defects (e.g., tilting risk) of the first and second dummy gate structures DG1 and DG2 can be improved.

[0089] Figure 8 is a plan view showing a semiconductor device according to example embodiments, Fig.9A and Fig. 9B yes Figure 8 The semiconductor device shown is a cross-sectional view taken along lines I1-I1' and I2-I2', respectively, and Fig. 10A and Fig. 10B yes Figure 8 The semiconductor device shown is a cross-sectional view taken along lines II 1-II 1′ and II 2 -II 2′, respectively.

[0090] Reference Figure 8 , Fig.9A , Fig. 9B , Fig. 10A and Fig. 10B , except that the channel structure is provided with a plurality of active fins (105a1, 105b1 and 105a2, 105b2), the semiconductor device 100D according to this example embodiment may be understood as Figures 1 to 3BThe semiconductor device 100 shown in FIG. 1 is similar to the semiconductor device 100 shown in FIG. 1 . In addition, unless otherwise specified, the components of this example embodiment may refer to the components of the semiconductor device 100 shown in FIG. Figures 1 to 3B The description of the same or similar components of the semiconductor device 100 shown in FIG. 1 should be understood.

[0091] Unlike the multi-channel structure adopted in the previous example embodiment, the channel structure adopted in this example embodiment may include corresponding pairs of first and second groups of active fins 105a1 and 105b1, 105a2 and 105b2, respectively. The active fins 105a and 105b are shown as being provided in pairs, but are not limited thereto, and may be provided individually or in groups of three or more.

[0092] The active fins 105a1, 105b1 and 105a2, 105b2 respectively have structures extending in a first direction (e.g., D1 direction) on the substrate 101 and protruding upward (e.g., D3 direction) from the active region 102. In this example embodiment, each of the active fins 105a1, 105b1 and 105a2, 105b2 may be a structure obtained by separating one fin structure by a separation pattern SP extending in a second direction (e.g., D2 direction).

[0093] The device isolation layer 110 may be disposed on the substrate 101 to define an active region 102 including active fins 105a1 and 105b1 and 105a2 and 105b2. For example, the device isolation layer 110 may include silicon oxide or a silicon oxide-based insulating material. The device isolation layer 110 may be divided into a first device isolation layer 110a defining the active region 102, and a second device isolation layer 110b defining the active fins 105a1 and 105b1 and 105a2 and 105b2 (see FIG. 1 ). Fig. 10A and Fig. 10B ). The first device isolation layer 110a may have a bottom surface deeper than a bottom surface of the second device isolation layer 110b. For example, the first device isolation layer 110a is also referred to as a deep trench isolation (DTI), and the second device isolation layer 110b may also be referred to as a shallow trench isolation (STI). In this example embodiment, the depth of the first trench TR1 and the second trench TR2 of the separation pattern SP may be the same as the depth of the first device isolation layer 110a.

[0094] Similar to Figure 1 In the exemplary embodiment, the separation pattern SP employed in the exemplary embodiment may have a partially shifted pattern. Figure 8As shown, the first dummy gate structure DG1 can be divided into a first dummy gate portion DG1a on a first side of the first separation pattern SP1 and a first dummy gate portion DG1b on a first side of the second separation pattern SP2. Similarly, the second dummy gate structure DG2 can be divided into a second dummy gate portion DG2a on a second side of the first separation pattern SP1 and a second dummy gate portion DG2b on a second side of the second separation pattern SP2. In this way, the lengths of the first dummy gate structure DG1 and the second dummy gate structure DG2 in the second direction (e.g., D2 direction) can be shortened, and structural defects such as the above-mentioned tilt defects can be significantly alleviated.

[0095] The separation pattern SP may have a connection separation pattern SP' provided in an area shifted between the first separation pattern SP1 and the second separation pattern SP2. The connection separation pattern SP' may have a width overlapping each of the first separation pattern SP1 and the second separation pattern SP2 in a second direction (e.g., D2 direction) between the first separation pattern SP1 and the second separation pattern SP2.

[0096] The semiconductor device 100D according to this example embodiment includes power transmission structures arranged along the second direction (e.g., direction D2) in the separation pattern SP. Each of the power transmission structures employed in this example embodiment includes a buried conductive structure 150 and a conductive through structure 170 extending from the second side of the substrate 101 toward the first side and connected to the buried conductive structure 150.

[0097] exist Fig.9A and Fig. 9B In the example embodiment, the buried conductive structure 150 extends to the first side of the substrate 101, and the conductive through structures 170 may penetrate the substrate 101 and respectively contact the bottom surface of the buried conductive structure 150 on the first side of the substrate 101. Each of the conductive through structures 170 receives power from the backside power line PL (or the second power line) located on the second side of the substrate 101, and supplies the power to each logic unit through the buried conductive structure 150. Power may be supplied to the source / drain pattern 120. In this example embodiment, the buried conductive structure 150 may be electrically connected to the source / drain pattern 120 through the first power line PM of the first interconnect structure 210.

[0098] As described above, according to the above example embodiments, by shifting the separation pattern in which the power transmission structure is arranged together with the power transmission structure by a constant width, the structural fragility (eg, tilting risk) of the (dummy) gate structure adjacent to the separation pattern may be reduced.

[0099] Although some example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the inventive concept as defined by the appended claims.

Claims

1. A semiconductor device comprising: a substrate having a first surface and a second surface opposite to each other; a plurality of active patterns, wherein the plurality of active patterns extend along a first direction on the first surface of the substrate respectively; a separation pattern extending in a second direction on the first surface of the substrate, the second direction intersecting the first direction, the separation pattern dividing each of the plurality of active patterns into a first active pattern and a second active pattern, the separation pattern including a first separation pattern and a second separation pattern, the second separation pattern being shifted from the first separation pattern in the first direction to partially overlap with the first separation pattern in the second direction; a first dummy gate structure and a second dummy gate structure, wherein the first dummy gate structure and the second dummy gate structure are respectively located at two sides of the separation pattern, and the first dummy gate structure and the second dummy gate structure respectively extend in the second direction along corresponding ends of the first active pattern and the second active pattern; a plurality of first gate structures and a plurality of second gate structures, wherein the plurality of first gate structures and the plurality of second gate structures cross the first active pattern and the second active pattern respectively, and the plurality of first gate structures and the plurality of second gate structures extend in the second direction; a source / drain pattern at both sides of each of the plurality of first gate structures and the plurality of second gate structures and on the first active pattern and the second active pattern; an interlayer insulating layer on the substrate and covering the source / drain pattern; a contact structure penetrating the interlayer insulating layer and connected to at least one of the source / drain patterns; a plurality of buried conductive structures arranged in the separation pattern and along the second direction, at least one of the plurality of buried conductive structures penetrating the interlayer insulating layer and electrically connected to the contact structure; as well as A plurality of conductive through structures extend from the second surface of the substrate toward the first surface, and the plurality of conductive through structures are respectively connected to the plurality of buried conductive structures.

2. The semiconductor device according to claim 1, wherein The first dummy gate structure located at the first side of the first separation pattern is connected to one of the plurality of first gate structures located at the first side of the second separation pattern, and The second dummy gate structure located at the second side of the second separation pattern is connected to one of the plurality of second gate structures located at the second side of the first separation pattern.

3. The semiconductor device according to claim 1, wherein The plurality of buried conductive structures include first buried conductive structures arranged along the second direction in the first separated pattern and second buried conductive structures arranged along the second direction in the second separated pattern, and The arrangement of the second buried conductive structures is shifted from the arrangement of the first buried conductive structures in the first direction.

4. The semiconductor device according to claim 1, wherein The plurality of first gate structures or the plurality of second gate structures are arranged at a first pitch along the first direction, and A shift distance between the first separated pattern and the second separated pattern in the first direction is equal to the first interval.

5. The semiconductor device according to claim 4, wherein: A width of each of the first separated patterns and the second separated patterns in the first direction is an integral multiple of the first pitch.

6. The semiconductor device according to claim 4, wherein: The first separation pattern and the second separation pattern have the same width.

7. The semiconductor device according to claim 1, wherein A spacing between adjacent buried conductive structures of the plurality of buried conductive structures defines a cell height, and The lengths of the first separation pattern and the second separation pattern in the second direction are equal to the cell height.

8. The semiconductor device according to claim 7, wherein: A length of each of the first separated patterns and the second separated patterns in the second direction is 1 μm or less.

9. The semiconductor device according to claim 1, wherein: The separation pattern includes a connection separation pattern between the first separation pattern and the second separation pattern, the connection separation pattern having a width defined by a spacing between the first dummy gate structure located at a first side of the first separation pattern and the second dummy gate structure located at a second side of the second separation pattern.

10. The semiconductor device according to claim 9, wherein A length of the connection separation pattern in the second direction is equal to a pitch between adjacent buried conductive structures between the first separation pattern and the second separation pattern.

11. The semiconductor device according to claim 1, wherein The separation pattern includes a third separation pattern connected to the second separation pattern in the second direction, the third separation pattern being shifted in the first direction to partially overlap the second separation pattern.

12. The semiconductor device according to claim 11, wherein The width of the third separation pattern in the first direction is equal to the width of the first separation pattern in the first direction, and the third separation pattern overlaps the first separation pattern in the second direction.

13. The semiconductor device according to claim 1, wherein The semiconductor device includes a plurality of channel layers on a corresponding one of the first active pattern and the second active pattern, the plurality of channel layers being spaced apart from each other in a direction perpendicular to the first surface of the substrate, and Each of the plurality of first gate structures and the plurality of second gate structures includes a gate electrode surrounding the plurality of channel layers and extending in the second direction, and a gate insulating film between the plurality of channel layers and the gate electrode.

14. The semiconductor device according to claim 1, wherein The plurality of buried conductive structures extend to the first surface of the substrate, and the plurality of conductive through structures each contact a buried conductive structure on the first surface of the substrate.

15. The semiconductor device according to claim 1, wherein The plurality of buried conductive structures extend into the substrate, and the plurality of conductive through structures each contact a buried conductive structure within the substrate.

16. A semiconductor device comprising: A plurality of active patterns, wherein the plurality of active patterns extend along a first direction on the substrate respectively; a separation pattern extending along a second direction on the substrate, the second direction intersecting the first direction, the separation pattern dividing each of the plurality of active patterns into a first active pattern and a second active pattern, the separation pattern comprising a plurality of first separation patterns and a plurality of second separation patterns alternating with each other in the second direction, the plurality of second separation patterns being shifted from the plurality of first separation patterns in the first direction to partially overlap with the plurality of first separation patterns in the second direction; a first dummy gate structure and a second dummy gate structure, wherein the first dummy gate structure and the second dummy gate structure are respectively located at two sides of the separation pattern, and the first dummy gate structure and the second dummy gate structure respectively extend in the second direction along corresponding ends of the first active pattern and the second active pattern; a plurality of first gate structures and a plurality of second gate structures, wherein the plurality of first gate structures and the plurality of second gate structures cross the first active pattern and the second active pattern respectively, and the plurality of first gate structures and the plurality of second gate structures extend in the second direction; a source / drain pattern at both sides of each of the plurality of first gate structures and the plurality of second gate structures and on the first active pattern and the second active pattern; an interlayer insulating layer on the substrate and covering the source / drain pattern; a contact structure penetrating the interlayer insulating layer and connected to at least one of the source / drain patterns; a plurality of buried conductive structures arranged in the separation pattern and along the second direction, at least one of the plurality of buried conductive structures penetrating the interlayer insulating layer and electrically connected to the contact structure; a plurality of conductive through structures extending from the lower surface of the substrate toward the upper surface of the substrate, the plurality of conductive through structures being respectively connected to the plurality of buried conductive structures; as well as A first interconnect structure is on the interlayer insulating layer, wherein the first interconnect structure comprises a first interconnect layer connecting the contact structure with the plurality of buried conductive structures.

17. The semiconductor device according to claim 16, wherein: The width of each of the plurality of first separation patterns and the plurality of second separation patterns in the first direction is equal to an integral multiple of the pitch between the plurality of first gate structures or the plurality of second gate structures arranged in the first direction, and A length of each of the plurality of first separated patterns and the plurality of second separated patterns in the second direction is 1 μm or less.

18. The semiconductor device according to claim 16, wherein: The separation pattern has a zigzag pattern in a plan view.

19. The semiconductor device according to claim 16, further comprising: A second interconnect structure is on a lower surface of the substrate, the second interconnect structure comprising a second interconnect layer connected to a corresponding one of the plurality of conductive through structures.

20. A semiconductor device comprising: A plurality of active patterns, wherein the plurality of active patterns extend along a first direction on the substrate respectively; a separation pattern extending along a second direction on the substrate, the second direction intersecting the first direction, the separation pattern dividing each of the plurality of active patterns into a first active pattern and a second active pattern, the separation pattern comprising a plurality of first separation patterns and a plurality of second separation patterns alternating with each other in the second direction, the plurality of second separation patterns being shifted from the plurality of first separation patterns in the first direction to partially overlap with the plurality of first separation patterns in the second direction; a first dummy gate structure and a second dummy gate structure, wherein the first dummy gate structure and the second dummy gate structure are respectively located at a first side and a second side of the separation pattern, and the first dummy gate structure and the second dummy gate structure respectively extend in the second direction along corresponding ends of the first active pattern and the second active pattern; as well as a plurality of first gate structures and a plurality of second gate structures, the plurality of first gate structures and the plurality of second gate structures extending in the second direction and respectively crossing the first active pattern and the second active pattern, wherein the first dummy gate structure located at a first side of each of the plurality of first separation patterns is connected to a corresponding one of the plurality of first gate structures located at a first side of an adjacent second separation pattern among the plurality of second separation patterns, and The second dummy gate structure located at a second side of each of the plurality of second separation patterns is connected to a corresponding one of the plurality of second gate structures located at a second side of an adjacent first separation pattern among the plurality of first separation patterns.

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