Three-dimensional memory and manufacturing method thereof

Abstract

The invention provides a three-dimensional memory and a manufacturing method thereof, and the method comprises the steps: forming a stacking layer which comprises dielectric layers and sacrificial layers which are alternately stacked; forming a channel hole penetrating through the stacking layer; removing at least a portion of the sacrificial layer through the channel hole to form a recess; forming a charge storage part in the recess, wherein the charge storage part is arranged between the adjacent dielectric layers; removing the rest part of the sacrificial layer to expose one side, deviating from the channel hole, of the charge storage part; and oxidizing at least one part of the exposed charge storage part away from one side of the channel hole into a blocking part.

Description

[0001] Divisional application

[0002] This application is a divisional application of the Chinese invention patent application with invention name “Three-dimensional memory and manufacturing method thereof” and application number 202111036507.9 filed on September 6, 2021. Technical Field

[0003] The present application relates to the field of semiconductor technology. Specifically, the present application relates to a three-dimensional memory device and a manufacturing method thereof. Background Art

[0004] As the number of stacked layers of three-dimensional memory increases, it is usually necessary to thin the gate layer and dielectric layer in the stack to reduce the overall height of the stack, thereby alleviating the load caused by deep hole etching. However, thinning the thickness of the gate layer and dielectric layer will produce a coupling effect between the storage cells and weaken the data retention ability of the three-dimensional memory.

[0005] It should be understood that this background technology section is intended in part to provide a useful background for understanding the technology, however, these contents are not necessarily what are known or understood by those skilled in the art before the filing date of this application. Summary of the invention

[0006] One aspect of the present application provides a method for manufacturing a three-dimensional memory, the method comprising: forming a stacked layer on a substrate, the stacked layer comprising alternately stacked dielectric layers and sacrificial layers; forming a channel hole penetrating the stacked layer; removing at least a portion of the sacrificial layer through the channel hole to form a recess; forming a charge storage portion in the recess, the charge storage portion being arranged between adjacent dielectric layers; removing the remaining portion of the sacrificial layer to expose the charge storage portion; and oxidizing at least a portion of the exposed charge storage portion into a blocking portion.

[0007] In one embodiment of the present application, the method further includes: forming a gate slit passing through the stacked layer; wherein the step of removing the remaining portion of the sacrificial layer to expose the charge storage portion includes: removing the remaining portion of the sacrificial layer through the gate slit to expose the charge storage portion.

[0008] In one embodiment of the present application, the method further includes: filling a conductive layer in a gap formed by removing the remaining portion of the sacrificial layer through the gate slit.

[0009] In one embodiment of the present application, before forming the charge storage portion, the method further includes:

[0010] An etch stop layer is formed on a portion of the sacrificial layer located on a sidewall of the recess, wherein the etch stop layer comprises polysilicon.

[0011] In one embodiment of the present application, forming the etch stop layer includes: forming an initial etch stop layer on the walls of the sacrificial layer and the dielectric layer exposed to the channel hole; and removing a portion of the initial etch stop layer located on the wall of the dielectric layer to form the etch stop layer on a portion of the sacrificial layer located on the side wall of the recess.

[0012] In one embodiment of the present application, the sacrificial layer has a predetermined first etching selectivity ratio with respect to the charge storage portion, so that the charge storage portion is retained when the sacrificial layer is removed.

[0013] In one embodiment of the present application, forming the charge storage portion includes: forming a storage layer in the recess and on the sidewalls of the dielectric layer; and removing a portion of the storage layer located on the sidewalls of the dielectric layer to form a plurality of discrete charge storage portions in the recess.

[0014] In one embodiment of the present application, a chemical vapor deposition process is performed to form the stacked layer, and an atomic layer deposition process is performed to form the charge storage portion.

[0015] In one embodiment of the present application, before removing the remaining portion of the sacrificial layer, the method further comprises: depositing a tunneling layer, a channel layer and a dielectric core in sequence along the sidewall of the channel hole.

[0016] In one embodiment of the present application, removing the remaining portion of the sacrificial layer includes: etching the remaining portion of the sacrificial layer and stopping at the etch stop layer; and removing the etch stop layer.

[0017] One aspect of the present application provides another method for manufacturing a three-dimensional memory, comprising:

[0018] A stacked layer is formed on a substrate, the stacked layer comprising alternately stacked dielectric layers and sacrificial layers; a channel hole is formed through the stacked layer; at least a portion of the sacrificial layer is removed through the channel hole to form a recess; an etch stop layer is formed on the sidewall of the sacrificial layer; a charge storage portion is formed in the recess, wherein the charge storage portion covers the sidewall of the etch stop layer; the remaining portion of the sacrificial layer is removed to expose the etch stop layer; and the etch stop layer is oxidized to at least a portion of the blocking portion.

[0019] In one embodiment of the present application, forming the etch stop layer includes: forming an initial etch stop layer on the walls of the sacrificial layer and the dielectric layer exposed to the channel hole; and removing a portion of the initial etch stop layer located on the wall of the dielectric layer to form the etch stop layer on a portion of the sacrificial layer located on the side wall of the recess.

[0020] In one embodiment of the present application, forming the charge storage part in the recess includes: forming a storage layer in the recess and on the sidewalls of the dielectric layer; and removing a portion of the storage layer located on the sidewalls of the dielectric layer to form the charge storage part in the recess.

[0021] In one embodiment of the present application, the sacrificial layer has a predetermined second etching selectivity ratio relative to the etch stop layer, so that the etch stop layer is retained when the sacrificial layer is removed.

[0022] In one embodiment of the present application, a chemical vapor deposition process is performed to form the stacked layer, and an atomic layer deposition process is performed to form the charge storage portion.

[0023] In one embodiment of the present application, before removing the remaining portion of the sacrificial layer, the method further comprises: depositing a tunneling layer, a channel layer and a dielectric core in sequence along the sidewall of the channel hole.

[0024] In one embodiment of the present application, oxidizing the etch stop layer into at least a portion of the blocking portion includes: oxidizing the etch stop layer into a portion of the blocking portion; and simultaneously oxidizing a portion of the charge storage portion into the remaining portion of the blocking portion.

[0025] Another aspect of the present application provides a three-dimensional memory, comprising: a stacked structure, including alternatingly stacked conductive layers and dielectric layers; and a channel structure, having a first part passing through the stacked structure and a plurality of second parts arranged between adjacent dielectric layers, the second parts comprising: a plurality of blocking parts, the blocking parts covering the side walls of the corresponding conductive layers facing the first parts; and a plurality of storage parts, the storage parts covering the side walls of the corresponding blocking parts facing the first parts.

[0026] In one embodiment of the present application, the three-dimensional memory further includes: a gate slit structure, including an insulating layer formed in a gate slit penetrating the memory stack structure and a conductive channel formed on the insulating layer.

[0027] In one embodiment of the present application, the first portion includes a tunneling layer, a channel layer, and a dielectric core sequentially stacked on the dielectric layer and the sidewalls of the storage portion.

[0028] In one embodiment of the present application, the blocking portion includes silicon oxynitride or silicon oxide, and the storage portion includes silicon nitride. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Other features, objects and advantages of the present application will become more apparent by reading the detailed description of the non-limiting embodiments made with reference to the following drawings. In the drawings,

[0030] Figure 1 is a flow chart of a method for manufacturing a three-dimensional memory according to the first embodiment of the present application;

[0031] Figure 2 is a partial schematic diagram of a device structure after forming a channel hole according to the three-dimensional memory manufacturing method of the first embodiment of the present application;

[0032] Figure 3 A partial schematic diagram of a device structure formed after removing at least a portion of a sacrificial layer according to the three-dimensional memory manufacturing method of the first embodiment of the present application;

[0033] Figure 4 is a partial schematic diagram of a device structure after forming a storage layer according to the three-dimensional memory manufacturing method of the first embodiment of the present application;

[0034] Figure 5 A partial schematic diagram of a device structure after forming a plurality of charge storage parts according to the method for manufacturing a three-dimensional memory device in accordance with the first embodiment of the present application;

[0035] Figure 6 It is a partial schematic diagram of a device structure formed after the channel hole is filled according to the three-dimensional memory manufacturing method of the first embodiment of the present application;

[0036] Figure 7 It is a partial schematic diagram of a device structure formed after removing the remaining part of the sacrificial layer according to the method for manufacturing a three-dimensional memory device in accordance with the first embodiment of the present application;

[0037] Figure 8 A partial schematic diagram of a device structure after oxidation of a charge storage portion according to a method for manufacturing a three-dimensional memory device in accordance with the first embodiment of the present application;

[0038] Fig. 9 A partial schematic diagram of a device structure after forming a barrier layer in a three-dimensional memory manufacturing method according to some embodiments of the present application;

[0039] Fig.10 It is a partial schematic diagram of a device structure formed after filling a conductive layer according to the three-dimensional memory manufacturing method of the first embodiment of the present application;

[0040] Fig.11 is a partial schematic diagram of a three-dimensional memory according to the first embodiment of the present application;

[0041] Fig.12 is a flow chart of a method for manufacturing a three-dimensional memory according to the second embodiment of the present application;

[0042] Fig.13 A partial schematic diagram of a device structure after an initial etch stop layer is formed according to a three-dimensional memory manufacturing method of a second embodiment of the present application;

[0043] Fig.14 A partial schematic diagram of a device structure after an etch stop layer is formed according to the three-dimensional memory manufacturing method of the second embodiment of the present application;

[0044] Fig.15 A partial schematic diagram of a device structure after forming a storage layer according to a three-dimensional memory manufacturing method of a second embodiment of the present application;

[0045] Fig.16 A partial schematic diagram of a device structure after forming a plurality of charge storage parts according to a three-dimensional memory manufacturing method of a second embodiment of the present application;

[0046] Fig.17 A partial schematic diagram of a device structure formed after the channel hole is filled according to the three-dimensional memory manufacturing method of the second embodiment of the present application;

[0047] Fig.18 It is a partial schematic diagram of a device structure formed after removing the remaining part of the sacrificial layer according to the three-dimensional memory manufacturing method of the second embodiment of the present application;

[0048] Fig.19 It is a partial schematic diagram of a device structure formed after the etching stop layer is oxidized according to the three-dimensional memory manufacturing method of the second embodiment of the present application;

[0049] Fig. 20 A partial schematic diagram of a device structure after the etch stop layer is oxidized and a portion of the charge storage portion is simultaneously oxidized according to the three-dimensional memory manufacturing method of the second embodiment of the present application DETAILED DESCRIPTION

[0050] In order to better understand the present application, a more detailed description will be made of various aspects of the present application with reference to the accompanying drawings. It should be understood that these detailed descriptions are only descriptions of exemplary embodiments of the present application, and do not limit the scope of the present application in any way. Throughout the specification, the same figure numerals refer to the same elements.

[0051] Note that references in the specification to "one embodiment," "an embodiment," "an example embodiment," "some embodiments," etc. indicate that the described embodiment may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Furthermore, these phrases do not necessarily refer to the same embodiment. Furthermore, when a particular feature, structure, or characteristic is described in conjunction with an embodiment, whether or not explicitly described, it will be within the knowledge of a person skilled in the relevant art to implement such feature, structure, or characteristic in conjunction with other embodiments.

[0052] Typically, a term can be understood at least in part from its use in context. For example, depending at least in part on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, terms such as "a" or "the" can also be understood to convey singular usage or to convey plural usage, depending at least in part on the context. In addition, the term "based on" can be understood to not necessarily be intended to convey an exclusive set of factors, and can alternatively allow for the presence of additional factors that are not necessarily explicitly described, which also depends at least in part on the context.

[0053] It should be readily understood that the meaning of “on,” “above,” and “over” in the present disclosure should be interpreted in the broadest manner, so that “on” means not only “directly on something,” but also includes the meaning of “on something” with intervening features or layers therebetween, and “above” or “over” means not only the meaning of “above” or “over” something, but also includes the meaning of being “above” or “over” something without intervening features or layers therebetween (i.e., directly on something).

[0054] In addition, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein for ease of description to describe the relationship of one element or feature to another (multiple) element or (multiple) feature as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and accordingly, the spatially relative descriptors used herein may be similarly interpreted.

[0055] As used herein, the term "layer" refers to a material portion including an area with a thickness. A layer may extend over the entire superstructure or substructure, or may have a range that is smaller than the substructure or superstructure. In addition, a layer may be an area of ​​a uniform or non-uniform continuous structure whose thickness is less than the thickness of the continuous structure. For example, a layer may be between the top surface and the bottom surface of the continuous structure or between any pair of horizontal planes at the top surface and the bottom surface of the continuous structure. A layer may extend horizontally, vertically and / or along a tapered surface. A substrate may be a layer, may include one or more layers therein, and / or may have one or more layers thereon, above it and / or below it. A layer may include multiple layers.

[0056] In the drawings, the thickness, size and shape of the components have been slightly adjusted for ease of illustration. The drawings are for illustration only and are not drawn strictly to scale. For example, as used herein, the terms "substantially," "approximately," and similar terms are used as terms of approximation, not as terms of degree, and are intended to account for inherent deviations in measurements or calculations that would be recognized by one of ordinary skill in the art.

[0057] It should also be understood that the terms "comprises", "including", "having", "includes" and / or "comprising", when used in this specification, indicate the presence of the stated features, elements and / or components, but do not exclude the presence or addition of one or more other features, elements, components and / or combinations thereof. In addition, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire listed features rather than modifying the individual elements in the list. In addition, when describing embodiments of the present application, "may" is used to mean "one or more embodiments of the present application". And, the term "exemplary" is intended to refer to an example or illustration.

[0058] Unless otherwise specified, all words (including engineering terms and scientific and technological terms) used in this article have the same meaning as those commonly understood by ordinary technicians in the field to which this application belongs. It should also be understood that, unless clearly stated in this application, words defined in common dictionaries should be interpreted as having the same meaning as their meaning in the context of the relevant technology, and should not be interpreted in an idealized or overly formal sense.

[0059] It should be noted that, in the absence of conflict, the embodiments and features of the embodiments in this application can be combined with each other. In addition, unless explicitly limited or contradictory to the context, the specific steps included in the method described in this application are not necessarily limited to the order described, but can be performed in any order or in parallel. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0060] When describing the embodiments of the present application, for the sake of convenience, the schematic diagram representing the device structure will not be partially enlarged according to the general proportion, and the schematic diagram is only an example, which should not limit the scope of protection of the present application. In addition, in actual production, a three-dimensional space scale of length, width and depth should be included. It should be understood that the operations shown in the method are not exhaustive, and other operations may also be performed before, after or between any of the operations described.

[0061] Implementation Method 1

[0062] Figure 1 2 is a flow chart of a method 200 for manufacturing a three-dimensional memory device according to the first embodiment. Figure 1 The manufacturing method includes operation S210, forming a stacked layer on a substrate, wherein the stacked layer includes alternately stacked dielectric layers and sacrificial layers.

[0063] like Figure 2 As shown, a stacked layer formed by alternating multiple dielectric layers 101 and sacrificial layers 102 can be formed on a substrate (not shown in the figure), and the preparation material of the substrate can be selected from any suitable semiconductor material, for example, it can be single crystal silicon, polycrystalline silicon, single crystal germanium (Ge), silicon germanium (GeSi), silicon carbide (SiC), silicon on insulator (SOI), germanium on insulator (GOI) or gallium arsenide and other III-V compounds.

[0064] In this step, the substrate has a top surface and a bottom surface opposite to each other, and the top surface of the substrate represents a surface in contact with the stacked layer. A first direction in or parallel to the top surface of the substrate represents an X direction, a second direction in or parallel to the top surface of the substrate represents a Y direction, and a direction perpendicular to the top surface of the substrate represents a Z direction, and a symbol showing a combination of a circle and a cross near the letter "Y" indicates that the Y direction in the figure points inward relative to the drawing page of the figure. In some examples, the dielectric layer 101 and the sacrificial layer 102 may be alternately stacked along the Z direction from the top surface of the substrate.

[0065] In some embodiments, the stacked layer may include a plurality of dielectric layer 101 / sacrificial layer 102 pairs, and the number of pairs may be selected according to various application scenarios, for example, the number of pairs may be 32, 64, 96, 128, 160, 192, 224, 256 or more. In some examples, materials that may be used for the dielectric layer 101 include, but are not limited to, silicon oxide (including doped silicate glass or undoped silicate glass), silicon nitride, silicon oxynitride, organic silicate glass (OSG), spin-on dielectric materials, dielectric metal oxides (e.g., aluminum oxide, hafnium oxide, etc.) and their silicates, dielectric metal oxynitrides and their silicates, and organic insulating materials, which are generally referred to as high dielectric constant (high-k) dielectric oxides. Under the same etching process, the dielectric layer 101 and the sacrificial layer 102 have a high etching selectivity to ensure that the dielectric layer 101 is hardly removed when the sacrificial layer 102 is subsequently removed. As an example, the sacrificial layer 102 may include silicon nitride, and the dielectric layer 101 may include silicon oxide.

[0066] For example, a stacked layer may be formed on the substrate by repeatedly and alternately performing a deposition process of the dielectric layer 101 and the sacrificial layer 102, and the deposition process may include, for example, a thin film deposition process of chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. In some embodiments, due to the increasing requirements for the number of layers of the stacked layer, in order to increase the deposition time to increase the production capacity, a deposition process with a higher deposition rate, such as chemical vapor deposition, is generally used.

[0067] In some embodiments, a step structure may be formed on both sides or in the middle of the stacked layer (not shown). Figure 2 ). The formation of the staircase structure may include repeatedly etching the dielectric layer 101 and the sacrificial layer 102 by using a mask layer (e.g., a patterned photoresist or PR layer) over the stacked layers. Exemplarily, the mask layer may be trimmed to expose the portions of the dielectric layer 101 and the sacrificial layer 102 to be etched, so that the exposed portions may be etched using a suitable etching process. Among them, the etching of the dielectric layer 101 and the sacrificial layer 102 may include a wet etching process, and then the mask layer may be removed. It should be understood that the staircase structure may be formed at any suitable stage of the method for manufacturing a three-dimensional memory device without departing from the teachings of the present invention.

[0068] Back to Figure 1 The method continues to operation S220 , and a channel hole may be formed in a stacked layer formed by alternately stacking sacrificial layers and dielectric layers.

[0069] like Figure 2As shown, after forming the stacked layers, a plurality of channel holes 110 can be formed in the stacked layers. In some embodiments, the plurality of channel holes 110 can be arranged in an array in the stacked layers, and each channel hole 110 can extend vertically through the stacked layers in the Z direction and extend into the substrate. In addition, the channel holes 110 can have a high aspect ratio and can be formed by etching the stacked layers. Exemplarily, a mask layer can be formed on the stacked layers and patterned using, for example, a photolithography process, and then a suitable etching process, such as wet etching, dry etching, or a combination thereof, can be performed to etch the stacked layers into the substrate. In some embodiments, the mask layer can be removed after forming the plurality of channel holes 110.

[0070] Back to Figure 1 The method continues to operation S230, wherein at least a portion of the sacrificial layer may be removed through the channel hole to form a recess, Figure 3 The corresponding structure is shown.

[0071] like Figure 4 As shown, in some embodiments, a portion of each sacrificial layer 102 along the X direction and the Z direction can be removed through the channel hole 110 by an isotropic wet etching process to expose a portion of the top surface and the bottom surface of each dielectric layer 101, so that each adjacent dielectric layer 101 and the sacrificial layer 102 therebetween form a recess 111 along the X direction, and the recess 111 is perpendicular to and communicates with the channel hole 110.

[0072] Back to Figure 1 The method continues to operation S240, wherein a charge storage portion may be formed in each recess, the charge storage portion being disposed between adjacent dielectric layers, Figure 5 The corresponding structure is shown.

[0073] like Figure 4 As shown, in some embodiments, a suitable deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof may be used to form a storage layer 103-1 in the recess (not shown) and on the sidewall of the dielectric layer 101 along the channel hole 110. The storage layer 103-1 may be formed of a material including silicon nitride, silicon oxynitride, silicon or any combination thereof. Then, the portion of the storage layer 103-1 on the sidewall of the channel hole 110 of the dielectric layer 101 is removed, thereby forming a storage layer 103-1 as shown in FIG. Figure 5As shown, multiple discrete charge storage parts 103-2 are provided, wherein the charge storage parts 103-2 can be disposed between adjacent dielectric layers 101. The charge storage parts 103-2 can store charges to perform storage operations, so the film quality of the storage layer 103-1 is relatively high. In some examples, in order to form the storage layer 103-1 with low roughness and high density, an atomic-level deposition process, such as an atomic layer deposition process, is generally used.

[0074] During the operation of the three-dimensional memory device, the multiple charge storage parts 103-2 can reduce the diffusion of the charges stored therein between adjacent memory cells along the Z direction, thereby reducing the charge loss of the storage layer and enhancing the data retention capability of the three-dimensional memory. On the other hand, the coupling effect of the memory cells caused by the uneven distribution of the electric field can be improved, thereby improving the reliability of the three-dimensional memory device.

[0075] like Figure 6 As shown, in some examples, after forming multiple charge storage parts 103-2, a tunneling layer 105, a channel layer 106 and a dielectric core 107 can be deposited in sequence on the side walls of the charge storage parts 103-2 and the dielectric layer 101 radially toward the center of the channel hole 110 by a thin film deposition process such as CVD, PVD, ALD or any combination thereof, wherein the charges of the charge storage parts 103-2 can be tunneled into the channel layer 106 via the tunneling layer 105 and transmitted in the channel layer 106.

[0076] Exemplary materials for the tunneling layer 105 may include silicon oxide, silicon nitride, silicon oxynitride, high-K dielectric materials such as aluminum oxide or hafnium oxide. Materials for the channel layer 106 may include one or more semiconductor materials, for example, single element semiconductor materials, III-V compound semiconductor materials, II-VI compound semiconductor materials, and / or organic semiconductor materials. In some embodiments, the channel layer 106 may include a polysilicon layer to facilitate charge transport.

[0077] In some examples, the dielectric core 107 may include a suitable dielectric material, such as silicon oxide, and may fill the remaining space of the channel hole 110 surrounded by the channel layer 106 .

[0078] Back to Figure 1 , the method continues to operation S250, wherein the remaining portion of the sacrificial layer may be removed to expose the charge storage portion, Figure 7 In some examples, after forming a portion of the channel structure, a gate slit ( Figure 7(not shown). For example, a gate slit ( Figure 7 not shown).

[0079] Then, the remaining portion of the sacrificial layer 102 is removed through the gate slit, thereby exposing the sidewalls of the plurality of charge storage portions 103-2 on the side away from the channel hole. At the same time, the remaining portions of the top and bottom surfaces of the dielectric layer 101 can also be exposed, so that adjacent dielectric layers 101 and the charge storage portions 103-2 therebetween form a gap 112 that is perpendicular to and communicates with the gate slit.

[0080] In some embodiments, the process of removing the remaining portion of the sacrificial layer 102 may include isotropic wet etching. Under the same wet etching process, the sacrificial layer 102 has a higher etching selectivity than the charge storage portion 103-2, so the charge storage portion 103-2 is hardly damaged.

[0081] In some embodiments, the sacrificial layer 102 and the charge storage part 103-2 may include silicon nitride at the same time. While ensuring that the nitrogen-silicon ratio of the charge storage part 103-2 can achieve better storage performance, the ratio of nitrogen and silicon in the sacrificial layer 102 can be adjusted to make it have a large difference from the ratio of nitrogen and silicon included in the charge storage part 103-2, thereby enabling selective etching.

[0082] In some examples, when the sacrificial layer 102 and the charge storage portion 103 - 2 both include silicon nitride, both may be doped to change the element type, thereby enabling selective etching.

[0083] Back to Figure 1 The method continues to operation S260, wherein at least a portion of the exposed charge storage portion may be oxidized into a blocking portion, Figure 8 The corresponding structure is shown.

[0084] like Figure 8 As shown, in some examples, after the gap 112 is formed, the gate slit ( Figure 8), a portion of the plurality of charge storage portions 103-2 (e.g., silicon nitride) away from the channel hole 110 is oxidized into a plurality of blocking portions (e.g., silicon oxide or silicon oxynitride) by a thermal oxidation process and / or a chemical oxidation process to form a plurality of blocking portions 104 and a final storage portion 103. For example, thermal oxidation may include an in-situ steam process that uses oxygen and hydrogen to generate water in the form of steam. Exemplary materials for the blocking portions 104 may include silicon oxide, silicon nitride, silicon oxynitride, a high-K dielectric material such as aluminum oxide or hafnium oxide. As an alternative, the channel structure may include a silicon-oxide-nitride-oxide (SONO) structure.

[0085] The manufacturing method provided in the present application can directly oxidize the charge storage part 103 - 2 after removing the remaining part of the sacrificial layer 102 , thereby reducing the quality damage of the charge storage part 103 - 2 caused by excessive etching processes.

[0086] In some embodiments, Fig. 9 As shown, after the recess 111 is formed, a barrier layer 104' can be first formed on the inner wall of the recess 111 and the dielectric layer 111. The formed barrier layer 104' often occupies a certain space in the direction perpendicular to the substrate (Z direction), which reduces the utilization rate of the vertical space by the gate layer formed in the subsequent steps, thereby reducing the number of layers of the stacked structure, resulting in a decrease in storage capacity.

[0087] like Fig.10 As shown, in some embodiments, after forming the blocking portion 104, the gate slit ( Fig.10 (not shown) in the gap 112 ( Figure 8 ) is filled with a conductive layer 108. As an example, the conductive layer 108 can be used as a gate layer of a three-dimensional memory.

[0088] Exemplarily, the materials used to form the conductive layer 108 include conductive materials, which may include W, Co, Cu, Al, Ti, Ta, TiN, TaN, Ni, doped silicon, silicide (e.g., NiSix, WSix, CoSix, TiSix), or any combination thereof.

[0089] In some embodiments of the present application, a charge storage portion 103-2 is first formed in the recess 111, and its size in the z direction can be the same as the size of the conductive layer 108 in the z direction, and then at least a portion of the charge storage portion 103-2 is oxidized to form a blocking portion 104, and the size of the blocking portion 104 in the z direction can be the same as the size of the conductive layer 108 in the z direction, and will not occupy the vertical space of the conductive layer 108. At the same stacking height, more layers of the dielectric 101 layer and the conductive layer 108 can be stacked, thereby increasing the storage capacity. Moreover, the blocking portion 104 formed by oxidizing the charge storage portion 103-2 has better film density and uniformity, which can effectively reduce the leakage of charges.

[0090] In some embodiments, an insulating layer may be formed in the gate slit (not shown) and a conductive channel may be formed on the insulating layer, wherein the insulating layer may be used to electrically isolate the conductive layer 108 from the conductive channel, and the conductive channel may serve as a lead-out channel for electrically connecting a common source line.

[0091] Another aspect of the present application provides a three-dimensional memory 100, such as Fig.11 As shown, the three-dimensional memory 100 includes: a substrate ( Fig.11 ), a stacked structure 109 formed on a substrate, and a channel structure 119 formed in the stacked structure 109. The stacked structure 109 includes alternately stacked dielectric layers 101 and conductive layers 108, the conductive layer 108 can be used as a gate layer, and a memory cell can be formed at the intersection of the gate layer and the channel structure 119. As an example, the dielectric layer 101 may include silicon oxide, and the conductive layer 108 may include W.

[0092] Reference again Fig.11 The channel structure 119 may include a first portion 120 vertically passing through the stack structure 109 and a plurality of second portions 121 disposed between adjacent dielectric layers 101 , and the first portion 120 and the second portion 121 between each adjacent dielectric layer 101 may remain connected.

[0093] In some examples, the second portion 121 includes a plurality of discrete blocking portions 104 and a plurality of discrete storage portions 103 , wherein the blocking portions 104 may cover the side walls of the corresponding conductive layer 108 facing the first portion 120 , and the storage portions 103 may cover the side walls of the corresponding blocking portions 104 facing the first portion 120 .

[0094] In some examples, the size of the blocking portion 104 and the storage portion 103 in the Z direction is the same as the size of the conductive layer 108 in the same direction, so that in the Z direction, the blocking portion can directly contact the inner surface of the adjacent dielectric layer 101. Therefore, the blocking portion 104 will not occupy the vertical space of the conductive layer 108 in the Z direction. At the same stacking height, more layers of dielectric 101 and conductive layer 108 can be stacked, thereby increasing the storage capacity.

[0095] During the operation of the three-dimensional memory device, the storage portion 103 can, on the one hand, prevent the stored charge from diffusing between adjacent memory cells, reduce the charge loss of the storage portion 103, and enhance the data retention capability of the three-dimensional memory; on the other hand, it can improve the coupling effect of the memory cells caused by the uneven electric field distribution, and improve the reliability of the three-dimensional memory device.

[0096] In some examples, the first portion 120 includes a tunneling layer, a channel layer, and a dielectric core (not shown) sequentially stacked on the sidewalls of the dielectric layer 101 and the storage portion 103 .

[0097] Exemplarily, the blocking portion 104 may include silicon oxide or silicon oxynitride, which may reduce leakage of charge; the storage portion 103 may include silicon nitride, which may capture and store charge, which may tunnel through a tunneling layer (not shown in the figure) into a channel layer (not shown in the figure) and may be transmitted in the channel layer (not shown in the figure). In some embodiments, the tunneling layer (not shown in the figure) may include silicon oxide, and the channel layer (not shown in the figure) may include a polysilicon layer for facilitating charge transmission.

[0098] In some examples, the three-dimensional memory 100 further includes a gate slit structure ( Fig.11 The structure 108 is a gate electrode slit formed through the stacked structure 109 and the insulating layer and the conductive channel are filled therein. The insulating layer can be used to electrically isolate the conductive layer 108 from the conductive channel, and the conductive channel can be used as an extraction channel for electrically connecting the common source line.

[0099] Implementation Method 2

[0100] When the sacrificial layer 102 and the charge storage portion 103-2 both include silicon nitride, when the etching process is used to remove the remaining portion of the sacrificial layer 102, some embodiments can select a suitable etching process by increasing the material difference between the sacrificial layer 102 and the charge storage portion 103-2. In some embodiments, an etching stop layer having a material difference from the charge storage portion 103-2 and the sacrificial layer 102 can be formed between the charge storage portion 103-2 and the sacrificial layer, thereby separating the charge storage portion 103-2 from the sacrificial layer.

[0101] Fig.12FIG. 3 is a flow chart of a method 300 for manufacturing a three-dimensional memory according to a second embodiment. The memory manufacturing method according to the second embodiment includes operations S210, S220, and S230. Fig.12 S210, S220 and S230 in the second embodiment are similar to the steps of forming a stacked layer on the substrate and forming a channel hole 110 through the stacked layer in the first embodiment. Figure 2 ) and the process of removing at least a portion of the sacrificial layer 102 through the channel hole 110 to form the recess 111 are the same, so a detailed description thereof is omitted.

[0102] like Fig.12 As shown, the operation continues to S340 , and an etch stop layer may be formed on a portion of the sacrificial layer located on a sidewall of the recess.

[0103] like Fig.13 As shown, an appropriate deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof may be used to form an initial etch stop layer 130' on the walls of the sacrificial layer 102 and the dielectric layer 101 exposed to the channel hole 110. The initial etch stop layer 130' has a certain difference in material from the sacrificial layer 102. Then, as shown in FIG. Fig.14 As shown, the portion of the initial etch stop layer 130 ′ located on the wall of the dielectric layer 101 may be removed, thereby forming an etch stop layer 130 on the sidewall of the sacrificial layer 102 in the recess 111 .

[0104] In some examples, the portion of the initial etch stop layer 130' located on the wall of the dielectric layer 101 can be removed by an etching process, wherein the initial etch stop layer 130' has a predetermined range of etching selectivity relative to the dielectric layer 101, and the range of the etching selectivity can be, for example, 2500 to 1000: 1. Due to the higher etching selectivity, when etching the initial etch stop layer 130', the dielectric layer 101 exposed to the etching environment is less lost.

[0105] In some embodiments, the etching process of the channel hole 110 will cause etching loss to the dielectric layer 101 on the side wall of the channel hole 110 to a certain extent, causing the radial size of the channel hole 110 to increase. Under a certain storage area, the number of channel holes 110 will decrease, thereby reducing the storage density.

[0106] In some examples, the dielectric layer 101 includes silicon oxide, the initial etch stop layer 130' includes polysilicon, and the first etch selectivity ratio may be 1000. Compared with when the initial etch stop layer 130' is other materials with lower etch selectivity ratios, when the initial etch stop layer 130' includes polysilicon, the loss of the dielectric layer 101 along the sidewall of the channel hole 110 is relatively reduced, and the loss of storage density caused by the etching process through the channel hole 110 can be reduced.

[0107] In some examples, by adjusting the etching conditions, the first etching selection may also be 1500.

[0108] Back to Fig.12 The operation continues to S350 , and a charge storage portion may be formed in the recess, wherein the charge storage portion covers a sidewall of the etch stop layer.

[0109] In some embodiments, Fig.15 As shown, after forming the etching stop layer 130, a storage layer 103-1 can be formed in the recess (not shown) and on the sidewall of the dielectric layer 101 along the channel hole 110 by using a suitable thin film deposition process. The forming material includes silicon nitride, silicon oxynitride, silicon or any combination thereof. Then, the portion of the storage layer 103-1 located on the sidewall of the dielectric layer 101 is removed, thereby forming Fig.16 The charge storage portion 103-2 shown in the figure can cover the sidewall of the etch stop layer 130 facing the channel hole 110. The charge storage portion 103-2 can store charges to perform storage operations, so the film quality of the storage layer 103-1 is relatively high. In some examples, in order to form the storage layer 103-1 with low roughness and high density, an atomic-level deposition process, such as an atomic layer deposition process, is generally used.

[0110] During the operation of the three-dimensional memory device, the plurality of discrete charge storage portions 103-2 can reduce the diffusion of the charges stored therein between adjacent memory cells along the Z direction, thereby reducing the charge loss of the storage layer 103-1 and enhancing the data retention capability of the three-dimensional memory. On the other hand, the coupling effect of the memory cells caused by the uneven electric field distribution can be improved, thereby improving the reliability of the three-dimensional memory device.

[0111] In some examples, such as Fig.17 As shown, after forming a plurality of charge storage parts 103 - 2 , a tunneling layer 105 , a channel layer 106 and a dielectric core 107 are sequentially deposited radially toward the center of the channel hole 110 on the sidewalls of the charge storage parts 103 - 2 and the dielectric layer 101 .

[0112] In some examples, the tunneling layer 105 , the channel layer 106 , and the dielectric core 107 may be formed using the same deposition process and materials as those in the first embodiment, which will not be described in detail herein.

[0113] Back to Fig.12 The operation continues to S360 , and the remaining portion of the sacrificial layer may be removed to expose the etch stop layer.

[0114] In some embodiments, a gate slit (not shown) may be formed in the stacked layer to penetrate the stacked dielectric layer 101 and the sacrificial layer 102. The remaining portion of the sacrificial layer 102 is then removed through the gate slit to expose the etch stop layer 130 on the side away from the channel hole.

[0115] like Fig.18 As shown, when removing the rest of the sacrificial layer 102, a suitable etching process may be used to make the sacrificial layer 102 have a higher etching selectivity than the etch stop layer 130, so that when etching and removing the sacrificial layer 102, the etching may stop at a surface of the etch stop layer 130 away from the channel hole 110. At the same time, the rest of the top and bottom surfaces of the dielectric layer 101 may also be exposed, so that the adjacent dielectric layers 101 and the etch stop layer 130 therebetween form a gap 112 that is perpendicular to and communicates with the gate slit.

[0116] Back to Fig.12 Then, the operation proceeds to S370 , and the etch stop layer may be oxidized into at least a portion of the blocking portion.

[0117] In some embodiments, the etch stop layer 130 includes, for example, polysilicon. Fig.18 and 19 As shown, the etch stop layer 130 can be oxidized into a plurality of blocking portions 104 (e.g., silicon oxide) through a gate slit (not shown) by, for example, a chemical oxidation process including ozone. Compared to some embodiments in which the etch stop layer 130 includes silicon nitride, at a similar oxidation temperature, in some embodiments in which the etch stop layer 130 includes polysilicon, the oxidation rate of the etch stop layer 130 is relatively high, and the ratio of the oxidation rate is in the range of 400-800:1.

[0118] In some embodiments, Fig. 20 As shown, the etch stop layer 130 includes, for example, polysilicon, and the etch stop layer 130 and a portion of the charge storage portion 103-2 may be oxidized to form the blocking portion 104. For example, the etch stop layer 130 may be oxidized to form a portion of the blocking portion 104 through a suitable oxidation process, and a portion of the charge storage portion 103-2 in contact with the etch stop layer 130 may be oxidized to form the remaining portion of the blocking portion 104, thereby forming the final storage portion 103.

[0119] In some embodiments, after forming the plurality of blocking portions 104 , a conductive layer may be filled in the gap through the gate slit in a suitable step, and the conductive layer may serve as a gate layer of the three-dimensional memory.

[0120] In some embodiments, after removing the remaining portion of the sacrificial layer 102, the etch stop layer 130 may be removed by a suitable etching process to expose the charge storage portion 103-2 on the side away from the channel hole 110, and then at least a portion of the charge storage portion 103-2 may be oxidized into the blocking portion 104 by a thermal oxidation process and / or a chemical oxidation process. For example, the thermal oxidation may include an in-situ steam method that uses oxygen and hydrogen to generate water in the form of steam. The device structure formed by the three-dimensional memory manufacturing method of the second embodiment may be the same as the structure of the three-dimensional memory 100 of the first embodiment, and will not be described in detail here.

[0121] The above description is only an implementation method of the present application and an explanation of the technical principles used. Those skilled in the art should understand that the scope of protection involved in the present application is not limited to the technical solution formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the technical concept. For example, the above features are replaced with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A method for manufacturing a three-dimensional memory, comprising: forming a stacked layer, wherein the stacked layer comprises dielectric layers and sacrificial layers that are alternately stacked; forming a channel hole penetrating the stacked layers; removing at least a portion of the sacrificial layer through the channel hole to form a recess; forming a charge storage portion in the recess, wherein the charge storage portion is disposed between adjacent dielectric layers; removing the remaining portion of the sacrificial layer to expose a side of the charge storage portion facing away from the channel hole; as well as At least a portion of the exposed charge storage portion on a side facing away from the channel hole is oxidized into a blocking portion.

2. The manufacturing method according to claim 1, characterized in that: The method further includes: forming a gate slit penetrating the stacked layer; The step of removing the remaining portion of the sacrificial layer to expose the charge storage portion comprises: The remaining portion of the sacrificial layer is removed through the gate slit to expose the charge storage portion.

3. The manufacturing method according to claim 2, characterized in that: The method further comprises: A conductive layer is filled in a gap formed by removing the remaining portion of the sacrificial layer through the gate slit.

4. The manufacturing method according to claim 1, characterized in that: Before forming the charge storage portion, the method further comprises: An etch stop layer is formed on a portion of the sacrificial layer located on a sidewall of the recess.

5. The manufacturing method according to claim 4, characterized in that: Forming the etch stop layer comprises: forming an initial etch stop layer on the sacrificial layer and the walls of the dielectric layer exposed to the channel hole; and The portion of the initial etch stop layer located on the wall of the dielectric layer is removed to form the etch stop layer on the portion of the sacrificial layer located on the sidewall of the recess.

6. The manufacturing method according to any one of claims 1 to 5, characterized in that: Forming the charge storage portion includes: forming a storage layer in the recess and on the sidewalls of the dielectric layer; and A portion of the storage layer located on the sidewall of the dielectric layer is removed to form a plurality of discrete charge storage portions in the recess.

7. The manufacturing method according to claim 1, characterized in that: A chemical vapor deposition process is performed to form the stacked layers, and an atomic layer deposition process is performed to form the charge storage portion.

8. The manufacturing method according to claim 4 or 5, characterized in that: Removing the remaining portion of the sacrificial layer comprises: etching the remaining portion of the sacrificial layer and stopping at the etch stop layer; and The etch stop layer is removed.

9. A method for manufacturing a three-dimensional memory, comprising: forming a stacked layer, wherein the stacked layer comprises dielectric layers and sacrificial layers that are alternately stacked; forming a channel hole penetrating the stacked layers; removing at least a portion of the sacrificial layer through the channel hole to form a recess; forming an etch stop layer on the sidewalls of the sacrificial layer; forming a charge storage portion in the recess, wherein the charge storage portion covers a sidewall of the etch stop layer; removing a remaining portion of the sacrificial layer to expose a side of the etch stop layer facing away from the channel hole; and The etch stop layer is oxidized into at least a portion of the barrier portion.

10. The manufacturing method according to claim 9, characterized in that: Forming the etch stop layer comprises: forming an initial etch stop layer on the sacrificial layer and the walls of the dielectric layer exposed to the channel hole; and The portion of the initial etch stop layer located on the wall of the dielectric layer is removed to form the etch stop layer on the portion of the sacrificial layer located on the sidewall of the recess.

11. The manufacturing method according to claim 10, characterized in that: The forming the charge storage portion in the recess comprises: forming a storage layer in the recess and on the sidewalls of the dielectric layer; and A portion of the storage layer located on the sidewall of the dielectric layer is removed to form the charge storage portion in the recess.

12. The manufacturing method according to claim 9, characterized in that: A chemical vapor deposition process is performed to form the stacked layers, and an atomic layer deposition process is performed to form the charge storage portion.

13. The manufacturing method according to claim 9, characterized in that: Oxidizing the etch stop layer into at least a portion of the blocking portion includes: The etch stop layer is oxidized into a portion of the blocking portion; and a portion of the charge storage portion is simultaneously oxidized into a remaining portion of the blocking portion.

14. Three-dimensional memory, including: A stacked structure comprising alternately stacked conductive layers and dielectric layers; as well as A channel structure having a first portion passing through the stacked structure and a plurality of second portions disposed between adjacent dielectric layers, wherein the first portion comprises a tunneling layer, a channel layer and a dielectric core sequentially stacked on the dielectric layer and the sidewalls of the storage portion; The second part includes: a plurality of blocking portions, the blocking portions covering corresponding side walls of the conductive layer facing the first portion; and a plurality of storage portions, the storage portions covering the side walls of the corresponding blocking portions facing the first portion; Wherein, the material of the blocking part includes silicon oxide and high-K dielectric material.

15. The three-dimensional memory according to claim 14, further comprising: The gate slit structure includes an insulating layer formed in the gate slit penetrating the memory stack structure and a conductive channel formed on the insulating layer.

16. The three-dimensional memory according to claim 14, characterized in that: The blocking portion further includes silicon oxynitride, and the storage portion includes silicon nitride.

17. The three-dimensional memory according to claim 14, characterized in that: The high-K dielectric material includes aluminum oxide or hafnium oxide.

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