Memory, preparation method thereof and electronic equipment

Abstract

The invention discloses a memory, a preparation method thereof and electronic equipment, and relates to the technical field of semiconductor storage. The memory comprises a substrate, a plurality of memory arrays, a filling structure and an isolation side wall. Wherein the storage array comprises a plurality of storage units, each storage unit comprises a transistor and at least one capacitor which are arranged in a stacked mode, and the at least one capacitor is electrically connected to the side, away from the substrate, of the transistor. In the direction parallel to the substrate, the filling structure is located between the transistors of the two adjacent storage arrays. The isolation side wall is located on the side, away from the substrate, of the filling structure and located between the capacitors of the two adjacent storage arrays in the direction parallel to the substrate. Through the arrangement of the filling structure, the structural density of the area between the adjacent storage arrays is increased, during the technological process, the technological defect of the film layer structure of the edge area of the storage array can be improved, and the phenomenon that the performance of the transistor located in the edge area of the storage array is degraded is further improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor storage technology, and in particular to a memory device and a method for preparing the same, and an electronic device. Background Art

[0002] With the explosive development of information, the development direction of storage technology is higher storage density to obtain higher storage capacity, and thus, three-dimensional (3D) memory came into being. A three-dimensional memory usually includes a plurality of storage arrays for storing data, and the storage array is stacked vertically upward on the substrate to form a 3D structure. Among them, the storage array may include a plurality of storage cells, each of which includes a metal oxide semiconductor field effect transistor (metal-oxide-semiconductor field-effect transistor, MOSFET), and at least one capacitor electrically connected to the transistor. However, in the storage cells located at the edge of the storage array of the related art, the transistors are prone to performance degradation. Summary of the invention

[0003] The embodiments of the present application provide a memory and a method for manufacturing the same, and an electronic device, which are used to improve the phenomenon that performance degradation easily occurs to transistors in memory cells located at the edge of a memory array.

[0004] To achieve the above objectives, the embodiments of the present application adopt the following technical solutions:

[0005] In a first aspect, a memory is provided. The memory includes: a substrate, a plurality of memory arrays, a filling structure, an insulating portion, and an isolation sidewall. The plurality of memory arrays are located on the substrate, the memory arrays include a plurality of memory cells, the memory cells include transistors and at least one capacitor stacked along a first direction, at least one capacitor is electrically connected to a side of the transistor facing away from the substrate; the first direction is perpendicular to the substrate. The filling structure is located on the substrate, and in a direction parallel to the substrate, the filling structure is located between transistors of two adjacent memory arrays. The isolation sidewall is located on a side of the filling structure facing away from the substrate, and in a direction parallel to the substrate, the isolation sidewall is located between capacitors of two adjacent memory arrays.

[0006] When making a storage array, it is necessary to use etching (Etch), Chemical Mechanical Polishing (CMP) and other processes to make transistors. It is understandable that the transistor structures of multiple storage arrays need to be made simultaneously through the above-mentioned processes. Since the structural density of the isolation area is quite different from the structural density of the edge area, when performing the above-mentioned process, process defects may occur in the film layer structure located in the edge area (for example, the film layer structure is concave and deformed), which in turn causes the performance of the transistor located in the edge area to degrade. Here, "isolation area" refers to the area located between adjacent storage arrays, and "edge area" refers to the area located at the edge of the storage array. Here, "structural density" refers to the number of transistors per unit area of ​​the area. Here, "performance degradation" refers to phenomena such as excessive off-state current of the transistor.

[0007] By setting a filling structure between two adjacent memory arrays, the structural density in the isolation area is increased, thereby reducing the difference in structural density between the edge area of ​​the memory array and the isolation area. During the process, the process defects of the film layer structure in the edge area of ​​the memory array can be improved, thereby improving the performance degradation of the transistors in the edge area of ​​the memory array.

[0008] In some implementations, the filling structure includes a dummy transistor, at least part of the dummy transistor is arranged in the same layer as at least part of the transistor, and the dummy transistor is arranged at intervals from the transistor. The above arrangement is conducive to simplifying the manufacturing process of the filling structure and improving the manufacturing efficiency and manufacturing cost of the memory. At the same time, by arranging the dielectric part of the conductive line and the second electrode of the dummy transistor in the same layer, the dummy transistor does not have a control function, which is also conducive to avoiding interference of the dummy transistor with other transistors, and is conducive to improving the performance of the storage array.

[0009] In some implementations, the first pole of the transistor and the second pole of the transistor are arranged along a first direction, the first pole of the transistor is electrically connected to at least one capacitor, the channel layer of the transistor is located between the first pole of the transistor and the second pole of the transistor, and the gate of the transistor surrounds the channel layer of the transistor. The first pole of the virtual transistor and the second pole of the virtual transistor are arranged along the first direction, the first pole of the virtual transistor is connected to the isolation sidewall, the channel layer of the virtual transistor is located between the first pole of the virtual transistor and the second pole of the virtual transistor, and the gate of the transistor surrounds the channel layer of the transistor. Among them, the first pole of the transistor and the first pole of the virtual transistor are arranged in the same layer, the channel layer of the transistor and the channel layer of the virtual transistor are arranged in the same layer, and the gate of the transistor and the gate of the virtual transistor are arranged in the same layer. Through the above arrangement, it is helpful to simplify the manufacturing process of the filling structure and improve the manufacturing efficiency and manufacturing cost of the memory.

[0010] In some implementations, a plurality of storage cells are arranged at intervals along the second direction, and a plurality of storage cells are arranged at intervals along the third direction; the second direction and the third direction are both perpendicular to the first direction, and the second direction intersects with the third direction. The memory also includes a plurality of conductive lines arranged at intervals along the third direction, the extension direction of the conductive lines is parallel to the second direction, the conductive lines include a plurality of conductive parts and a plurality of dielectric parts, the conductive parts and the dielectric parts are alternately arranged along the second direction, the conductive parts are arranged in the same layer and in contact with the second pole of the transistor, and the dielectric parts are arranged in the same layer and in contact with the second pole of the virtual transistor. The memory also includes a plurality of bit lines arranged at intervals along the third direction, the bit lines are located between the conductive lines and the substrate, the extension direction of the bit lines is parallel to the second direction, and the bit lines are electrically connected to the conductive parts of the conductive lines. Through the above arrangement, it is conducive to simplifying the manufacturing process of transistors and virtual transistors, and can improve the manufacturing efficiency and manufacturing cost of the memory. At the same time, the virtual transistor does not have a control function, which is also conducive to avoiding the virtual transistor from interfering with other transistors, and is conducive to improving the performance of the storage array.

[0011] In some implementations, a plurality of memory cells are arranged at intervals along the second direction, and a plurality of memory cells are arranged at intervals along the third direction; the second direction and the third direction are both perpendicular to the first direction, and the second direction intersects the third direction. There are a plurality of virtual transistors located between two adjacent memory arrays, and the plurality of virtual transistors are arranged at intervals along the third direction, and the virtual transistors and the plurality of transistors arranged along the second direction are arranged at intervals in the second direction. Through the above arrangement, the structural density of each row of transistors located in the isolation area can be increased, which is conducive to further reducing the structural density difference between the edge area of ​​the memory array and the isolation area, improving the process defects of the film layer structure of each row in the edge area of ​​the memory array, and further improving the performance degradation of the transistors located in the edge area of ​​the memory array.

[0012] In some implementations, a row of virtual transistors arranged along the third direction constitutes a virtual transistor group, the number of virtual transistor groups located between two adjacent memory arrays is multiple, and the multiple virtual transistor groups are arranged at intervals along the second direction. By increasing the number of virtual transistor groups, it is beneficial to further increase the structural density of each row of transistors located in the edge area of ​​the memory array, further reduce the difference in structural density between the edge area of ​​the memory array and the isolation area, improve the process defects of the film layer structure of each row in the edge area of ​​the memory array, and further improve the phenomenon of performance degradation of transistors located in the edge area of ​​the memory array.

[0013] In some implementations, the distance between the virtual transistors and the transistors arranged and adjacent to each other along the second direction is equal to the distance between the two transistors arranged and adjacent to each other along the second direction. The above arrangement is conducive to further reducing the difference in structural density between the edge region of the memory array and the isolation region, improving the process defects of the film layer structure of each row in the edge region of the memory array, and further improving the phenomenon of performance degradation of the transistors located in the edge region of the memory array.

[0014] In some implementations, the distance between two adjacent dummy transistors arranged along the second direction is equal to the distance between two adjacent transistors arranged along the second direction. The above arrangement is conducive to further reducing the difference in structural density between the edge region of the memory array and the isolation region, improving the process defects of the film layer structure of each row in the edge region of the memory array, and further improving the performance degradation of the transistors located in the edge region of the memory array. At the same time, the above arrangement is also conducive to increasing the regularity of the arrangement of the dummy transistors and the transistors.

[0015] In some implementations, the memory further includes a plurality of word lines spaced apart along the second direction, the word lines extending in a direction parallel to the third direction, at least one word line being electrically connected to the gates of a row of transistors arranged along the third direction, and at least one word line being electrically connected to the gates of a row of dummy transistors arranged along the third direction. Such an arrangement is conducive to simplifying the manufacturing process of transistors and dummy transistors, and improving the manufacturing efficiency and manufacturing cost of the memory.

[0016] In some implementations, the filling structure includes a support block, and the material of the support block includes an insulating material. Through the above arrangement, the film layer structure of the support block is simple, which is conducive to improving the regularity of the filling structure, thereby further improving the role of the support block in providing mechanical support and / or load balancing. At the same time, by setting the material of the support block to an insulating material, it is also helpful to avoid the support block from interfering with other transistors, which is conducive to improving the performance of the storage array.

[0017] In some implementations, the memory further includes an insulating portion, the insulating portion is located between the filling structure and the memory array, the insulating portion is also located between the isolation sidewall and the memory array, and the insulating portion and the filling structure are made of different materials. Here, "different materials" means that the insulating portion and at least part of the film layer of the filling structure are made of different materials. For example, the insulating portion and all the film layers of the filling structure are made of different materials, or the insulating portion and part of the film layers of the filling structure are made of different materials. Through the above arrangement, the insulating portion can achieve an isolation effect between the isolation sidewall and the memory array, and can also achieve an isolation effect between the filling structure and the memory array.

[0018] In some implementations, the capacitor is a ferroelectric capacitor. Through the above configuration, the memory is a ferroelectric memory, which has the characteristics of non-volatile stored data and fast access rate.

[0019] In a second aspect, a method for preparing a memory is also provided. The preparation method comprises: providing a substrate. Forming a plurality of memory arrays and filling structures, wherein the plurality of memory arrays and filling structures are all located on the substrate; wherein the memory array comprises a plurality of memory cells, the memory cells comprise transistors and at least one capacitor stacked along a first direction, and the at least one capacitor is electrically connected to a side of the transistor away from the substrate; the first direction is perpendicular to the substrate; and the filling structure is located between two adjacent memory arrays. Forming an isolation sidewall, the isolation sidewall is located on a side of the filling structure away from the substrate and is located between two adjacent memory arrays.

[0020] In some implementations, after providing the substrate and before forming a plurality of memory arrays and a filling structure, the preparation method further includes: forming a plurality of bit lines spaced apart along a third direction and a plurality of intermediate conductive lines spaced apart along the third direction, the intermediate conductive lines being located on the side of the bit lines away from the substrate, and the extension directions of the bit lines and the intermediate conductive lines being parallel to the second direction; the second direction and the third direction are both perpendicular to the first direction, and the second direction intersects the third direction. Removing part of the intermediate conductive lines to form a plurality of spaced apart grooves, wherein the intermediate conductive lines between adjacent grooves constitute conductive parts. Forming dielectric parts in the grooves, wherein the plurality of dielectric parts and the plurality of conductive parts alternately arranged along the second direction constitute conductive lines. Forming a plurality of word lines spaced apart along the second direction, wherein the word lines are located on the side of the conductive lines away from the substrate, and the extension directions of the word lines are parallel to the third direction. By arranging a filling structure between two adjacent memory arrays, the structural density in the isolation region is increased, thereby reducing the structural density difference between the edge region of the memory array and the isolation region. When performing a process, the process defects of the film layer structure in the edge region of the memory array can be improved, thereby improving the performance degradation of the transistor in the edge region of the memory array.

[0021] In some implementations, the filling structure includes a dummy transistor. When the plurality of conductive portions are formed, a second electrode of the transistor is also formed. When the dielectric portion is formed in the groove, a second electrode of the dummy transistor is also formed. When the plurality of word lines spaced apart along the second direction are formed, a metal gate of the transistor and a metal gate of the dummy transistor are also formed. The arrangement is such that the metal gate of the transistor and the metal gate of the dummy transistor are arranged in the same layer.

[0022] In some implementations, after forming a plurality of word lines spaced apart along the second direction, forming a plurality of storage arrays and filling structures, further comprising: forming a first channel hole and a second channel hole that penetrate the word line. Filling the first channel hole and the second channel hole with gate dielectric material and channel material to form a gate dielectric layer of the transistor and a channel layer of the transistor in the first channel hole, and forming a gate dielectric layer of the virtual transistor and a channel layer of the virtual transistor in the second channel hole; wherein the metal gate of the transistor and the gate dielectric layer of the transistor constitute the gate of the transistor, the gate of the transistor surrounds the channel layer of the transistor, the metal gate of the virtual transistor and the gate dielectric layer of the virtual transistor constitute the gate of the virtual transistor, and the gate of the virtual transistor surrounds the channel layer of the virtual transistor. Forming the first pole of the transistor and the first pole of the virtual transistor, the first pole of the transistor is located on the side of the channel layer of the transistor away from the substrate, and the first pole of the virtual transistor is located on the side of the channel layer of the virtual transistor away from the substrate. Such arrangement enables the virtual transistor and the transistor part to be arranged in the same layer.

[0023] In some implementations, after forming the gate of the transistor and the gate of the virtual transistor, a plurality of storage arrays are formed, further comprising: forming alternately stacked multiple dielectric layers and multiple conductive layers. Forming through-holes that penetrate the multiple dielectric layers and the multiple conductive layers. Filling the through-holes with capacitor materials and electrode materials in sequence to form capacitor layers and capacitor electrodes in the through-holes, the capacitor layers being located between the capacitor electrodes and the sidewalls of the through-holes, wherein the capacitor electrodes are the shared second capacitor electrodes of the multiple capacitors, and at least a portion of the conductive layer surrounding the periphery of the capacitor layers is the first capacitor electrode of the capacitors. Such an arrangement is performed so that at least one capacitor is formed, and multiple capacitors are arranged in a stacked manner.

[0024] In some implementations, after forming the alternately stacked multiple dielectric layers and multiple conductive layers, forming the isolation sidewalls includes: forming a filling space that penetrates the multiple dielectric layers and the multiple conductive layers. Filling the filling space with an isolation material to form the isolation sidewalls. The isolation sidewalls are formed in this way to ensure that adjacent memory arrays are at least partially electrically isolated.

[0025] In a third aspect, an electronic device is provided, comprising: a processor; and a memory as described in any one of the first aspects, or a memory made by the method for making a memory as described in any one of the second aspects; the memory and the processor are electrically connected.

[0026] The technical effects brought about by any design method in the third aspect can refer to the technical effects brought about by different design methods in the first aspect, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 A schematic diagram of the architecture of an electronic device exemplarily provided in an embodiment of the present application;

[0028] Figure 2 A structural diagram of a memory provided exemplarily in an embodiment of the present application;

[0029] Figure 3a A structural diagram of a storage array based on 1TnC structure;

[0030] Figure 3b A structural diagram of a storage array based on a plurality of bit cells arranged in a honeycomb structure;

[0031] Figure 4 A circuit structure diagram of a storage unit in a storage array based on a 1TnC structure;

[0032] Figure 5 A timing diagram for reading a storage unit in a storage array based on a 1TnC structure;

[0033] Figure 6 A structural diagram of a plurality of storage arrays connected in a memory provided as an example in some embodiments;

[0034] Figure 7 A structural diagram of a memory provided exemplarily for some embodiments;

[0035] Figure 8 A structural diagram of another memory provided exemplarily for some embodiments;

[0036] Fig. 9 A structural diagram of another memory provided exemplarily in an embodiment of the present application;

[0037] Fig.10 A structural diagram of another memory provided exemplarily in an embodiment of the present application;

[0038] Fig.11a A top view of a memory device omitting a capacitor and an isolation sidewall is provided as an example in an embodiment of the present application;

[0039] Fig.11b A top view of another memory omitting capacitors and isolation sidewalls provided as an example in an embodiment of the present application;

[0040] Fig.12 for Fig.10 A structural diagram of a transistor of a memory in FIG.

[0041] Fig.13 for Fig.10 A structural diagram of a virtual transistor of a memory in FIG.

[0042] Fig.14 A flowchart of a method for preparing a memory device provided exemplarily in an embodiment of the present application;

[0043] Fig.15 A structural diagram of forming an intermediate conductive line in a method for preparing a memory device exemplarily provided in an embodiment of the present application;

[0044] Fig.16 A structural diagram of removing part of the middle conductive line in a method for preparing a memory device provided exemplarily in an embodiment of the present application;

[0045] Fig.17 A structural diagram of a dielectric portion formed in a method for preparing a memory device exemplarily provided in an embodiment of the present application;

[0046] Fig.18 A structural diagram of forming an insulating portion in a method for preparing a memory device exemplarily provided in an embodiment of the present application;

[0047] Fig.19 A structural diagram of forming a first channel hole and a second channel hole in a method for preparing a memory device exemplarily provided in an embodiment of the present application;

[0048] Fig. 20 A structural diagram of forming a transistor and a dummy transistor in a method for preparing a memory provided exemplarily in an embodiment of the present application;

[0049] Fig.21 A structural diagram of forming a conductive layer and a dielectric layer in a method for preparing a memory device exemplarily provided in an embodiment of the present application;

[0050] Fig. 22 A structural diagram of forming a through hole in a method for preparing a memory device exemplarily provided in an embodiment of the present application;

[0051] Fig.23 A structural diagram of a capacitor formed in a method for preparing a memory device exemplarily provided in an embodiment of the present application;

[0052] Fig.24 A structural diagram of forming a filling space in a method for preparing a memory device provided exemplarily in an embodiment of the present application;

[0053] Fig.25 A structural diagram of forming an isolation sidewall in a method for preparing a memory device exemplarily provided in an embodiment of the present application. DETAILED DESCRIPTION

[0054] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments.

[0055] In the following, the terms "first", "second", etc. are used only for convenience of description and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first", "second", etc. may explicitly or implicitly include one or more of the features. In the description of this application, unless otherwise specified, "plurality" means two or more.

[0056] In the embodiments of the present application, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

[0057] When describing some embodiments, the expressions "connected", "electrically connected" and their derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical contact with each other, and the term "electrically connected" may be used to indicate that two or more components are in electrical contact with each other.

[0058] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0059] In the context of this application, the meaning of "on", "above", and "over" should be interpreted in the broadest manner, so that "on" not only means "directly on something", but also includes the meaning of "on something" with intervening features or layers in between, and "above" or "over" not only means "above" or "over" something, but also includes the meaning of "above" or "over" something without intervening features or layers in between (i.e., directly on something).

[0060] In the embodiments of the present application, "same-layer arrangement" refers to using the same film-forming process to form a film layer for forming a specific pattern, and then using the same mask to form a layer structure through a single patterning process, and the material of the layer structure is the same. Depending on the specific pattern, a single patterning process may include multiple exposure, development or etching processes, and the specific patterns in the formed layer structure may be continuous or discontinuous, and these specific patterns may also be at different heights or have different thicknesses.

[0061] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0062] The embodiments of the present application provide an electronic device, which may be, for example, a mobile phone, a tablet computer (pad), a personal digital assistant (PDA), a television, a smart wearable product (e.g., a smart watch, a smart bracelet), a virtual reality (VR) terminal device, an augmented reality (AR) terminal device, a rechargeable small household appliance (e.g., a soymilk machine, a sweeping robot), a drone, a radar, an aerospace equipment, and a vehicle-mounted device, etc., and may also be a network device such as a base station. The embodiments of the present application do not impose any special restrictions on the specific form of the electronic device.

[0063] Figure 1 The following is a schematic diagram of the architecture of an electronic device 001 provided exemplarily in an embodiment of the present application. Figure 1 As shown, the electronic device 001 includes components such as a storage device 002 and a processor 003. Those skilled in the art can understand that Figure 1 The structure of the electronic device 001 shown in the figure does not constitute a limitation on the electronic device 001. The electronic device 001 may include, for example, Figure 1 More or fewer components may be shown, or they may be combined as shown. Figure 1 Some of the components shown may be combined with Figure 1 The components shown are arranged differently.

[0064] The storage device 002 is used to store software programs and modules. The storage device 002 mainly includes a program storage area and a data storage area, wherein the program storage area can store an operating system, at least one application required for a function (such as a sound playback function, an image playback function, etc.), etc.; the data storage area can store data created according to the use of the electronic device 001 (such as audio data, image data, phone book, etc.), etc. In addition, the storage device 002 includes an external memory 021 and an internal memory 022. The data stored in the external memory 021 and the internal memory 022 can be transmitted to each other. The external memory 021 may include, for example, a hard disk, a USB flash drive, a floppy disk, etc. The internal memory 022 may include, for example, a random access memory, a read-only memory, etc. Among them, the random access memory may include, for example, a ferroelectric random access memory (FeRAM), a phase change memory, or a magnetic memory, etc.

[0065] The processor 003 is the control center of the electronic device 001. It uses various interfaces and lines to connect various parts of the entire electronic device 001. By running or executing software programs and / or modules stored in the storage device 002, and calling data stored in the storage device 002, it executes various functions of the electronic device 001 and processes data, thereby monitoring the electronic device 001 as a whole. Optionally, the processor 003 may include one or more processing units. For example, the processor 003 may include an application processor (application processor, AP), a modem processor, a graphics processing unit (graphics processing unit, GPU), etc. Among them, different processing units may be independent devices, or they may be integrated into one or more processors 003. For example, the processor 003 may integrate an application processor and a modem processor, wherein the application processor mainly processes an operating system, a user interface, and an application program, etc., and the modem processor mainly processes wireless communication. It is understandable that the above-mentioned modem processor may not be integrated into the processor 003. The above-mentioned application processor 003 may be, for example, a central processing unit (CPU).

[0066] Figure 2 The structure diagram of a memory 01 provided as an example in an embodiment of the present application. The memory 01 can be used as an internal memory 022, such as a ferroelectric memory. The following description is made by taking the memory 01 as a three-dimensional ferroelectric capacitor (FeCAP) memory (three-dimensional ferroelectric memory) as an example.

[0067] like Figure 2As shown, in the embodiment of the present application, the memory 01 may include a substrate 2 and a plurality of memory arrays 1 located on the substrate 2. For the convenience of description, the direction perpendicular to the substrate 2 is referred to as the first direction X, the second direction Y and the third direction Z are both perpendicular to the first direction X, and the second direction Y intersects the third direction Z. The description is only made by taking the second direction Y and the third direction Z as an example in which they are perpendicular to each other.

[0068] In some embodiments, multiple memory arrays 1 may be arranged spaced apart from each other along the second direction Y or the third direction Z, so that the multiple memory arrays 1 form a memory array layer, and the memory array layer is parallel to the substrate. In some other embodiments, the multiple memory arrays 1 may also be arranged spaced apart from each other along the first direction X, that is, multiple memory array layers may be formed, and the multiple memory array layers are stacked along the first direction X. The following description will only take the memory 01 including one memory array layer as an example.

[0069] Figure 3a FIG. 1 is a structural diagram of a storage array 1 based on a 1TnC structure. Figure 3a As shown, each memory array 1 may include a plurality of memory cells 10. A memory cell 10 includes a transistor 11 and at least one capacitor 12 stacked along a first direction X. The at least one capacitor 12 is electrically connected to a side of the transistor 11 facing away from the substrate 2.

[0070] Among them, the capacitor 12 can be a ferroelectric capacitor. Through the above settings, the memory 01 is a ferroelectric memory, which has the characteristics of non-volatile storage data and fast access rate. For example, the capacitor layer in the capacitor 12 can be a ferroelectric material such as ZrO2, HfO2, Al-doped HfO2, Si-doped HfO2, Zr-doped HfO2, La-doped HfO2, Y-doped HfO2, or a material doped with other elements based on the material and any combination thereof.

[0071] When the number of capacitors 12 is one, the memory cell 10 has a 1T1C (1-transistor-1-capacitor) structure, that is, one memory cell 10 includes one capacitor 12 and one transistor 11. When the number of capacitors 12 is n, the memory cell 10 has a 1TnC (1-transistor-n-capacitor) structure, that is, one memory cell 10 includes n capacitors 12 and one transistor 11.

[0072] A memory cell 10 includes a transistor 11 and n capacitors 12. The n capacitors 12 can be used to form n bit cells in a stacked arrangement. The n bit cells share the one transistor 11. The following description will only take the memory cell 10 of the 1TnC structure as an example.

[0073] Continue to refer to Figure 3a , the memory array 1 may further include: a plurality of bit lines (BL), a plurality of word lines (WL) and a plurality of memory cell physical layers (plates). Each of the plurality of memory cell physical layers includes a plurality of bit cells (i.e., bit cells) arranged in a plane. In some embodiments, the plurality of bit cells are arranged in a plurality of rows and columns. For each memory cell physical layer, a plurality of bit cells located in the same row (i.e., a plurality of bit cells arranged along the third direction Z) share the same word line WL, and a plurality of bit cells located in the same column (i.e., a plurality of bit cells arranged along the second direction Y) share the same bit line BL. The memory cells 10 located in the same row at the same position in different memory cell physical layers also share the same word line WL, and the plurality of memory cells 10 located in the same column at the same position in different memory cell physical layers also share the same bit line BL.

[0074] In some other embodiments, such as Figure 3b , multiple bit cells can also be arranged in a honeycomb structure. For example, multiple bit cells in the same column (i.e., multiple bit cells arranged along the second direction Y) share the same bit line BL, and multiple bit cells sharing the same word line WL are arranged alternately along the third direction Y. Among them, a honeycomb structure can be composed of seven bit cells, and the seven bit cells can be respectively located at the six vertices of the hexagon and the center point of the hexagon. The seven bit cells constituting a honeycomb structure correspond to three word lines WL.

[0075] Further, the three-dimensional memory 01 may also include a sense amplifier (SA), which may be used to amplify signals during the reading and writing process of the three-dimensional memory 01. Optionally, the sense amplifier SA may include a bit line sense amplifier BL_SA and / or a global sense amplifier (GSA). In addition, the three-dimensional memory 01 may also include one or more of other devices such as a row address decoder, a column address decoder, a physical layer address decoder, and a bit line selector (BL MUX).

[0076] The following describes the read process of a bit cell by taking a 1TnC (eg, n=3) structure in the three-dimensional ferroelectric memory 01 as an example. Figure 4 is a circuit structure diagram of a storage unit 10 in a storage array 1 based on a 1TnC structure; Figure 5 FIG. 1 is a timing diagram for reading a storage unit 10 in a storage array 1 based on a 1TnC structure. Figure 4As shown, the 1TnC structure includes a transistor and three capacitors. The gate of the transistor is connected to the word line WL, one electrode (e.g., source or drain) of the transistor is coupled to the bit line BL and the bit line sense amplifier BL_SA, and the bit line sense amplifier BL_SA is also coupled to the inverted / BL of the bit line BL. The other electrode (e.g., source or drain) of the transistor is connected to the first end of each of the three capacitors, and the second ends of the three capacitors are respectively connected to the plate lines (i.e., PL0, PL1 and PL2) of the physical layers of the three storage cells in a one-to-one correspondence.

[0077] In one embodiment, the reading process of the memory cell 10 may include four stages, namely, a pre-charge stage A1, a switch stage A2, a charge sharing stage A3 and a sense amplification stage A4. The timing diagram of the four stages may be as follows: Figure 5 shown.

[0078] In the precharge phase A1, the word line WL is set to a high level, and the potential of the first end of the capacitor in the memory cell 10 is pulled down to 0V by the potential of the bit line BL. Then, the word line WL is set to a low level, and the second end of the capacitor is in a floating state.

[0079] In the exchange phase A2, the first end of the capacitor remains in a floating state, and the potential of the layer line PL changes from a low position to a high position, and the stored charge in the memory cell 10 is read; in the process of the potential of the layer line PL changing from low to high, the potential of the first end of the capacitor is raised due to the coupling effect; at this time, the potential of the bit line BL and the potential of the inverted bit line / BL of the bit line 14 are both maintained at the reference voltage VREF.

[0080] In the charge sharing stage A3: the word line WL is turned on, and the first end of the capacitor and the bit line BL share charge. If the storage data of the memory cell 10 is 0, the memory cell 10 has no charge release, and due to the coupling effect, the potential of the first end of the capacitor is slightly raised (lower than VREF); the potential of the bit line BL will be pulled down by the potential of the first end of the capacitor to obtain VREF-, which is lower than the potential VREF of the inverted / BL of the bit line 14. If the storage data of the memory cell 10 is 1, the memory cell 10 releases the charge and the coupling effect will raise the potential of the first end of the capacitor (higher than VREF); the potential of the bit line BL will be pulled up by the potential of the first end of the capacitor to obtain VREF+, which is higher than the potential VREF of the inverted / BL of the bit line 14.

[0081] In the sensing and amplifying stage A4, the SA corresponding to the bit line BL amplifies the potential difference between the bit line BL and the inverted / BL of the bit line 14, thereby determining whether the read data is "0" or "1".

[0082] Figure 6 The following is a structural diagram of a plurality of storage arrays 1 connected in a memory 01 provided as an example in some embodiments. Figure 6 As shown, in the embodiment of the present application, in order to reduce the power consumption of pulling up or down the potential of the layer line PL, multiple memory arrays 1 constitute a memory array 1 piece (MAT), and multiple memory arrays 1 in the memory array 1 piece share multiple bit lines BL.

[0083] Figure 7 FIG. 1 is a structural diagram of a memory 01 provided exemplarily in some embodiments. Figure 7 As shown, the memory 01 further includes an isolation spacer 3, which is located on the substrate 2. In a direction parallel to the substrate 2, the isolation spacer 3 is located between two adjacent memory arrays 1. By providing the isolation spacer 3, at least partial electrical isolation between the two adjacent memory arrays 1 is achieved. Exemplarily, the isolation spacer 3 can be located between the capacitors 12 of the two adjacent memory arrays 1, and there is a certain distance between the isolation spacer 3 and the substrate 2. Among them, the isolation spacer 3 can be a spacer formed by filling an isolation material in a slit.

[0084] The memory 01 further includes an insulating portion 1501, which is located between the isolation spacer 3 and the substrate 2. Exemplarily, in a direction parallel to the substrate 2, the insulating portion 1501 is also located between the transistors 11 of the memory array 1, and between the transistors 11 of two adjacent memory arrays 1. By providing the insulating portion 1501, isolation between the transistors 11 of the memory array 1 can be achieved, and isolation between the transistors 11 of two adjacent memory arrays 1 can be achieved.

[0085] Since multiple memory arrays 1 are arranged at intervals, the structural density in the isolation area N1 is lower than the structural density in the edge area N2 of the memory array 1. Since the edge area N2 is adjacent to the isolation area N1 and the central area N3, the structural density is reduced in the direction from the central area N3 of the memory array 1 to the isolation area N1. Here, "isolation area N1" refers to the area between adjacent memory arrays 1, "edge area N2" refers to the area at the edge of the memory array 1, and "central area N3" refers to the area at the center of the memory array 1. The above division of "isolation area", "edge area" and "central area" is only for illustration, and the embodiments of the present application do not limit the specific size of the area. Here, "structural density" refers to the number of transistors per unit area of ​​the area.

[0086] When manufacturing the memory array 1, it is necessary to use etching (Etch), chemical mechanical polishing (CMP) and other processes to manufacture the transistor 11. It is understandable that the transistor 11 structures of multiple memory arrays 1 need to be manufactured simultaneously through the above process. Since the structural density of the isolation area N1 is quite different from the structural density of the edge area N2, when performing the above process, process defects may occur in the film layer structure located in the edge area N2, which may lead to functional degradation of the transistor 11 located in the edge area N2 (such as excessive off-state current, etc.). The functional degradation of the transistor will lead to a decrease in the read and write pass rate of the memory.

[0087] In some embodiments, in order to solve the problem of connectivity failure of the transistor 11 located in the edge area of ​​the memory array 1, a dummy memory cell 10' is usually added in the isolation area N1. Figure 8 FIG. 1 is a structural diagram of another memory 01 provided exemplarily in some embodiments. Figure 8 As shown, in each memory array 1, a plurality of virtual memory cells 10' may be added on one side of the memory array 1. The structure of the virtual memory cell 10' may be the same as that of the memory cell 10. The virtual memory cell 10' may not play a storage role, but play a role in providing mechanical support and / or load balancing for the three-dimensional memory 01. By providing the virtual memory cell 10', it is helpful to improve the problem of a large difference between the structural density of the isolation area N1 and the structural density of the edge area N2. When performing etching, chemical mechanical polishing and other processes, the memory cell 10 adjacent to the virtual memory cell 10' is not prone to deformation of the film structure, which is helpful to improve the phenomenon of performance degradation of the transistor 11 in the edge area N2 of the memory array 1.

[0088] However, by providing the virtual storage unit 10', the occupied area of ​​the memory 01 increases, resulting in a decrease in the storage density of the memory 01. For example, when each storage array 1 includes 64 storage units 10 distributed in an array, adding two columns of virtual storage units 10' on one side of each storage array 1 will increase the occupied area of ​​the storage array 1 by about 5%.

[0089] Fig. 9 A structural diagram of another memory provided exemplarily in an embodiment of the present application; Fig.10 This is a structural diagram of another memory 01 provided exemplarily in the embodiment of the present application. Fig. 9 and Fig.10 As shown, the memory 01 provided in the embodiment of the present application further includes a filling structure 4. The filling structure 4 is located on the substrate 2 and between the transistors 11 of two adjacent memory arrays 1. Exemplarily, the filling structure 4 is also located between the substrate 2 and the isolation spacer 3, that is, the isolation spacer 3 is located on the side of the filling structure 4 away from the substrate 2.

[0090] Based on the above structure, the insulating part 1501 is also located between the filling structure 4 and the memory array 1, and the insulating part 1501 is also located between the isolation sidewall 3 and the memory array 1, and the insulating part 1501 and the filling structure 4 are made of different materials. Here, "different materials" means that the insulating part 1501 and at least part of the film layer of the filling structure 4 are made of different materials. For example, the insulating part 1501 and the entire film layer of the filling structure 4 are made of different materials, or the insulating part 1501 and part of the film layer of the filling structure 4 are made of different materials. Through the above arrangement, the insulating part 1501 can achieve the isolation effect between the isolation sidewall 3 and the memory array 1, and can also achieve the isolation effect between the filling structure 4 and the memory array 1.

[0091] The filling structure 4 can be formed before the transistor 11, or the filling structure 4 can be made simultaneously with the transistor 11. By arranging the filling structure 4 between two adjacent memory arrays 1, the structure density in the isolation region N1 is increased, thereby reducing the difference in structure density between the edge region N2 of the memory array 1 and the isolation region N1. When performing the process, the process defects of the film layer structure in the edge region N2 of the memory array 1 can be improved, thereby improving the performance degradation of the transistor 11 in the edge region of the memory array 1.

[0092] like Fig. 9 As shown, in some embodiments, the filling structure 4 may include, for example, a support block 43, and the material of the support block 43 may include an insulating material. The material of the support block 43 may include, for example, one of silicon dioxide and silicon nitride. The embodiment of the present application does not specifically limit the number of support blocks 43, and it is sufficient to reduce the difference in structural density between the edge area N2 of the storage array 1 and the isolation area N1. Exemplarily, the filling structure 4 may include three support blocks 43 arranged at intervals. Through the above arrangement, the film layer structure of the support block 43 is simple, which is conducive to improving the regularity of the filling structure 4, thereby further improving the role of the filling structure 4 in providing mechanical support and / or load balancing. At the same time, by setting the material of the support block 43 to an insulating material, it is also beneficial to avoid the support block 43 from interfering with other transistors 11, which is beneficial to improving the performance of the storage array 1.

[0093] Of course, in some other embodiments, the filling structure 4 may also include multiple film layer structures. Fig.10As shown, the filling structure 4 may include a dummy transistor 41, at least part of the film layer of the dummy transistor 41 is arranged in the same layer as at least part of the film layer of the transistor 11, and the dummy transistor 41 is arranged at intervals from the transistor 11. Here, "arranged at intervals" means that there is a certain distance between the dummy transistor 41 and the transistor 11, so that the dummy transistor 41 does not contact the transistor 11. The above arrangement is conducive to simplifying the manufacturing process of the filling structure 4 and improving the manufacturing efficiency and manufacturing cost of the memory 01.

[0094] In some embodiments, all film layers of the dummy transistor 41 may be arranged in the same layer as all film layer structures in the transistor 11, so that the structure of the dummy transistor 41 is the same as that of the transistor 11. In some other embodiments, part of the film layers of the dummy transistor 41 may be arranged in the same layer as part of the film layers in the transistor 11. Here, the dummy transistor 41 may not play a control role, but may play a role in providing mechanical support and / or load balancing for the three-dimensional memory 01.

[0095] The embodiment of the present application does not limit the number of virtual transistors 41, and the number of virtual transistors 41 can be one or more. When the number of virtual transistors 41 is one, the virtual transistor 41 can be located between any group of adjacent storage arrays 1. When the number of virtual transistors 41 is multiple, multiple virtual transistors 41 can be located between a group of adjacent storage arrays 1, or one or more virtual transistors 41 can be provided between multiple groups of adjacent storage arrays 1.

[0096] Fig.11a A top view of a memory 01 omitting the capacitor 12 and the isolation spacer 3 is provided as an example in an embodiment of the present application; Fig.11b Another memory 01 provided by way of example in the present application is a top view omitting the capacitor 12 and the isolation spacer 3. Fig.10 , Fig.11a as well as Fig.11b As shown, in each memory array 1, a plurality of memory cells 10 may be arranged at intervals along the second direction Y, and a plurality of memory cells 10 may be arranged at intervals along the third direction Z. Since each memory cell 10 includes a transistor 11 and at least one capacitor 12 stacked along the first direction X, a plurality of transistors 11 may be arranged at intervals along the second direction Y, and a plurality of transistors 11 may be arranged at intervals along the third direction Z.

[0097] Reference Fig.11a, when there are multiple dummy transistors 41 between two adjacent memory arrays 1, the multiple dummy transistors 41 can be arranged at intervals along the third direction Z, and the dummy transistors 41 and the multiple transistors 11 arranged along the second direction Y are arranged at intervals in the second direction Y. Exemplarily, each memory array 1 may include 16 transistors 11 arranged in an array, for example, the multiple transistors 11 are arranged in 4 rows, and each row includes 4 transistors 11. Accordingly, the multiple dummy transistors 41 can be arranged in columns, and each dummy transistor 41 is arranged at intervals along the third direction Z with a corresponding row of transistors 11.

[0098] Through the above-mentioned settings, the structural density located in the isolation area N1 can be further increased, the structural density difference between the edge area N2 of the storage array 1 and the isolation area N1 can be further reduced, the process defects of the film layer structure of each row in the edge area of ​​the storage array 1 can be improved, and the performance degradation phenomenon of the transistor 11 located in the edge area N2 of the storage array 1 can be further improved.

[0099] Further, refer to Fig.11b , a plurality of virtual transistors 41 arranged along the third direction Z can constitute a virtual transistor group 42, the number of virtual transistor groups 42 between two adjacent storage arrays 1 is multiple, and the plurality of virtual transistor groups 42 are arranged at intervals along the second direction Y. Exemplarily, three virtual transistor groups 42 can be provided between two adjacent storage arrays 1, and the three virtual transistor groups 42 are arranged at intervals along the second direction Y. By increasing the number of virtual transistor groups 42, the structural density located in the isolation region N1 can be further increased, the difference in structural density between the edge region N2 of the storage array 1 and the isolation region N1 can be further reduced, the process defects of the film layer structure of each row in the edge region of the storage array 1 can be improved, and the performance degradation phenomenon of the transistor 11 located in the edge region N2 of the storage array 1 can be further improved.

[0100] Based on the above structure, the structural density located in the isolation area N1 can be further adjusted by adjusting the position of the dummy transistor 41. In some embodiments, the distance D1 between the dummy transistor 41 and the transistor 11 arranged and adjacent along the second direction Y can be equal to the distance D2 between two transistors 11 arranged and adjacent along the second direction Y. It can be understood that the transistor 11 adjacent to the dummy transistor 41 in the memory array 1 is the transistor 11 located in the edge area N2 of the memory array 1. Through the above arrangement, it is beneficial to further reduce the difference in structural density between the edge area N2 of the memory array 1 and the isolation area N1, improve the process defects of the film layer structure of each row in the edge area N2 of the memory array 1, and further improve the performance degradation of the transistor 11 located in the edge area N2 of the memory array 1.

[0101] Furthermore, the distance D3 between two adjacent virtual transistors 41 arranged along the second direction Y can also be equal to the distance D2 between two adjacent transistors 11 arranged along the second direction Y. That is, a plurality of virtual transistor groups 42 are arranged at equal intervals along the second direction Y, and a plurality of columns of transistors 11 are arranged at equal intervals along the second direction Y, and the spacing distances between the two are equal. Through the above arrangement, it is beneficial to further reduce the difference in structural density between the edge area N2 of the storage array 1 and the isolation area N1, improve the process defects of the film layer structure of each row in the edge area N2 of the storage array 1, and further improve the performance degradation of the transistor 11 located in the edge area N2 of the storage array 1. At the same time, through the above arrangement, it is also beneficial to increase the regularity of the arrangement of the virtual transistors 41 and the transistors 11.

[0102] As described in the above embodiment, at least part of the film layer of the dummy transistor 41 can be arranged in the same layer as at least part of the film layer of the transistor 11. Fig.10 The structure of the virtual transistor 41 is described based on a transistor 11 in the storage array 1. In some other embodiments, the structure of the transistor 11 can also be other structures in the related art, and accordingly, the structure of the virtual transistor 41 can also be other structures in the related art. Fig.12 for Fig.10 A structural diagram of the transistor 11 of the memory 01; Fig.13 for Fig.10 Structural diagram of the virtual transistor 41 of the memory 01 in FIG.

[0103] like Fig.12 As shown. The first electrode 111 of the transistor and the second electrode 112 of the transistor are arranged along the first direction X. Fig.10 , the first electrode 111 of the transistor is electrically connected to at least one capacitor 12, the channel layer 114 of the transistor is located between the first electrode 111 of the transistor and the second electrode 112 of the transistor, and the gate 113 of the transistor surrounds the channel layer 114 of the transistor. In the embodiment involved in the present application, one of the drain or source of the transistor 11 is called the first electrode 111 of the transistor, and the other corresponding electrode is called the second electrode 112 of the transistor, and the gate 113 of the transistor is a control terminal. The drain and source of the transistor 11 can be determined according to the direction of current flow.

[0104] Further, the gate 113 of the transistor surrounds the channel layer 114 of the transistor, and the gate 113 of the transistor includes a metal gate 1132 of the transistor and a gate dielectric layer 1131 of the transistor, and the metal gate 1132 of the transistor and the channel layer 114 of the transistor are isolated by the gate dielectric layer 1131 of the transistor. That is, the transistor 11 in the embodiment of the present application can be a gate-all-around (GAA) transistor.

[0105] like Fig.13 As shown, the first electrode 411 of the dummy transistor and the second electrode 412 of the dummy transistor are arranged along the first direction X. Fig.10 , the first electrode 411 of the virtual transistor is connected to the isolation sidewall 3, the channel layer 414 of the virtual transistor is located between the first electrode 411 of the virtual transistor and the second electrode 412 of the virtual transistor, and the gate 413 of the virtual transistor surrounds the channel layer 414 of the virtual transistor. In the embodiment involved in the present application, one of the drain or source of the virtual transistor 41 is called the first electrode 411 of the virtual transistor, and the corresponding other electrode is called the second electrode 412 of the virtual transistor, and the gate 413 of the virtual transistor is the control terminal. The drain and source of the virtual transistor 41 can be determined according to the direction of current flow.

[0106] Further, the gate 413 of the dummy transistor surrounds the channel layer 414 of the dummy transistor, and the gate 413 of the dummy transistor includes a metal gate 4132 of the dummy transistor and a gate dielectric layer 4131 of the dummy transistor, and the metal gate 4132 of the dummy transistor and the channel layer 414 of the dummy transistor are isolated by the gate dielectric layer 4131 of the dummy transistor. That is, the dummy transistor 41 in the embodiment of the present application may also be a gate-all-around transistor.

[0107] In the embodiments involved in this application, for example, Fig.10 The transistor 11 and the dummy transistor 41 shown may be NMOS (N-channel metal oxide semiconductor) tubes, or may be PMOS (P-channel metal oxide semiconductor) tubes.

[0108] Based on the above structure, the first electrode 111 of the transistor and the first electrode 411 of the dummy transistor can be arranged in the same layer, the channel layer 114 of the transistor and the channel layer 414 of the dummy transistor can be arranged in the same layer, and the gate 113 of the transistor and the gate 413 of the dummy transistor can be arranged in the same layer. The above arrangement is conducive to simplifying the manufacturing process of the transistor 11 and the dummy transistor 41, and improving the manufacturing efficiency and manufacturing cost of the memory 01.

[0109] Exemplarily, the materials of the first electrode 111 of the transistor and the first electrode 411 of the virtual transistor are both conductive materials, for example, they may include a combination of one or more conductive materials such as TiN (titanium nitride), Ti (titanium), Au (gold), W (tungsten), Mo (molybdenum), In-Ti-O (ITO, indium tin oxide), Al (aluminum), Cu (copper), Ru (ruthenium), Ag (silver), etc.

[0110] Exemplarily, the materials of the metal gate 1132 of the transistor and the metal gate 4132 of the virtual transistor can both be metal materials, for example, they can include a combination of one or more conductive materials such as Ti (titanium), Au (gold), W (tungsten), Mo (molybdenum), Al (aluminum), Cu (copper), Ru (ruthenium), and Ag (silver).

[0111] Exemplarily, the material of the channel layer 114 of the transistor and the channel layer 414 of the virtual transistor may include one or more combinations of semiconductor materials such as Si (silicon), poly-Si (p-Si, polycrystalline silicon), amorphous-Si (a-Si, amorphous silicon), In-Ga-Zn-O (IGZO, indium gallium zinc oxide) polyvalent compounds, ZnO (zinc oxide), ITO (indium tin oxide), TiO2 (titanium dioxide), MoS2 (molybdenum disulfide), WS2 (tungsten disulfide), graphene, black phosphorus, etc.

[0112] Exemplarily, the material of the gate dielectric layer 1131 of the transistor and the gate dielectric layer 4131 of the virtual transistor may include a combination of one or more insulating materials such as SiO2 (silicon dioxide), Al2O3 (aluminum oxide), HfO2 (hafnium dioxide), ZrO2 (zirconium oxide), TiO2 (titanium dioxide), Y2O3 (yttrium oxide) and Si3N4 (silicon nitride).

[0113] Based on the above structure, in some embodiments, the second electrode 112 of the transistor and the second electrode 412 of the virtual transistor can be set in the same layer, and the virtual transistor 41 can be set in the same layer as all the film layer structures in the transistor 11, so that the structure of the virtual transistor 41 is the same as that of the transistor 11.

[0114] However, in some other embodiments, the materials of the second electrode 112 of the transistor and the second electrode 412 of the dummy transistor may be different. For example, the material of the second electrode 112 of the transistor may be the same as the material of the first electrode 111 of the transistor, that is, the first electrode 111 of the transistor is a conductive material. The material of the second electrode 412 of the dummy transistor may be an insulating material so that the dummy transistor 41 does not have a control function.

[0115] Combination Fig.10 and Fig.11a , wherein the memory 01 further includes a plurality of conductive wires 13 spaced apart along a third direction Z, the extension direction of the conductive wires 13 is parallel to the second direction Y, the conductive wires 13 may include a plurality of conductive portions 131 and a plurality of dielectric portions 132, and the conductive portions 131 and the dielectric portions 132 are alternately arranged along the second direction Y. Exemplarily, the conductive portion 131 of the conductive wire 13 is directly opposite to the transistor 11 of the storage array 1, and the dielectric portion 132 of the conductive wire 13 is directly opposite to the dummy transistor 41. Based on the above structure, the conductive portion 131 may be arranged in the same layer and in contact with the second pole 112 of the transistor, and the dielectric portion 132 may be arranged in the same layer and in contact with the second pole 412 of the dummy transistor. The above arrangement is conducive to simplifying the manufacturing process of the transistor 11 and the dummy transistor 41, and can improve the manufacturing efficiency and manufacturing cost of the memory 01.

[0116] At the same time, by arranging the dielectric portion 132 of the conductive line 13 and the second electrode 412 of the dummy transistor in the same layer and in contact with each other, the dummy transistor 41 does not have a control function, which is also beneficial to avoid the dummy transistor 41 from interfering with other transistors 11, and is beneficial to improving the performance of the storage array 1.

[0117] In some embodiments, the second electrodes 112 of the plurality of transistors arranged along the second direction Y may be connected into an integral structure to form a conductive portion 131. In an embodiment where the number of dummy transistors 41 is multiple, the second electrodes 412 of the plurality of dummy transistors arranged along the second direction Y may be connected into an integral structure to form a dielectric portion 132, and the dielectric portion 132 and the conductive portion 131 are adjacent. Since the dummy transistors 41 are located between two adjacent memory arrays 1, the dielectric portion 132 and the conductive portion 131 are alternately arranged.

[0118] Further, the memory 01 further includes a plurality of bit lines 14 arranged at intervals along the third direction Z, the bit lines 14 are located between the conductive line 13 and the substrate 2, the extension direction of the bit lines 14 is parallel to the second direction Y, and the bit lines 14 are electrically connected to the conductive portion 131 of the conductive line 13. Exemplarily, the bit lines 14 may be located on the side of the conductive line 13 away from the transistor 11, and one bit line 14 is directly opposite to one conductive line 13. A plurality of contact pillars are further arranged on each bit line 14, and one end of the contact pillar away from the bit line 14 is connected to the conductive portion 131 of the conductive line 13, so that the bit line 14 and the conductive portion 131 are electrically connected.

[0119] Continue to refer to Fig.10 and Fig.11a The memory 01 may further include a plurality of word lines 15 spaced apart along the second direction Y, and the extending direction of the word lines 15 is parallel to the third direction Z. At least one word line 15 is electrically connected to the gates 113 of a row of transistors arranged along the third direction Z, and at least one word line 15 is electrically connected to the gates 413 of a row of dummy transistors arranged along the third direction Z.

[0120] For ease of distinction, the word line 15 is divided into a first word line 151 and a second word line 152, wherein the first word line 151 is electrically connected to the gates 113 of a row of transistors arranged along a third direction Z, and the second word line 152 is electrically connected to the gates 413 of a row of dummy transistors arranged along the third direction Z.

[0121] Exemplarily, the first word line 151 is arranged around the gate 113 of the transistor, and the first word line 151 can be arranged on the same layer as the gate 113 of the transistor, and the second word line 152 is arranged around the gate 413 of the dummy transistor, and the second word line 152 can be arranged on the same layer as the gate 413 of the dummy transistor. The second word line 152 is arranged on the same layer as the first word line 151. Such an arrangement is conducive to simplifying the manufacturing process of the transistor 11 and the dummy transistor 41, and improving the manufacturing efficiency and manufacturing cost of the memory 01.

[0122] In summary, for the transistors 11 in the memory array 1, the gate electrodes 113 of the plurality of transistors arranged along the second direction Y can be electrically connected to the same word line 15; and the second electrodes 112 of the plurality of transistors arranged along the third direction Z are electrically connected to the same bit line 14. The word line 15 is used to receive a word line control signal to turn on the transistor 11, and the bit line 14 is used to receive a bit line 14 control signal to read or write the bit unit.

[0123] Furthermore, if Fig.10As shown, the memory array 1 may also include a plurality of first conductive contacts 161, one first conductive contact 161 is provided corresponding to one transistor 11, and the first conductive contact 161 is located between the first pole 111 of the transistor and the capacitor 12. By providing the first conductive contact, it is convenient for at least one capacitor 12 to be electrically connected to the first pole 111 of the transistor. The filling structure 4 may also include a plurality of second conductive contacts 162, one second conductive contact 162 is provided corresponding to one dummy transistor 41, and the second conductive contact 162 is located between the first pole 411 of the dummy transistor and the isolation sidewall 3. Based on the above structure, the second conductive contact 162 can be provided in the same layer as the first conductive contact 161. The above arrangement is conducive to simplifying the manufacturing process of the memory 01, and can improve the manufacturing efficiency and manufacturing cost of the memory 01.

[0124] The first conductive contact 161 and the second conductive contact 162 can both be made of metal materials, for example, one or more conductive materials such as TiN (titanium nitride), Ti (titanium), Au (gold), W (tungsten), Mo (molybdenum), In-Ti-O (ITO, indium tin oxide), Al (aluminum), Cu (copper), Ru (ruthenium), and Ag (silver).

[0125] Continue to refer to Fig.10 In an embodiment where the number of capacitors 12 is multiple, multiple capacitors 12 corresponding to one transistor 11 are stacked along the first direction X. Each capacitor 12 includes a first capacitor electrode 121, a capacitor layer 122, and a second capacitor electrode 123. Exemplarily, the first capacitor electrode 121 can be arranged around the capacitor layer 122, and the capacitor layer 122 can be arranged around the second capacitor electrode 123. Multiple capacitors 12 stacked along the first direction X can share the same second capacitor electrode 123, and the second capacitor electrode 123 can also be called a pillar.

[0126] In the same plane parallel to the substrate 2, the first capacitor electrodes 121 of the plurality of capacitors 12 are electrically connected to the plate line (PL). The plate line PL is used to receive the plate line control signal, and the voltage difference between the bit line control signal and the plate line control signal causes the capacitor layer 122 of the selected capacitor 12 to be positively polarized or negatively polarized, so as to write different logic information in the selected capacitor 12. For example, when the capacitor layer 122 is positively polarized, the logic signal "0" is written, and for another example, when the capacitor layer 122 is negatively polarized, the logic signal "1" is written.

[0127] The first capacitor electrode 121 and the second capacitor electrode 123 in the capacitor 12 are both made of conductive materials. Among the selectable materials, one or more conductive materials such as TiN (titanium nitride), Ti (titanium), Au (gold), W (tungsten), Mo (molybdenum), In-Ti-O (ITO, indium tin oxide), Al (aluminum), Cu (copper), Ru (ruthenium), and Ag (silver) can be used.

[0128] The capacitance layer 122 in the capacitor 12 can be made of ferroelectric materials such as ZrO2, HfO2, Al-doped HfO2, Si-doped HfO2, Zr-doped HfO2, La-doped HfO2, Y-doped HfO2, or materials doped with other elements based on the materials and any combination thereof.

[0129] The embodiment of the present application also provides a method for preparing the memory 01, which is used to prepare the memory 01 in any of the above embodiments. Fig.14 The following is a flowchart of a method for preparing a memory 01 exemplarily provided in the embodiment of the present application. Fig.14 , the preparation method comprises steps S101-S103:

[0130] S101. Provide a substrate.

[0131] The following is combined with Figures 15 to 18 The specific process flow involved in step S101 is introduced. In the embodiment of the present application, after providing the substrate 2, the following is also included:

[0132] Fig.15 This is a structural diagram of forming an intermediate conductive line 1302 in a method for preparing a memory 01 provided exemplarily in an embodiment of the present application. Fig.15 As shown, a plurality of bit lines 14 spaced apart along a third direction Z and a plurality of intermediate conductive lines 1302 spaced apart along the third direction Z are formed, the intermediate conductive lines 1302 are located on the side of the bit lines 14 away from the substrate 2, and the extension directions of the bit lines 14 and the intermediate conductive lines 1302 are parallel to the second direction Y; the second direction Y and the third direction Z are both perpendicular to the first direction X, and the second direction Y intersects with the third direction Z.

[0133] In some embodiments, a bit line conductive layer and an intermediate conductive layer may be sequentially stacked on the substrate 2, and a portion of the bit line conductive layer and the intermediate conductive layer may be etched to form a plurality of bit lines 14 spaced apart along the third direction Z and a plurality of intermediate conductive lines 1302 spaced apart along the third direction Z. The material of the bit line 14 may be as described in the above embodiment, and will not be described in detail in the embodiment of the present application.

[0134] Fig.16This is a structural diagram of removing part of the middle conductive line 1302 in a method for preparing a memory 01 provided exemplarily in an embodiment of the present application. Fig.16 After forming the middle conductive line 1302, the method further includes: removing part of the middle conductive line 1302 to form a plurality of grooves 1301 arranged at intervals, and the middle conductive line 1302 between adjacent grooves 1301 constitutes the conductive part 131. Exemplarily, part of the middle conductive line 1302 can be removed by processes such as exposure and etching to form a plurality of grooves 1301. The remaining middle conductive line 1302 between adjacent grooves 1301 is the conductive part 131.

[0135] Furthermore, while forming a plurality of conductive portions 131, the second electrode 112 of the transistor is also formed. That is, the conductive portion 131 is disposed in the same layer as the second electrode 112 of the transistor. The conductive portion 131 and the second electrode 112 of the transistor are made of the same material, which can be as described in the above embodiment and will not be described in detail here.

[0136] Fig.17 This is a structural diagram of a dielectric portion 132 formed in a method for preparing a memory 01 provided exemplarily in an embodiment of the present application. Fig.17 , a dielectric portion 132 is formed in the groove 1301, and the conductive portion 131 and the dielectric portion 132 alternately arranged along the second direction Y constitute the conductive line 13. Exemplarily, a deposition process or the like can be used to fill the groove 1301 with a dielectric material. After the dielectric material is filled, a chemical mechanical polishing process can be used to planarize the surface of the dielectric material to form the dielectric portion 132, and the surface of the dielectric portion 132 facing away from the substrate 2 and the surface of the conductive portion 131 facing away from the substrate 2 are located in the same plane.

[0137] In some embodiments, the filling structure 4 includes a dummy transistor 41. Further, while the dielectric portion 132 is formed in the groove 1301, a second electrode 412 of the dummy transistor is also formed. That is, the dielectric portion 132 and the second electrode 412 of the dummy transistor are arranged in the same layer. The dielectric portion 132 and the second electrode 412 of the dummy transistor are made of the same material, which can be as described in the above embodiment and will not be repeated here.

[0138] In the embodiment of the present application, after forming the second electrode 412 of the dummy transistor, the further step includes: forming an insulating portion 1501 .

[0139] Fig.18 This is a structural diagram of forming an insulating portion 1501 in a method for preparing a memory 01 provided exemplarily in an embodiment of the present application. Fig.18, an insulating layer 1501a may be formed on the conductive portion 131 and the dielectric portion 132. After the insulating layer 1501a is formed, a plurality of word lines 15 spaced apart along the second direction Y are formed on the insulating layer 1501a. The word lines 15 are located on the side of the conductive line 13 away from the substrate 2. The extending direction of the word lines 15 is parallel to the third direction Z. Exemplarily, the word lines 15 include a first word line 151 and a second word line 152, wherein the projection of the first word line 151 on the conductive line 13 intersects with the conductive portion 131, and the projection of the second word line 152 on the conductive line 13 intersects with the dielectric portion 132.

[0140] In some embodiments, after forming the insulating layer 1501a, a word line conductive layer may be formed on the insulating layer 1501a so as to achieve electrical isolation between the subsequently formed word line 15 and the conductive line 13; and a portion of the word line conductive layer may be removed to form the first word line 151 and the second word line 152. In this way, the first word line 151 and the second word line 152 are arranged on the same layer.

[0141] Furthermore, after forming the first word line 151 and the second word line 152, an insulating material 1501b may be filled between two adjacent word lines 15. The insulating material 1501b is made of the same material as the insulating layer 1501a, so that the insulating material 1501b and the insulating layer 1501a together constitute an insulating portion 1501 to achieve electrical isolation between two adjacent word lines 15. Through the above arrangement, the insulating portion 1501 is located between multiple transistors 11 of the memory array 1, and in the direction parallel to the substrate 2, the insulating portion 1501 is also located between transistors 11 of adjacent memory arrays 1.

[0142] In the embodiment where the filling structure 4 includes a dummy transistor 41, a metal gate 1132 of the transistor and a metal gate 4132 of the dummy transistor are formed while forming a plurality of word lines 15 spaced apart along the second direction Y. That is, the first word line 151 is disposed at the same layer and in contact with the metal gate 1132 of the transistor, and the second word line 152 is disposed at the same layer and in contact with the metal gate 4132 of the dummy transistor, and the materials thereof may be as described in the above embodiment, and will not be described in detail herein.

[0143] In the embodiment of the present application, after forming the conductive line 13, the following steps are further included:

[0144] S102, forming a plurality of storage arrays and filling structures, wherein the plurality of storage arrays and filling structures are all located on a substrate; wherein the storage array comprises a plurality of storage cells, the storage cells comprise transistors and at least one capacitor stacked along a first direction, and the at least one capacitor is electrically connected to a side of the transistor facing away from the substrate; the first direction is perpendicular to the substrate; in a direction parallel to the substrate, the filling structure is located between two adjacent storage arrays.

[0145] The following is combined with Fig.19 To Attachment Fig.23 The specific process flow involved in the above step S102 is introduced. In the embodiment of the present application, the step of forming a plurality of storage arrays 1 and a filling structure 4 further includes:

[0146] Fig.19 The structure diagram of forming the first channel hole 1503 and the second channel hole 1505 in the manufacturing method of the memory 01 provided by the embodiment of the present application is exemplified. Fig.19 As shown, a first channel hole 1503 and a second channel hole 1505 are formed through the word line 15. The first channel hole 1503 can penetrate the first word line 151 and reach the conductive portion 131 of the conductive line 13; the second channel hole 1505 can penetrate the second word line 152 and reach the dielectric portion 132 of the conductive line 13.

[0147] Fig. 20 The structure diagram of forming a transistor 11 and a dummy transistor 41 in a method for preparing a memory 01 provided by way of example in an embodiment of the present application. Fig. 20 As shown, the gate dielectric material and the channel material are filled in the first channel hole 1503 and the second channel hole 1505 to form the gate dielectric layer 1131 of the transistor and the channel layer 114 of the transistor in the first channel hole 1503, and the gate dielectric layer 4131 of the dummy transistor and the channel layer 414 of the dummy transistor are formed in the second channel hole 1505. The metal gate 1132 of the transistor and the gate dielectric layer 1131 of the transistor constitute the gate 113 of the transistor, the gate 113 of the transistor surrounds the channel layer 114 of the transistor, the metal gate 4132 of the dummy transistor and the gate dielectric layer 4131 of the dummy transistor constitute the gate 413 of the dummy transistor, and the gate 413 of the dummy transistor surrounds the channel layer 414 of the dummy transistor.

[0148] Through the above configuration, the gate 113 of the transistor and the gate 413 of the dummy transistor are arranged in the same layer, and their materials can be as described in the above embodiment, which will not be repeated here. The channel layer 114 of the transistor and the channel layer 414 of the dummy transistor are arranged in the same layer, and their materials can be as described in the above embodiment, which will not be repeated here.

[0149] like Fig. 20As shown, the first electrode 111 of the transistor and the first electrode 411 of the virtual transistor are formed, the first electrode 111 of the transistor is located on the side of the channel layer 114 of the transistor away from the substrate 2, and the first electrode 411 of the virtual transistor is located on the side of the channel layer 414 of the virtual transistor away from the substrate 2. Through the above arrangement, the first electrode 111 of the transistor can be arranged in the same layer as the first electrode 411 of the virtual transistor, that is, the first electrode 111 of the transistor and the first electrode 411 of the virtual transistor are made of the same material, and the material can be as described in the above embodiment, which will not be repeated here. Among them, the material of the formed virtual transistor 41 is different from that of the insulating portion 1501.

[0150] In the present application embodiment, Fig. 20 As shown, after forming the first electrode 111 of the transistor and the first electrode 411 of the dummy transistor, a first conductive contact 161 and a second conductive contact 162 are also formed, wherein the first conductive contact 161 and the second conductive contact 162 are arranged in the same layer. The first conductive contact 161 and the second conductive contact 162 are the same, and their materials can be as described in the above embodiment, which will not be repeated here.

[0151] In the embodiment of the present application, after forming the first electrode 111 of the transistor and the first electrode 411 of the dummy transistor, a plurality of storage arrays 1 are formed, further comprising:

[0152] Fig.21 The structure diagram of forming a conductive layer 1201 and a dielectric layer in a method for preparing a memory 01 provided by an exemplary embodiment of the present application. Fig.21 As shown, multiple dielectric layers 1202 and multiple conductive layers 1201 are alternately stacked. The materials of the dielectric layers 1202 and the conductive layers 1201 can be as described in the above embodiments, which will not be described again.

[0153] The number of dielectric layers 1202 and the number of conductive layers 1201 may be equal. It is understood that the number of dielectric layers 1202 and the number of conductive layers 1201 may be adjusted accordingly according to the number of capacitors 12 in a storage unit 10. For example, for a storage unit 10 having a 1T3C structure, three dielectric layers 1202 and three conductive layers 1201 may be stacked.

[0154] Fig. 22 This is a structural diagram of forming a through hole 1203 in a method for preparing a memory 01 provided exemplarily in an embodiment of the present application. Fig. 22 As shown, a through hole 1203 is formed to penetrate the multi-layer dielectric layer 1202 and the multi-layer conductive layer 1201. Exemplarily, the through hole 1203 can penetrate to the first conductive contact 161. The number of through holes 1203 can be the same as the number of transistors 11, and one through hole 1203 is opposite to one transistor 11.

[0155] Fig.23 The structure diagram of forming a capacitor 12 in a method for preparing a memory 01 provided by way of example in an embodiment of the present application. Fig.23 As shown, capacitor material and electrode material are filled in the through hole 1203 in sequence to form a capacitor layer 122 and a capacitor electrode in the through hole 1203. The capacitor layer 122 is located between the capacitor electrode and the side wall of the through hole 1203. The capacitor electrode is a common second capacitor electrode 123 of multiple capacitors 12. At least a portion of the conductive layer 1201 surrounding the capacitor layer 122 is the first capacitor electrode 121 of the capacitor 12.

[0156] In summary, combined with Fig.10 The multiple transistors 11 and the multiple capacitors 12 formed by the above steps constitute the memory array 1. By setting a filling structure 4 between the two memory arrays 1, the structure density located in the isolation area N1 is increased, thereby reducing the difference in structure density between the edge area N2 of the memory array 1 and the isolation area N1. When performing the process, the process defects of the film layer structure in the edge area N2 of the memory array 1 can be improved, thereby improving the performance degradation of the transistor 11 located in the edge area N2 of the memory array 1.

[0157] S103 , forming an isolation sidewall, wherein the isolation sidewall is located on a side of the filling structure facing away from the substrate, and in a direction parallel to the substrate, the isolation sidewall is located between two adjacent memory arrays.

[0158] The following is combined with Fig.24 and attached Fig.25 The specific process flow involved in the above step S103 is introduced. In the embodiment of the present application, after forming the alternately stacked multi-layer dielectric layer 1202 and the multi-layer conductive layer 1201, the isolation sidewall 3 is formed, including:

[0159] Fig.24 The structure diagram of forming a filling space 31 in a method for preparing a memory 01 provided by way of example in an embodiment of the present application. Fig.24 As shown, a filling space 31 is formed that penetrates the multi-layer dielectric layer 1202 and the multi-layer conductive layer 1201. The filling space 31 can penetrate to the second conductive contact 162, and the filling space 31 can face the dummy transistor 41, that is, located between the two memory arrays 1. The filling space 31 is a slit.

[0160] Fig.25 The structure diagram of forming the isolation sidewall 3 in the manufacturing method of a memory 01 provided by an example of the present application. Fig.25As shown, an isolation material is filled in the filling space 31 to form an isolation spacer 3. The filled insulating material may be, for example, one or a combination of silicon nitride, silicon oxide, and silicon oxynitride.

[0161] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A memory, characterized in that: include: substrate; A plurality of memory arrays, the plurality of memory arrays being located on the substrate, the memory arrays comprising a plurality of memory cells, the memory cells comprising transistors and at least one capacitor stacked along a first direction, the at least one capacitor being electrically connected to a side of the transistor away from the substrate; the first direction being perpendicular to the substrate; A filling structure, located on the substrate, and in a direction parallel to the substrate, the filling structure is located between two adjacent transistors of the memory array; The isolation spacer is located on a side of the filling structure away from the substrate. In a direction parallel to the substrate, the isolation spacer is located between two adjacent capacitors of the storage array.

2. The memory according to claim 1, characterized in that: The filling structure includes a dummy transistor, at least a portion of a film layer of the dummy transistor is arranged in the same layer as at least a portion of a film layer of the transistor, and the dummy transistor is arranged at an interval from the transistor.

3. The memory according to claim 2, characterized in that: The first electrode of the transistor and the second electrode of the transistor are arranged along the first direction, the first electrode of the transistor is electrically connected to the at least one capacitor, the channel layer of the transistor is located between the first electrode of the transistor and the second electrode of the transistor, and the gate of the transistor surrounds the channel layer of the transistor; The first electrode of the dummy transistor and the second electrode of the dummy transistor are arranged along the first direction, the first electrode of the dummy transistor is connected to the isolation sidewall, the channel layer of the dummy transistor is located between the first electrode of the dummy transistor and the second electrode of the dummy transistor, and the gate of the dummy transistor surrounds the channel layer of the dummy transistor; The first electrode of the transistor and the first electrode of the virtual transistor are arranged in the same layer, the channel layer of the transistor and the channel layer of the virtual transistor are arranged in the same layer, and the gate of the transistor and the gate of the virtual transistor are arranged in the same layer.

4. The memory according to claim 3, characterized in that: A plurality of the storage units are arranged at intervals along a second direction, and a plurality of the storage units are arranged at intervals along a third direction; the second direction and the third direction are both perpendicular to the first direction, and the second direction intersects with the third direction; The memory further comprises a plurality of conductive lines arranged at intervals along the third direction, the extending direction of the conductive lines being parallel to the second direction, the conductive lines comprising conductive portions and dielectric portions alternately arranged along the second direction, the conductive portions being arranged in the same layer and in contact with the second electrode of the transistor, and the dielectric portions being arranged in the same layer and in contact with the second electrode of the dummy transistor; The memory further includes a plurality of bit lines spaced apart along the third direction, the bit lines being located between the conductive line and the substrate, the extending direction of the bit lines being parallel to the second direction, and the bit lines being electrically connected to the conductive portions of the conductive lines.

5. The memory according to any one of claims 2 to 4, characterized in that: A plurality of the storage units are arranged at intervals along a second direction, and a plurality of the storage units are arranged at intervals along a third direction; the second direction and the third direction are both perpendicular to the first direction, and the second direction intersects with the third direction; There are multiple dummy transistors located between two adjacent storage arrays, the multiple dummy transistors are arranged at intervals along the third direction, and the dummy transistors and the multiple transistors arranged along the second direction are arranged at intervals in the second direction.

6. The memory according to claim 5, characterized in that: A row of the dummy transistors arranged along the third direction constitutes a dummy transistor group, a plurality of the dummy transistor groups are located between two adjacent storage arrays, and the plurality of dummy transistor groups are arranged at intervals along the second direction.

7. The memory according to claim 6, characterized in that: The distance between the dummy transistor and the transistor that are adjacent to each other and arranged along the second direction is equal to the distance between two of the transistors that are adjacent to each other and arranged along the second direction.

8. The memory according to claim 7, characterized in that: The distance between two adjacent dummy transistors arranged along the second direction is equal to the distance between two adjacent transistors arranged along the second direction.

9. The memory according to claim 7 or 8, characterized in that: The memory also includes a plurality of word lines spaced apart along the second direction, wherein the word lines extend in a direction parallel to the third direction, at least one of the word lines is electrically connected to the gates of the plurality of transistors arranged along the third direction, and at least one of the word lines is electrically connected to the gates of the plurality of dummy transistors arranged along the third direction.

10. The memory according to claim 1, characterized in that: The filling structure includes a support block, and the material of the support block includes insulating material.

11. The memory according to any one of claims 1 to 10, characterized in that: The memory further comprises an insulating portion, wherein the insulating portion is located between the filling structure and the memory array, and the insulating portion is also located between the isolation sidewall and the memory array, and the insulating portion and the filling structure are made of different materials.

12. The memory according to any one of claims 1 to 11, characterized in that: The capacitor is a ferroelectric capacitor.

13. A method for preparing a memory, characterized in that: include: providing a substrate; A plurality of memory arrays and filling structures are formed, wherein the plurality of memory arrays and the filling structures are all located on the substrate; wherein the memory array comprises a plurality of memory cells, the memory cells comprise transistors and at least one capacitor stacked along a first direction, the at least one capacitor being electrically connected to a side of the transistor away from the substrate; the first direction is perpendicular to the substrate; in a direction parallel to the substrate, the filling structure is located between two adjacent memory arrays; An isolation spacer is formed. The isolation spacer is located on a side of the filling structure away from the substrate. In a direction parallel to the substrate, the isolation spacer is located between two adjacent storage arrays.

14. The method for preparing a memory according to claim 13, characterized in that: After providing the substrate and before forming a plurality of storage arrays and a filling structure, the preparation method further includes: forming a plurality of bit lines spaced apart along a third direction and a plurality of intermediate conductive lines spaced apart along the third direction, wherein the intermediate conductive lines are located on a side of the bit lines away from the substrate, and the extending directions of the bit lines and the intermediate conductive lines are parallel to a second direction; the second direction and the third direction are both perpendicular to the first direction, and the second direction intersects the third direction; Removing part of the middle conductive line to form a plurality of grooves arranged at intervals, wherein the middle conductive line between adjacent grooves constitutes a conductive portion; A dielectric portion is formed in the groove, and a plurality of the dielectric portions and a plurality of the conductive portions alternately arranged along the second direction constitute a conductive line; A plurality of word lines are formed and arranged at intervals along the second direction. The word lines are located on a side of the conductive line away from the substrate, and an extending direction of the word lines is parallel to the third direction.

15. The method for preparing a memory according to claim 14, characterized in that: The filling structure includes a dummy transistor, While forming the plurality of conductive parts, a second electrode of the transistor is also formed; While forming the dielectric portion in the groove, a second electrode of the dummy transistor is also formed; While forming the plurality of word lines spaced apart along the second direction, the metal gate of the transistor and the metal gate of the dummy transistor are also formed.

16. The method for preparing a memory according to claim 15, characterized in that: After forming a plurality of word lines spaced apart along the second direction, forming a plurality of storage arrays and filling structures further includes: forming a first channel hole and a second channel hole penetrating the word line; Filling the first channel hole and the second channel hole with a gate dielectric material and a channel material to form a gate dielectric layer of the transistor and a channel layer of the transistor in the first channel hole, and forming a gate dielectric layer of the dummy transistor and a channel layer of the dummy transistor in the second channel hole; wherein the metal gate of the transistor and the gate dielectric layer of the transistor constitute the gate of the transistor, the gate of the dummy transistor surrounds the channel layer of the dummy transistor, the metal gate of the dummy transistor and the gate dielectric layer of the dummy transistor constitute the gate of the dummy transistor, and the gate of the dummy transistor surrounds the channel layer of the dummy transistor; A first electrode of the transistor and a first electrode of the dummy transistor are formed. The first electrode of the transistor is located on a side of the channel layer of the transistor away from the substrate. The first electrode of the dummy transistor is located on a side of the channel layer of the dummy transistor away from the substrate.

17. The method for preparing a memory according to claim 16, characterized in that: After forming the gate of the transistor and the gate of the dummy transistor, forming a plurality of memory arrays further includes: forming a plurality of dielectric layers and a plurality of conductive layers that are alternately stacked; forming a through hole penetrating the multi-layer dielectric layer and the multi-layer conductive layer; Capacitor material and electrode material are sequentially filled in the through hole to form a capacitor layer and a capacitor electrode in the through hole, wherein the capacitor layer is located between the capacitor electrode and the side wall of the through hole, wherein the capacitor electrode is a common second capacitor electrode of a plurality of the capacitors, and at least a portion of the conductive layer surrounding the capacitor layer is a first capacitor electrode of the capacitor.

18. The method for preparing a memory according to claim 17, characterized in that: After forming the alternately stacked multiple dielectric layers and multiple conductive layers, forming the isolation sidewalls includes: forming a filling space penetrating the multiple dielectric layers and the multiple conductive layers; An isolation material is filled in the filling space to form an isolation sidewall.

19. An electronic device, characterized in that: include: processor; and A memory as claimed in any one of claims 1 to 12, or a memory made by the method for making a memory as claimed in any one of claims 13 to 18; the memory is electrically connected to the processor.

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