Preparation method of trench gate silicon carbide VDMOS (Vertical Double-diffused Metal Oxide Semiconductor) with low on-resistance

Abstract

The invention provides a preparation method of a trench gate silicon carbide VDMOS (Vertical Double-diffused Metal Oxide Semiconductor) with low on-resistance, which comprises the following steps of: depositing metal on the lower side surface of a silicon carbide substrate to form a drain metal layer, and epitaxially growing on the upper side surface of the silicon carbide substrate to form a drift layer; forming a barrier layer above the drift layer, and performing etching and ion implantation to form a freewheeling region and a P-type source region; a barrier layer is formed again, etching and ion implantation are carried out, and a P-type well region, a masking layer and an N-type source region are formed; a barrier layer is formed again, etching is carried out to form a groove, then oxidation is carried out to form a gate dielectric layer, and a groove is formed in the gate dielectric layer; a barrier layer is formed again, the barrier layer is etched to form a through hole, metal is deposited, and a gate metal layer is formed; and re-forming a barrier layer, etching the barrier layer to form a through hole, etching the drift layer, depositing metal, forming a source metal layer, and removing the barrier layer to complete preparation. The on-resistance of the device can be effectively reduced, the body diode conduction loss of the device is reduced, and the switching speed of the device is improved.

Description

Technical Field

[0001] The invention relates to a method for preparing a trench gate silicon carbide VDMOS with low on-resistance. Background Art

[0002] Silicon carbide MOSFET is a typical representative of silicon carbide power devices, and is widely used in electric vehicles, aerospace, power conversion and other fields. For silicon carbide power MOSFET, different fields have different requirements for device performance, but in general, the overall requirements are lower on-resistance, faster switching speed, higher reliability (including gate reliability, drain voltage impact reliability, etc.) and lower body diode conduction loss. Summary of the invention

[0003] The technical problem to be solved by the present invention is to provide a method for preparing a trench gate silicon carbide VDMOS with low on-resistance, which can effectively reduce the on-resistance of the device, reduce the body diode conduction loss of the device, and improve the switching speed of the device.

[0004] The present invention is implemented as follows: a method for preparing a trench gate silicon carbide VDMOS with low on-resistance, comprising the following steps:

[0005] Step 1: depositing metal on the lower side of the silicon carbide substrate to form a drain metal layer, and epitaxially growing on the side of the silicon carbide substrate to form a drift layer;

[0006] Step 2: forming a barrier layer above the drift layer, etching the barrier layer to form a through hole, and performing ion implantation into the drift layer to form a freewheeling region;

[0007] Step 3, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and performing ion implantation into the drift layer to form a P-type source region;

[0008] Step 4, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and performing ion implantation into the freewheeling region to form a P-type well region;

[0009] Step 5, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and performing ion implantation into the freewheeling region to form a masking layer;

[0010] Step 6, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and performing ion implantation into the freewheeling region to form an N-type source region;

[0011] Step 7, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, etching the drift layer and the freewheeling region to form a groove, and then oxidizing to form a gate dielectric layer, wherein the gate dielectric layer is provided with a groove;

[0012] Step 8, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, depositing metal, and forming a gate metal layer;

[0013] Step 9: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, etch the drift layer, deposit metal to form a source metal layer, remove the barrier layer, and complete the preparation.

[0014] The advantages of the present invention are:

[0015] 1. The present invention adopts a trench gate structure and constructs a freewheeling region in the conductive channel of the device, thereby reducing the on-resistance below the P-type well region of the device and directly below the gate metal layer. While reducing the on-resistance, the current from the left and right sides of the trench gate flows to the bottom of the gate metal layer, thereby avoiding current concentration in the device;

[0016] Second, the present invention constructs two body diode paths, one is that the source metal layer of the device directly contacts the P-type source region to form an ohmic contact, the P-type source region and the N-type drift layer form a silicon carbide pn junction, and the conduction voltage drop is about 2.5V; the other is that the source metal layer of the device and the N-type freewheeling region form a Schottky junction, forming a Schottky diode, and the conduction voltage drop is about 1.2V. In traditional devices, only the silicon carbide pn junction has a large conduction voltage drop, and the body diode freewheeling loss is large;

[0017] 3. A shielding layer for the device is constructed to protect the gate corners of the device from being broken down by concentrated electric fields, thereby improving the reliability of the device gate. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The present invention will be further described below in conjunction with embodiments with reference to the accompanying drawings.

[0019] Figure 1 The present invention is a flow chart of a method for preparing a trench gate silicon carbide VDMOS with low on-resistance.

[0020] Figure 2 A cross-sectional view of the process of manufacturing a trench gate silicon carbide VDMOS with low on-resistance according to the present invention Figure 1 .

[0021] Figure 3 A cross-sectional view of the process of manufacturing a trench gate silicon carbide VDMOS with low on-resistance according to the present invention Figure 2 .

[0022] Figure 4 A cross-sectional view of the process of manufacturing a trench gate silicon carbide VDMOS with low on-resistance according to the present invention Figure 3 .

[0023] Figure 5 A cross-sectional view of the process of manufacturing a trench gate silicon carbide VDMOS with low on-resistance according to the present invention Figure 4 .

[0024] Figure 6 A cross-sectional view of the process of manufacturing a trench gate silicon carbide VDMOS with low on-resistance according to the present invention Figure 5 .

[0025] Figure 7 A cross-sectional view of the process of manufacturing a trench gate silicon carbide VDMOS with low on-resistance according to the present invention Figure 6 .

[0026] Figure 8 A cross-sectional view of the process of manufacturing a trench gate silicon carbide VDMOS with low on-resistance according to the present invention Figure 7 .

[0027] Fig. 9 A cross-sectional view of the process of manufacturing a trench gate silicon carbide VDMOS with low on-resistance according to the present invention Figure 8 .

[0028] Fig.10 A cross-sectional view of the process of manufacturing a trench gate silicon carbide VDMOS with low on-resistance according to the present invention Figure 9 .

[0029] Fig.11 A cross-sectional view of the process of manufacturing a trench gate silicon carbide VDMOS with low on-resistance according to the present invention Figure 10 .

[0030] Fig.12 A cross-sectional view of the process of manufacturing a trench gate silicon carbide VDMOS with low on-resistance according to the present invention Figure 10 one.

[0031] Fig.13 The schematic diagram of a trench gate silicon carbide VDMOS with low on-resistance of the present invention is shown. DETAILED DESCRIPTION

[0032] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0033] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0034] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "in contact with ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or part discussed below can be represented as a second element, component, region, layer or part.

[0035] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of one element or feature described in the figures to other elements or features. It should be understood that, in addition to the orientations described in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0036] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0037] like Figures 1 to 12 As shown, the embodiment of the present application provides a method for preparing a trench gate silicon carbide VDMOS with low on-resistance, comprising the following steps:

[0038] Step 1: depositing metal on the lower side of the silicon carbide substrate 1 to form a drain metal layer 8, and epitaxially growing on the side of the silicon carbide substrate 1 to form a drift layer 2;

[0039] Step 2, forming a barrier layer a above the drift layer 2, etching the barrier layer a to form a through hole, and performing ion implantation into the drift layer 2 to form a freewheeling region 4, wherein the ion implantation energy is 100-400 kev;

[0040] Step 3, remove the original barrier layer a, re-form the barrier layer a, etch the barrier layer a to form a through hole, perform ion implantation into the drift layer 2 to form a P-type source region 3, and the ion implantation energy is 100-400kev;

[0041] Step 4, remove the original barrier layer a, re-form the barrier layer a, etch the barrier layer a to form a through hole, perform ion implantation into the freewheeling region 4 to form a P-type well region 43, and the ion implantation energy is 200-300kev;

[0042] Step 5, remove the original barrier layer a, re-form the barrier layer a, etch the barrier layer a to form a through hole, perform ion implantation into the freewheeling region 4 to form a masking layer 42, and the ion implantation energy is 300-370kev;

[0043] Step 6, remove the original barrier layer a, re-form the barrier layer a, etch the barrier layer a to form a through hole, perform ion implantation into the freewheeling region 4 to form an N-type source region 44, and the ion implantation energy is 100-200kev;

[0044] Step 7, removing the original barrier layer a, re-forming the barrier layer a, etching the barrier layer a to form a through hole, etching the drift layer 2 and the freewheeling region 4 to form a groove 41, and then oxidizing to form a gate dielectric layer 5, wherein the gate dielectric layer 5 is provided with a groove 51;

[0045] Step 8, removing the original barrier layer a, re-forming the barrier layer a, etching the barrier layer a to form a through hole, depositing metal, and forming a gate metal layer 6;

[0046] Step 9, remove the original barrier layer a, re-form the barrier layer a, etch the barrier layer a to form a through hole, etch the drift layer 2, deposit metal to form a source metal layer 7, remove the barrier layer a, and complete the preparation.

[0047] like Fig.13 As shown, the silicon carbide VDMOS obtained by the above manufacturing method includes:

[0048] Silicon carbide substrate 1,

[0049] A drift layer 2, wherein the lower side of the drift layer 2 is connected to the upper side of the silicon carbide substrate 1;

[0050] A P-type source region 3, the lower side of the P-type source region 3 is connected to the upper side of the drift layer 2;

[0051] A freewheeling region 4, wherein the lower side of the freewheeling region 4 is connected to the upper side of the drift layer 2, and the outer side of the freewheeling region 4 is connected to the inner side of the P-type source region 3; a groove 41 is provided in the freewheeling region 4, and a masking layer 42 is provided at the bottom of the groove 41; a P-type well region 43 and an N-type source region 44 are provided in the freewheeling region 4, and the upper side of the P-type well region 43 is connected to the lower side of the N-type source region 44;

[0052] A gate dielectric layer 5, wherein the lower portion of the gate dielectric layer 5 is disposed in the groove 41, the outer sides of the gate dielectric layer 5 are respectively connected to the N-type source region 44 and the P-type well region 43, and the lower side of the gate dielectric layer 5 is connected to the upper side of the masking layer 42; a groove 51 is disposed on the gate dielectric layer 5;

[0053] A gate metal layer 6, wherein the gate metal layer 6 is disposed in the groove 51;

[0054] A source metal layer 7, wherein the source metal layer 7 is respectively connected to the P-type source region 3, the freewheeling region 4 and the N-type source region 44;

[0055] and, a drain metal layer 8 , wherein the drain metal layer 8 is connected to the lower side of the silicon carbide substrate 1 .

[0056] The silicon carbide substrate 1, the drift layer 2 and the freewheeling region 4 are all N-type; the masking layer 42 is P-type, and the doping concentration of the silicon carbide substrate 1 is 2e18cm -3 The doping concentration of the drift layer 2 is 1e16cm -3 The doping concentration of the freewheeling region 4 is 1e17cm -3 The doping concentration of the masking layer 42 is 1e18cm -3 The doping concentration of the P-type well region 43 is 5e17cm -3 The doping concentration of the N-type source region 44 is 2e18cm -3 The doping concentration of the P-type source region 3 is 1e19cm -3 The concentration of the N-type silicon carbide substrate 1 is to ensure that a low-resistance ohmic contact is formed with the drain metal layer 8, thereby reducing the overall on-resistance of the device; the doping concentration of the N-type drift layer 2 is a compromise between the reverse withstand voltage and the on-resistance of the device; the doping concentration of the N-type freewheeling region 4 is to reduce the on-resistance of the device while forming a Schottky metal rather than an ohmic contact with the source metal layer 7; the P-type shielding layer 42 is to suppress the electric field concentration at the gate corner of the device and suppress the influence of the drain voltage shock on the gate of the device; the doping concentration of the N-type source region 44 and the P-type source region 3 is to form an ohmic contact with the source metal layer 7 and reduce the contact resistance.

[0057] The thickness of the N-type silicon carbide substrate 1 of the present invention is 1 μm, and the thickness of the N-type drift layer 2 is 15-25 μm, which can be adjusted within the above range according to different requirements for the withstand voltage characteristics of the device. The thickness of the P-type well region 43 is 300 nm, and the N-type freewheeling region 4 in the area below the P-type shielding layer 42 can effectively shield the capacitance effect of the gate to the drain, reduce the gate-drain charge of the device, and improve the switching speed of the device. The thickness of the P-type shielding layer 42 is 200 nm, which is to protect the gate of the device and suppress the breakdown problem caused by the electric field concentration at the gate corner. The side wall thickness of the gate dielectric layer 5 is 50 nm, the thickness of the P-type source region 3 is 900 nm, the thickness of the N-type source region 44 is 250 nm, and the thickness of the P-type well region 43 is 300 nm; the distance between the lower side of the shielding layer 42 and the upper side of the drift layer 2 is 100 nm.

[0058] The present invention adopts a trench gate structure, constructs an N-type freewheeling region 4 in the conductive channels on the left and right sides of the device, reduces the on-resistance below the P-type well region 43 of the device and directly below the gate, reduces the on-resistance and directs the current from the left and right sides of the trench gate of the device to flow below the gate of the device, avoiding current concentration in the device;

[0059] The present invention constructs two body diode paths, one is that the device source metal layer 7 directly contacts with the P-type source region 3 to form an ohmic contact, the P-type source region 3 and the N-type drift layer 2 constitute a silicon carbide pn junction, and the conduction voltage drop is about 2.5V; the other is that the device source metal layer 7 and the N-type freewheeling region 4 constitute a Schottky junction, forming a Schottky diode, and the conduction voltage drop is about 1.2V. In traditional devices, only the silicon carbide pn junction has a large conduction voltage drop, and the body diode freewheeling loss is large.

[0060] Although the specific implementation modes of the present invention are described above, those skilled in the art should understand that the specific implementation modes described are only illustrative and are not intended to limit the scope of the present invention. Equivalent modifications and changes made by those skilled in the art in accordance with the spirit of the present invention should be included in the scope of protection of the claims of the present invention.

Claims

1. A method for preparing a low on-resistance trench gate silicon carbide VDMOS, characterized in that: The steps include: Step 1: depositing metal on the lower side of the silicon carbide substrate to form a drain metal layer, and epitaxially growing on the side of the silicon carbide substrate to form a drift layer; Step 2: forming a barrier layer above the drift layer, etching the barrier layer to form a through hole, and performing ion implantation into the drift layer to form a freewheeling region; Step 3, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and performing ion implantation into the drift layer to form a P-type source region; Step 4, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and performing ion implantation into the freewheeling region to form a P-type well region; Step 5, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and performing ion implantation into the freewheeling region to form a masking layer; Step 6, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and performing ion implantation into the freewheeling region to form an N-type source region; Step 7, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, etching the drift layer and the freewheeling region to form a groove, and then oxidizing to form a gate dielectric layer, wherein the gate dielectric layer is provided with a groove; Step 8, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, depositing metal, and forming a gate metal layer; Step 9: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, etch the drift layer, deposit metal to form a source metal layer, remove the barrier layer, and complete the preparation.

2. The method for preparing a trench gate silicon carbide VDMOS with low on-resistance according to claim 1, characterized in that: The silicon carbide substrate, drift layer and freewheeling region are all N-type; the masking layer is P-type.

3. The method for preparing a trench gate silicon carbide VDMOS with low on-resistance according to claim 1, characterized in that: The doping concentration of the silicon carbide substrate is 2e18cm -3 The doping concentration of the drift layer is 1e16cm -3 The doping concentration of the freewheeling region is 1e17cm -3 The doping concentration of the masking layer is 1e18cm -3 The doping concentration of the P-type well region is 5e17 cm -3 The doping concentration of the N-type source region is 2e18cm -3 The doping concentration of the P-type source region is 1e19cm -3 .

4. The method for preparing a trench gate silicon carbide VDMOS with low on-resistance according to claim 1, characterized in that: The thickness of the P-type source region is equal to the thickness of the freewheeling region.

5. The method for preparing a trench gate silicon carbide VDMOS with low on-resistance according to claim 1, characterized in that: The thickness of the masking layer is 200 nm.

6. The method for preparing a trench gate silicon carbide VDMOS with low on-resistance according to claim 1, characterized in that: The distance between the lower side of the masking layer and the upper side of the drift layer is 100 nm.

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