A monolithic integrated double voltage rectifier based on quasi-vertical JTE SBD

Abstract

The application discloses a kind of monolithic integrated double voltage rectifier devices based on quasi-vertical JTE SBD, comprising: two quasi-vertical JTE SBD, respectively form first and second charge diode;Passivation layer, first layer metal in its interior: first capacitor cathode plate, second capacitor anode plate, first and second charge diode cathode;Second layer metal on the upper surface of passivation layer: first to fourth port, first and second charge diode anode, first capacitor anode plate and second capacitor cathode plate;First interlayer interconnect metal, connect second port and first capacitor cathode plate;Second interlayer interconnect metal, connect second charge diode anode and first charge diode cathode;Third interlayer interconnect metal, connect third port, second capacitor anode plate and second charge diode cathode.The device provided by the application has higher electrical performance and can be applied to high frequency, high power, strong radiation and other occasions.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of integrated circuits, and particularly relates to a monolithic integrated voltage doubler rectifier based on quasi-vertical JTE SBD (Schottky Rectifier Diode). BACKGROUND

[0002] Voltage doubler rectifier units are commonly used in voltage conversion of medium and low voltage power electronic devices and radio frequency systems. Traditional voltage doubler rectifier units are mostly composed of silicon single tube discrete devices, among which a more representative one is a DC-DC voltage stabilizing converter, the voltage boosting unit of which is composed of voltage doubler circuits connected in series, and each voltage doubler circuit is composed of two capacitors, two diodes and a bleeder resistor, so as to realize multi-stage amplification of voltage through multi-stage series connection. However, the voltage doubler rectifier unit composed of discrete devices has low integration, which is difficult to meet the needs of the times.

[0003] In addition, the core device of the existing voltage doubler rectifier unit, the rectifier diode, is mostly made of Si material, which has low power density, low withstand voltage and narrow application range, and is difficult to be miniaturized under high power conditions. With the increasing requirements of efficiency, power density and device size of power handling devices, Si-based devices are rapidly approaching the theoretical limit of their intrinsic material properties.

[0004] Therefore, there is an urgent need for a monolithic integrated voltage doubler rectifier unit with high electrical performance and capable of being applied to high-frequency, high-power and strong radiation occasions. SUMMARY

[0005] In order to solve the above problems existing in the prior art, the application provides a monolithic integrated voltage doubler rectifier based on quasi-vertical JTE SBD.

[0006] The technical problem to be solved by the application is solved by the following technical scheme:

[0007] A monolithic integrated voltage doubler rectifier based on quasi-vertical JTE SBD, comprising:

[0008] Two quasi-vertical JTE SBDs located on a silicon substrate; the two quasi-vertical JTE SBDs form a first charge diode and a second charge diode, respectively;

[0009] A passivation layer covering the two quasi-vertical JTE SBDs and the silicon substrate;

[0010] a first layer of metal inside the passivation layer; the first layer of metal comprises metal forming a first capacitor cathode plate, a second capacitor anode plate, a first charge diode cathode and a second charge diode cathode respectively; wherein the second capacitor anode plate and the second charge diode cathode are connected;

[0011] a second layer of metal on the upper surface of the passivation layer; the second layer of metal comprises metal forming a first port, a second port, a third port, a fourth port, a first charge diode anode, a second charge diode anode, a first capacitor anode plate and a second capacitor cathode plate respectively; wherein the first port, the second capacitor cathode plate and the first charge diode anode are connected, the first capacitor anode plate, the second charge diode anode and the fourth port are connected;

[0012] a first interlayer interconnect metal; the first interlayer interconnect metal connects the second port and the first capacitor cathode plate;

[0013] a second interlayer interconnect metal; the second interlayer interconnect metal connects the second charge diode anode and the first charge diode cathode;

[0014] a third interlayer interconnect metal; the third interlayer interconnect metal connects the third port and the second charge diode cathode.

[0015] Optionally, the quasi-vertical JTE SBD comprises: an epitaxial structure, a first JTE ring superimposed on the epitaxial structure, a second JTE ring superimposed on the first JTE ring, and a third JTE ring superimposed on the second JTE ring.

[0016] wherein the first JTE ring, the second JTE ring and the third JTE ring are superimposed to form a stepped JTE ring structure; the epitaxial structure comprises a GaN conduction layer and a GaN drift layer superimposed on the GaN conduction layer; the anode of the quasi-vertical JTE SBD is located at the center of the JTE ring structure; the cathode of the quasi-vertical JTE SBD is located on the GaN drift layer.

[0017] Optionally, the first JTE ring, the second JTE ring and the third JTE ring are all Mg-doped P-type BN.

[0018] Optionally, the doping concentration of the Mg-doped P-type BN is 1.0×10 16 cm -3 ~1.0×10 18 cm -3 .

[0019] Optionally, the width of the first JTE ring, the second JTE ring and the third JTE ring is 10-30 μm; wherein the width of the first JTE ring, the second JTE ring and the third JTE ring decreases in turn.

[0020] Optionally, the Si doping concentration of the GaN drift layer is 1.0×10 16 cm -3 -5.0×10 17 cm -3 .

[0021] Optionally, the Si doping concentration of the GaN conduction layer is 1.0×10 18 cm -3 -1.0×10 19 cm -3 .

[0022] Optionally, the length of the first capacitor cathode plate, the second capacitor anode plate, the first capacitor anode plate and the second capacitor cathode plate is 10-100 μm, and the width is 10-100 μm.

[0023] The application further provides a preparation method of a monolithic integrated double-voltage rectifier device based on a quasi-vertical JTE SBD, comprising:

[0024] Growth of an epitaxial layer on a silicon substrate, mesa etching and isolation etching of the epitaxial layer to form two epitaxial structures;

[0025] Preparation of JTE ring structures on the upper surfaces of the two epitaxial structures, respectively, to form two quasi-vertical JTE SBDs by using the two JTE ring structures subsequently; the two quasi-vertical JTE SBDs form a first charging diode and a second charging diode, respectively;

[0026] Deposition of a first passivation layer on the surface of the current device, and opening of the passivation layer to expose an anode region and a cathode region; the anode region corresponds to the anode of the quasi-vertical JTE SBD, and the cathode region corresponds to the cathode of the quasi-vertical JTE SBD;

[0027] Deposition of Schottky metal on the anode region and deposition of ohmic metal on the cathode region to form the two quasi-vertical JTE SBDs;

[0028] Deposition of a second passivation layer on the surface of the current device, and opening of the passivation layer to expose the Schottky metal and the ohmic metal;

[0029] Depositing a first metal layer on the current device; the first metal layer includes metal forming a first capacitor cathode plate, a second capacitor anode plate, a first charge diode cathode and a second charge diode cathode respectively; wherein the second capacitor anode plate and the second charge diode cathode are connected; the metal forming the first charge diode cathode and the second charge diode cathode is connected with the Schottky metal;

[0030] Depositing a third passivation layer on the surface of the current device, and performing an opening process on the passivation layer to expose the Schottky metal, the metal forming the first charge diode cathode and the second charge diode cathode, and the metal forming the first capacitor cathode plate.

[0031] Depositing a second metal layer, a first interlayer metal, a second interlayer metal and a third interlayer metal on the current device; the second metal layer includes metal forming a first port, a second port, a third port, a fourth port, a first charge diode anode, a second charge diode anode, a first capacitor anode plate and a second capacitor cathode plate respectively;

[0032] Wherein the first port, the second capacitor cathode plate and the first charge diode anode are connected, the first capacitor anode plate, the second charge diode anode and the fourth port are connected; wherein the metal forming the first charge diode anode and the second charge diode anode is connected with the Schottky metal; the first interlayer metal is connected with the second port and the first capacitor cathode plate; the second interlayer metal is connected with the second charge diode anode and the first charge diode cathode; the third interlayer metal is connected with the third port and the second charge diode cathode.

[0033] Optionally, the JTE ring structure includes: a first JTE ring superimposed on the epitaxial structure, a second JTE ring superimposed on the first JTE ring, and a third JTE ring superimposed on the second JTE ring; the first JTE ring, the second JTE ring and the third JTE ring are superimposed to form a stepped JTE ring structure.

[0034] The single-chip integrated voltage doubler rectifier device based on the quasi-vertical JTE SBD has the following advantages

[0035] Advantages:

[0036] (1) The single-chip integrated voltage doubler device provided by the application adopts silicon-based GaN single-chip integration, compared with traditional GaN integrated circuits, has smaller size, smaller parasitic, higher power density, lower cost and higher reliability, so that it can be applied to high-power power conversion systems with complex working conditions and limited size. Moreover, in the quasi-vertical JTE SBD adopted by the application, the JTE terminal structure has good electric field adjusting ability, improves the voltage resistance of the diode, and enhances the power handling capability of the voltage doubler device.

[0037] (2) The application uses silicon-based GaN material to reduce circuit cost, and uses quasi-vertical JTE SBD with Mg-doped P-BN to replace traditional Schottky diodes, uses the high breakdown field strength of BN material and the electric field adjusting ability of JTE terminal structure to improve the voltage resistance of the diode and enhance the power handling capability of the voltage doubler device.

[0038] (3) The core device of the application adopts GaN-based material, GaN has larger band gap, higher critical breakdown field and higher saturation velocity than Si material, so it has better electrical properties. In addition, its heat conductivity, temperature stability and corrosion resistance are much better than Si material. Therefore, the single-chip integrated voltage doubler device provided by the application has excellent characteristics such as low saturation velocity, low breakdown voltage, low inversion layer mobility and high device resistance, and can work stably under complex working conditions such as high frequency, high power and strong radiation, and has wider application prospect.

[0039] The application will be further described in detail below with reference to the accompanying drawings and the application. BRIEF DESCRIPTION OF DRAWINGS

[0040] Figure 1 is a three-dimensional structure diagram of a single-chip integrated voltage doubler device based on quasi-vertical JTE SBD provided by an embodiment of the application;

[0041] Figure 2 is a top view of a single-chip integrated voltage doubler device based on quasi-vertical JTE SBD provided by an embodiment of the application;

[0042] Figure 3(a) is a circuit schematic diagram of a single-chip integrated voltage doubler device based on quasi-vertical JTE SBD provided by an embodiment of the application;

[0043] Figure 3(b) shows the working principle of a single-chip integrated voltage doubler device based on quasi-vertical JTE SBD provided by an embodiment of the application;

[0044] Figure 4 shows the epitaxial structure of a single-chip integrated voltage doubler device based on quasi-vertical JTE SBD provided by an embodiment of the application;

[0045] Figure 5 A three-dimensional structure of the quasi-vertical JTE SBD in the embodiment of the present application is shown in FIG. 1;

[0046] Figure 6 A three-dimensional structure profile of the quasi-vertical JTE SBD in the embodiment of the present application is shown in FIG. 2;

[0047] Figures 7 to 17 A preparation process of the monolithic integrated voltage doubler rectifier device based on the quasi-vertical JTE SBD provided by the embodiment of the present application is shown in FIG. 3. DETAILED DESCRIPTION

[0048] The present application will be further described in detail below with specific embodiments, but the embodiments of the present application are not limited thereto.

[0049] In order to realize a monolithic integrated voltage doubler rectifier unit with higher electrical performance and capable of being applied to high frequency, high power, strong radiation and other occasions, the embodiment of the present application provides a monolithic integrated voltage doubler rectifier device based on a quasi-vertical JTE SBD. Referring to FIG. 1 and FIG. 2, Figure 1 and Figure 2 The device includes a silicon substrate (Si-substrate, crystal face (111)), two quasi-vertical JTE SBDs, a passivation layer, a first layer of metal, a second layer of metal, a first interlayer interconnection metal a, a second interlayer interconnection metal b and a third interlayer interconnection metal c.

[0050] The two quasi-vertical JTE SBDs are located on the silicon substrate; the two quasi-vertical JTE SBDs form a first charge diode D1 and a second charge diode D2, respectively.

[0051] The passivation layer covers the two quasi-vertical JTE SBDs and the silicon substrate.

[0052] The first layer of metal is located inside the passivation layer; the first layer of metal includes metal forming a first capacitor cathode plate, a second capacitor anode plate, a first charge diode cathode and a second charge diode cathode, respectively; wherein the second capacitor anode plate and the second charge diode cathode are connected.

[0053] The second layer of metal is located on the upper surface of the passivation layer; the second layer of metal includes metal forming a first port 1, a second port 2, a third port 3, a fourth port 4, a first charge diode anode, a second charge diode anode, a first capacitor anode plate and a second capacitor cathode plate, respectively. Among them, the first port 1 and the second port 2 are two alternating current input ports, and the third port 3 and the fourth port 4 are two voltage-boosting alternating current output ports. The first port 1, the second capacitor cathode plate and the first charge diode anode are connected, and the first capacitor anode plate, the second charge diode anode and the fourth port 4 are connected.

[0054] The first interlayer interconnect metal connects the second port 2 and the first capacitor cathode plate; the second interlayer interconnect metal connects the second charging diode anode and the first charging diode cathode; and the third interlayer interconnect metal connects the third port 3 and the second charging diode cathode.

[0055] In the embodiment of the present application, the first capacitor cathode plate and the first capacitor anode plate correspond to each other in up and down directions, cooperate with the inter-plate passivation layer, and form the first MIM parallel-plate dielectric capacitor C1; and the second capacitor cathode plate and the second capacitor anode plate correspond to each other in up and down directions, cooperate with the inter-plate passivation layer, and form the second MIM parallel-plate dielectric capacitor C2. The first MIM parallel-plate dielectric capacitor C1 and the second MIM parallel-plate dielectric capacitor C2 adopt the MIM structure and are suitable for monolithic integration.

[0056] In the embodiment of the present application, the first MIM parallel-plate dielectric capacitor C1 and the second MIM parallel-plate dielectric capacitor C2 have the inter-plate passivation layer thicknesses of 0.5 μm to 5 μm; and the second capacitor anode plate, the first capacitor cathode plate, the first capacitor anode plate and the second capacitor cathode plate have the lengths of 10 μm to 100 μm and the widths of 10 μm to 100 μm. By adjusting the inter-plate passivation layer thickness and the plate area, different capacitances can be obtained.

[0057] Figures 3(a) to 3(b) The circuit principle diagram of the monolithic integrated voltage doubler rectifier device provided by the embodiment of the present application is shown; and the working principle of the monolithic integrated voltage doubler rectifier device provided by the embodiment of the present application is described below in combination with the circuit principle diagram:

[0058] In the initial state of all diodes and capacitors in the device, assuming that an alternating current input signal with a peak voltage U0 is input into the device, the approximate running process of the signal in the device is shown as follows:

[0059] In the first period, the positive polarity voltage U0 is input into the first port 1, the first charging diode D1 is turned on, the second charging diode D2 is cut off, the first port 1 charges the first MIM parallel-plate dielectric capacitor C1 through the first charging diode D1, and the right side of the first MIM parallel-plate dielectric capacitor C1 has the potential of U0; the polarity is reversed, the positive polarity voltage is input into the device from the second port 2, the total voltage at the right end of the first MIM parallel-plate dielectric capacitor C1 is the sum of the power supply voltage and the voltage of the first MIM parallel-plate dielectric capacitor C1, i.e. 2U0, the second charging diode D2 is turned on, the first MIM parallel-plate dielectric capacitor C1 starts to charge the second MIM parallel-plate dielectric capacitor C2 through the second charging diode D2, and finally reaches the balance after the right side of the second MIM parallel-plate dielectric capacitor C2 has the potential of U0.

[0060] In the second cycle, at this time the positive voltage U0 is input to the first port 1, at this time the first charging diode D1 is turned on, the second charging diode D2 is cut off, the first port 1 charges the first MIM parallel plate dielectric capacitor C1 through the first charging diode D1, and makes the right side of the first MIM parallel plate dielectric capacitor C1 have the potential of U0; at this time the polarity is reversed, the positive voltage is input to the device from the second port 2, at this time the total voltage at the right end of the first MIM parallel plate dielectric capacitor C1 is the sum of the power supply voltage and the voltage of the first MIM parallel plate dielectric capacitor C1, 2U0, at this time the second charging diode D2 is turned on, the first MIM parallel plate dielectric capacitor C1 starts to charge the second MIM parallel plate dielectric capacitor C2 through the second charging diode D2, at this time the right side of the second MIM parallel plate dielectric capacitor C2 keeps the voltage U0 charged in the last cycle, that is, finally it will reach equilibrium after the first MIM parallel plate dielectric capacitor C1 has 0.5U0 and the right side of the second MIM parallel plate dielectric capacitor C2 has 1.5U0 potential.

[0061] In the third cycle, at this time the positive voltage U0 is input to the first port 1, at this time the first charging diode D1 is turned on, the second charging diode D2 is cut off, the first port 1 charges the first MIM parallel plate dielectric capacitor C1 through the first charging diode D1, and makes the right side of the first MIM parallel plate dielectric capacitor C1 have the potential of U0; at this time the polarity is reversed, the positive voltage is input to the circuit from the second port 2, at this time the total voltage at the right end of the first MIM parallel plate dielectric capacitor C1 is the sum of the power supply voltage and the voltage of the first MIM parallel plate dielectric capacitor C1, 2U0, at this time the second charging diode D2 is turned on, the first MIM parallel plate dielectric capacitor C1 starts to charge the second MIM parallel plate dielectric capacitor C2 through the second charging diode D2, at this time the right side of the second MIM parallel plate dielectric capacitor C2 keeps the voltage 1.5U0 charged in the last cycle, that is, finally it will reach equilibrium after the first MIM parallel plate dielectric capacitor C1 has 0.75U0 and the right side of the second MIM parallel plate dielectric capacitor C2 has 1.75U0 potential.

[0062] From the above three cycles, it can be seen that with the reciprocating of the voltage cycle, the potential on the second MIM parallel plate dielectric capacitor C2 will be more and more infinitely close to 2U0, that is, twice the amplitude of the input signal, realizing the function of voltage doubling.

[0063] The monolithic integrated double voltage rectifier device based on the quasi-vertical JTE SBD has silicon-based GaN monolithic integration, and has smaller size, smaller parasitic, higher power density, lower cost and higher reliability compared with traditional GaN integrated circuits, so that it can be applied to high-power power conversion systems with complex working conditions and limited size. In the quasi-vertical JTE SBD, the JTE terminal structure has good electric field adjusting ability, improves the voltage resistance of the diode, and enhances the power handling capacity of the double voltage rectifier device.

[0064] In one embodiment, the quasi-vertical JTE SBD includes an epitaxial structure, a first JTE ring superimposed on the epitaxial structure, a second JTE ring superimposed on the first JTE ring, and a third JTE ring superimposed on the second JTE ring.

[0065] In one embodiment, the quasi-vertical JTE SBD includes an epitaxial structure, a first JTE ring superimposed on the epitaxial structure, a second JTE ring superimposed on the first JTE ring, and a third JTE ring superimposed on the second JTE ring. Figure 5 Figure 6 The first JTE ring (JTE1), the second JTE ring (JTE2) and the third JTE ring (JTE3) form a stepped JTE ring structure. The anode of the quasi-vertical JTE SBD is located at the center of the JTE ring structure; the radius of the anode can be set to 30um-90um according to different power capacity of the device.

[0066] The first JTE ring, the second JTE ring and the third JTE ring in the stepped JTE ring structure have different widths and thicknesses, so as to play the best electric field modulation function under different sizes and doping conditions.

[0067] Preferably, the widths of the first JTE ring, the second JTE ring and the third JTE ring are 10um-30um; wherein the widths of the first JTE ring, the second JTE ring and the third JTE ring decrease in turn.

[0068] Preferably, the materials of the first JTE ring, the second JTE ring and the third JTE ring are Mg-doped P-type BN. Thus, the quasi-vertical JTE SBD with Mg-doped P-BN is used to replace the traditional Schottky diode, the high breakdown field strength of the BN material and the electric field adjusting ability of the JTE terminal structure are utilized to improve the voltage resistance of the diode and enhance the power handling capacity of the double voltage rectifier device.

[0069] Preferably, the doping concentration of the Mg-doped P-type BN is 1.0x10 16 cm -3 -1.0x10 18 cm -3 .

[0070] In the embodiment of the present application, the quasi-vertical JTE SBD includes an epitaxial structure, a first JTE ring superimposed on the epitaxial structure, a second JTE ring superimposed on the first JTE ring, and a third JTE ring superimposed on the second JTE ring. Figure 4 ​The epitaxial structure comprises a GaN conducting layer (N-GaN) and a GaN drift layer (N+GaN) superimposed on the GaN conducting layer; a cathode of the quasi-vertical JTE SBD is located on the GaN drift layer.

[0071] Preferably, the Si doping concentration of the GaN drift layer is 1.0*10 16 cm -3 ~5.0*10 17 cm -3 .

[0072] Preferably, the Si doping concentration of the GaN conducting layer is 1.0*10 18 cm -3 ~1.0*10 19 cm -3 .

[0073] Based on the same inventive concept, the application also provides a preparation method of a quasi-vertical JTE SBD-based monolithic integrated double-voltage rectifier device, comprising:

[0074] Step one, growing an epitaxial layer on a silicon substrate, mesa etching and isolation etching the epitaxial layer to form two epitaxial structures.

[0075] Specifically, a GaN conducting layer and a GaN drift layer are epitaxially grown on a silicon substrate in sequence to form an epitaxial layer. Then, the epitaxial layer is etched into two independent circular mesas so as to subsequently prepare two quasi-vertical JTE SBDs on the two circular blocks respectively. The two circular mesas are mesa etched respectively to expose a ring of GaN conducting layer, as shown in the left subgraph of FIG. 1. Figure 7 Then, the exposed ring of GaN conducting layer is continuously isolated etched to form an isolation region, thereby obtaining two epitaxial structures as shown in the right subgraph of FIG. 1. Figure 7

[0076] Step two, preparing a JTE ring structure on the upper surface of each epitaxial structure so as to subsequently form two quasi-vertical JTE SBDs by using the two JTE ring structures; the two quasi-vertical JTE SBDs form a first charging diode and a second charging diode respectively.

[0077] Here, the JTE ring structure is prepared on the epitaxial structure, which is convenient for subsequent connection of the device by using on-chip wiring. Specifically, a sputtering process is adopted to prepare a JTE ring structure on the upper surface of each epitaxial structure, i.e., the upper surface of the GaN drift layer.

[0078] ​Specifically, sputtering is first performed on the upper surface of the GaN drift layer to form a first JTE ring, and then sputtering is performed again on the upper surface of the JTE ring to form a second JTE ring. The second JTE ring is superimposed on the first JTE ring and is concentric with the first JTE ring, with a smaller radius than the first JTE ring; then, referring to the method of sputtering the second JTE ring on the first JTE ring, a third JTE ring is sputtered on the second JTE ring to form a third JTE ring, and so on, thereby forming a structure in which multiple JTE rings are stacked in sequence, that is, a JTE ring structure.

[0079] In one embodiment, the JTE ring structure may include: a first JTE ring superimposed on the epitaxial structure, a second JTE ring superimposed on the first JTE ring, and a third JTE ring superimposed on the second JTE ring; the first JTE ring, the second JTE ring, and the third JTE ring are superimposed to form a stepped JTE ring structure. In the specific preparation, a sputtering is first performed on the upper surface of the GaN drift layer to form the first JTE ring, such as Figure 8 Then, a secondary sputtering is performed on the upper surface of the first JTE ring to form a second JTE ring, as shown in FIG. Figure 8 Then, three sputterings are performed on the upper surface of the second JTE ring to form a third JTE ring, as shown in the right sub-figure; Figure 9 The left sub-graph in .

[0080] Step 3: deposit a first passivation layer on the surface of the current device, and perform openings in the passivation layer to expose the anode region and the cathode region; the anode region corresponds to the anode of the quasi-perpendicular JTE SBD, and the cathode region corresponds to the cathode of the quasi-perpendicular JTE SBD.

[0081] Specifically, a first passivation layer (material such as SiN) is deposited on the surface of the current device using a growth process. x ),like Figure 9 The right sub-figure in FIG. Then, a cathode region is selected on the passivation layer directly above the GaN conductive layer with a passivation layer deposited on the surface, and an anode region is selected on the passivation layer directly above the anode of the quasi-vertical JTE SBD. Holes are opened in the passivation layer in the cathode region and the anode region to expose the GaN drift layer directly below the anode region, which corresponds to the anode of the quasi-vertical JTE SBD, and to expose the GaN conductive layer directly below the cathode region, which corresponds to the cathode of the quasi-vertical JTE SBD, as shown in FIG. Figure 10 The left subgraph in .

[0082] Step 4: Deposit Schottky metal in the anode region and deposit ohmic metal in the cathode region to form two quasi-vertical JTE SBDs.

[0083] Specifically, a Schottky metal (e.g., a Ni / Au stack) is deposited in the anode region using a metal evaporation process to form the anode of the quasi-vertical JTE SBD, as shown in the right sub-diagram of FIG. 1. Figure 10 Then, an ohmic metal (e.g., a Ti / Al / Ni / Au stack) is deposited in the cathode region using a metal evaporation process to form the cathode of the quasi-vertical JTE SBD, as shown in the left sub-diagram of FIG. 2. Figure 11 .

[0084] Step five, a second passivation layer is deposited on the surface of the current device, and the first passivation layer is opened to expose the Schottky metal and the ohmic metal.

[0085] Specifically, the second passivation layer is deposited on the surface of the current device using an epitaxial growth process, as shown in FIG. 3. Figure 12 Then, the passivation layer is opened to expose the underlying Schottky metal and ohmic metal, as shown in FIG. 4. Figure 13 .

[0086] Step six, a first metal layer is prepared on the current device.

[0087] Here, the first metal layer (Metal layer 1) includes metals that form the first capacitor cathode plate, the second capacitor anode plate, the first charge diode cathode (i.e., the cathode of one quasi-vertical JTE SBD), and the second charge diode cathode (i.e., the cathode of another quasi-vertical JTE SBD), respectively; the second capacitor anode plate and the second charge diode cathode are connected; and the metals that form the first charge diode cathode and the second charge diode cathode are ohmic metals.

[0088] Specifically, the regions where the metals included in the first metal layer and the interconnection metal between the metals are located on the surface of the current device are selected; the interconnection metal refers to the metal that connects the second capacitor anode plate and the second charge diode cathode. Then, the metals are evaporated in the selected regions using a metal evaporation process; by evaporating the metals, the metals that form the first charge diode cathode and the second charge diode cathode are also connected to the underlying ohmic metal, as shown in FIG. 5. Figure 14 .

[0089] Step seven, a third passivation layer is deposited on the surface of the current device, and the passivation layer is opened to expose the Schottky metal, the metals that form the first charge diode cathode and the second charge diode cathode, and the metal that forms the first capacitor cathode plate.

[0090] Specifically, the third passivation layer is deposited on the surface of the current device using an epitaxial growth process, as shown in FIG. 6. Figure 15Then, the third passivation layer is opened in the regions where the metal of the Schottky contact, the metal forming the cathode of the first charge diode, the metal forming the cathode of the second charge diode and the metal forming the cathode plate of the first capacitor are located, as shown in Fig. 3c. Figure 16 .

[0091] Step eight, a second metal layer, a first interlayer metal, a second interlayer metal and a third interlayer metal are prepared on the current device.

[0092] Here, the second metal layer (Metal layer 2) includes metals forming the first port, the second port, the third port, the fourth port, the anode of the first charge diode, the anode of the second charge diode, the anode plate of the first capacitor and the cathode plate of the second capacitor respectively.

[0093] In which, the first port, the cathode plate of the second capacitor and the anode of the first charge diode are connected, the anode plate of the first capacitor, the anode of the second charge diode and the fourth port are connected; the metals forming the anode of the first charge diode and the anode of the second charge diode are connected to the Schottky metal; the first interlayer metal connects the second port and the cathode plate of the first capacitor; the second interlayer metal connects the anode of the second charge diode and the cathode of the first charge diode; the third interlayer metal connects the third port and the cathode of the second charge diode; the three interlayer metals actually form metal vias.

[0094] Specifically, the regions where the metals in the second metal layer and the interlayer metals between the metals are located are selected on the surface of the current device; the interlayer metals include the metal connecting the first port, the cathode plate of the second capacitor and the anode of the first charge diode, and also include the metal connecting the anode plate of the first capacitor, the anode of the second charge diode and the fourth port. Then, the metals are evaporated in the selected regions by using the metal evaporation process; by evaporating the metals, not only the metals forming the anode of the first charge diode and the anode of the second charge diode are connected to the Schottky metal, but also the three metal vias are formed, as shown in Fig. 3c. Figure 17 .

[0095] Thus, the preparation of the monolithic integrated voltage doubler rectifier device is completed, and the structure of the prepared monolithic integrated voltage doubler rectifier device is shown in Figs. 4a and 4b. Figure 1 and Figure 2 .

[0096] It should be noted that the structure of the device prepared by the preparation method embodiment is basically similar to that of the device embodiment, so the description is relatively simple, and the related parts can be referred to the part of the device embodiment.

[0097] In conclusion, the embodiment of the present application first proposes a monolithic integrated voltage doubling rectifier unit based on the JTE SBD with Mg-doped P-BN, realizes the improvement of integration, greatly improves the withstand voltage level of the Schottky diode, greatly reduces the circuit volume, improves the circuit reliability, and widens the voltage application window of the integrated voltage doubling rectifier unit

[0098] The embodiment of the present application utilizes the high breakdown field strength of the BN material and the electric field adjusting capability of the JTE structure, greatly improves the withstand voltage level of the Schottky diode, and widens the voltage application window of the integrated voltage doubling rectifier unit. The prior art mainly uses the traditional Schottky diode, lacks effective junction termination technology to improve the working voltage of the device, and limits the working range of the existing device.

[0099] It should be noted that the terms "first", "second", and the like are used to distinguish similar objects, and do not necessarily have to be used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances, so that the embodiments of the disclosure described herein can be implemented in an order other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present disclosure. Rather, they are merely examples of devices and methods consistent with some aspects of the present disclosure.

[0100] In the description of the present specification, the description of the terms "one embodiment", "some embodiments", "an example", "a specific example", or "some examples" and the like means that the specific features or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In the present specification, the illustrative description of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine different embodiments or examples described in the present specification.

[0101] Although the present application is described herein in conjunction with various embodiments, other variations of the disclosed embodiments can be understood and implemented by those skilled in the art with reference to the drawings and the disclosure. In the description of the present application, the word "comprising" does not exclude other components or steps, "one" or "an" does not exclude a plurality, and "plurality" means two or more, unless otherwise explicitly specified. In addition, some measures are described in different embodiments, but this does not mean that these measures cannot be combined to produce good results.

[0102] In the description of the present application, it needs to be understood that the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise" and the like indicate the orientation or positional relationship shown in the drawings, which are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation of the present application.

[0103] In the present application, unless otherwise explicitly specified and limited, the terms "mounting", "connecting", "connecting", "fixing" and the like should be understood broadly, for example, it can be fixed connection, or detachable connection, or integral; it can be mechanical connection, or electrical connection; it can be direct connection, or indirect connection through intermediate medium; it can be the internal communication of two elements or the interaction relationship between two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0104] In the present application, unless otherwise explicitly specified and limited, the first feature "on" or "under" the second feature can include that the first and second features are in direct contact, or that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, the first feature "on", "above" and "over" the second feature includes that the first feature is directly above and obliquely above the second feature, or only indicates that the horizontal height of the first feature is higher than that of the second feature. The first feature "under", "below" and "under" the second feature includes that the first feature is directly below and obliquely below the second feature, or only indicates that the horizontal height of the first feature is less than that of the second feature.

[0105] The above is a further detailed description of the present application in combination with specific preferred embodiments, which cannot be considered as limiting the specific implementation of the present application to these descriptions. For those skilled in the art to which the present application belongs, without departing from the concept of the present application, a number of simple deductions or replacements can also be made, which should be considered as falling within the protection scope of the present application.

Claims

1. A monolithic integrated voltage doubler rectifier device based on a quasi-vertical JTE SBD, characterized in that: include: Two quasi-vertical JTE SBDs are located on a silicon substrate; the two quasi-vertical JTE SBDs respectively form a first charging diode and a second charging diode; Passivation layer; The passivation layer covers the two quasi-vertical JTE SBDs and the silicon substrate; a first metal layer located within the passivation layer; the first metal layer comprising metals forming a first capacitor cathode plate, a second capacitor anode plate, a first charging diode cathode, and a second charging diode cathode, respectively; wherein the second capacitor anode plate is connected to the second charging diode cathode; a second metal layer located on the upper surface of the passivation layer; the second metal layer includes metals forming a first port, a second port, a third port, a fourth port, a first charging diode anode, a second charging diode anode, a first capacitor anode plate, and a second capacitor cathode plate, respectively; wherein the first port, the second capacitor cathode plate, and the first charging diode anode are connected, and the first capacitor anode plate, the second charging diode anode, and the fourth port are connected; a first interlayer interconnection metal; the first interlayer interconnection metal connecting the second port and the first capacitor cathode plate; a second interlayer interconnection metal; wherein the second interlayer interconnection metal connects the anode of the second charging diode and the cathode of the first charging diode; A third inter-layer interconnection metal is provided; the third inter-layer interconnection metal is connected to the third port and the cathode of the second charging diode.

2. The monolithic integrated voltage doubler rectifier device based on quasi-vertical JTE SBD according to claim 1, characterized in that: The quasi-vertical JTE SBD includes: an epitaxial structure, a first JTE ring superimposed on the epitaxial structure, a second JTE ring superimposed on the first JTE ring, and a third JTE ring superimposed on the second JTE ring; The first JTE ring, the second JTE ring and the third JTE ring are stacked to form a stepped JTE ring structure; the epitaxial structure includes a GaN conductive layer and a GaN drift layer superimposed on the GaN conductive layer; the anode of the quasi-vertical JTE SBD is located at the center of the JTE ring structure; and the cathode of the quasi-vertical JTE SBD is located on the GaN drift layer.

3. The monolithic integrated voltage doubler rectifier device based on quasi-vertical JTE SBD according to claim 2, characterized in that: The first JTE ring, the second JTE ring, and the third JTE ring are all made of Mg-doped P-type BN.

4. The monolithic integrated voltage doubler rectifier device based on quasi-vertical JTE SBD according to claim 3, characterized in that: The doping concentration of the Mg-doped P-type BN is 1.0×10 16 cm -3 ~1.0×10 18 cm -3 .

5. The monolithic integrated voltage doubler rectifier device based on quasi-vertical JTE SBD according to claim 3, characterized in that: The widths of the first JTE ring, the second JTE ring, and the third JTE ring are 10 μm to 30 μm; wherein the widths of the first JTE ring, the second JTE ring, and the third JTE ring decrease in sequence.

6. The monolithic integrated voltage doubler rectifier device based on quasi-vertical JTE SBD according to claim 3, characterized in that: The Si doping concentration of the GaN drift layer is 1.0×10 16 cm -3 ~5.0×10 17 cm -3 .

7. The monolithic integrated voltage doubler rectifier device based on quasi-vertical JTE SBD according to claim 3, characterized in that: The Si doping concentration of the GaN conductive layer is 1.0×10 18 cm -3 ~1.0×10 19 cm -3 .

8. The monolithic integrated voltage doubler rectifier device based on quasi-vertical JTE SBD according to claim 1, characterized in that: The length of the first capacitor cathode plate, the second capacitor anode plate, the first capacitor anode plate and the second capacitor cathode plate is 10 μm to 100 μm, and the width is 10 μm to 100 μm.

9. A method for preparing a monolithic integrated voltage doubler rectifier device based on a quasi-vertical JTE SBD, characterized in that: include: Growing an epitaxial layer on a silicon substrate, and performing mesa etching and isolation etching on the epitaxial layer to form two epitaxial structures; preparing JTE ring structures on the upper surfaces of the two epitaxial structures respectively, so as to subsequently form two quasi-vertical JTE SBDs using the two JTE ring structures; the two quasi-vertical JTE SBDs respectively forming a first charging diode and a second charging diode; Depositing a first passivation layer on the surface of the current device, and opening holes in the passivation layer to expose the anode region and the cathode region; The anode region corresponds to the anode of the quasi-perpendicular JTE SBD, and the cathode region corresponds to the cathode of the quasi-perpendicular JTE SBD; Depositing a Schottky metal in the anode region and an ohmic metal in the cathode region to form two quasi-vertical JTE SBDs; Depositing a second passivation layer on the surface of the current device, and opening holes in the passivation layer to expose the Schottky metal and the ohmic metal; preparing a first metal layer on the current device; The first metal layer includes metals forming a first capacitor cathode plate, a second capacitor anode plate, a first charging diode cathode, and a second charging diode cathode, respectively; wherein the second capacitor anode plate and the second charging diode cathode are connected; and the metals forming the first charging diode cathode and the second charging diode cathode are connected to the ohmic metal; Depositing a third passivation layer on the surface of the current device, and opening holes in the passivation layer to expose the Schottky metal, the metal forming the cathode of the first charging diode and the cathode of the second charging diode, and the metal forming the cathode plate of the first capacitor; A second metal layer, a first interlayer interconnection metal, a second interlayer interconnection metal, and a third interlayer interconnection metal are prepared on the current device; the second metal layer includes metals for forming a first port, a second port, a third port, a fourth port, a first charging diode anode, a second charging diode anode, a first capacitor anode plate, and a second capacitor cathode plate, respectively; The first port, the second capacitor cathode plate and the first charging diode anode are connected, and the first capacitor anode plate, the second charging diode anode and the fourth port are connected; the metal forming the first charging diode anode and the second charging diode anode is connected to the Schottky metal; the first interlayer interconnection metal is connected to the second port and the first capacitor cathode plate; the second interlayer interconnection metal is connected to the second charging diode anode and the first charging diode cathode; and the third interlayer interconnection metal is connected to the third port and the second charging diode cathode.

10. The preparation method according to claim 9, characterized in that The JTE ring structure includes: a first JTE ring superimposed on the epitaxial structure, a second JTE ring superimposed on the first JTE ring, and a third JTE ring superimposed on the second JTE ring; the first JTE ring, the second JTE ring and the third JTE ring are superimposed to form a stepped JTE ring structure.

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