Display panel and display device

Abstract

The application discloses a display panel and a display device; the pixel driving circuit of the display panel comprises a switch transistor connected to a first node, a driving transistor, a first light-emitting transistor and a first reset transistor, the gate of the first light-emitting transistor is connected to a light-emitting control line, the conductive segment of the region where the first node is located is located in an active layer, the light-emitting control line is located in a first source-drain layer, and the conductive segment and the light-emitting control line have an overlapping part; by locating the conductive segment of the region where the first node is located in the active layer and locating the light-emitting control line in the first source-drain layer, the conductive segment is replaced from a metal layer to a conductorized semiconductor layer, the spacing between the light-emitting control line and the conductive segment is increased, the coupling capacitance between the light-emitting control line and the first node is reduced, the abnormality of the first node potential is improved, and the display effect of the display panel is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display panel and a display device. BACKGROUND

[0002] OLED (Organic Light-Emitting Diode) display technology is a new type of display technology, which gradually attracts people's attention with its unique advantages of low power consumption, high saturation, fast response time and wide viewing angle, and occupies a certain position in the field of panel display technology.

[0003] In the related art, the pixel driving circuit of the OLED display panel usually includes a switching transistor, a driving transistor and a light-emitting transistor, the switching transistor, the driving transistor and the light-emitting transistor are connected to a first node, the gate of the light-emitting control transistor is connected to a light-emitting control line, and because the light-emitting control line and the first node overlap, and the light-emitting control line is located in the first gate layer, the conductive segment in the region of the first node is located in the source-drain layer, so that there is a large coupling capacitance between the light-emitting control line and the first node, and the voltage of the first node is not reset to the reference voltage in the working stage, resulting in display abnormality of the display panel. SUMMARY

[0004] The present application provides a display panel and a display device to improve the technical problem of display abnormality of the existing display panel.

[0005] To solve the above-mentioned scheme, the technical scheme provided by the present application is as follows:

[0006] The present application provides a display panel, which includes a plurality of sub-pixel units, each of which is provided with a light-emitting device and a pixel driving circuit connected to the light-emitting device, the pixel driving circuit includes a switching transistor, a driving transistor, a first light-emitting transistor and a first reset transistor connected to a first node, and the gate of the first light-emitting transistor is connected to a light-emitting control line; wherein the display panel includes:

[0007] a substrate substrate;

[0008] an active layer provided on one side of the substrate substrate;

[0009] a first gate layer provided on the side of the active layer away from the substrate substrate;

[0010] a second gate layer provided on the side of the first gate layer away from the substrate substrate;

[0011] a first source-drain layer provided on the side of the second gate layer away from the substrate substrate;

[0012] The active layer includes a conductive segment in a region where the first node is located, and the first source-drain layer includes the light-emitting control line.

[0013] Optionally, the active layer includes a switching active part of the switching transistor, a first light-emitting active part of the first light-emitting transistor, a first reset active part of the first reset transistor, and an active connection segment, the active connection segment extends along a first direction, the switching active part, the first light-emitting active part, and the first reset active part all extend along a second direction, and the first light-emitting active part and the first reset active part are arranged at intervals along the first direction.

[0014] The switching active part and the first light-emitting active part are connected to a first connection point, one end of the active connection segment is connected to the first connection point, the other end of the active connection segment is connected to the first reset active part, and the light-emitting control line has a first overlapping part with the first reset active part.

[0015] Optionally, the first light-emitting active part includes a first light-emitting channel, and the light-emitting control line has a second overlapping part with the first light-emitting active part between the first light-emitting channel and the first connection point.

[0016] Optionally, the light-emitting control line includes a first sub-segment, a second sub-segment, and a third sub-segment connected in sequence, the first sub-segment and the third sub-segment extend along the first direction, and the second sub-segment is arranged at an angle with the first sub-segment and the third sub-segment.

[0017] The first light-emitting active part includes a first light-emitting channel, the first sub-segment has an overlapping part with the first light-emitting channel, and the third sub-segment has the first overlapping part with the first reset active part.

[0018] Optionally, the first gate layer includes a first light-emitting gate of the first light-emitting transistor.

[0019] The first end of the first light-emitting gate is arranged between the first light-emitting active part and the first reset active part, the first end of the first light-emitting gate is electrically connected to the light-emitting control line, the second end of the first light-emitting gate extends towards the first light-emitting active part, and overlaps with the first light-emitting active part.

[0020] Optionally, the pixel driving circuit further includes a second light-emitting transistor connected to the driving transistor at a second node, the second light-emitting transistor includes a second light-emitting active part in the active layer and a second light-emitting gate in the first gate layer.

[0021] The second light-emitting active part extends along the second direction and is arranged on a side of the first reset active part away from the first light-emitting active part, a first end of the second light-emitting gate electrode is arranged between the second light-emitting active part and the first reset active part, and the first end of the first light-emitting gate electrode is electrically connected with the light-emitting control line, a second end of the second light-emitting gate electrode extends towards the second light-emitting active part and overlaps the second light-emitting active part.

[0022] Optionally, the active part further comprises a driving active part of the driving transistor, a first end of the driving active part is connected to the switching active part, and a second end of the driving active part is connected to a second connection point.

[0023] Optionally, the pixel driving circuit further comprises a compensation transistor, a first electrode of the compensation transistor is connected to a second node, and a second electrode of the compensation transistor is connected to a gate electrode of the driving transistor.

[0024] The active part comprises a first compensation active part and a second compensation active part of the compensation transistor, one end of the first compensation active part and the second light-emitting active part are connected to a second connection point, and the other end of the first compensation active part and the second compensation active part are connected.

[0025] The first gate electrode layer comprises a first control line extending along a first direction and a first extension segment connected with the first control line, the first extension segment extends along the second direction, the first control line has an overlapping part with the switching active part and the first compensation active part, and the first extension segment has an overlapping part with the second compensation active part.

[0026] Optionally, the pixel driving circuit further comprises a second reset transistor, a third reset transistor and a storage capacitor.

[0027] The first electrode of the switching transistor is connected to a data signal line, the second electrode of the switching transistor is connected to the first node, and the gate electrode of the switching transistor is connected to a first control line.

[0028] The first electrode of the driving transistor is connected to the first node, the second electrode of the driving transistor is connected to the second node, and the gate electrode of the driving transistor is connected to a third node.

[0029] The first electrode of the compensation transistor is connected to the third node, the second electrode of the compensation transistor is connected to the second node, and the gate electrode of the compensation transistor is connected to the first control line.

[0030] A first electrode of the first reset transistor is connected to a first reset line, a second electrode of the first reset transistor is connected to the first node, and a gate of the first reset transistor is connected to a second control line;

[0031] A first electrode of the second reset transistor is connected to a second reset line, a second electrode of the second reset transistor is connected to the third node, and a gate of the second reset transistor is connected to a third control line;

[0032] A first electrode of the third reset transistor is connected to a third reset line, a second electrode of the third reset transistor is connected to an anode of the light emitting device, and a gate of the third reset transistor is connected to the second control line;

[0033] A first electrode of the first light emitting transistor is connected to a high potential line, and a second electrode of the first light emitting transistor is connected to the first node;

[0034] A first electrode of the second light emitting transistor is connected to the second node, a second electrode of the second light emitting transistor is connected to the anode of the light emitting device, and a gate of the second light emitting transistor is connected to the light emitting control line;

[0035] A first plate of the storage capacitor is connected to the high potential line, and a second plate of the storage capacitor is connected to the third node.

[0036] The application also provides a display device comprising the display panel.

[0037] Beneficial effects: The application replaces the conductive segment in the region where the first node is located with a conductive semiconductor layer, increases the distance between the light emitting control line and the conductive segment, reduces the coupling capacitance between the light emitting control line and the first node, improves the abnormality of the first node potential, and improves the display effect of the display panel. BRIEF DESCRIPTION OF DRAWINGS

[0038] The technical solutions and other beneficial effects of the application will become apparent through the following detailed description of specific embodiments of the application in conjunction with the accompanying drawings.

[0039] Figure 1 FIG. 1 is a structural diagram of a display panel according to the application;

[0040] Figure 2 FIG. 2 is an equivalent circuit diagram of a pixel driving circuit in the display panel according to the application;

[0041] Figure 3 FIG. 3 is a schematic diagram of a film layer in the display panel according to the application;

[0042] Figure 4 A film layer stack diagram of a sub-pixel unit in the display panel is shown in the present application;

[0043] Figure 5 A structure diagram of the light shielding layer in the present application is shown in the present application; Figure 4

[0044] Figure 6 A structure diagram of the first gate layer in the present application is shown in the present application; Figure 4

[0045] Figure 7 A structure diagram of the active layer in the present application is shown in the present application; Figure 4

[0046] Figure 8 A structure diagram of the second gate layer in the present application is shown in the present application; Figure 4

[0047] Figure 9 A first structure diagram of the first source-drain layer in the present application is shown in the present application; Figure 4

[0048] Figure 10 A second structure diagram of the first source-drain layer in the present application is shown in the present application; Figure 4

[0049] Figure 11 A structure diagram of the first source-drain layer in the present application is shown in the present application. Figure 4 DETAILED DESCRIPTION

[0050] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application. In addition, it should be understood that the specific embodiments described herein are only used to illustrate and explain the present application, and are not used to limit the present application. In the present application, the orientation words such as "upper" and "lower" generally refer to the upper and lower of the device in the actual use or working state, and specifically refer to the direction of the drawing surface in the drawings; and "inner" and "outer" refer to the outline of the device.

[0051] Referring to Figures 1 to 11 The present application provides a display panel 100, which can include a display part 200 and a gate drive circuit 300 located on one side of the display part 200, and the gate drive circuit 300 is used to input a control signal to the display part 200.

[0052] In the present embodiment, referring to Figure 1 ​​​​​​​The display part 200 includes a plurality of sub-pixel rows 210, each of the sub-pixel rows 210 includes a plurality of sub-pixel units 211, each of the sub-pixel units 211 is provided with a light emitting device 211b and a pixel driving circuit 211a connected with the light emitting device 211b, and the gate driving circuit 300 is used for inputting a gate control signal to a transistor in the pixel driving circuit 211a.

[0053] In the embodiment, the pixel driving circuit 211a includes a switch transistor T2 connected to the first node A, a driving transistor T1, a first light emitting transistor T5 and a first reset transistor T8, and a gate of the first light emitting transistor T5 is connected to an emitting control line EM.

[0054] In the embodiment, the display panel 100 includes a substrate 110, an active layer 123, a first gate layer 125, a second gate layer 127 and a first source-drain layer 129, the active layer 123 is arranged on one side of the substrate 110, the first gate layer 125 is arranged on a side of the active layer 123 away from the substrate 110, the second gate layer 127 is arranged on a side of the first gate layer 125 away from the substrate 110, the first source-drain layer 129 is arranged on a side of the second gate layer 127 away from the substrate 110, the active layer 123 includes a conductive segment in a region of the first node A, the first source-drain layer 129 includes the emitting control line EM, and the conductive segment and the emitting control line EM have an overlapping part.

[0055] The application places the conductive segment in the region of the first node A in the active layer 123 and places the emitting control line EM in the first source-drain layer 129, replaces the conductive segment from a metal layer to a conductorized semiconductor layer, increases the spacing between the emitting control line EM and the conductive segment, reduces the coupling capacitance between the emitting control line EM and the first node A, improves the abnormality of the first node A potential, and improves the display effect of the display panel 100.

[0056] It should be noted that the light emitting device 211b of the application can be an organic light emitting diode, a Mini LED, a Micro LED, a regular size LED or other light emitting source.

[0057] The technical solutions of the application will be described in combination with specific embodiments.

[0058] Please refer to Figure 1The display panel 100 includes a display area AA and a non-display area NA disposed adjacent to the display area AA, and the display area AA is provided with a display part 200. Optionally, the non-display area NA surrounds the display area AA, so that the display area AA is surrounded by the non-display area NA. The display area AA is an area in the display panel 100 for playing a display function, and is internally provided with a plurality of sub-pixel units 211 for realizing the display function. The non-display area NA can be a frame area of the display panel 100, and can be internally provided with a functional component for assisting the sub-pixel units 211 in the display area AA in display.

[0059] Referring to Figure 1 The lower side of the display area AA is provided with a binding terminal 400, which can be connected with an external circuit. The binding terminal 400 transmits a signal input by the external circuit to a data wire, so as to drive the display panel 100 to display a picture. For example, the binding terminal 400 can be connected with a chip or a chip on film, and is used to provide a power supply and a driving signal for the display panel 100.

[0060] In the embodiment, the gate drive circuit 300 is disposed in the non-display area NA, and the gate drive circuit 300 can be disposed on both sides of the display area AA. The gate drive circuit 300 can include a plurality of gate drive units connected in cascade, and the structure of the gate drive unit is not specifically limited in the present application.

[0061] In the embodiment, a plurality of light emitting devices 211b and pixel drive circuits 211a for driving the light emitting devices 211b can be arrayed in the display area AA. The pixel drive circuit 211a can be a 7T1C, 7T2C, 8T1C, 8T2C, 8T3C, 8T4C, or the like, and the following embodiment will be described by taking an 8T1C pixel drive circuit 211a as an example.

[0062] Referring to Figure 2 The pixel drive circuit 211a can include a switching transistor T2, a driving transistor T1, a compensation transistor T3, a second reset transistor T4, a third reset transistor T7, a first reset transistor T8, a first light emitting transistor T5, a second light emitting transistor T6, and a storage capacitor Cst including a first plate Cst1 and a second plate Cst1.

[0063] Referring to Figure 2The first electrode of the switch transistor T2 is connected to the data signal line Data, the second electrode of the switch transistor T2 is connected to the first node A, and the switch gate T2G of the switch transistor T2 is connected to the first control line Scan1; the first electrode of the drive transistor T1 is connected to the first node A, the second electrode of the drive transistor T1 is connected to the second node B, and the drive gate T1G of the drive transistor T1 is connected to the third node Q; the first electrode of the compensation transistor T3 is connected to the third node Q, the second electrode of the compensation transistor T3 is connected to the second node B, and the compensation gate T3G of the compensation transistor T3 is connected to the first control line Scan1; the first electrode of the second reset transistor T4 is connected to the second reset line Vib, the second electrode of the second reset transistor T4 is connected to the third node Q, and the gate T4G of the second reset transistor T4 is connected to the third control line Scan3; the first electrode of the third reset transistor T7 is connected to the third reset line Vic, the second electrode of the third reset transistor T7 is connected to the anode of the light emitting device 211b, and the gate T7G of the third reset transistor T7 is connected to the second control line Scan2; the first electrode of the first reset transistor T8 is connected to the first reset line Via, the second electrode of the first reset transistor T8 is connected to the first node A, and the gate T8G of the first reset transistor T8 is connected to the second control line Scan2; the first electrode of the first light emitting transistor T5 is connected to the high potential line VDD, the second electrode of the first light emitting transistor T5 is connected to the first node A, and the first light emitting gate T5G of the first light emitting transistor T5 is connected to the light emitting control line EM; the first electrode of the second light emitting transistor T6 is connected to the second node B, the second electrode of the second light emitting transistor T6 is connected to the anode of the light emitting device 211b, and the second light emitting gate T6G of the second light emitting transistor T6 is connected to the light emitting control line EM; the first plate Cst1 of the storage capacitor Cst is connected to the third node Q, and the second plate Cst1 of the storage capacitor Cst is connected to the high potential line VDD; and the cathode of the light emitting device 211b is connected to the low potential line VSS.

[0064] It should be noted that the data signal line connected to the switch transistor T2 in different sub-pixel units 211 is different, and only one of them is taken as an example for description.

[0065] In this embodiment, the high potential line VDD is used to provide a constant voltage high level to the pixel driving circuit 211a, and the low potential line VSS is used to provide a constant voltage low level to the pixel driving circuit 211a.

[0066] In the embodiment, the switch transistor T2, the drive transistor T1, the third reset transistor T7, the first reset transistor T8, the first light emitting transistor T5, the second light emitting transistor T6, the compensation transistor T3, and the second reset transistor T4 can be one of a P-type transistor or an N-type transistor; the application is described by taking the switch transistor T2, the drive transistor T1, the third reset transistor T7, the first reset transistor T8, the first light emitting transistor T5, the second light emitting transistor T6, the compensation transistor T3, and the second reset transistor T4 as P-type transistors as an example.

[0067] In the embodiment, the first electrode can be one of a source electrode or a drain electrode, and the second electrode can be the other of the source electrode or the drain electrode.

[0068] In the following embodiment, the angle between the first direction X and the second direction Y is greater than 0 and less than or equal to 90°, for example, the first direction X is a horizontal direction, and the second direction Y is a vertical direction.

[0069] The film layer structure of the pixel driving circuit 211a of the application is described below with respect to the structure of Figure 2

[0070] Please refer to Figure 3 The display area AA and the non-display area NA of the display panel 100 can be provided with a substrate 110 and an array driving layer 120 disposed on the substrate 110; in the display area AA, the display panel 100 can further be provided with a pixel definition layer (not shown) disposed on the array driving layer 120, a light emitting device layer (not shown) disposed in the same layer as the pixel definition layer, and an encapsulation layer (not shown) disposed on the pixel definition layer. The film layer structure in the display area AA is mainly described below.

[0071] In the embodiment, the substrate 110 supports each layer disposed on the substrate 110. When the display panel 100 is a bottom emission light emitting display device or a double-sided emission light emitting display device, a transparent substrate is used. When the display panel 100 is a top emission light emitting display device, a semi-transparent or opaque substrate and a transparent substrate can be used.

[0072] In the embodiment, the substrate 110 is used to support each film layer disposed on the substrate 110, and the substrate 110 can be made of an insulating material such as glass, quartz, or a polymer resin. The substrate 110 can be a rigid substrate or a flexible substrate that can be bent, folded, curled, etc. Examples of flexible materials for flexible substrates include polyimide (PI), but are not limited to polyimide (PI).

[0073] ​In the embodiment, the substrate 110 can include a first flexible substrate 111, a first barrier layer 112, a second flexible substrate 113, and a second barrier layer 114 which are stacked, the first flexible substrate 111 and the second flexible substrate 113 can be formed of the same material such as polyimide, and the first barrier layer 112 and the second barrier layer 114 can be formed of an inorganic material including at least one of SiOx and SiNx, for example.

[0074] Referring to Figure 3 , the array driving layer 120 can include a plurality of thin film transistors, the thin film transistors can be etch barrier type, back channel etch type, or divided into bottom gate thin film transistors, top gate thin film transistors and the like according to the position of the gate and the active layer, or divided into N-type thin film transistors, P-type thin film transistors according to the performance of the thin film transistors; wherein, Figure 3 The thin film transistors in Figure 2 are not structural diagrams of any transistor in , but are schematic diagrams of each film layer of the display panel 100 of the present application.

[0075] Figure 3 Referring to , the array driving layer 120 can include a light shielding layer 121 disposed on the substrate 110, a buffer layer 122 disposed on the light shielding layer 121, an active layer 123 disposed on the buffer layer 122, a first gate insulating layer 124 disposed on the active layer 123, a first gate layer 125 disposed on the first gate insulating layer 124, a second gate insulating layer 126 disposed on the first gate layer 125, a second gate layer 127 disposed on the second gate insulating layer 126, an interlayer insulating layer 128 disposed on the second gate layer 127, a first source-drain layer 129 disposed on the interlayer insulating layer 128, a first planar layer 130 disposed on the first source-drain layer 129, a second source-drain layer 131 disposed on the first planar layer 130, and a second planar layer 132 disposed on the second source-drain layer 131.

[0076] Figure 3 Referring to , the light shielding layer 121 is disposed on the second barrier layer 114, the light shielding layer 121 is used to shield external light from entering the thin film transistor from the bottom, and the material of the light shielding layer 121 can be composed of black light shielding material, such as black light shielding metal or black organic material, etc.

[0077] Figure 3 Referring to , the buffer layer 122 is disposed on the light shielding layer 121, the buffer layer 122 is used to isolate the light shielding layer 121 and the upper metal material, and the material of the buffer layer 122 can include a compound composed of nitrogen element, silicon element and oxygen element, such as a single layer of silicon oxide film layer or a stacked structure of silicon oxide-silicon nitride.

[0078] In the embodiment, the light shielding layer 121 can also be embedded in the buffer layer 122.

[0079] Referring to Figure 3 The material of the active layer 123 can be amorphous silicon or low-temperature polysilicon. For example, the material of the active layer 123 can be low-temperature polysilicon.

[0080] Referring to Figure 3 The first gate insulating layer 124, the second gate insulating layer 126, and the interlayer insulating layer 128 are respectively arranged on the corresponding metal layer or semiconductor layer, and are arranged separately from the different layers of metal layer or semiconductor layer. The material of the first gate insulating layer 124, the second gate insulating layer 126, and the interlayer insulating layer 128 can be inorganic material combined with silicon and oxygen or organic material with flatness.

[0081] Referring to Figure 3 The first gate layer 125 and the second gate layer 127 are respectively arranged on the corresponding insulating layer. The material of the first gate layer 125 and the second gate layer 127 can be copper, molybdenum, or molybdenum-titanium alloy, etc.

[0082] Referring to Figure 3 The material of the first source-drain layer 129 and the second source-drain layer 131 can be copper, molybdenum, molybdenum-titanium alloy, or titanium-aluminum-titanium three-layer metal, etc.

[0083] Referring to Figure 3 The first flat layer 130 and the second flat layer 132 are integrally laid to ensure the flatness of the film layer of the array driving layer 120. The material of the first flat layer 130 and the second flat layer 132 can be inorganic material combined with silicon and oxygen or organic material with flatness.

[0084] It should be noted that Figure 4 The structure is only one cross-sectional view of the present application. If the wiring of the display panel 100 is relatively compact, the display panel 100 of the present application can further include a third source-drain layer arranged on the second flat layer 132, which is not specifically limited here.

[0085] Referring to Figure 5 and Figure 4 , Figure 5 is a film layer stacking diagram of a sub-pixel unit 211 in the display panel 100 of the present application, Figure 4 is Figure 5 a structure diagram of the light shielding layer 121 in the display panel 100 of the present application.

[0086] Referring to Figure 4The light shielding layer 121 includes a light shielding body 121a and a first light shielding segment 121b, a second light shielding segment 121c, a third light shielding segment 121d, a fourth light shielding segment 121e, and a fifth light shielding segment 121f connected with the light shielding body 121a. The light shielding body 121a is located in the central region of the sub-pixel unit 211. The first light shielding segment 121b is arranged at a first top corner of the light shielding body 121a. The second light shielding segment 121c is arranged at a second top corner of the light shielding body 121a. The third light shielding segment 121d and the fourth light shielding segment 121e extend along the second direction Y. One end of the third light shielding segment 121d away from the light shielding body 121a is connected with the second light shielding segment 121c. One end of the fourth light shielding segment 121e away from the light shielding body 121a is connected with the second light shielding segment 121c. The fifth light shielding segment 121f is arranged at both sides of the light shielding body 121a along the first direction X. The light shielding layers 121 in adjacent two sub-pixel units 211 along the first direction X are connected with each other through the fifth light shielding segment 121f. The light shielding layers 121 in adjacent two sub-pixel units 211 along the second direction Y are connected through the third light shielding segment 121d of one sub-pixel unit 211 and the fourth light shielding segment 121e of another sub-pixel unit 211.

[0087] In this embodiment, the orthographic projection of the channel of the switching active part T2A of the switching transistor T2 on the light shielding layer 121 is located in the first light shielding segment 121b. The orthographic projection of the channel of the compensation active part of the compensation transistor T3 on the light shielding layer 121 is located in the second light shielding segment 121c. The orthographic projection of the channel of the driving active part T1A of the driving transistor T1 on the light shielding layer 121 is located in the light shielding body 121a.

[0088] Please refer to Figure 6 and Figure 6 , Figure 4 is Figure 4 the structural diagram of the first gate layer 125. The first gate layer 125 includes a first third control line Scan3, a first first control line Scan1, and a first second control line Scan2 extending along the first direction X. The third control line Scan3, the first control line Scan1, and the second control line Scan2 are arranged at intervals along the second direction Y. The first gate layer 125 further includes a first extension segment 125a and a second extension segment 125b connected with the first control line Scan1. The first extension segment 125a and the second extension segment 125b both extend along the second direction Y. The length of the first extension segment 125a along the second direction Y is smaller than the length of the second extension segment 125b along the second direction Y.

[0089] In the embodiment, the first gate layer 125 further comprises a first plate Cst1 arranged between the first control line Scan1 and the second control line Scan2, a first light-emitting gate T5G of the first light-emitting transistor T5 and a second light-emitting gate T6G of the second light-emitting transistor T6, the first light-emitting gate T5G and the second light-emitting gate T6G are arranged in a spaced manner and close to the second control line Scan2, and the first plate Cst1 is arranged close to the first control line Scan1.

[0090] Please refer to Figure 7 and Figure 7 , Figure 4 for Figure 4 the structure diagram of the active layer 123 in FIG. 1. The active layer 123 comprises a switching active part T2A of the switching transistor T2, a first light-emitting active part T5A of the first light-emitting transistor T5, a first reset active part T8A of the first reset transistor T8, a driving active part T1A of the driving transistor T1, a second light-emitting active part T6A of the second light-emitting transistor T6, a second reset active part T4A of the second reset transistor T4, a third reset active part T7A of the third reset transistor T7, a first compensation active part T3Aa and a second compensation active part T3Ab of the compensation transistor T3, and an active connection segment 123a.

[0091] The active connection segment 123a and the second compensation active part T3Ab extend along a first direction X, the first compensation active part T3Aa, the switching active part T2A, the first light-emitting active part T5A, the second light-emitting active part T6A, the first reset active part T8A, and the third reset active part T7A extend along a second direction Y, and the first light-emitting active part T5A, the first reset active part T8A, and the second light-emitting active part T6A are arranged in a spaced manner along the first direction X.

[0092] The switching active part T2A and the first light-emitting active part T5A are connected to a first connection point M1, one end of the active connection segment 123a is connected to the first connection point M1, the other end of the active connection segment 123a is connected to the first reset active part T8A, one end of the first compensation active part T3Aa and the second light-emitting active part T6A are connected to a second connection point M2, the other end of the first compensation active part T3Aa is connected to the second compensation active part T3Ab, a first end of the driving active part T1A is connected to the switching active part T2A, a second end of the driving active part T1A is connected to the second connection point M2, the second reset active part T4A and the second compensation active part T3Ab are connected to a third connection point M3, the third reset active part T7A and the second light-emitting active part T6A are connected to the second light-emitting active part T6A, and the other end of the second light-emitting active part T6A is connected to a fourth connection point M4.

[0093] In the embodiment, the driving active part T1A and the second reset active part T4A can be in U shape.

[0094] In the embodiment, the first control line Scan1 and the switching active part T2A overlap, the first control line Scan1 at the overlapping position is the switching gate T2G of the switching transistor T2, and the switching active part T2A at the overlapping position is the switching channel of the switching transistor T2; the first control line Scan1 and the first compensation active part T3Aa overlap, the first control line Scan1 at the overlapping position is the first compensation gate T3Ga of the compensation transistor T3, and the first compensation active part T3Aa at the overlapping position is the first compensation channel of the compensation transistor T3; the first extension segment 125a and the second compensation active part T3Ab overlap, the first extension segment 125a at the overlapping position is the second compensation gate T3Gb of the compensation transistor T3, and the second compensation active part T3Ab at the overlapping position is the second compensation channel of the compensation transistor T3.

[0095] In the embodiment, the third control line Scan3 and the second reset active part T4A overlap, the third control line Scan3 at the overlapping position is the second reset gate T4G of the second reset transistor T4, and the second reset active part T4A at the overlapping position is the second reset channel of the second reset transistor T4; the second control line Scan2 and the third reset active part T7A overlap, the second control line Scan2 at the overlapping position is the third reset gate T7G of the third reset transistor T7, and the third reset active part T7A at the overlapping position is the third reset channel of the third reset transistor T7.

[0096] In the embodiment, the first end of the first light-emitting gate T5G is arranged between the first light-emitting active part T5A and the first reset active part T8A, and the first end of the first light-emitting gate T5G is electrically connected with the light-emitting control line EM, the second end of the first light-emitting gate T5G extends towards the first light-emitting active part T5A and overlaps with the first light-emitting active part T5A.

[0097] In the embodiment, the first end of the second light-emitting gate T6G is arranged between the second light-emitting active part T6A and the first reset active part T8A, and the first end of the first light-emitting gate T5G is electrically connected with the light-emitting control line EM, the second end of the second light-emitting gate T6G extends towards the second light-emitting active part T6A and overlaps with the second light-emitting active part T6A.

[0098] Please refer to Figure 8 and Figure 8 , Figure 4 for Figure 4Figure 1 shows a structural diagram of the second gate layer 127. The second gate layer 127 includes a second plate Cst2 of a storage capacitor and a first connecting electrode 127a. The second plate Cst2 is disposed opposite the first plate Cst1, and the area of ​​the second plate Cst2 is larger than that of the first plate Cst1. The first connecting electrode 127a corresponds to the connection point between the first compensation active portion T3Aa and the second compensation active portion T3Ab. Furthermore, the second gate layer 127 also includes electrical connection segments 127b disposed on both sides of the second plate Cst2. The second plates Cst2 in two adjacent sub-pixel units 211 are electrically connected via the electrical connection segments 127b.

[0099] In this embodiment, the second electrode plate Cst2 is provided with a through hole HL, and the upper layer of the wire transmitting the high potential signal passes through the through hole and is connected to the first electrode plate Cst1.

[0100] See also Figure 9 、 Figure 10 and Figure 9 , Figure 4 for Figure 10 The first structural diagram of the first source and drain layer 129, Figure 4 for Figure 9 FIG. 1 is a second structural diagram of the first source / drain layer 129.

[0101] The first source-drain layer 129 includes a second third control line Scan3, a second reset line Vi2, a second first control line Scan1, a lateral high potential line Vdd1, a light-emitting control line EM, a second second control line Scan2, a third reset line Vi3, and a first reset line Vi1, which are arranged at intervals along the second direction Y. The second third control line Scan3, the second reset line Vi2, the second first control line Scan1, the second second control line Scan2, the third reset line Vi3, and the first reset line Vi1 all extend along the first direction X.

[0102] In this embodiment, the second third control line Scan3 and the first third control line Scan3 partially overlap, and the second third control line Scan3 and the first third control line Scan3 are electrically connected through a via; the second second control line Scan2 and the first second control line Scan2 partially overlap, and the second second control line Scan2 and the first second control line Scan2 are electrically connected through a via; the first first control line Scan1 and the second first control line Scan1 are arranged at intervals, and the second first control line Scan1 is arranged between the first first control line Scan1 and the second reset line Vi2, one end of the second extension segment 125b is connected to the first first control line Scan1, and the other end of the second extension segment 125b passes through the via and is electrically connected to the second first control line Scan1.

[0103] In the embodiment, the first source-drain layer 129 further comprises a second connection electrode 129a, a third connection electrode 129b and a fourth connection electrode 129c, the second connection electrode 129a and the third connection electrode 129b are arranged between the lateral high potential line Vdd1 and the second first control line Scan1, the third connection electrode 129b is arranged between the second connection electrode 129a and the fourth connection electrode 129c, one end of the second connection electrode 129a is connected away from the first connection point M1 through a via and a switch active part T2A, the other end of the second connection electrode 129a is connected through a via and a data signal line Data; the third connection electrode 129b extends along the second direction Y, one end of the third connection electrode 129b is connected through a via and a first plate Cst1, the other end of the third connection electrode 129b is connected through a via and a longitudinal high potential line Vdd2 of the second source-drain layer 131; one end of the fourth connection electrode 129c is connected with the lateral high potential line Vdd1, the other end of the fourth connection electrode 129c is connected with the first connection electrode 127a of the second gate layer 127.

[0104] In the embodiment, the lateral high potential line Vdd1 is V-shaped and recessed towards the second second control line Scan2 to avoid the third connection electrode 129b away from one end of the second first control line Scan1, the bottom of the recessed segment of the lateral high potential line Vdd1 is connected with the longitudinal high potential line Vdd2 of the second source-drain layer 131 through a via.

[0105] Please refer to Figure 10 and Figure 9 , the light-emitting control line EM has a first overlapping part N1 with the first reset active part T8A; meanwhile in Figure 9 , the light-emitting control line EM has a second overlapping part N2 with the first light-emitting active part T5A between the first light-emitting channel and the first connection point M1.

[0106] In Figure 10In the specific embodiment, the light-emitting control line EM is a horizontal segment extending along the first direction X, and the light-emitting control line EM overlaps the first light-emitting active part T5A and the first reset active part T8A. Since the first light-emitting channel of the first light-emitting active part T5A and the first reset channel of the first reset active part T8A are located on the side of the overlapping area away from the active connection segment 123a, the active layer 123 of the first overlapping part N1 and the second overlapping part N2 is a conductive segment in the region of the first node A. Since the coupling capacitor between the first overlapping part N1 and the second overlapping part N2 is formed by the electrode plate formed by the conductive semiconductor material and the electrode plate formed by the first source-drain layer 129, the two electrode plates are separated by the first gate insulating layer 124, the first gate layer 125, the second gate insulating layer 126, the second gate layer 127, and the insulating layer 128. The coupling capacitor in the prior art is formed by the first gate layer 125 and the first source-drain layer 129. The technical solution of the present application increases the distance between the two electrode plates in the overlapping part, and the metal electrode plate is replaced by the conductive semiconductor material, which also reduces the coupling capacitor.

[0107] In Figure 9 , the light-emitting control line EM includes a first sub-segment EM1, a second sub-segment EM2 and a third sub-segment EM3 connected in series, the first sub-segment EM1 and the third sub-segment EM3 extend along the first direction X, and the second sub-segment EM2 is arranged at an angle with respect to the first sub-segment EM1 and the third sub-segment EM3; that is, the first sub-segment EM1 has an overlapping part with the first light-emitting channel, and the third sub-segment EM3 has the first overlapping part N1 with the first reset active part T8A.

[0108] In Figure 10 , on the basis of the above, Figure 4 , the light-emitting control line EM is lowered to avoid overlapping of the light-emitting control line EM and the conductive segment of the first node A in the first light-emitting active part T5A, further reducing the coupling capacitor between the light-emitting control line EM and the conductive segment in the region of the first node A, improving the abnormality of the potential of the first node A, and improving the display effect of the display panel 100.

[0109] Please refer to Figure 11 and Figure 11 , Figure 4 , the light-emitting control line EM is lowered to avoid overlapping of the light-emitting control line EM and the conductive segment of the first node A in the first light-emitting active part T5A, further reducing the coupling capacitor between the light-emitting control line EM and the conductive segment in the region of the first node A, improving the abnormality of the potential of the first node A, and improving the display effect of the display panel 100. ​A structural diagram of a second source-drain layer 131 is shown. The second source-drain layer 131 includes a data signal line Data, a longitudinal high potential line Vdd2 and a fifth connection electrode 131a arranged at intervals along a first direction X, and the data signal line Data, the longitudinal high potential line Vdd2 and the fifth connection electrode 131a all extend along a second direction Y, the data signal line Data is connected through a via hole and a second connection electrode 129a, and the longitudinal high potential line Vdd2 is connected through a via hole and a transverse high potential line Vdd1.

[0110] In the embodiment, one end of the fifth connection electrode 131a is connected with the fourth connection point M4 through a via hole, and the other end of the fifth connection electrode 131a is connected with the anode of the light emitting device 211b. It should be noted that the lengths of the fifth connection electrodes 131a of different color sub-pixel units 211 are different due to the difference in the positions of the anodes of the different color sub-pixel units 211.

[0111] The application further provides a display device, and the display device comprises the display panel.

[0112] The application discloses a display panel and a display device; the pixel driving circuit of the display panel comprises a switching transistor connected to a first node, a driving transistor, a first light emitting transistor and a first reset transistor, a gate of the first light emitting transistor is connected to a light emitting control line, a conductive segment of a region where the first node is located is located in an active layer, the light emitting control line is located in a first source-drain layer, and the conductive segment and the light emitting control line have an overlapping part; the application replaces the metal layer of the conductive segment with the semiconductor layer, increases the distance between the light emitting control line and the conductive segment, reduces the coupling capacitance between the light emitting control line and the first node, improves the abnormality of the first node potential, and improves the display effect of the display panel.

[0113] In the above embodiments, the description of each embodiment has its own focus, and the parts not described in detail in a certain embodiment can be referred to the relevant description of other embodiments.

[0114] The above has carried out the detailed introduction to the display panel and the display device provided by the embodiment of the application, the principle and the implementation mode of the application are described in the text by applying specific examples, the above embodiment is only used for helping understanding the technical scheme of the application and its core idea; the ordinary skilled in the art should understand that: it can still modify the technical scheme recorded by the foregoing each embodiment, or equivalent replacement is carried out to part of the technical features; and these modifications or replacements do not make the essence of the corresponding technical scheme deviate from the scope of the technical scheme of the embodiments of the application.

Claims

1. A display panel, characterized in that: The display panel includes a plurality of sub-pixel units, each of which is provided with a light-emitting device and a pixel driving circuit connected to the light-emitting device, wherein the pixel driving circuit includes a switching transistor connected to a first node, a driving transistor, a first light-emitting transistor, and a first reset transistor, wherein the gate of the first light-emitting transistor is connected to a light-emitting control line; wherein the display panel includes: substrate; An active layer is provided on one side of the base substrate; A first gate layer is provided on a side of the active layer away from the base substrate; a second gate layer, disposed on a side of the first gate layer away from the base substrate; a first source-drain electrode layer, disposed on a side of the second gate layer away from the base substrate; The active layer includes a conductive segment in the area where the first node is located, the first source and drain layer includes the light emitting control line, and the conductive segment and the light emitting control line have an overlapping portion; The active layer includes a switch active portion of the switch transistor, a first light-emitting active portion of the first light-emitting transistor, a first reset active portion of the first reset transistor, and an active connecting section. The switch active portion and the first light-emitting active portion are connected to a first connecting point. One end of the active connecting section is connected to the first connecting point, and the other end of the active connecting section is connected to the first reset active portion. The light-emitting control line and the first reset active portion have a first overlapping portion.

2. The display panel according to claim 1, wherein: The active connection section extends along a first direction, the switch active portion, the first light emitting active portion, and the first reset active portion all extend along a second direction, and the first light emitting active portion and the first reset active portion are spaced apart along the first direction.

3. The display panel according to claim 2, wherein: The first light emitting active portion includes a first light emitting channel, and the light emitting control line has a second overlapping portion with the first light emitting active portion between the first light emitting channel and the first connection point.

4. The display panel according to claim 2, wherein: The light-emitting control line includes a first sub-segment, a second sub-segment, and a third sub-segment connected to each other, the first sub-segment and the third sub-segment extending along the first direction, and the second sub-segment being arranged at an angle to the first sub-segment and the third sub-segment; The first light emitting active portion includes a first light emitting channel, the first sub-segment and the first light emitting channel have an overlapping portion, and the third sub-segment and the first reset active portion have the first overlapping portion.

5. The display panel according to claim 2, wherein: The first gate layer includes a first light emitting gate of the first light emitting transistor; The first end of the first light-emitting gate is arranged between the first light-emitting active portion and the first reset active portion, and the first end of the first light-emitting gate is electrically connected to the light-emitting control line, and the second end of the first light-emitting gate extends toward the first light-emitting active portion and overlaps with the first light-emitting active portion.

6. The display panel according to claim 5, wherein: The pixel driving circuit further includes a second light emitting transistor connected to the driving transistor at a second node, the second light emitting transistor including a second light emitting active portion located in the active layer and a second light emitting gate located in the first gate layer; The second light-emitting active portion extends along the second direction and is arranged on a side of the first reset active portion away from the first light-emitting active portion. The first end of the second light-emitting gate is arranged between the second light-emitting active portion and the first reset active portion, and the first end of the first light-emitting gate is electrically connected to the light-emitting control line. The second end of the second light-emitting gate extends toward the second light-emitting active portion and overlaps with the second light-emitting active portion.

7. The display panel according to claim 6, wherein: The pixel driving circuit further includes a compensation transistor, wherein a first electrode of the compensation transistor is connected to the second node, and a second electrode of the compensation transistor is connected to the gate of the driving transistor; The active portion includes a first compensation active portion and a second compensation active portion of the compensation transistor, one end of the first compensation active portion and the second light emitting active portion are connected to a second connection point, and the other end of the first compensation active portion is connected to the second compensation active portion; The first gate layer includes a first control line extending along a first direction and a first extension segment connected to the first control line, the first extension segment extends along the second direction, the first control line has an overlapping portion with the switch active portion and the first compensation active portion, and the first extension segment has an overlapping portion with the second compensation active portion.

8. The display panel according to claim 7, wherein: The pixel driving circuit further includes a second light emitting transistor, a second reset transistor, a third reset transistor and a storage capacitor; The first electrode of the switch transistor is connected to the data signal line, the second electrode of the switch transistor is connected to the first node, and the gate of the switch transistor is connected to the first control line; The first electrode of the driving transistor is connected to the first node, the second electrode of the driving transistor is connected to the second node, and the gate of the driving transistor is connected to a third node; The first electrode of the compensation transistor is connected to the third node, the second electrode of the compensation transistor is connected to the second node, and the gate of the compensation transistor is connected to the first control line; A first electrode of the first reset transistor is connected to a first reset line, a second electrode of the first reset transistor is connected to the first node, and a gate of the first reset transistor is connected to a second control line; A first electrode of the second reset transistor is connected to a second reset line, a second electrode of the second reset transistor is connected to the third node, and a gate of the second reset transistor is connected to a third control line; A first electrode of the third reset transistor is connected to a third reset line, a second electrode of the third reset transistor is connected to an anode of the light emitting device, and a gate of the third reset transistor is connected to the second control line; A first electrode of the first light emitting transistor is connected to a high potential line, and a second electrode of the first light emitting transistor is connected to the first node; The first electrode of the second light emitting transistor is connected to the second node, the second electrode of the second light emitting transistor is connected to the anode of the light emitting device, and the gate of the second light emitting transistor is connected to the light emitting control line; The first plate of the storage capacitor is connected to the high potential line, and the second plate of the storage capacitor is connected to the third node.

9. The display panel according to claim 5, wherein: The active portion further includes a driving active portion of the driving transistor, a first end of the driving active portion is connected to the switch active portion, and a second end of the driving active portion is connected to a second connection point.

10. A display device, characterized in that: The display device includes the display panel according to any one of claims 1 to 9.

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