ELECTRONIC PACKAGE INCLUDING IC DIES ARRANGED IN REVERSE RELATIVE Orientations

Abstract

An electronic package includes: a first integrated circuit (IC) die, the first integrated circuit (IC) die being arranged in a first orientation; a second IC die arranged in a second orientation opposite to the first orientation; at least one upper conductive wiring layer, the at least one upper conductive wiring layer extending over the first IC die and the second IC die; at least one lower conductive wiring layer, the at least one lower conductive wiring layer extending under the first IC die and the second IC die; and a molding compound at least partially encapsulating the first IC die and the second IC die.

Description

[0001] Related patent applications

[0002] This application claims priority to commonly owned U.S. Provisional Patent Application No. 63 / 422,068, filed on November 3, 2022, the entire contents of which are hereby incorporated by reference for all purposes. Technical Field

[0003] The present disclosure relates to electronic packages, and more particularly to electronic packages including IC dies arranged in inverted relative orientations. Background Art

[0004] The semiconductor industry continues to develop advanced packaging technologies, such as to reduce costs by improving yields, materials, and production processes. For example, semiconductor manufacturers are developing various panel-level packaging (PLP) technologies for high-volume manufacturing on large panels (compared to wafer-level manufacturing), typically with wafer-level precision. PLP is commonly used to package field programmable gate arrays (FPGAs), CPU / GPU devices, power modules (e.g., silicon carbide (SiC)-based power modules), baseband devices, and other electronic devices. One type of PLP is a panel-level fan-out package that applies the concept of "fan-out" die connections from die packaging conventionally used in wafer-level processing to panel-level manufacturing.

[0005] The PLP manufacturing process includes: a "mold first" process, in which a mold package is formed over the IC die before forming at least one metal redistribution layer (RDL) to electrically contact the IC die; and an "RDL first" process, in which at least one RDL is formed before the IC die is mounted and the mold package is formed.

[0006] There is a need for improved semiconductor packages and packaging processes, for example, with small package size, low manufacturing cost, and / or improved performance of packaged electronic components. Summary of the invention

[0007] An electronic package may include: (a) at least one IC die facing upward (e.g., a MOSFET die); (b) at least one IC die facing downward (e.g., a MOSFET die); and (c) corresponding conductive wiring structures located on both the upper side and the lower side of the die facing upward and the die facing downward. Such electronic packages may be referred to as "double-sided electronic packages". In some examples, the double-sided electronic package may be formed using a panel-level packaging (PLP) process, for example, where an array of double-sided electronic packages is formed on a common panel and then segmented to produce a plurality of discrete double-sided electronic packages.

[0008] One aspect provides an electronic package, which includes: a first integrated circuit (IC) die, which is arranged in a first orientation; a second IC die, which is arranged in a second orientation opposite to the first orientation; an upper conductive wiring structure, which extends above the first IC die and the second IC die; a lower conductive wiring structure, which extends below the first IC die and the second IC die; and an encapsulation structure, which at least partially encapsulates the first IC die and the second IC die.

[0009] In some examples, the electronic package includes a panel level package (PLP).

[0010] In some examples, the first IC die arranged in the first orientation includes a first metal oxide silicon field effect transistor (MOSFET) die arranged together with: (a) a first MOSFET gate connection pad and a first MOSFET source connection pad located on the upper side of the first MOSFET die, and (b) a first MOSFET drain connection pad located on the lower side of the first MOSFET die; and the second IC die arranged in the second orientation includes a second MOSFET die arranged together with: (a) a second MOSFET drain connection pad located on the upper side of the second MOSFET die, and (b) a second MOSFET gate connection pad and a second MOSFET source connection pad located on the lower side of the second MOSFET die.

[0011] In some examples, the upper conductive wiring structure defines: (a) a high voltage terminal connected to the second MOSFET drain connection pad located on the upper side of the second MOSFET tube core and (b) a ground terminal connected to the first MOSFET source connection pad located on the upper side of the first MOSFET tube core; and the lower conductive wiring structure defines an output terminal, which is connected to the following items: (a) the first MOSFET drain connection pad located on the lower side of the first MOSFET tube core and (b) the second MOSFET source connection pad located on the lower side of the second MOSFET tube core.

[0012] In some examples, the first IC die includes a first silicon carbide (SiC) MOSFET, and the second IC die includes a second SiC MOSFET.

[0013] In some examples, at least one of the upper conductive wiring structure or the lower conductive wiring structure includes a redistribution layer (RDL).

[0014] In some examples, the upper conductive wiring structure includes a plurality of stacked upper redistribution layers (RDLs), and the lower conductive wiring structure includes a plurality of stacked lower RDLs.

[0015] In some examples, the upper conductive wiring structure and the lower conductive wiring structure include electroplated copper.

[0016] In some examples, at least one of the upper conductive wiring structure or the lower conductive wiring structure includes a lead frame.

[0017] In some examples, the electronic package includes: a third integrated circuit (IC) die, the third integrated circuit (IC) die arranged in the first orientation; and a fourth IC die, the fourth IC die arranged in the second orientation opposite to the first orientation; wherein the upper conductive wiring structure extends over the first IC die, the second IC die, the third IC die, and the fourth IC die; and wherein the lower conductive wiring structure extends below the first IC die, the second IC die, the third IC die, and the fourth IC die.

[0018] One aspect provides an electronic device, which includes an electronic package. The electronic package includes: a plurality of first metal oxide silicon field effect transistor (MOSFET) dies, the plurality of first metal oxide silicon field effect transistor (MOSFET) dies are arranged in a first orientation; a plurality of second MOSFET dies, the plurality of second MOSFET dies are arranged in a second orientation opposite to the first orientation; a first conductive wiring structure, the first conductive wiring structure includes at least one first conductive wiring layer extending above the plurality of first MOSFET dies and above the plurality of second MOSFET dies; and a second conductive wiring structure, the second conductive wiring structure includes at least one second conductive wiring layer extending below the plurality of first MOSFET dies and below the plurality of second MOSFET dies. The first conductive wiring structure defines: a first MOSFET drain connection structure, the first MOSFET drain connection structure connected to corresponding drain connection pads on the plurality of first MOSFET dies; a second MOSFET source connection structure, the second MOSFET source connection structure connected to corresponding source connection pads on the plurality of second MOSFET dies; and a second MOSFET gate connection structure, the second MOSFET gate connection structure connected to corresponding gate connection pads on the plurality of second MOSFET dies. The second conductive wiring structure defines: a second MOSFET drain connection structure, which is connected to corresponding drain connection pads on the plurality of second MOSFET tube cores; and a first MOSFET source connection structure, which is connected to corresponding source connection pads on the plurality of first MOSFET tube cores.

[0019] In some examples, the electronic package includes an encapsulation structure that at least partially encapsulates the plurality of first MOSFET dies, the plurality of second MOSFET dies, the first conductive routing structure, and the second conductive routing structure.

[0020] In some examples, the electronic package includes a first MOSFET gate connection structure connected to corresponding gate connection pads on the plurality of first MOSFET dies, the first MOSFET gate connection structure including at least one conductive element formed in the first conductive wiring structure and at least one conductive element formed in the second conductive wiring structure.

[0021] In some examples, the electronic device includes a bus bar connected to the second MOSFET source connection structure and the first MOSFET drain connection structure.

[0022] In some examples, the electronic device includes a printed circuit board, wherein the second MOSFET drain connection structure and the first MOSFET source connection structure are mounted to corresponding electronic components on the printed circuit board.

[0023] In some examples, the electronic device includes a printed circuit board, wherein the second MOSFET source connection structure, the first MOSFET drain connection structure, the first MOSFET gate connection structure, and the second MOSFET gate connection structure are mounted to corresponding electronic components on the printed circuit board.

[0024] One aspect provides a method for forming an electronic package. A heat release layer is formed on a carrier. A first IC die and a second IC die are arranged on the heat release layer, the first IC die is arranged in a first orientation, and the second IC die is arranged in a second orientation opposite to the first orientation, wherein the first side of the first IC die and the second side of the second IC die face the carrier, and the second side of the first IC die and the first side of the second IC die face away from the carrier. A mold encapsulation is formed above the first IC die and the second IC die. A first conductive wiring structure is formed above the second side of the first IC die and the first side of the second IC die, the first conductive wiring structure defining a first conductive connection to corresponding contacts located on the second side of the first IC die and the first side of the second IC die. The carrier is removed. A second conductive routing structure is formed on the first side of the first IC die and the second side of the second IC die, the second conductive routing structure defining second conductive connections to corresponding contacts located on the first side of the first IC die and the second side of the second IC die.

[0025] In some examples, the method includes: forming a first contact element on the first IC die before placing the first IC die on the thermal release layer, wherein placing the first IC die on the thermal release layer includes: placing the first IC die together with the first contact element facing the thermal release layer.

[0026] In some examples, the method includes: forming a first contact element on the first IC die before placing the first IC die on the thermal release layer, wherein forming the first conductive wiring structure includes: forming at least one first conductive wiring element in contact with the first contact element on the first IC die.

[0027] In some examples, the method includes forming a vertically extending contact extending upward from the thermal release layer, wherein forming the second conductive routing structure includes forming a conductive connection between the vertically extending contact and a corresponding contact on the first side of the first IC die.

[0028] In some examples, the method includes forming the vertically extending contacts extending upward from the thermal release layer before placing the first IC die and the second IC die on the thermal release layer.

[0029] In some examples, the method includes: forming a first vertically extending contact and a second vertically extending contact extending upward from the thermal release layer, wherein forming the second conductive wiring structure includes: forming (a) a first conductive connection between the first vertically extending contact and a corresponding contact located on the first side of the first IC die, and forming (b) a second conductive connection between the second vertically extending contact and a corresponding contact located on the second side of the second IC die.

[0030] In some examples, the first IC die includes a first MOSFET die; the second IC die includes a second MOSFET die; and arranging the first IC die and the second IC die on the heat release layer includes: (i) arranging the first IC die together with: (a) a first MOSFET gate connection pad and a first MOSFET source connection pad located on the second side of the first IC die facing away from the carrier, and (b) a first MOSFET drain connection pad located on the first side of the first IC die facing the carrier; and (ii) arranging the second IC die together with: (a) a second drain connection pad located on the first side of the second IC die facing away from the carrier, and (b) a second gate connection pad and a second source connection pad located on the second side of the second IC die facing the carrier.

[0031] In some examples, forming the first conductive wiring structure or forming the second conductive wiring structure includes forming a stack of a plurality of redistribution layers (RDLs).

[0032] In some examples, forming the first conductive wiring structure or forming the second conductive wiring structure includes: forming electroplated copper.

[0033] In some examples, forming the first conductive wiring structure or forming the second conductive wiring structure includes: attaching a lead frame. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Example aspects of the present disclosure are described below in conjunction with the accompanying drawings, in which:

[0035] Figure 1A A top view of an example double-sided electronic package including an IC die facing up, an IC die facing down, and conductive wiring layers extending above and below the IC die facing up and the IC die facing down is shown, and Figure 1B The example double-sided electronic package is shown through Figure 1AA cross-sectional side view of line 1B-1B is shown;

[0036] Figure 2A A top view of an example electronic device including an example double-sided electronic package is shown, and Figure 2B The example electronic device is shown through Figure 2A A cross-sectional side view of line 2B-2B is shown;

[0037] Figures 3A to 3Z is a series of cross-sectional side views illustrating an example method of forming an example double-sided electronic package; and

[0038] Figure 4A and Figure 4B An example alternative process for forming vertically extending contacts (eg, for connecting respective elements of upper and lower conductive wiring layers) is illustrated.

[0039] It should be understood that the reference numerals of any illustrative elements appearing in multiple different figures have the same meaning in the multiple figures, and references or discussions herein to any illustrative element in the context of any particular figure also apply to each other figure (if any) in which the same illustrative element is shown. DETAILED DESCRIPTION

[0040] Figure 1A and Figure 1B An example double-sided electronic package 100 (or, for convenience, simply referred to as electronic package 100 ) including conductive wiring layers above and below a pair of IC dies that are arranged in opposite directions relative to each other is shown. Figure 1A A top view of an example electronic package 100 is shown, and Figure 1B Shown through Figure 1A A cross-sectional side view of line 1B-1B is shown.

[0041] The example electronic package 100 includes: a first IC die 102 arranged in a first orientation; and a second IC die 104 arranged in a second orientation opposite to the first orientation. The first orientation of the first IC die 102 and the second orientation of the second IC die 104 are discussed below, for example, with reference to the positioning of the corresponding source connection pads, gate connection pads, and drain connection pads of the first IC die 102 and the second IC die 104.

[0042] The electronic package 100 may include a conductive wiring structure 110, which includes: (a) an upper conductive wiring structure 112, which extends above the first IC die 102 and the second IC die 104; (b) a lower conductive wiring structure 114, which extends below the first IC die 102 and the second IC die 104; and (c) an intermediate conductive wiring structure 116, which is located between the upper conductive wiring structure 112 and the lower conductive wiring structure 114, for example, to connect corresponding elements of the upper conductive wiring structure 112 with corresponding elements of the lower conductive wiring structure 114.

[0043] The encapsulation structure 118 at least partially encapsulates the first IC die 102 and the second IC die 104. The encapsulation structure 118 may include one or more encapsulation regions, for example, the one or more encapsulation regions include epoxy or other molding compounds, photosensitive materials (e.g., polyimide (PI) or polyphenylene ester (POB)), or one or more other insulating materials. In some examples, for example, as described below with reference to FIG. 2A to FIG. 2B as well as Figures 3A to 3Z As discussed, the encapsulation structure 118 includes: (a) a molding compound region (e.g., including epoxy resin) formed around the first IC die 102, the second IC die 104 and the intermediate conductive wiring structure 116; (b) a first photosensitive material region (e.g., including PI or POB) in which the upper conductive wiring structure 112 is formed; and (c) a second photosensitive material region (e.g., including PI or POB) in which the lower conductive wiring structure 114 is formed.

[0044] As used herein, relative terms such as "upper", "lower", "above", "below", "facing upward", and "facing downward" describe, for example, the relative position or orientation of various elements in the context of the example orientations shown in the various figures. These relative terms are not intended to be fixed or absolute terms, but are intended to encompass other orientations of the associated structures (e.g., other orientations of the electronic package 100) other than those shown in the figures. The various structures shown in the figures (including Figure 1A to Figure 1B The illustrated orientation of the electronic package 100 is arbitrary; the electronic package 100 and other illustrated structures may be rotated or otherwise oriented in any other manner (with corresponding adjustments to any relative terms used herein, e.g., "up," "down," "above," "below," "facing up," and "facing down") without departing from the scope of the present disclosure. For example, the electronic package 100 may be rotated or otherwise oriented relative to the electronic package 100. Figure 1A to Figure 1B The orientation shown is oriented upside down, or the electronic package 100 may be oriented such as by surrounding the electronic package 100 with the electronic package 100. Figure 1AThe x-axis or y-axis shown is rotated 90 degrees (or other angles) to be vertical (rather than Figure 1A to Figure 1B Horizontally) oriented as shown.

[0045] In some examples, electronic package 100 may be a panel level package (PLP), eg, where multiple instances of electronic package 100 or similar electronic packages may be formed on a common panel.

[0046] In some examples, first IC die 102 and second IC die 104 include respective metal oxide silicon field effect transistor (MOSFET) dies, such as vertical MOSFET dies. In one example, first IC die 102 includes a first silicon carbide (SiC) MOSFET and second IC die 104 includes a second SiC MOSFET.

[0047] In some examples, the first IC die 102 in the first orientation is a first MOSFET die arranged in a "face-up" orientation with: (a) a first MOSFET gate connection pad 120 and a first MOSFET source connection pad 122 located on an upper side of the first MOSFET die 102, and (b) a first MOSFET drain connection pad 124 located on a lower side of the first MOSFET die 102; and the second IC die 104 arranged in the second orientation is a second MOSFET die arranged in a "face-down" orientation with: (a) a second MOSFET drain connection pad 130 located on an upper side of the second MOSFET die 104, and (b) a second MOSFET gate connection pad 132 and a second MOSFET source connection pad 134 located on a lower side of the second MOSFET die 104. In some examples, the first MOSFET die 102 and the second MOSFET die 104 are the same type of components, where the second MOSFET die 104 is flipped relative to the first MOSFET die 102.

[0048] First MOSFET gate connection pad 120, first MOSFET source connection pad 122, first MOSFET drain connection pad 124, second MOSFET drain connection pad 130, second MOSFET gate connection pad 132, and second MOSFET source connection pad 134 may include respective solder pads (or alternatively, sintered paste) formed on first IC die 102 and second IC die 104, respectively. In some examples, respective connection pads 120, 122, 124, 130, 132, and 134 may be formed on aluminum on respective upper and lower sides of first IC die 102 and second IC die 104.

[0049] In other examples, the first IC die 102 and the second IC die 104 may be arranged relative to each other. Figure 1B The orientation shown is reversed; thus, the first IC die 102 may be arranged in a face-down orientation and the second IC die 104 may be arranged in a face-up orientation.

[0050] The upper conductive wiring structure 112 extending over the first IC die 102 and the second IC die 104 may include one or more conductive layers. FIG. 2A to FIG. 2B as well as Figures 3A to 3Z As discussed, the upper conductive wiring structure 112 may include a plurality of upper conductive wiring layers 212 (e.g., a plurality of RDLs or a plurality of metal interconnect layers) formed in a stacked manner to define the geometry of the upper conductive wiring structure 112. In other examples, the upper conductive wiring structure 112 may be formed as a single conductive layer 212 (e.g., a single RDL or a single metal interconnect layer).

[0051] Similarly, the lower conductive wiring structure 114 extending below the first IC die 102 and the second IC die 104 may include one or more conductive layers. FIG. 2A to FIG. 2B as well as Figures 3A to 3Z As discussed, the lower conductive wiring structure 114 may include a plurality of lower conductive wiring layers 214 (e.g., a plurality of RDLs or a plurality of metal interconnect layers) formed in a stacked manner to define the geometry of the lower conductive wiring structure 114. In other examples, the lower conductive wiring structure 114 may be formed as a single conductive layer 214 (e.g., a single RDL or a single metal interconnect layer).

[0052] Similarly, the intermediate conductive wiring structure 116 located between the upper conductive wiring structure 112 and the lower conductive wiring structure 114 may include one or more conductive layers. FIG. 2A to FIG. 2B as well as Figures 3A to 3Z (Specifically, Figures 3K to 3M ), the intermediate conductive wiring structure 116 may include one or more vertically extending contacts formed by a single deposited metal layer. In other examples, the intermediate conductive wiring structure 116 may include multiple conductive layers that are formed in a stacked manner to define the geometry of the intermediate conductive wiring structure 116.

[0053] In some examples, one or more of the upper conductive wiring structure 112, the lower conductive wiring structure 114, and the intermediate conductive wiring structure 116 include electroplated copper or other deposited conductors, such as sputtered gold or sputtered aluminum. In some examples, at least one of the upper conductive wiring structure 112 or the lower conductive wiring structure 114 includes a lead frame (e.g., a copper lead frame), for example, for certain high current applications.

[0054] In some examples, the conductive wiring structure 110 (including elements of the upper conductive wiring structure 112, the lower conductive wiring structure 114, and the middle conductive wiring structure 116) may define:

[0055] (a) a first MOSFET gate contact 140 connected to a first MOSFET gate connection pad 120 located on the upper side of the first MOSFET die 102,

[0056] (b) a ground terminal 142 connected to the first MOSFET source connection pad 122 located on the upper side of the first MOSFET die 102,

[0057] (c) a high voltage terminal 144 connected to a second MOSFET drain connection pad 130 located on the upper side of the second MOSFET die 104,

[0058] (d) a second MOSFET gate contact 146 connected to a second MOSFET gate connection pad 132 located on the underside of the second MOSFET die 104, and

[0059] (e) An output terminal 150 connected to: (i) a first MOSFET drain connection pad 124 located on the underside of the first MOSFET die 102 and (ii) a second MOSFET source connection pad 134 located on the underside of the second MOSFET die 104 .

[0060] exist Figure 1A and Figure 1B In the example shown, the first MOSFET gate contact 140, the ground terminal 142 and the high voltage terminal 144 include corresponding elements of the upper conductive wiring structure 112; and the second MOSFET gate contact 146 and the output terminal 150 include corresponding elements of the upper conductive wiring structure 112, the middle conductive wiring structure 116 and the lower conductive wiring structure 114.

[0061] As shown, the first MOSFET gate contact 140, the ground terminal 142, the high voltage terminal 144, the second MOSFET gate contact 146, and the output terminal 150 can be exposed on the upper side 160 of the electronic package 100, for example, to allow electrical connection between the corresponding contacts 140, 142, 144, 146, and 150 and the corresponding electronic components disposed on the PCB or other substrate or device to which the upper side 160 of the electronic package 100 is mounted. The output terminal 150 can also be exposed on the lower side 162 of the electronic package 100, for example, for connection to a bus bar.

[0062] Example electronic package 100 may include Figure 1A and Figure 1B Other dies not shown in the figure, for example, one or more gate drivers, resistors, and capacitors.

[0063] In some examples, the example electronic package 100 can exhibit reduced inductance compared to certain conventional packages (e.g., conventional packages that include, without limitation, various traces or bond wires in a corresponding gate drive control loop defining a resonant cavity (LC cavity). For example, the electronic package 100 can exhibit a total inductance of less than 2 nanohenries (nH).

[0064] Figure 2A and Figure 2B An example electronic device 200 is shown, which includes an example double-sided electronic package 201 (or simply referred to as electronic package 201 for convenience), a device substrate 236 and a bus bar 238. Specifically, Figure 2A A top view of an example electronic device 200 is shown, and Figure 2B Shown through Figure 2A A cross-sectional side view of line 2B-2B is shown.

[0065] As shown, an upper side 260 of the electronic package 201 may be mounted or otherwise secured to a device substrate 236 (eg, a PCB, interposer, or other electronic device), and the busbars 238 may be mounted or otherwise secured to a lower side 262 of the electronic package 201 .

[0066] The example electronic package 201 may include: three first IC dies 202 arranged in a first orientation; and three second IC dies 204 arranged in a second orientation opposite to the first orientation. (In an alternative example, a similar electronic package may be formed with four IC dies per switch).

[0067] The electronic package 201 may also include a conductive wiring structure 210, which includes: (a) an upper conductive wiring structure 212, which extends above the first IC die 202 and the second IC die 204; (b) a lower conductive wiring structure 214, which extends below the first IC die 202 and the second IC die 204; and (c) an intermediate conductive wiring structure 216, which is located between the upper conductive wiring structure 212 and the lower conductive wiring structure 214, for example, to connect corresponding elements of the upper conductive wiring structure 212 with corresponding elements of the lower conductive wiring structure 214.

[0068] The encapsulation structure 218 at least partially encapsulates the first IC die 202 and the second IC die 204. The encapsulation structure 218 may include one or more encapsulation regions, for example, the one or more encapsulation regions include epoxy resin or other molding compound, photosensitive material (e.g., polyimide (PI) or polyphenylene ester (POB)), or one or more other insulating materials. In this example, for example, Figure 2B As shown, the encapsulation structure 218 includes: (a) a molding compound region 218a (e.g., including epoxy resin), which is formed around the first IC die 202, the second IC die 204 and the intermediate conductive wiring structure 216; (b) a first photosensitive material region 218b (e.g., including PI or POB), in which the upper conductive wiring structure 212 is formed; and (c) a second photosensitive material region 218c (e.g., including PI or POB), in which the lower conductive wiring structure 214 is formed.

[0069] In some examples, electronic package 201 may be a panel level package (PLP), eg, where multiple instances of electronic package 201 or similar electronic packages may be formed on a common panel.

[0070] In some examples, the first IC die 202 and the second IC die 204 include respective MOSFET dies, eg, vertical MOSFETs. In one example, the first IC die 202 and the second IC die 204 include silicon carbide (SiC) MOSFETs.

[0071] In this example, the first IC die 202 is a MOSFET die arranged in a "face-up" orientation with a corresponding first IC die 202 having the following items: (a) a corresponding first MOSFET gate connection pad 220 and a corresponding first MOSFET source connection pad 222 located on the upper side of the corresponding first MOSFET die 202, and (b) a corresponding first MOSFET drain connection pad 224 located on the lower side of the corresponding first MOSFET die 202. In contrast, the second IC die 204 is a MOSFET die arranged in a "face-down" orientation with a corresponding second IC die 204 having the following items: (a) a corresponding second MOSFET drain connection pad 230 located on the upper side of the corresponding second MOSFET die 204, and (b) a corresponding second MOSFET gate connection pad 232 and a corresponding second MOSFET source connection pad 234 located on the lower side of the corresponding second MOSFET die 204.

[0072] The respective first MOSFET gate connection pad 220, the first MOSFET source connection pad 222, the first MOSFET drain connection pad 224, the second MOSFET drain connection pad 230, the second MOSFET gate connection pad 232, and the second MOSFET source connection pad 234 may include respective solder pads (or alternatively, sintered paste) formed on the first IC die 202 and the second IC die 204, respectively. In some examples, the respective connection pads 220, 222, 224, 230, 232, and 234 may be formed on aluminum on respective upper and lower sides of the respective first IC die 202 and the second IC die 204.

[0073] In other examples, the first IC die 202 and the second IC die 204 may be located relative to each other. Figure 2B Thus, the first IC die 202 may be arranged in a face-down orientation and the second IC die 204 may be arranged in a face-up orientation.

[0074] like Figure 2B As best shown, the upper conductive wiring structure 212 extending above the first IC die 202 and the second IC die 204 may include a plurality of upper conductive wiring layers 270 (in this example, four metal layers), and the lower conductive wiring structure 214 extending below the first IC die 202 and the second IC die 204 may similarly include a plurality of lower conductive wiring layers 272 (in this example, four metal layers). The upper conductive wiring layers 270 may include respective RDLs and / or respective metal interconnect layers that are formed in a stacked manner to define the geometry of the upper conductive wiring structure 212. Similarly, the lower conductive wiring layers 272 may include respective RDLs and / or respective metal interconnect layers that are formed in a stacked manner to define the geometry of the lower conductive wiring structure 214. In some examples, the plurality of upper conductive wiring layers 270 and the plurality of lower conductive wiring layers 272 may be formed by electrochemical deposition (electroplating) of copper or deposition of other metals (e.g., sputtered gold or sputtered aluminum), as described below with reference to FIG. Figures 3A to 3Z In some examples, one or more of the upper conductive wiring layers 270 or the lower conductive wiring layers 272 can include a lead frame, such as a copper lead frame.

[0075] In this example, the intermediate conductive wiring structure 216 located between the upper conductive wiring structure 212 and the lower conductive wiring structure 214 is formed as a single conductive layer, for example, by electrochemical deposition of copper or other metals, as described below with reference to Figure 3LIn other examples, the intermediate conductive wiring structure 216 may include multiple conductive layers (eg, multiple RDL and / or metal interconnect layers) formed in a stacked manner to define the geometry of the intermediate conductive wiring structure 216 .

[0076] like FIG. 2A to FIG. 2B As shown, the conductive wiring structure 210 (including the elements of the upper conductive wiring structure 212, the lower conductive wiring structure 214 and the middle conductive wiring structure 216) defines:

[0077] (a) first MOSFET gate contacts 240 connected to respective first MOSFET gate connection pads 220 located on respective upper sides of the three first MOSFET dies 202,

[0078] (b) a ground terminal 242 connected to a respective first MOSFET source connection pad 222 located on a respective upper side of the three first MOSFET dies 202,

[0079] (c) a high voltage terminal 244 connected to a respective second MOSFET drain connection pad 230 located on a respective upper side of the three second MOSFET dies 204,

[0080] (d) second MOSFET gate contacts 246 connected to respective second MOSFET gate connection pads 232 located on respective undersides of the three second MOSFET dies 204, and

[0081] (e) an output terminal 250 connected to: (i) corresponding first MOSFET drain connection pads 224 located on the corresponding lower sides of the three first MOSFET die 204 and (ii) corresponding second MOSFET source connection pads 234 located on the corresponding lower sides of the three second MOSFET die 202.

[0082] As shown, the first MOSFET gate contact 240, the ground terminal 242 and the high voltage terminal 244 include corresponding elements of the upper conductive wiring structure 212; and the second MOSFET gate contact 246 and the output terminal 250 include corresponding elements of the upper conductive wiring structure 212, the middle conductive wiring structure 216 and the lower conductive wiring structure 214.

[0083] The first MOSFET gate contact 240, the ground terminal 242, the high voltage terminal 244, the second MOSFET gate contact 246, and the output terminal 250 each include elements of multiple conductive wiring layers (e.g., multiple copper layers). Therefore, the contacts and terminals 240, 242, 244, 246, and 250 can be referred to as multi-layer contacts / terminals 240, 242, 244, 246, and 250.

[0084] As shown, the first MOSFET gate contact 240, the ground terminal 242, the high voltage terminal 244, the second MOSFET gate contact 246, and the output terminal 250 include an exposed upper surface (exposed by the first photosensitive material region 218b) located on the upper side 260 of the electronic package 201, thereby providing electrical connections between the corresponding contacts 240, 242, 244, 246 and 250 and the corresponding electronic components disposed on the device substrate (e.g., PCB) 236. The output terminal 250 includes an exposed lower surface (exposed by the second photosensitive material region 218c) located on the lower side 262 of the electronic package 201, thereby providing an electrical connection to the bus bar 238.

[0085] In this example, the second MOSFET gate contact 246 and the output terminal 250 utilize corresponding elements of the intermediate conductive wiring structure 216 to provide electrical connection between the lower sides of the first IC die 202 and the second IC die 204 and corresponding electronic components on the device substrate 236 disposed on the upper side 260 of the electronic package 201.

[0086] An example electronic package 201 may include Figure 2A and Figure 2B Other dies not shown in the figure, for example, one or more gate drivers, resistors, and capacitors.

[0087] In some examples, the example electronic package 201 can exhibit reduced inductance compared to certain conventional packages (e.g., conventional packages including, without limitation, various traces or bond wires in a corresponding gate drive control loop defining a resonant cavity (LC cavity). For example, the electronic package 201 can exhibit a total inductance of less than 2 nanohenries (nH).

[0088] Figures 3A to 3Z is a series of cross-sectional side views illustrating an example method of forming an example double-sided electronic package 400 (or, for convenience, simply referred to as electronic package 400) that includes conductive wiring layers above and below a pair of IC dies that are arranged in an inverted manner relative to each other, e.g., similar to that discussed above. Figure 1A to Figure 1B as well as FIG. 2A to FIG. 2B An example double-sided electronic package 100 or double-sided electronic package 201 is shown. Figure 3Z A completed double-sided electronic package 400 is shown, as discussed below.

[0089] like Figure 3AAs shown, a wafer 300 (e.g., comprising silicon or silicon carbide) is formed of a component having a plurality of MOSFET dies, the component including respective doped regions (e.g., defining respective source regions, drain regions, and gate regions) and bonding pads 302 (e.g., aluminum bonding pads) located on the upper side of the wafer 300. The bonding pads 302 may include respective gate connection bonding pads 302a and source connection bonding pads 302b.

[0090] like Figure 3B As shown, a copper seed layer 304 is formed (eg, by PVD deposition) on respective bond pads 302a, 302b.

[0091] like Figure 3C As shown, a photoresist layer is deposited, patterned, and etched to form a patterned photoresist 306 that defines respective photoresist openings 308 that are aligned over respective bond pads 302a, 302b having a copper seed layer 304 formed thereon.

[0092] like Figure 3D As shown, a copper wiring layer 310 is deposited (e.g., by an electrochemical deposition process) in the corresponding photoresist opening 308 and attached to the copper seed layer 304 on the corresponding bonding pads 302a, 302b to form a corresponding gate contact element 312 above the corresponding gate connection bonding pad 302a and a corresponding source contact element 314 above the corresponding source connection bonding pad 302b.

[0093] like Figure 3E As shown, the remaining portions of the patterned photoresist 306 may be removed.

[0094] like Figure 3F As shown, wafer 300 may be flipped so that the back side (MOSFET drain region) faces upward, and wafer 300 may be back ground to achieve the desired thickness of the IC die 324 being formed (see FIG. Fig. 3I ).

[0095] like Figure 3G As shown, a thin seed layer 316 of titanium copper (TiCu) is deposited (eg, sputtered) on the back side of the wafer 300 .

[0096] like Figure 3H As shown, a copper wiring layer 318 is deposited (eg, by an electrochemical deposition process) and attached to the TiCu seed layer 316 to form a drain contact layer 320 over the drain region of the corresponding MOSFET.

[0097] like Fig. 3IAs shown, the wafer 300 can be cut (or diced) to define a plurality of singulated MOSFET dies 324, wherein respective MOSFET dies 324 have respective gate contact elements 312, respective source contact elements 314, and respective drain contact elements 322 defined by respective portions of the drain contact layer 320. The singulated MOSFET dies 324 can then be mounted on a carrier, as described below with reference to Figure 3N discussed.

[0098] like Figure 3J As shown, thermal release layer 330 is deposited on a carrier 332 (eg, a rigid panel including epoxy or metal).

[0099] like Figure 3K As shown, a thick photoresist layer (e.g., having a thickness greater than the thickness of the segmented MOSFET die 324 discussed above) is deposited, patterned, and etched to form a patterned photoresist 334 that includes narrow slot openings 336a and 336b extending downwardly to the thermal release layer 330.

[0100] like Figure 3L As shown, vertically extending contacts 340 and 342 are formed in slot openings 336a and 336b, respectively, such as by sputtering a thin copper seed layer followed by depositing a thick copper layer by electrochemical deposition. In other examples, vertically extending contacts 340 and 342 may be formed by different processes, such as by forming a mold encapsulation over MOSFET dies 324a and 324b, etching vertically extending slot openings in the mold encapsulation, and filling the slot openings with copper or other conductive material, such as discussed below. FIG. 4A to FIG. 4B shown.

[0101] like Figure 3M As shown, remaining portions of patterned photoresist 334 may be removed, leaving vertically extending contacts 340 and 342 extending upward from thermal release layer 330 on carrier 332 .

[0102] like Figure 3N As shown, a plurality of segmented MOSFET dies 324 including a first MOSFET die 324a and a second MOSFET die 324b are mounted on a thermal release layer 330 on a carrier 332, the MOSFET dies being laterally spaced apart from each other and from vertically extending contacts 340 and 342. The first MOSFET die 324a is mounted in a first orientation (a face-up orientation) with a first side facing upward and a second side facing downward, and the second MOSFET die 324b is mounted in a second orientation (a face-down orientation) with a first side facing downward and a second side facing upward, i.e., opposite to the first orientation (a face-up orientation) of the first MOSFET die 324a.

[0103] In the face-up orientation of the first MOSFET die 324a, the drain contact element 322 (adjacent to the MOSFET drain) located on the second side of the first MOSFET die 324a faces downward (mounted to the thermal release layer 330), and the gate contact element 312 and the source contact element 314 (adjacent to the MOSFET gate and the MOSFET source, respectively) located on the first side of the first MOSFET die 324a face upward away from the thermal release layer 330. Conversely, in the face-down orientation of the second MOSFET die 324b, the gate contact element 312 and the source contact element 314 (adjacent to the MOSFET gate and the MOSFET source, respectively) located on the first side of the second MOSFET die 324b face downward (mounted to the thermal release layer 330), and the drain contact element 322 (adjacent to the MOSFET drain) located on the second side of the second MOSFET die 324b faces upward away from the thermal release layer 330.

[0104] like Fig.3O As shown, a mold encapsulant 344 is formed over the MOSFET dies 324a and 324b and the vertically extending contacts 340 and 342. The mold encapsulant 344 may include epoxy or other suitable molding compound.

[0105] like Figure 3P As shown, a planarization process (e.g., a grinding process) is performed to remove an upper portion of the mold encapsulation 344, thereby exposing the gate contact element 312 and the source contact element 314 of the first MOSFET die 324a, the drain contact element 322 of the second MOSFET die 324b, and the top surfaces of the vertically extending contacts 340 and 342.

[0106] A series of conductive wiring layers are deposited over the planarized structure to form various multi-layer contacts or terminals (or corresponding portions thereof), such as Figure 3Q to Figure 3V shown.

[0107] like Figure 3Q As shown, the photosensitive layer 350 is deposited on the planarized structure by a coating process. In some examples, the photosensitive layer 350 may include polyimide (PI) or polyphenylene ester (POB).

[0108] like Figure 3RAs shown, the photosensitive layer 350 can be patterned (e.g., by selectively exposing, developing, and cleaning the photosensitive layer 350) to define corresponding photosensitive layer openings 352 that expose the gate contact element 312 of the first MOSFET die 324a, the source contact element 314 of the first MOSFET die 324a, the drain contact element 322 of the second MOSFET die 324b, and the upper surfaces of the vertically extending contacts 340 and 342.

[0109] like Figure 3S As shown, a copper wiring layer (e.g., by an electrochemical deposition process) is deposited in corresponding photosensitive layer openings 352 to form corresponding contact elements 356 that contact the gate contact element 312 of the first MOSFET die 324a, the source contact element 314 of the first MOSFET die 324a, the drain contact element 322 of the second MOSFET die 324b, and the vertically extending contacts 340 and 342. The patterned photosensitive layer 350 may remain intact, thereby forming part of a mold encapsulation of a resulting electronic package.

[0110] Then, Figure 3Q to Figure 3S The process shown may be repeated any number of times, for example, as discussed below. Figure 3T to Figure 3Z As shown, to produce an additional copper wiring layer with corresponding contact elements, thereby forming corresponding multi-layer contacts and terminals (e.g., corresponding to the above-discussed Figure 2B Multi-layer contacts / terminals 240, 242, 244, 246 and 250 are shown).

[0111] like Figure 3T As shown, a photosensitive layer 360 (eg, comprising PI or POB) is deposited and patterned (eg, by selectively exposing, developing, and cleaning the photosensitive layer 360 ) to define corresponding photosensitive layer openings 362 that expose upper surfaces of the contact elements 356 .

[0112] like Figure 3U As shown, a copper wiring layer is deposited (eg, by an electrochemical deposition process) in corresponding photosensitive layer openings 362 to form corresponding contact elements 366 that contact corresponding contact elements 356. Patterned photosensitive layer 360 may remain intact, forming part of a mold encapsulation of a resulting electronic package.

[0113] like Figure 3V As shown, another layer of contact elements 370 in contact with corresponding contact elements 366 may similarly be formed in a corresponding patterned photosensitive layer 372, which may also remain intact to form part of the mold encapsulation of the resulting electronic package.

[0114] like Figure 3WAs shown, the structure can be flipped over and the carrier 332 and the thermal release layer 330 can be removed (for example, by a thermal release process or a mechanical release process) to expose the upper surfaces of the drain contact element 322 of the first MOSFET die 324a, the gate contact element 312 and the source contact element 314 of the second MOSFET die 324b, and the upper surfaces of the vertically extending contacts 340 and 342.

[0115] A series of conductive wiring layers are deposited on Figure 3W The structure shown is formed to form various multi-layer contacts or terminals (or their corresponding parts), such as Figure 3X to Figure 3Z shown.

[0116] like Figure 3X As shown, according to the above reference Figure 3Q to Figure 3S The above process can similarly form the same Figure 3W A layer of contact elements 380 is shown contacting corresponding contact elements 312, 314, 322, 340 and 342. The patterned photosensitive layer 382 may remain intact, thereby forming part of a mold encapsulation of a resulting electronic package.

[0117] Similarly, if Figure 3Y As shown, another layer of contact elements 386 in contact with corresponding contact elements 380 may be formed in a corresponding patterned photosensitive layer 388, which may remain intact to form part of a mold encapsulation of a resulting electronic package.

[0118] Similarly, if Figure 3Z As shown, another layer of contact elements 390 in contact with corresponding contact elements 386 may be formed in a corresponding patterned photosensitive layer 392, which may remain intact to form part of a mold encapsulation of a resulting electronic package.

[0119] Figure 3ZThe resulting structure shown defines an example double-sided electronic package 400. The example double-sided electronic package 400 includes a conductive wiring structure 402 defined by various contact elements formed on and around the first MOSFET die 324a and the second MOSFET die 324b, including the contact elements 312, 314, 322, 340, 342, 356, 366, 370, 380, 386 formed in multiple wiring layers as discussed above. Corresponding elements of the conductive wiring structure 402 define various multi-layer contacts and terminals, which include: (a) a multi-layer first MOSFET gate contact 404 connected to the gate of the first MOSFET die 324a; (b) a multi-layer ground terminal 406 connected to the source of the first MOSFET die 324a; (c) a multi-layer high voltage terminal 408 connected to the drain of the second MOSFET die 324b; (d) a multi-layer second MOSFET gate contact 410 connected to the gate of the second MOSFET die 324b; and (e) a multi-layer output terminal 412 connected to: (i) the drain of the first MOSFET die 324a and (ii) the source of the second MOSFET die 324b.

[0120] The MOSFET die 324a and 324b and the various multi-layer contacts and terminals 404, 406, 408, 410 and 412 defined by the conductive wiring structure 402 are at least partially encapsulated by an encapsulation structure 416, which is jointly defined by a mold encapsulation 344 (e.g., comprising epoxy resin) and photosensitive layers 350, 360, 372, 382, ​​388 and 392 (e.g., comprising PI or POB).

[0121] As described above, in other examples, vertically extending contacts 340 and 342 may be formed by alternative processes. Figure 4A and Figure 4B An alternative process for forming vertically extending contacts 340 and 342 is illustrated. Figure 4A As shown, after MOSFET dies 324a and 324b are mounted on carrier 332, mold encapsulation 444 may be formed over MOSFET dies 324a and 324b, and vertically extending slot openings 450 and 452 may be etched in mold encapsulation 444 (e.g., extending downward to thermal release layer 330). Figure 4B As shown, copper may be deposited (eg, by electrochemical deposition) in vertically-extending slot openings 450 and 452 to form vertically-extending contacts 460 and 460 .

[0122] In other examples, vertically extending contacts may be formed by placing conductive shunts or other passive components on carrier 332 .

[0123] Although example embodiments have been described above, other modifications and embodiments may be made by this disclosure without departing from the spirit and scope of these embodiments.

Claims

1. An electronic package, comprising: a first integrated circuit (IC) die arranged in a first orientation; a second IC die arranged in a second orientation opposite to the first orientation; an upper conductive wiring structure extending over the first IC die and the second IC die; a lower conductive wiring structure extending below the first IC die and the second Iv die; and An encapsulation structure at least partially encapsulates the first IC die and the second IC die. 2 . The electronic package of claim 1 , wherein the electronic package comprises a panel level package (PLP).

3. The electronic package according to any one of claims 1 to 2, wherein: the first IC die arranged in the first orientation comprising a first metal oxide silicon field effect transistor (MOSFET) die arranged with: (a) a first MOSFET gate connection pad and a first MOSFET source connection pad on an upper side of the first MOSFET die, and (b) a first MOSFET drain connection pad on a lower side of the first MOSFET die; and The second IC die arranged in the second orientation includes a second MOSFET die arranged together with: (a) a second MOSFET drain connection pad located on the upper side of the second MOSFET die, and (b) a second MOSFET gate connection pad and a second MOSFET source connection pad located on the lower side of the second MOSFET die.

4. The electronic package of claim 3, wherein: The upper conductive wiring structure defines: (a) a high voltage terminal connected to the second MOSFET drain connection pad and (b) a ground terminal connected to the first MOSFET source connection pad; and The lower conductive wiring structure defines an output terminal connected to: (a) the first MOSFET drain connection pad and (b) the second MOSFET source connection pad. 5 . The electronic package of claim 3 , wherein the first IC die comprises a first silicon carbide (SiC) MOSFET and the second IC die comprises a second SiC MOSFET. 6 . The electronic package of claim 1 , wherein at least one of the upper conductive wiring structure or the lower conductive wiring structure comprises a redistribution layer (RDL). 7 .

7. The electronic package according to any one of claims 1 to 6, wherein: The upper conductive wiring structure includes a plurality of stacked upper redistribution layers (RDLs); and The lower conductive wiring structure includes a plurality of stacked lower RDLs.

8. The electronic package of any one of claims 1 to 7, wherein at least one of the upper conductive wiring structure or the lower conductive wiring structure comprises a lead frame.

9. The electronic package according to any one of claims 1 to 8, comprising: a third integrated circuit (IC) die arranged in the first orientation; and a fourth IC die arranged in the second orientation opposite to the first orientation; wherein the upper conductive wiring structure extends over the first IC die, the second IC die, the third IC die, and the fourth IC die; and Wherein the lower conductive wiring structure extends below the first IC die, the second IC die, the third IC die and the fourth IC die.

10. An electronic device, comprising: An electronic package, comprising: a plurality of first metal oxide silicon field effect transistor (MOSFET) dies arranged in a first orientation; a plurality of second MOSFET dies arranged in a second orientation opposite to the first orientation; A first conductive wiring structure, the first conductive wiring structure comprising at least one first conductive wiring layer extending over the plurality of first MOSFET dies and over the plurality of second MOSFET dies, the first conductive wiring structure defining: a first MOSFET drain connection structure connected to respective drain connection pads on the plurality of first MOSFET dies; a second MOSFET source connection structure connected to respective source connection pads on the plurality of second MOSFET dies; and second MOSFET gate connection structures connected to respective gate connection pads on the plurality of second MOSFET dies; and A second conductive wiring structure, the second conductive wiring structure comprising at least one second conductive wiring layer extending below the plurality of first MOSFET dies and below the plurality of second MOSFET dies, the second conductive wiring structure defining: a second MOSFET drain connection structure connected to respective drain connection pads on the plurality of second MOSFET dies; and A first MOSFET source connection structure is connected to corresponding source connection pads on the plurality of first MOSFET dies. 11 . The electronic device of claim 10 , the electronic package comprising an encapsulation structure at least partially encapsulating the plurality of first MOSFET dies, the plurality of second MOSFET dies, the first conductive routing structure, and the second conductive routing structure.

12. An electronic device according to any one of claims 10 to 11, wherein the electronic package comprises a first MOSFET gate connection structure, wherein the first MOSFET gate connection structure is connected to corresponding gate connection pads on the plurality of first MOSFET tube cores, and the first MOSFET gate connection structure comprises at least one conductive element formed in the first conductive wiring structure and at least one conductive element formed in the second conductive wiring structure.

13. The electronic device according to any one of claims 10 to 12, comprising a bus bar connected to the second MOSFET source connection structure and the first MOSFET drain connection structure.

14. The electronic device according to any one of claims 10 to 13, comprising a printed circuit board; The second MOSFET drain connection structure and the first MOSFET source connection structure are mounted to corresponding electronic components on the printed circuit board.

15. The electronic device according to any one of claims 10 to 14, comprising a printed circuit board; The second MOSFET source connection structure, the first MOSFET drain connection structure, the first MOSFET gate connection structure and the second MOSFET gate connection structure are mounted to corresponding electronic components on the printed circuit board.

16. A method comprising: forming a heat release layer on the carrier; Arranging a first IC die and a second IC die on the thermal release layer, the first IC die being arranged in a first orientation and the second IC die being arranged in a second orientation opposite to the first orientation, wherein a first side of the first IC die and a second side of the second IC die face the carrier, and the second side of the first IC die and a first side of the second IC die face away from the carrier; forming a mold encapsulation over the first IC die and the second IC die; forming a first conductive routing structure over the second side of the first IC die and the first side of the second IC die, the first conductive routing structure defining first conductive connections to respective contacts located on the second side of the first IC die and the first side of the second IC die; removing the carrier; A second conductive routing structure is formed on the first side of the first IC die and the second side of the second IC die, the second conductive routing structure defining a second conductive connection to corresponding contacts located on the first side of the first IC die and the second side of the second IC die.

17. The method according to claim 16, comprising: before placing the first IC die on the thermal release layer, forming a first contact element on the first IC die; Wherein arranging the first IC die on the thermal release layer includes: arranging the first IC die together with the first contact element facing the thermal release layer.

18. The method according to any one of claims 16 to 17, comprising: before placing the first IC die on the thermal release layer, forming a first contact element on the first IC die; Wherein forming the first conductive wiring structure includes: forming at least one first conductive wiring element in contact with the first contact element on the first IC die.

19. The method according to any one of claims 16 to 18, comprising: forming a vertically extending contact extending upward from the thermal release layer; Wherein forming the second conductive wiring structure includes forming a conductive connection between the vertically extending contact and a corresponding contact located on the first side of the first IC die.

20. The method according to claim 19, comprising: The vertically extending contacts extending upward from the thermal release layer are formed prior to placing the first IC die and the second IC die on the thermal release layer.

21. The method according to any one of claims 16 to 20, comprising: forming a first vertically extending contact and a second vertically extending contact extending upward from the thermal release layer; The formation of the second conductive wiring structure includes: forming (a) a first conductive connection between the first vertically extending contact and the corresponding contact located on the first side of the first IC tube core, and forming (b) a second conductive connection between the second vertically extending contact and the corresponding contact located on the second side of the second IC tube core.

22. A method according to any one of claims 16 to 21, wherein: The first IC die includes a first MOSFET die; The second Iv die comprises a second MOSFET die; Arranging the first IC die and the second IC die on the thermal release layer comprises: arranging the first IC die together with: (a) a first MOSFET gate connection pad and a first MOSFET source connection pad on the second side of the first IC die facing away from the carrier, and (b) a first MOSFET drain connection pad on the first side of the first IC die facing the carrier; as well as The second IC die is arranged together with: (a) a second drain connection pad located on the first side of the second IC die facing away from the carrier, and (b) a second gate connection pad and a second source connection pad located on the second side of the second IC die facing the carrier.

23. The method according to any one of claims 16 to 22, wherein forming the first conductive wiring structure or forming the second conductive wiring structure comprises: A stack of multiple redistribution layers (RDLs) is formed.

24. A device formed by any of the methods claimed in claims 16 to 23.

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