Substrate perforation with metal planar layer and method of making same

Abstract

Particular examples herein include post-TSV exposure processing methods and devices formed using these methods. In some examples, the methods include forming an electrically conductive and thermally conductive layer on the devices, which may serve as a power / ground connection path or a heat spreading plane in a device assembly including a number of interconnected stacked devices.

Description

Technical Field

[0001] The present disclosure relates generally to semiconductor device fabrication and assembly, and more particularly to electronic device assemblies formed using through-substrate vias (TSVs) and methods of forming such device assemblies. Background Art

[0002] A through substrate via (TSV) is a conductive feature disposed completely through a substrate, such as from the device side or "active" surface to the non-device side or "backside" surface of a silicon wafer, i.e., a "through silicon via" that can be used to provide electrical connections between individual devices. TSVs allow for a substantial increase in the density of inter-device connections and a substantial reduction in the length of inter-device connections compared to conventional connections such as wire bonding or flip chip connections. As a result, TSVs are increasingly relied upon in multi-device integration schemes to meet the seemingly endless demand for reduced power consumption and smaller electronic device packaging, such as TSVs for power delivery or inter-device communication in three-dimensional integrated circuit (3D-IC) device assembly schemes.

[0003] TSVs are typically formed within the boundaries of a die using via-first, via-middle, or via-last manufacturing schemes. Typically, in via-first and via-middle manufacturing schemes, the conductive features that will become TSVs are first formed in the device-side surface of the substrate to extend into the substrate in the thickness direction rather than extending all the way through, i.e., "blind vias." In the via-first scheme, the blind vias are formed prior to front-end-of-line (FEOL) manufacturing of individual device elements such as transistors, resistors, and capacitors. In the via-middle scheme, the blind vias are formed after the FEOL process and prior to back-end-of-line (BEOL) manufacturing of metal interconnects. Typically, in either scheme, the substrate surface of the blind via is exposed once device manufacturing is substantially complete, such as during post-manufacturing device assembly and testing operations. Exposing the substrate surface of the blind via includes removing material from the non-device-side surface of the substrate using a series of substrate thinning operations, collectively referred to as TSV exposure.

[0004] Unfortunately, process non-uniformity in blind via formation and the relatively narrow process window in which TSVs are revealed often combine to cause significant connection defects during device assembly and test operations. Such non-uniformity may include variations in blind vias formed within a device (intra-die non-uniformity), variations in blind vias formed across a substrate (intra-substrate non-uniformity), and / or variations in blind vias formed between devices formed on different substrates (inter-substrate non-uniformity). The problems associated with blind via non-uniformity are further complicated at outsourced assembly and test (OSAT) facilities that receive and assemble devices from different device manufacturers. The combined effects of process non-uniformity and resulting connection defects frequently result in failure of packaged device assemblies, thereby reducing yield and increasing overall manufacturing costs. As a result, advanced integration technologies using TSV interconnects, such as three-dimensional integrated circuits (3D-ICs), have not yet reached widespread commercial viability. Therefore, there is a need for an improved and more robust TSV reveal and post-reveal method with a wider process window that accounts for incoming variations in blind vias formed in via-first or via-middle TSV fabrication schemes. Summary of the invention

[0005] Embodiments herein include TSV post-reveal processing methods and devices formed using these methods. In some embodiments, these methods include forming an electrically conductive and thermally conductive layer on these devices, which can be used as a power / ground connection path or a heat spreading plane in a device assembly including a plurality of interconnected stacked devices.

[0006] In one embodiment, a method for forming a conductive plane around a via post protruding from a surface of a substrate is provided. The method includes forming a support layer stack, the support layer stack including a metal planar layer and a first dielectric layer disposed on the metal planar layer. Here, the metal planar layer surrounds at least a base portion of the via post, and the first dielectric layer covers an upward surface of the via post. The method further includes using a polishing process to remove a first portion of the first dielectric layer and a portion of the via post to expose a surface of the metal via. Here, the surface of the metal via is surrounded by a second portion of the first dielectric layer, and the second portion is retained after the polishing process. In some embodiments, one or more second dielectric layers may be disposed between the metal planar layer and the inactive surface of the substrate and between the metal planar layer and the base portion of the via post. In some embodiments, the substrate includes a semiconductor portion, the metal via extends through the semiconductor portion, and a dielectric liner is disposed between the metal via and the semiconductor portion and between the metal via and the one or more second dielectric layers.

[0007] In some embodiments, forming the metal plane layer includes depositing a metal support layer and recessing a surface of the metal support layer below the upward-facing surface of the via post. Recessing the surface of the metal layer may include removing a portion of the metal layer by using a polishing process, an etching process, or a combination thereof. In some embodiments, the metal plane layer forms a ground or power plane of a power distribution network to two or more interconnected devices.

[0008] In another embodiment, a method for forming uniform substrate through-holes in a microelectronic device is provided. The method may include: depositing a support layer to surround a plurality of through-hole posts protruding from a surface of a substrate; and exposing an upward surface of each of the substrate through-holes by removing the support layer and the plurality of through-hole posts. In some embodiments, the support layer is deposited to a thickness greater than the height of the plurality of through-hole posts. In some embodiments, a polishing process is used to remove the support layer. In some embodiments, the support layer is formed of a metal or a metal alloy. In some embodiments, the metal may include copper, tungsten, nickel, mixtures thereof, and / or alloys thereof. In some embodiments, the exposed through-hole surface may be formed of one or more of the same metals as the metal used to form the support layer.

[0009] In another embodiment, a microelectronic structure is provided. The microelectronic structure may include: a semiconductor substrate having a first surface and a second surface opposite to the first surface; a first dielectric layer disposed on the first surface; and a via structure disposed to pass through the first dielectric layer. Here, the via structure is at least partially disposed to pass through the semiconductor substrate, wherein at least a portion of the via structure protrudes above the first dielectric layer to define a via post. The microelectronic structure may further include a metal planar layer disposed on the first dielectric layer and a second dielectric layer disposed on the metal planar layer. In some embodiments, the via structure is formed of a conductive material, which is electrically isolated from the metal planar layer by a portion of a dielectric liner disposed between the conductive material and the metal planar layer. In some embodiments, the metal planar layer is formed of a material selected from the group consisting of copper, tungsten, nickel, mixtures thereof, and / or alloys thereof.

[0010] In some embodiments, the metal plane layer is coupled to an external power supply. In some embodiments, the metal plane layer is coupled to a ground connection path. In some embodiments, the metal plane layer forms a bias plane of a packaged electronic device. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The above and other objects and advantages of the present disclosure will become apparent upon consideration of the following detailed description in conjunction with the accompanying drawings, in which:

[0012] Figures 1A to 1F The cross-sectional view is a diagram showing a blind via formed in a through-hole first or through-hole intermediate process.

[0013] Figure 2 According to some specific examples, Figure 1A to Figure 1B A diagram of a method of one or more of the devices shown in .

[0014] FIG. 3A to FIG. 3E Based on some specific examples Figure 2 Schematic cross-sectional views of a substrate at different stages of the method described in FIG.

[0015] Figure 4 According to some specific examples, Figure 1C A diagram of a method of one or more of the devices shown in .

[0016] FIG. 5A to FIG. 5B Based on some specific examples Figure 4 Schematic cross-sectional views of a substrate at different stages of the method described in FIG.

[0017] Figure 6 and Figure 7 is a schematic cross-sectional view of a device assembly formed according to some embodiments.

[0018] The figures herein depict various embodiments of the present invention for purposes of illustration only. It should be appreciated that additional or alternative structures, systems and methods can be implemented within the principles set forth by the present disclosure. DETAILED DESCRIPTION

[0019] Embodiments provided herein are directed to methods for substantially reducing and / or eliminating processing defects in through substrate via (TSV) exposure processes and devices formed using these methods. In some embodiments, these methods can be advantageously used to substantially reduce TSV damage during one or more post-exposure chemical mechanical polishing (CMP) processes caused by incoming variations in blind vias formed using via first or via middle TSV manufacturing schemes. In some embodiments, these methods include forming an electrically conductive and thermally conductive layer on a device that can be used as a power / ground connection path or heat spreading plane in a device assembly including a plurality of interconnected stacked devices.

[0020] As used herein, the term "substrate" includes any workpiece that provides a supporting material on which components of a semiconductor device are fabricated or attached, as well as any material layers, features, and / or electronic devices formed thereon, in, or through it. Thus, the term substrate includes both a semiconductor substrate with device components fabricated thereon, and a reduced thickness semiconductor substrate, material layers, devices, and features formed thereon, in, or through a semiconductor substrate when fabrication and / or assembly is complete. It should also be understood that the term substrate as used herein further includes any material layers, devices, and features formed thereon, in, or through a semiconductor substrate at any point in the device fabrication and assembly process, regardless of whether such material layers, devices, or features are present in a finished device or assembly.

[0021] As described below, substrates herein generally have a "device side," e.g., a side on which semiconductor device elements such as transistors, resistors, and capacitors are fabricated, and a "back side" opposite the device side. The term "active surface" should be understood to include the surface of the device side of the substrate, and may include the device side surface of the semiconductor substrate and / or the surface of any material layer, device element, or feature formed thereon or extending outwardly therefrom, and / or any opening formed therein. Thus, it should be understood that the material forming the active surface may change depending on the stage of device fabrication and assembly. Similarly, the term "inactive surface" (as opposed to the active surface) includes the inactive surface of the substrate at any stage of device fabrication, including the surface of any material layer, any feature formed thereon or extending outwardly therefrom, and / or any opening formed therein. Thus, the terms "active surface" or "inactive surface" may include respective surfaces of the semiconductor substrate at the beginning of device fabrication and any surface formed during material removal (e.g., after a substrate thinning operation). Depending on the stage of device fabrication or assembly, the terms "active" and "inactive surfaces" are also used to describe the surfaces of material layers or features formed on, in, or through a semiconductor substrate, regardless of whether these material layers or features ultimately exist in the fabricated or assembled device.

[0022] Spatially relative terms are used herein to describe relationships between elements, such as between a semiconductor substrate and individual material layers, devices, and features described below. Unless a relationship is otherwise defined, terms such as "above," "above," "upward," "outward," "on," "below," "under," "below," "lower," and the like are generally used with reference to an active or inactive surface of a semiconductor substrate and / or a material layer disposed thereon. Thus, it should be understood that the spatially relative terms used herein are intended to encompass different orientations of the substrate, and unless otherwise indicated, these terms are not limited by the direction of gravity. Terms describing relationships between elements, such as "disposed on," "embedded therein," "coupled to," "connected by," alone or in combination with spatially relative terms, include both relationships within intervening elements and direct relationships without intervening elements.

[0023] Figures 1A to 1F Schematically illustrating the formation of a blind hole in the active surface 102 of the substrate 100 and the exposure of a via post 126 from the inactive surface 104 in a via first or via intermediate processing scheme ( Figure 1E ).expected Figures 1A to 1F The process illustrated in can be used in conjunction with any of the methods described herein to form through substrate vias (TSVs). Here, substrate 100 includes a semiconductor substrate 101 formed of a Group IV semiconductor (such as silicon, silicon germanium, or germanium), a III-V compound semiconductor, or a II-VI semiconductor, and any device elements formed or partially formed thereon. In some embodiments, semiconductor substrate 101 may be formed of a Group IV semiconductor (such as silicon, silicon germanium, or germanium); a III-V compound semiconductor; or a II-VI semiconductor. In some embodiments, such as a through-hole intermediate processing scheme, substrate 100 may include one or a combination of device elements, such as a transistor, a capacitor, or a resistor formed on or in active surface 102. To avoid overcomplicating the drawings, such devices are not shown here.

[0024] like Figure 1A As shown in , forming a through-hole first or through-hole middle TSV typically includes forming a high aspect ratio opening 106 in the active surface 102 of the substrate 100, wherein the opening 106 is formed to a depth D in the thickness direction (Z direction) of the substrate 100 but does not extend all the way to the inactive surface 104. In some specific examples, the depth D of the opening 106 may be between about 50 μm and about 200 μm, and the thickness T1 of the substrate 100 may be between about 600 μm and about 1000 μm.

[0025] exist Figure 1BIn the embodiment, one or more barrier layers 108 are deposited to line the walls of the opening 106 and the substrate surface, and a conductive material 116 is deposited on the barrier layer 108 to fill the remaining portion of the opening 106 and form a conductive via feature 118 ( Figure 3C In some embodiments, the conductive material 116 includes copper, copper alloy tungsten, tungsten alloy, and / or mixtures, alloys, and combinations thereof. Here, the copper alloy and tungsten alloy include a mixture of copper and / or tungsten with other metals that will form an alloy after annealing.

[0026] The barrier layer 108 may be used to prevent the conductive material 116 from undesirably diffusing into surrounding materials of the semiconductor substrate 101, provide an adhesion interface layer between the conductive material and the walls of the opening 106 and the substrate surface, and / or facilitate subsequent deposition of the conductive material 116. For example, the barrier layer 108 may include a dielectric material layer 110, one or more metal or metal nitride layers 112 deposited on the dielectric material layer 110, and a seed material layer 114 deposited on the one or more metal or metal nitride layers 112, each of which is shown in FIG. Figure 1B Examples of materials that can be used for the dielectric material layer 110 include silicon oxide (Si X O Y ), Silicon Nitride (SiN X ), silicon oxynitride (Si X O Y N Z ), silicon carbide (SiC), aluminum oxide (Al X O Y Examples of materials that can be used as the metal or metal nitride layer 112 include Ti, Ta, W, TiN, TaN, WN, and combinations thereof.

[0027] In some embodiments, the seed material layer 114 is formed of the same metal as the conductive material 116 used to fill the opening 106, for example, to facilitate the electrodeposition of the conductive material 116. For example, in some embodiments, the seed material layer 114 may include copper, a mixture of metals including copper, and / or a copper alloy. In other embodiments, the seed material layer 114 may include a different material, such as Co, Ru, Mn, Ti, Ta, W, or a combination thereof. In order to reduce visual background interference, only the dielectric material layer 110 of one or more barrier layers 108 is shown in the remaining figures.

[0028] exist Figure 1C In the embodiment, before sending the substrate 100 for further device manufacturing processing, the blanket layer of conductive material 116 is removed from the field of the active surface 102, for example by using a CMP process. Typically, when thinning the semiconductor substrate 101 in preparation for device assembly, such as in Figures 1D to 1F, the base surface 122 of each blind via 120 is exposed, which may be used in combination with any of the methods described below. Once thinned, the substrate 100 may be difficult to handle due to warping and bowing caused by the substrate thinning process and imparted by accumulated intrinsic stresses in the stack of material layers forming the active surface 102. Therefore, to facilitate substrate handling, the active surface 102 of the substrate 100 may be temporarily bonded to a second "carrier substrate" (not shown) that provides structural support during the TSV exposure and post-exposure processing methods described herein. The substrate 100 may be bonded to the carrier substrate before or after substrate thinning, and (if any) may be removed before or after singulation of the individual devices formed on the substrate 100.

[0029] Figures 1D to 1F The through hole revealing process is schematically shown as being performed after the device fabrication is substantially completed (e.g., after the interconnect layer 130 is formed in the active surface 102 of the substrate 100 during BEOL fabrication). Here, the revealing process includes a bulk material removal process to thin the substrate 100 to a thickness T2 ( Figure 1D ), and then a selective material removal process is performed to thin the substrate 100 to a thickness T3 ( Figure 1E The bulk material removal process typically includes a back grinding process and an optional CMP process that uniformly removes semiconductor material from the inactive surface 104 to a thickness T2. The thickness T2 may be selected based on the depth D of the opening 106 formed in the active surface 102 so as not to expose the substrate surface 122 of the blind via 120.

[0030] The substrate surface 122 is exposed during a selective material removal process, such as a wet etching process, a plasma (dry) based etching process, a CMP process, or a combination thereof. Typically, the semiconductor material is selectively removed from the back side of the semiconductor substrate 101 relative to the dielectric material layer 110, such that the conductive material 116 thereunder is not exposed during the exposure process. The selective material removal process protects the inactive surface 104 of the semiconductor substrate 101 from contamination that would occur if the semiconductor substrate 101 were exposed to the conductive material 116 during the exposure process. Thus, if Figure 1EAs shown in , the inactive surface 104 (recessed surface 124) of the semiconductor substrate 101 is recessed below a portion of the (previous) blind hole 120, and the portion of the blind hole protrudes above the recessed surface 124 to form a via post 126 having a height H1. The via post 126 includes a protruding portion of the through-hole feature 118 and a barrier layer 108 including a dielectric material layer 110 disposed thereon. In some specific examples, the average height H1 of the via post 126 across the inactive surface is between about 1 μm and about 10 μm, such as between about 1 μm and about 5 μm, and the difference in H1 between different via posts 126 can be in the range of about 1 μm to about 5 μm.

[0031] Typically, one or more dielectric material layers 128, such as one or more layers of silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof, are deposited on the recessed surface 124 and the via pillars 126 protruding upward from the recessed surface. The one or more dielectric material layers 128 form a passivation and / or isolation layer on the recessed surface 124 that protects the recessed surface 124 of the semiconductor substrate 101 from damage or contamination caused by exposure to atmospheric conditions and / or subsequent substrate processing operations. In some embodiments, the one or more dielectric material layers 128 are used to facilitate direct bonding device assembly methods such as those described in the following methods. Typically, the dielectric material layers 110 and 128 covering the conductive material 116 of the guide pillars 126 are removed prior to device assembly to form suitable TSV contacts and / or bonding surfaces, such as by using a planarizing CMP process. In those embodiments, the dielectric material layer 128 protects the recessed surface from contamination from conductive materials (e.g., copper) exposed during the planarization CMP process. In some embodiments, the dielectric material layer 128 includes a silicon oxide layer deposited on a silicon nitride layer, or a silicon nitride layer deposited on a silicon oxide layer. Figure 1F As shown in , the dielectric material layer 128 is deposited to a combined thickness T4 , such as between about 0.5 μm and about 3 μm, which is less than a height H1 of the guide pillar 126 measured from the recessed surface 124 .

[0032] Typically, the planarization CMP process includes pushing the inactive surface 104 of the substrate 100 against a polishing pad surface (not shown) in the presence of a polishing slurry. Pushing the inactive surface 104 against the polishing surface may include applying a force to the substrate 100 toward the polishing surface, for example in the Z direction, while moving the substrate 100 and the polishing surface relative to each other in the XY plane (orthogonal to the Z direction). Mechanical forces from the relative motion of the inactive surface 104, the polishing pad, and the slurry abrasive at the polishing interface and chemical reactions between the polishing slurry and the inactive surface 104 combine to planarize the surface, that is, to remove protruding portions of the through-hole pillars 126 from the surface. Unfortunately, the lateral force F ( Figure 1F) can contribute to undesirable guide post breakage or "guide post knockdown" of portions of the TSV and / or dielectric material layer 128. Guide post breakage and / or other defects, such as cracking of the dielectric material layer 128, often occur at or below the primary stress point 129 immediately adjacent to the recessed surface 124. Such defects can result in loss of electrical connection between devices and, therefore, device failure after assembly. Typically, such defects increase with increasing guide post height, which may be caused by increased torque around the primary stress point 129. As a result, the process window for material removal during the selective material removal process when the TSV is revealed is quite narrow, because a larger window that allows for increased variation in guide post height typically results in increased guide post breakage and cracking defects. Therefore, the method provided herein includes removing at least a portion of the guide post 126 from the inactive surface 104 while protecting the guide post 126 from the lateral polishing forces applied during the removal process.

[0033] In some embodiments, the via post 126 is protected from lateral polishing forces by one or more guide post support layers that surround the guide post 126 in the XY plane (orthogonal to the thickness direction Z), such as Figure 3C In those embodiments, lateral polishing forces that may otherwise cause undesirable breakage of individual via posts 126 are redistributed across the surface of the support layer at the polishing interface. Thus, one or more guide post support layers beneficially provide controlled and uniform planarization of both the guide post support layer and the outwardly facing surfaces of the TSV guide posts 126 disposed therein.

[0034] Figure 2 is a block diagram of a method 200 that can be used to redistribute lateral polishing forces across a surface of a support layer while forming an electrical contact or heat spreader plane for a stacked device assembly. FIG. 3A to FIG. 3E FIG. 2 is a cross-sectional view of a substrate 100 schematically illustrating various aspects of the method 200 according to some embodiments.

[0035] The method 200 generally includes forming a support layer stack 322 ( Figure 3C ) and planarize the surface of the support layer stack 322 to expose the plurality of through-hole contact surfaces 312 ( Figure 3D ). As mentioned above about Figure 1F As described, the inactive surface 104 may include a plurality of via posts 126 and one or more dielectric layers 128 disposed on the plurality of via posts 126 and on portions of the recessed surface 124 disposed between the plurality of via posts. Forming the support layer stack 322 includes forming a metal plane layer 306 ( Figure 3B ) and depositing a dielectric support layer 308 on the metal plane layer 306 ( Figure 3C ).

[0036] At step 202, the method 200 includes depositing a metal support layer 304 ( Figure 3A In some embodiments, the metal support layer 304 is formed of an electrically and / or thermally conductive material, such as a metal or a metal alloy. In some embodiments, the metal support layer 304 is formed of a material suitable for use as a stacked device assembly (such as Figure 6 The device assembly shown in FIG. 1 is formed by a conductive material of a power plane 619 or a ground plane 617 in a power distribution network of the device assembly shown in FIG.

[0037] Examples of materials that can be used to form the metal support layer 304 include the example materials described above with respect to the conductive material 116. In some embodiments, the metal support layer 304 is formed of a metal composition that is the same as or similar to the conductive material 116. In some embodiments, the metal support layer 304 can be formed directly on the dielectric material layer 128, that is, without using a barrier or adhesive film layer in between. In some embodiments, the metal support layer 304 can be formed using a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, or a combination thereof. In some embodiments, the metal support layer 304 can be formed by depositing a conductive seed layer (not shown) such as a metal or metal alloy on the dielectric material layer 128 (e.g., a CVD or PVD deposited seed layer), and depositing a bulk material of the metal support layer 304 on the seed layer using an electrodeposition process. The seed layer can be formed of a material composition that is different from or substantially similar to the bulk material. In other embodiments, the method 200 may include depositing one or more barrier layers or adhesion layers (not shown) on the dielectric material layer before depositing the metal support layer 304. Examples of suitable materials that may be used as barrier layers or adhesion layers include silicon nitride, titanium, titanium nitride, tantalum, tantalum nitride, tungsten nitride, titanium silicon nitride, tantalum silicon nitride, tungsten silicon nitride, and combinations thereof.

[0038] At step 204, method 200 includes selectively removing a portion of metal support layer 304 to form metal planar layer 306 ( Figure 3B Removing a portion of the metal support layer 304 causes the surface 318 to be recessed below the upper surface of the end portion 316 of the via post 126 ( Figure 3B ). The remaining portion of the metal support layer 304 forms a metal plane layer 306, which surrounds at least the base portion 314 of the via post 126 and is disposed on the recessed surface 124 between the via posts. Here, the base portion 314 of the via post 126 is adjacent to the recessed surface 124, and the end portion 316 is spaced apart from the recessed surface 124 by the base portion 314.

[0039] Metal planarization layer 306 may be formed at step 204 using a selective material removal process that is suitable for planarizing metal support layer 304 without removing portions of dielectric material layer 128 disposed above via post 126. In some embodiments, surface 318 may be recessed using an etching process that etches a portion of metal support layer 304 but removes relatively less dielectric material layer 128. In those embodiments, at least a portion of dielectric material layer 128 remains above the surface of via post 126. In some embodiments, the etching process is a planarization etching process using a liquid etchant, such as a spin-on etching process. In some embodiments, surface 318 may be recessed using a highly selective CMP process, such as by using a selective metal polishing slurry typically used in a damascene process. In some embodiments, the CMP process may use relatively lower polishing forces and / or relatively softer polishing pads (when compared to CMP processes typically used for planarization of dielectric materials) in order to avoid guide post breakage that may otherwise be caused by lateral forces applied during more aggressive CMP processes.

[0040] like Figure 3B , the metal plane layer 306 forms a continuous layer of electrically conductive and / or thermally conductive material across the inactive surface 104 of the substrate 100. A discontinuous plurality of openings are defined in the metal plane layer 306, wherein each of the plurality of openings has a corresponding via post 126 extending upwardly therethrough. Thus, in some embodiments, the metal plane layer 306 is formed to surround a base portion 314 of an individual via post 126 in the XY plane. In some embodiments, at least a portion of the dielectric material layer 128 disposed on the sidewalls of the via post 126 remains after the CMP process, such that the conductive via feature 118 is electrically isolated from the metal plane layer 306 by portions of the dielectric material layers 110 and 128 disposed between the conductive via feature 118 and the metal plane layer 306.

[0041] In some specific examples, the metal plane layer 306 has a thickness between about 0.1 μm and about 5 μm, such as about 0.1 μm to about 3 μm. In some specific examples, the via post 126 extends above the surface 318 of the metal plane layer 306 (in the Z direction) by a height H2 of about 0.25 μm or more, such as about 0.5 μm or more, for example in the range of about 0.25 μm to about 5 μm.

[0042] At step 206, the method 200 includes depositing a dielectric support layer 308 on the metal plane layer 306 and the via pillars 126 extending therethrough. Examples of materials that may be used to form the dielectric support layer 308 may be found in the example materials for the dielectric material layers 110 and 128 above. The dielectric support layer 308 and the metal plane layer 306 disposed thereunder surround the sidewall portions of the individual via pillars 126 in the XY direction. As shown, the dielectric support layer 308 is deposited to a thickness that surrounds the length of the end portion 316 in the XY direction. In some specific examples, the dielectric support layer 308 is deposited to a thickness of about 0.1 μm or greater, for example, between about 1 μm and about 5 μm, or about 1 μm or greater, such as between about 1 μm and about 5 μm.

[0043] At step 208, the method 200 includes using a CMP process to remove a portion of the dielectric support layer 308 and the upward-facing portion of the via pillar 126 disposed therein to form a dielectric planarization layer 310. Here, the dielectric planarization layer 310 is the portion of the dielectric support layer 308 that remains after the CMP process. As shown, the back surface 320 further includes a plurality of via contact surfaces 312 disposed through the dielectric planarization layer 310 and coplanar therewith or slightly recessed therefrom. The CMP process at step 208 may include any process suitable for planarizing a layer of dielectric material, and may be substantially similar to a CMP process used to planarize an interlayer dielectric material (such as a tetra-ethyl-ortho-silicate (TEOS) deposited oxide) in a BEOL CMP process.

[0044] At step 210, method 200 optionally includes forming a plurality of metal planar connection pads 324 ( Figure 3E ), the plurality of metal plane connection pads can be used as ground plane 617 and stacked device assembly (such as described below with respect to Figure 63. The connection pad 324 may be formed of any suitable conductive material, such as any of the example metals and metal alloys described above for the conductive material 116 and the metal support layer 304. In some embodiments, the connection pad 324 is formed of substantially the same material as the metal plane layer 306. In some embodiments, the connection pad 324 is formed by a damascene process, such as by patterning the dielectric plane layer 310, depositing a metal layer (not shown) on the patterned surface, and removing a blanket layer of the metal layer from a field of the dielectric material layer. In other embodiments, the connection pad 324 may be formed by patterning the dielectric support layer 308 and depositing the connection metal in a CMP process at step 208. In those embodiments, the CMP process used at step 208 may include several polishing stages, such as a first stage to remove a blanket layer of the connection metal and a second stage to form the back surface 320.

[0045] In some embodiments, the metal planar layer 306 can be used to tune the cumulative stress of the material layers deposited on the active surface and the inactive surface 104 in order to control the bow and warping of the substrate. Typically, the metal layer (such as the metal planar layer 306) has an intrinsic tensile stress, and the dielectric material layer has an intrinsic compressive stress. In some embodiments, the thickness of the metal planar layer 306 can be selected to offset the compressive stress in the material layers that have been deposited or are to be deposited. In some embodiments, the metal planar layer 306 can be deposited to a thickness that provides a substantially stress-neutral structure after the contact surface 312 is formed, thereby reducing undesirable stress-related warping and bowing of the substrate 101 and / or individual devices formed therefrom. In some embodiments, the thickness of the metal planar layer 306 can be adjusted so that the bow and warping are within the processing limits suitable for the direct bonding surface of different devices, such as described below with respect to Figure 6 to Figure 7 described.

[0046] Figure 4 is a block diagram of a method 400 that may be used to substantially reduce CMP-related guide post breakage and / or cracking when formation of a metal planar layer is not required, according to another embodiment. FIG. 5A to FIG. 5B 4 is a cross-sectional view of a substrate 100 schematically illustrating various aspects of the method 400 according to some embodiments. The method generally includes depositing a metal support layer 304 on the inactive surface 104 after the TSV is exposed, and simultaneously removing the metal support layer 304 and a plurality of via posts 126 using a planarization CMP process.

[0047] At step 402, the method includes depositing a metal support layer 304 on the inactive surface 104 of the substrate after the TSV reveal process. Figure 1FAs described, the inactive surface 104 after the TSV is exposed generally includes a plurality of via posts 126 extending upward from the recessed surface 124, and one or more dielectric layers 128 disposed on the plurality of via posts 126 and the recessed surface 124. The one or more dielectric layers 128 provide an isolation layer and / or a diffusion barrier that protects the recessed surface 124 of the semiconductor substrate 101 from undesired contamination and / or material diffusion from the metal support layer 304. In some embodiments, the metal support layer 304 is formed directly on the dielectric material layer without using a barrier and / or adhesion material layer. In other embodiments, the method 400 includes depositing one or more barrier and / or adhesion layers (not shown) on the dielectric material layer before depositing the metal support layer 304. Examples of suitable materials that can be used as barrier and / or adhesion layers are described above with respect to the method 200. In some embodiments, the metal support layer 304 is deposited to a thickness greater than the height H1 of the via post 126, such as Figure 5A , such that the metal support layer 304 surrounds each of the via posts 126 along the length of each of the via posts 126 (ie, in the Z direction).

[0048] At step 404, the method 400 includes simultaneously removing the metal support layer 304 and the via posts 126 disposed therein using a planarization CMP process. In some embodiments, the metal support layer 304 and the plurality of via posts 126 are simultaneously removed using a low selectivity CMP process that simultaneously planarizes the surface of the metal support layer 304 and the upward-facing surfaces of the via posts 126 disposed therein. For example, in some embodiments, the CMP process has a material removal rate selectivity of between 3:1 and 1:3 for one or more or each of the metal of the metal support layer 304 and the material forming the dielectric material layer 128, such as between about 2:1 and 1:2, between about 3:2 and 2:3, between about 4:3 and about 3:4, between about 5:4 and about 4:5, or about 1:1. In embodiments where dielectric material layer 128 includes a silicon oxide layer and a silicon oxide layer, the CMP process may have a material removal rate selectivity between about 2:1 and about 1:2, such as between about 3:2 and 2:3, between about 4:3 and about 3:4, or between about 5:4 and about 4:5, or about 1:1.

[0049] In some embodiments, the metal support layer 304 and the plurality of via posts 126 are removed simultaneously using two or more different selective polishing processes in an alternating sequence, including removing a portion of the metal support layer 304 and a portion of the via posts 126. For example, the sequence may include an alternating sequence of a metal selective CMP process and a dielectric selective CMP process. The material removal rate of the metal selective process for the metal support layer 304 may be higher than the material removal rate for the dielectric material layer 128, and the material removal rate of the dielectric selective process for the dielectric material layer 128 may be higher. In those embodiments, the alternating sequence may be repeated until the metal support layer 304 is removed from the field surface of the dielectric layer 128, and the via contact surface 312 of the via feature disposed in the metal support layer is substantially coplanar with the field surface or slightly recessed below the field surface.

[0050] The above article about Figure 2 and Figure 4 The described embodiments can be advantageously used to significantly reduce CMP-related breakage and / or cracking of the via post 126 during post-exposure processing. The support layer used in each of these methods redistributes lateral polishing forces from individual via posts 126 to a larger surface area of ​​the support layer surrounding the via post 126 while providing mechanical support to the via post 126 in the XY direction. During the CMP process described in the steps above, the polishing force is distributed across the surface of the support layer at the polishing interface, thereby reducing shear stress that would otherwise be imparted to the exposed via post sidewalls in the absence of the support layer. Lateral support is provided by the support layer surrounding the via post 126 in the XY plane to provide a mechanical reaction force (e.g., bracing) relative to the lateral polishing force applied to the via post 126, thereby reducing the shear stress at the stress point 129 ( Figure 1F ) causes a torque.

[0051] By redistributing polishing forces and simultaneously providing lateral support to the TSV guide pillars 126, the incidence of guide pillar breakage and or cracking can be reduced substantially independent of guide pillar height. Thus, the above-described method can be advantageously used to increase the amount of material removed from a semiconductor substrate during a selective material removal process, such as Figure 1E , without increasing the incidence of defects associated therewith. This increased process window can be used to accommodate unknown variations in the depth of blind vias formed in a via first or via intermediate process.

[0052] Figure 6 to Figure 7Schematic cross-sectional views of example device assemblies (e.g., three-dimensional integrated circuits (3D-ICs)) that may be formed using the methods described above. As shown, each of the device assemblies includes a plurality of devices stacked upon one another in a face-to-back bonding integration scheme. In other embodiments, the device assemblies may be formed using a face-to-face bonding scheme or a combination of face-to-back and face-to-face bonding integration schemes. In some embodiments, the active and inactive dielectric and / or metal surfaces of the individual devices are directly bonded to one another in an adhesive-free wafer-to-wafer, chip-to-wafer, or chip-to-chip assembly process. Examples of suitable direct bonding techniques that may be used to form device assemblies include (direct bonding interconnect) or Direct Interconnect technology, available from Xperi Holding, Inc. of San Jose, California. Figure 6 to Figure 7 Other embodiments of the device assemblies depicted in FIG. 1 may be formed using any suitable direct, hybrid, or conventional methods of forming electrical connections between TSV features, connection pads, and / or metal plane contacts of individual devices.

[0053] exist Figure 6 In FIG. 6 , device assembly 600 includes a plurality of devices 600a-600c disposed in a stacked arrangement and directly bonded to each other in a face-to-back bonding integration scheme. As shown, each of devices 600a-600c includes a semiconductor substrate 101 having an active side 602 and an opposite inactive side 604. Figure 6 6, active side 602 is shown in a face-down orientation and each includes a device element 605, such as a transistor, capacitor, resistor, and / or other active components formed therein or thereon. Devices 600a-600c each include a plurality of metal interconnect layers 130 disposed on active side 602, wherein metal interconnect layers 130 include regional and global interconnects for connecting device elements 605 to each other and to circuits external to devices 600a-600c (e.g., to other devices in device assembly 600). Base device 600a and intermediate device 600b in device assembly 600 each include a plurality of TSV features 118 formed through semiconductor substrate 101 in a via first or via intermediate fabrication process.

[0054] Here, TSV features 118 include signal TSVs 607 and power TSVs 609. Signal TSVs 607 communicatively connect individual device elements 605 to each other and / or to external circuits to facilitate the exchange of information therebetween. Power TSVs 609 connect each of the individual devices to a power plane 619 or a ground plane 617 of a power delivery network (PDN) 615. Here, the vertical arrangement of devices 600a-600c, and the shorter connection paths provided by the signal TSVs 607 disposed therethrough, substantially reduce data transfer time between active components of each of the devices. The shorter data transfer paths thus provide faster processing speeds and reduced power consumption compared to other data transfer methods such as wire bond interconnects.

[0055] The diameter of the power TSV 609 is typically larger than the diameter of the signal TSV 607 in order to accommodate the higher current flowing therethrough, for example, by reducing the resistance of the power delivery path. The relatively large size of the power TSV 609 means that it occupies valuable surface area within the individual devices 600a-600c, with the lower device 600a having a larger area dedicated to the power TSV 609 than the upper device 600b, i.e., to accommodate a direct power delivery path from the power plane 619 to the devices positioned above it. Despite the relative difference in size between the power TSV 609 and the signal TSV 607, the power TSV 609 typically has a smaller cross-sectional area than the cross-sectional area of ​​other power delivery connections, such as traces or wire bonds. Therefore, the resistance per unit length of a series of power TSVs 609 used to connect a power supply to an upper device in a multi-device stack can cause considerable power dissipation, undesirable heat generation, and undesirable voltage variations between devices.

[0056] Figure 6 The device assembly 600 shown in provides a current path, such as a ground connection path, through one or more metal plane layers 306 formed on corresponding inactive surfaces of individual devices 600a to 600b according to the methods described above. Each of the upper devices 600b to 600c is connected to a metal plane layer 306 formed on the inactive side 604 of the device below, for example, via a plurality of connection pads 324, and the metal plane layer 306 is connected to a ground plane 617 using an external connection path 621 (such as, a side trace or a plurality of wire bonding connections (not shown)). The metal plane layer 306 can be advantageously used to reduce the number of power TSVs 609 and / or increase the current capacity of the power delivery network 615 while reducing power consumption. In other specific examples, the device assembly includes a plurality of ground TSVs 611 connected to the ground plane 617, such as Figure 7As shown in FIG. 6 , the metal plane layer 306 is connected to the power plane 619 via the external connection path 621 .

[0057] In some embodiments, one or more of the metal plane layers 306 can be used as a bias plane that is configured to provide an independently controllable bias voltage to a device positioned thereon. In one example, one or more of the metal plane layers are electrically connected to an independently controllable bias voltage generator that is configured to provide a bias voltage thereto. In some embodiments, such as Figure 7 As shown in , one or more of the metal plane layers 306 may function as a heat spreader that redistributes heat generated and / or concentrated in localized areas of the active surface 602 disposed above or below the metal plane layers 306 .

[0058] Figure 7 A schematic cross-sectional view of a device assembly 700 is depicted, which features a plurality of devices 700a-700c disposed in a stacked, face-to-back arrangement. Power is delivered to each of the devices 700b-700c via a power TSV 609 and a ground TSV 611 formed through each of the lower devices 700a-700b, wherein the power TSV 609 is connected to a power plane 619 and one or more ground TSVs are connected to a ground plane 617. Here, each of the metal plane layers 306 of the devices 700a-700b is configured to act as a heat spreader to redistribute heat generated from an active surface 602 of a corresponding device and / or an adjacent device disposed thereon. As shown, each of the metal plane layers 306 is in thermal communication with a thermal TSV (TTSV) 703 (e.g., a through-last TSV formed of a thermally conductive material) that connects the metal plane layer 306 to a cooling system such as a heat sink 705. Inter-device heat spreaders may advantageously be used to remove heat from between devices in a stacked device assembly, thereby potentially increasing the number of devices that may be included in such an arrangement.

[0059] The methods, devices, and device assemblies discussed above are intended to be illustrative and not limiting. One of ordinary skill in the art will appreciate that individual aspects of the methods discussed herein may be omitted, modified, combined, and / or rearranged without departing from the scope of the invention. For example, in some embodiments, a device assembly may include one or more metal plane layers 306, each configured to function as a device indirect ground or power plane, such as Figure 6 , and one or more metal plane layers 306 configured to act as heat spreaders, such as Figure 7 More generally, the above disclosure is intended to be illustrative and not limiting. Only the following claims are intended to set limits on the scope of the present invention.

Claims

1. A method for forming a conductive plane around a via post protruding from a surface of a substrate, comprising: forming a support layer stack comprising a metal planar layer surrounding at least a base portion of the via post and a first dielectric layer disposed on the metal planar layer covering an upward-facing surface of the via post; and A portion of the first dielectric layer and a portion of the via post are removed by using a polishing process to expose a surface of the metal via surrounded by a remaining portion of the first dielectric layer.

2. The method of claim 1, wherein one or more second dielectric layers are disposed between the metal plane layer and the inactive surface of the substrate and between the metal plane layer and the base portion of the via post.

3. The method of claim 2, wherein the substrate includes a semiconductor portion, the metal via extends through the semiconductor portion, and a dielectric liner is disposed between the metal via and the semiconductor portion and between the metal via and the one or more second dielectric layers. The method of claim 1 , wherein the metal support layer comprises copper, tungsten, nickel, or a combination thereof.

5. The method of claim 1, wherein forming the metal planarization layer comprises depositing a metal support layer and recessing a surface of the metal support layer below the upward facing surface of the via post. 6 . The method of claim 1 , wherein recessing the surface of the metal layer comprises removing a portion of the metal layer by using a polishing process, an etching process, or a combination thereof.

7. The method of claim 1, wherein the metal plane layer forms a ground or power plane to a power distribution network of two or more interconnected devices.

8. A method for forming uniform through-substrate holes in a microelectronic device, comprising: depositing a support layer to surround a plurality of via posts protruding from a surface of the substrate, wherein the support layer is deposited to a thickness greater than a height of the plurality of via posts; and An upward-facing surface of each of the through-substrate vias is exposed by removing the support layer and the plurality of via posts.

9. The method of claim 8, wherein the support layer is formed of metal.

10. The method of claim 9, wherein the metal is copper, tungsten, nickel or a combination thereof. The method of claim 10 , wherein the exposed surface comprises the metal.

12. The method of claim 9, wherein the support layer is removed using a polishing process.

13. The method of claim 12, wherein the polishing process has a removal rate selectivity between about 2:1 and 1:2 for respective materials forming the support layer and the via posts.

14. A microelectronic structure comprising: A semiconductor substrate having a first surface and a second surface opposite to the first surface; A first dielectric layer disposed on the first surface; a via structure disposed through the first dielectric layer and at least partially through the semiconductor substrate, wherein at least a portion of the via structure protrudes above the first dielectric layer to define a via post; a metal plane layer disposed on the first dielectric layer; and A second dielectric layer is disposed on the metal plane layer.

15. The microelectronic structure of claim 14, wherein the via structure comprises a conductive material.

16. The microelectronic structure of claim 14, wherein the conductive material of the via structure is electrically isolated from the metal planar layer by a portion of a dielectric liner disposed between the conductive material of the via structure and the metal planar layer.

17. The microelectronic structure of claim 15, wherein the metal planarization layer comprises copper, tungsten, nickel, or a combination thereof.

18. The microelectronic structure of claim 14, wherein the metal planar layer is coupled to an external power supply.

19. The microelectronic structure of claim 14, wherein the metal plane layer is coupled to a ground connection path.

20. The microelectronic structure of claim 14, wherein the metal planar layer forms a biasing plane for encapsulating electronic devices.

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