Feedback topology for amplifier gain reduction

Abstract

Feedback methods and apparatus to reduce gain in RF amplifiers, particularly LNAs, are disclosed. The described method is based on providing a feedback path from the drain terminal of one of the LNA cascode transistors to the source terminal of the LNA input transistor, or from the gate terminal of the input transistor to the source terminal of the LNA input transistor. The disclosed methods may be combined with each other or with existing feedback methods to provide further flexibility and improved trade-off in designing LNAs for applications with different requirements.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. patent application serial number 17 / 804,470 filed on May 27, 2022, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] The present disclosure relates to methods and apparatus for amplifier gain reduction, and more particularly to feedback topologies implemented in radio frequency (RF) amplifiers (e.g., low noise amplifiers (LNAs) or power amplifiers) to provide greater flexibility in designing RF circuits having such amplifiers. The flexibility so provided results in an overall improved performance tradeoff. Background Art

[0004] Multi-stage gain LNAs are very commonly used in applications such as cellular RF front ends (RFFEs). Such LNAs are often required to support multiple gain states during operation. This needs to be done while meeting several performance requirements other than gain, such as noise figure (NF), input return loss (S11), output return loss (S22), reverse isolation (S12), input third order intercept point (IIP3), stability, etc. Depending on the application, the requirements imposed on each of these parameters may vary significantly.

[0005] Typically, changing the amplifier gain in an RF amplifier such as an LNA can be achieved in a variety of ways, such as attenuation, deQing the load (reducing the quality factor of the load), reducing current or bias, and feedback, each with its own advantages and disadvantages.

[0006] Known resistive feedback topologies provide a reduction in gain by providing a programmable resistive path from the output of an amplifier device (e.g., the drain terminal of a transistor in an amplifier) ​​to the input of the amplifier device (e.g., the gate terminal of an input transistor). Changing the resistor value in the feedback path allows gain adjustment. However, in this approach, and when operating at a reduced gain, input-output isolation may be reduced, and therefore, the S12 parameter (power transferred from the output port to the input port, also referred to as reverse transfer or isolation) will generally be significantly affected and may not meet the corresponding stringent requirements, and may result in undesirable oscillation conditions or instability.

[0007] In view of the above, when implementing an LNA (or more generally, an amplifier such as a power amplifier), providing multiple gain levels for a wide range of RF applications while maintaining overall performance requirements (e.g., also meeting S12 requirements) presents a design challenge. Summary of the invention

[0008] The disclosed method and apparatus address the above challenges by providing further flexibility in designing amplifiers for various RF applications having different performance requirements.

[0009] According to a first aspect of the present disclosure, a radio frequency (RF) amplifier is provided, comprising: one or more transistors connected in series, wherein a first transistor of the one or more transistors is configured to receive a first input signal from a first input terminal; and a first feedback path comprising a first programmable resistor, the first feedback path coupling a drain terminal of a transistor of the one or more transistors to a source terminal of a first transistor of the one or more transistors.

[0010] According to a second aspect of the present disclosure, a radio frequency (RF) amplifier is provided, comprising: one or more transistors connected in series, wherein a first transistor of the one or more transistors is configured to receive a first input signal from a first input terminal; and a first feedback path comprising a first programmable resistor, the first feedback path coupling a gate terminal of the first transistor to a source terminal of the first transistor.

[0011] According to a third aspect of the present disclosure, a method for reducing the gain in a radio frequency (RF) amplifier is disclosed, the method comprising: providing one or more transistors connected in series; applying an input signal to the gate terminal of a first transistor among the one or more transistors; providing a first feedback path including a first programmable resistor, the first feedback path coupling the drain terminal of a transistor among the one or more transistors to the gate terminal of the first transistor; providing a second feedback path including a second programmable resistor, the second feedback path coupling the drain terminal of the transistor to the source terminal of the first transistor; providing a third feedback path including a third programmable resistor, the third feedback path coupling the gate terminal of a first transistor among the one or more transistors to the source terminal of the first transistor among the one or more transistors; selectively turning on and off one or more of the first feedback path, the second feedback path and the third feedback path based on set requirements, and also adjusting the gain by changing one or more of the first programmable resistor, the second programmable resistor and the third programmable resistor.

[0012] Other aspects of the disclosure are provided in the description, drawings and claims of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 A low noise amplifier (LNA) implementing feedback is shown.

[0014] Figures 2 to 3 An exemplary LNA according to various embodiments of the present disclosure is shown.

[0015] Figure 4 A table summarizing the performance of an exemplary feedback method according to an embodiment of the present disclosure is shown.

[0016] FIG. 5A to FIG. 5D An exemplary LNA according to an embodiment of the present disclosure is shown.

[0017] Figure 5E Shows the summary based on Figure 5D An exemplary table of states of the feedback path of the switch states in FIG.

[0018] Figure 6 An exemplary LNA according to an embodiment of the present disclosure is shown.

[0019] FIG. 7A to FIG. 7D An exemplary switched-input LNA according to an embodiment of the present disclosure is shown.

[0020] FIG. 8A to FIG. 8C An exemplary multiple-input LNA according to an embodiment of the present disclosure is shown.

[0021] Fig. 9A A multiple-input LNA is shown.

[0022] Figures 9B to 9C An exemplary multiple-input LNA according to an embodiment of the present disclosure is shown.

[0023] Like reference numbers and designations in the various drawings indicate like elements. DETAILED DESCRIPTION

[0024] Figure 1An LNA (100) is shown that includes cascode transistors (T1, T2), an input terminal (IN1), an output terminal (OUT), and a programmable resistor (R1). The LNA (100) also includes direct current (DC) blocking capacitors (C1, C2, C3), an inductor (L1) coupling the input terminal (IN1) to the gate terminal of the transistor (T1), an inductor (Ls) coupling the source terminal of the transistor (T1) to ground, and an inductor (Ld) coupling a power supply (VDD) to the drain terminal of the transistor (T2). The transistors (T1, T2) are arranged in a common source configuration and a common gate configuration, respectively. The gain of the LNA (100) can be adjusted by changing the programmable resistor (R1). The smaller the resistance value of the programmable resistor (R1), the greater the negative feedback (or loop gain), and therefore, the lower the amplifier gain obtained. As previously mentioned, when changing the feedback to adjust to the desired gain, other performance parameters may be undesirably affected. As an example, when operating at reduced gain (ie, more feedback), reverse isolation (S12) may be affected and no longer meet the requirements.According to embodiments of the present disclosure, capacitors (C1, C3) may also be used for input and output matching.

[0025] Next, an exemplary embodiment of the present disclosure will be introduced. As will be discussed in more detail, such an embodiment provides greater flexibility in the design trade-offs required for different applications with different performance requirements.

[0026] Figure 2 An exemplary LNA (200) according to an embodiment of the present disclosure is shown. The operating principle of the LNA (200) is similar to that of Figure 1 The operation principle of the LNA (100) described above is similar to that described above, except that the feedback path through the programmable resistor (R2) is now from the drain terminal of the transistor (T2) to the source terminal of the transistor (T1). In accordance with the teachings of the present disclosure, when the gain is reduced, this topology is used and is used together with Figure 1 Compared with the case of the LNA (100) of FIG. 1 , the degradation of the reverse isolation (S12) and NF is small, and other performance parameters are not degraded. This will become clearer through some examples later.

[0027] Figure 3 FIG. 2 shows an exemplary LNA (300) according to another embodiment of the present disclosure. The working principle of the LNA (300) is similar to that of FIG. Figure 1 The LNA (100) described operates similarly except that the feedback path through the programmable resistor (R3) is now from the gate terminal of the transistor (T1) to the source terminal of the transistor (T1). A capacitor (C4) between the variable resistor (R1) and the inductor (Ls) is also shown.

[0028] Figure 4 An exemplary table (400) summarizing disclosed feedback topologies and Figure 1 The second column of table (400) shows exemplary performance parameter values ​​without applying feedback. On the other hand, columns 3 to 5 show the performance parameter values ​​of the feedback topologies shown in FIG. Figures 1 to 3 Example performance parameter values ​​for the feedback topology shown in FIG. As shown, when no feedback is implemented, the gain is 19.5 dB. As shown in Table (400), by implementing Figures 1 to 3 The feedback topology shown in , the gain is reduced to 14dB. Now comparing the performance parameter values ​​in the third and fourth columns, it can be noted that by implementing Figure 2 The feedback topology, with Figure 1 Compared to the feedback topology shown in , this will result in a smaller reduction in NF and reverse isolation (S12). But this comes at the expense of slightly reduced improvements in IIP3, output return loss (S22), and input return loss (S11). Furthermore, comparing the fifth column with the third column again, it can be concluded that Figure 3 The feedback topology provides improved reverse isolation (S12) over other feedback topologies. Figure 1 This comes with the caveat of greater degradation of NF and slightly greater degradation of (S11, S22) compared to the feedback topology of . It should be appreciated that the teachings of the present disclosure provide more trade-off flexibility and improved performance trade-offs when designing for applications with a wider range of requirements by providing the advantage of more design options. Figure 4 The performance parameter values ​​shown in the table (400) are example numbers, and different implementations may result in different numbers.

[0029] In some embodiments, Figures 1 to 3 The feedback topologies shown in can be combined to provide further design options and flexibility. Figure 5A An exemplary LNA (500A) according to an embodiment of the present disclosure is shown. It can be seen that the previous Figure 1 and Figure 2 A combination of the feedback topologies shown in , wherein a first feedback path is provided by coupling the drain terminal of a transistor (T2) to the gate terminal of a transistor (T1) via a programmable resistor (R1) via a DC blocking capacitor (C1), and a second feedback path is provided by coupling the drain terminal of a transistor (T2) to the source terminal of a transistor (T1) via a programmable resistor (R2) via a DC blocking capacitor (C1'). Exemplary performance parameter values ​​of the feedback topology are shown in FIG. Figure 4As shown in the sixth column of the table (400) of FIG. 4 , it can be seen that the combination of the two previously shown feedback topologies disclosed will provide improved IIP3 and improved input return loss (S11), which would not be the case when each feedback topology is implemented separately. In addition, it can be seen that in Figure 5A In the feedback topology shown in , for example, with Figure 1 The reverse isolation (S12) also experiences less degradation compared to the case of the feedback topology.

[0030] Figure 5B FIG. 5 shows an exemplary LNA (500B) according to another embodiment of the present disclosure. Figure 5A The LNA (500A) is similar to that of FIG. 1 , except that the two feedback paths through the resistors ( R1 , R2 ) now share a DC blocking capacitor ( C1 ′). This has the benefit of taking up less space in the overall design (three DC blocking capacitors instead of four in total).

[0031] Figure 5C FIG. 5 shows an exemplary LNA (500C) according to another embodiment of the present disclosure. It can be seen that the LNA (500C) is implemented Figures 1 to 3 A combination of feedback topologies, wherein a first feedback path is provided by coupling the drain terminal of a transistor (T2) to the gate terminal of a transistor (T1) via a programmable resistor (R1) via a DC blocking capacitor (C1'), a second feedback path is provided by coupling the drain terminal of a transistor (T2) to the source terminal of a transistor (T1) via the same DC blocking capacitor (C1'), and a third feedback path is provided by coupling the gate terminal of a transistor (T1) to the source terminal of a transistor (T1) via a programmable resistor (R3) and a DC blocking capacitor (C4). Figure 4 The seventh column of the table (400) shows exemplary performance parameter values ​​for this feedback topology. As shown, such a feedback topology can be used in applications where NF and reverse isolation (S12) are more critical than other performance parameters.

[0032] As described above, depending on the application and related requirements, one or a combination of two or more of the disclosed feedback topologies can be implemented. Therefore, another embodiment can also be envisioned, in which one or more feedback paths can be selectively turned on or off according to the priority and importance associated with various performance parameters in a specific gain mode of the amplifier for a specific application. Figure 5D An exemplary LNA (500D) according to an embodiment of the present disclosure is shown. Figure 5D The working principle of LNA (500D) and Figure 5CThe operating principle of the LNA (500C) described is similar, except that the feedback paths through the programmable resistors (R1, R2, R3) can be switched by switches (S1, S2, S3), respectively. Depending on the state of the switches (S1, S2, S3), zero, one, or more of the feedback paths can be activated. This will give designers greater flexibility to use nearly the same design to handle different applications with conflicting requirements.

[0033] Figure 5E An exemplary table (500E) is shown showing the state of the switches (S1, S2, S3) Figure 5D , the state of the feedback path shown in . As an example, when switches (S1, S2) are in the on state (closed) and switch (S3) is in the off state (open), the feedback path through programmable resistors (R1, R2) is in the active state, while the feedback path through programmable resistor (R3) is in the inactive state. Figure 4 , and continuing with the same example, this feedback topology is suitable for applications requiring better reverse isolation (S12). However, in this case, and for the same application, the resulting NF (e.g., 4.2 dB) may not be sufficient to meet the corresponding requirements. To overcome this problem, the switch (S3) can be controlled to be in the on state (closed) to achieve an improved NF (e.g., 1.9 dB) while maintaining the reverse isolation (S12) at an acceptable value, as shown in FIG. Figure 4 As shown in table (400).

[0034] Figure 6 An exemplary LNA (600) according to yet another embodiment of the present disclosure is shown. This is an embodiment showing a case where the disclosed teachings are applied to an LNA comprising multiple branches. The LNA (600) comprises a first branch having transistors (T1, T2) and a second branch having transistors (T3, T4). Figure 6 The working principle of LNA (600) is as follows Figure 5D The operating principle of the LNA (500D) described above is similar to that of the LNA (600), except that the LNA (600) includes two branches instead of one. The disclosed teachings can be applied to LNAs having any number of branches.

[0035] The disclosed method and apparatus can also be applied to implement an arrangement for switching LNAs. Fig. 7AAn exemplary LNA (700A) according to an embodiment of the present disclosure is shown. The LNA (700A) is a switching LNA that receives one of the inputs (IN1, ..., INn) according to a selected input frequency band, where n is an integer greater than 1. The selection of the input frequency band is performed by a frequency band switch (701). The remaining circuitry downstream of the frequency band switch (701) is similar to Figure 2 The LNA (200) is similar to the LNA (200), except that the feedback path through the programmable resistor (R2) can be turned on or off by the switch (S2).

[0036] Figure 7B An exemplary LNA (700B) according to an embodiment of the present disclosure is shown. Figure 7B The working principle of LNA (700B) and Fig. 7A The LNA (700A) operates similarly to that described above, except that the switch (S2) is now implemented closer to the drain terminal of the transistor (T2) rather than closer to the source terminal of the transistor (T1). The location of the switch (S2) is set according to the desired isolation and the overall layout of the circuit. In another embodiment, two switches may be implemented within the feedback path, one switch closer to the drain terminal of the transistor (T2) and the other switch closer to the source terminal of the transistor (T1) to improve isolation.

[0037] Figure 7C An exemplary LNA (700C) according to an embodiment of the present disclosure is shown. This is another example showing the application of the disclosed feedback topology in a switching LNA. Figure 7B Similar to the embodiment of the present invention, the LNA (700C) receives one of the inputs (IN1, IN2, IN3) according to the desired frequency band selected by the frequency band switch (701). The remaining circuitry downstream of the frequency band switch (701) is similar to Figure 3 The LNA (300) is similar to the LNA (300), except that the feedback path through the programmable resistor (R3) can be turned on or off by the switch (S3).

[0038] Fig.7D An exemplary LNA (700D) according to an embodiment of the present disclosure is shown. Fig.7D The working principle of LNA (700D) and Figure 7CThe LNA (700C) operates similarly to that described above, except that the switch (S3) is now implemented closer to the gate terminal of the transistor (T1) rather than closer to the source terminal of the transistor (T1). The location of the switch (S3) is set according to the desired isolation and the overall layout of the circuit. In another embodiment, two switches may be implemented in the feedback path, one switch closer to the gate terminal of the transistor (T1) and the other switch closer to the source terminal of the transistor (T1) to improve isolation.

[0039] The disclosed apparatus and method can also be applied to multi-input LNAs. Fig. 8A An exemplary LNA (800A) according to another embodiment of the present disclosure is shown. The LNA (800A) has two inputs (IN1, IN1') that receive respective inputs during operation. The cascode transistors (T1', T2') are mirror images of their corresponding cascode transistors (T1, T2). Likewise, the components (L1', R1', C2', C4', S3') are mirror images of their corresponding components (L1, R1, C2, C4, S3). The operating principle of the LNA (800A) is similar to that of the Figure 2 The LNA (200) described above operates similarly, except that the LNA (800A) has two functionally identical inputs, each receiving a respective input signal.

[0040] Figure 8B An exemplary LNA (800B) according to another embodiment of the present disclosure is shown. The functionality of the LNA (800B) is similar to that described with respect to the LNA (800A), except that the cascode transistor (T2) is now shared between the two inputs IN1 and IN1', rather than having a separate cascode transistor for each input. The benefit of this structure is that it saves more space on the chip by not requiring additional cascode transistors, and avoids output loading when many inputs are required.

[0041] Figure 8C An exemplary LNA (800C) according to another embodiment of the present disclosure is shown. The function of the LNA (800C) is similar to that of the Fig. 8A The LNA (800A) described above functions similarly, except that the inductor (Ls) is no longer shared between the two inputs, but each input now has its own dedicated independent inductor (Ls, Ls').

[0042] The disclosed feedback topology may be equally implemented in an LNA with any number of inputs, thereby implementing any feedback method or any combination of feedback methods.

[0043] According to the teachings of the present disclosure, in a multi-input LNA, each input can be used one at a time. Therefore, the feedback path can be shared between the various inputs. Next, the content followed by the implementation according to the present disclosure and the content that proves such a concept will be described in detail.

[0044] Fig. 9A An exemplary LNA (900A) according to an embodiment of the present disclosure is shown. It can be seen that the LNA (900A) has two inputs (IN1, IN1'), and the feedback path from the drain terminal of the transistor (T2) to the gate terminal of the transistor (T1) is shared between the two inputs. When the input (IN1) is working, the switch (S11) is in the on state (closed), and the switch (S11') is in the off state (open). Therefore, the feedback path is used by the input (IN1). On the other hand, when the input (IN2) is working, the switch (S11) is in the off state (open), and the switch (S11') is in the on state (closed), and therefore the feedback path is used by the input (IN1'). The benefit of sharing feedback between the inputs of a multi-input LNA is to save more space on the chip. According to an embodiment of the present disclosure, when the LNA (900A) is operating in a high gain mode, the switches (S11, S11') are in the off state (open).

[0045] Fig. 9B An exemplary LNA (900B) according to an embodiment of the present disclosure is shown. The LNA (900B) has two inputs (IN1, IN1'), and a feedback path from the drain terminal of the transistor (T2) to the source terminal of the transistor (T1) is shared between the two inputs. When the switch (S2) is in the on state (closed), the feedback path is connected. Either of the inputs (IN1, IN1') can use such a feedback path, depending on which input is working.

[0046] Fig. 9C An exemplary LNA (900C) according to another embodiment of the present disclosure is shown. The LNA (900C) has two inputs (IN1, IN1'), and a feedback path from the gate terminal of the transistor (T1) to the source terminal of the transistor (T1) is shared between the two inputs. When the input (IN1) is working, the switch (S31) is in the on state (closed), and the switch (S31') is in the off state (open). Therefore, the feedback path is used by the input (IN1). On the other hand, when the input (IN2) is working, the switch (S31) is in the off state (open), and the switch (S31') is in the on state (closed), and therefore, the feedback path is used by the input (IN1') at this time.

[0047] The above public 9A to 9CThe related teachings can be implemented in an LNA having any number of inputs.

[0048] In summary, for purposes of exemplary illustration, the embodiments shown in the present disclosure include two cascode transistors, one arranged in a common source configuration and the other arranged in a common gate configuration. However, those skilled in the art will appreciate that the disclosed teachings are equally applicable to amplifiers having more than two transistors and cascode transistors arranged in different configurations. Furthermore, some embodiments may include only one transistor.

[0049] The disclosed teachings as described above and shown in the accompanying drawings can also be applied to other types of RF amplifiers besides LNAs.

[0050] The term "MOSFET" as used in this disclosure includes any field effect transistor (FET) having an insulated gate whose voltage determines the conductivity of the transistor, and includes insulated gates having metal or metalloid, insulator and / or semiconductor structures. The terms "metal" or "metalloid" include at least one electrically conductive material (e.g., aluminum, copper or other metal, or highly doped polysilicon, graphene or other electrical conductors), "insulator" includes at least one insulating material (e.g., silicon oxide or other dielectric materials), and "semiconductor" includes at least one semiconductor material.

[0051] The term "radio frequency" (RF) as used in this disclosure refers to oscillation frequencies in the range of about 3 kHz to about 300 GHz. This term also includes frequencies used in wireless communication systems. RF frequencies can be the frequency of electromagnetic waves, or the frequency of alternating voltage or current in an electrical circuit.

[0052] With respect to the drawings cited in this disclosure, the dimensions of the various elements are not drawn to scale; some dimensions are significantly exaggerated in the vertical and / or horizontal directions for clarity or emphasis. In addition, references to positioning and orientation (e.g., "top," "bottom," "above," "below," "side," "vertical," "horizontal," etc.) are relative to the example drawings and are not necessarily absolute positioning or orientation.

[0053] Various embodiments of the present invention can be implemented to meet a wide variety of specifications. Unless otherwise specified above, the selection of suitable component values ​​depends on design choices. Various embodiments of the present invention can be implemented in any suitable integrated circuit (IC) technology (including but not limited to MOSFET structure) or in hybrid or discrete circuit form. Integrated circuit implementations can be manufactured using any suitable substrate and process, including but not limited to standard bulk silicon, high resistivity bulk CMOS, silicon on insulator (SOI) and silicon on sapphire (SOS). Unless otherwise specified above, embodiments of the present invention can be implemented using other transistor technologies, such as bipolar, BiCMOS, LDMOS, BCD, GaAs HBT, GaN HEMT, GaAs pHEMT and MESFET technology. However, embodiments of the present invention are particularly useful when manufactured using a process based on SOI or SOS, or when manufactured using a process with similar characteristics. Manufacturing in CMOS using SOI or SOS processes enables circuits to have low power consumption, the ability to withstand high power signals during operation, due to FET stacking, good linearity, and high frequency operation (i.e., up to and exceeding 300GHz radio frequency). Monolithic IC implementations are particularly useful because, with careful design, parasitic capacitances can usually be kept low (or at least consistent across all units, allowing them to compensate).

[0054] Voltage levels may be adjusted, and / or voltages may be inverted and / or logic signal polarity may be inverted, depending on the particular specification and / or implementation technology (e.g., NMOS, PMOS, or CMOS, and enhancement mode or depletion mode transistor devices). Component voltage, current, and power handling capabilities may be adjusted as needed, for example, by adjusting device size, "stacking" components (particularly FETs) in series to withstand higher voltages, and / or using multiple components in parallel to handle greater currents. Additional circuit components may be added to enhance the capabilities of the disclosed circuits and / or provide additional functionality without significantly changing the functionality of the disclosed circuits.

[0055] Circuits and devices according to the present invention can be used alone or in combination with other components, circuits and devices. Embodiments of the present invention can be manufactured as integrated circuits (ICs), which can be packaged in IC packages and / or modules for ease of processing, manufacturing and / or improved performance. Specifically, IC embodiments of the present invention are typically used in modules, where one or more such ICs are combined with other circuit blocks (e.g., filters, amplifiers, passive components, and possible additional ICs) into a package. The ICs and / or modules are then generally combined with other components, typically on a printed circuit board, to form a part of a final product such as a cellular phone, a laptop computer, or an electronic tablet, or to form a higher-level module that can be used for various products such as vehicles, test equipment, medical equipment, etc. Through various configurations of modules and components, such ICs are generally capable of implementing a communication mode, typically wireless communication.

[0056] A number of embodiments of the present invention have been described. It should be appreciated that various modifications may be made without departing from the spirit and scope of the present invention. For example, some of the steps described above may be sequence-independent and therefore may be performed in a sequence different from that described. In addition, some of the steps described above may be optional. The various activities described for the methods identified above may be performed in a repetitive, sequential and / or parallel manner.

[0057] It should be understood that the above description is intended to illustrate rather than limit the scope of the invention, which is limited by the scope of the appended claims, and other embodiments are also within the scope of the claims. Specifically, the scope of the invention includes any and all feasible combinations of one or more processes, machines, manufactures, or compositions of matter disclosed in the following claims. (Note that the bracketed markings of claim elements are for ease of reference to those elements and do not themselves indicate a specific order or enumeration of the elements; in addition, such markings may be reused in dependent claims as references to additional elements without being considered to start a conflicting marking order).

Claims

1. A radio frequency (RF) amplifier, comprising: one or more transistors connected in series, wherein a first transistor of the one or more transistors is configured to receive a first input signal from a first input terminal; and A first feedback path including a first programmable resistor couples a drain terminal of a transistor of the one or more transistors to a source terminal of the first transistor of the one or more transistors.

2. The RF amplifier according to claim 1, wherein: The first feedback path also includes a first direct current (DC) blocking capacitor disposed in series with the first programmable resistor. 3 . The RF amplifier of claim 2 , comprising a switch configured to selectively switch the first feedback path on and off.

4. The RF amplifier of claim 1 , further comprising a second feedback path, the second feedback path comprising a second programmable resistor, the second feedback path coupling the gate terminal of the first transistor to the source terminal of the first transistor.

5. The RF amplifier of claim 4, further comprising a second DC blocking capacitor arranged in series with the second programmable resistor. 6 . The RF amplifier of claim 5 , further comprising a switch configured to selectively switch the second feedback path on and off.

7. The RF amplifier of claim 4, further comprising a third feedback path comprising a third programmable resistor, the third feedback path coupling the drain terminals of the one or more transistors to the gate terminal of the first transistor.

8. The RF amplifier of claim 7, further comprising a third DC blocking capacitor arranged in series with the third programmable resistor.

9. The RF amplifier of claim 7, further comprising a first additional transistor and a second additional transistor, wherein: a gate terminal of the first additional transistor connected to the gate terminal of the first transistor; a source terminal of the first additional transistor is connected to the source terminal of the first transistor, and A drain terminal of the second additional transistor is connected to a drain terminal of the one or more transistors; and The source terminal of the second additional transistor is connected to the drain terminal of the first additional transistor.

10. The RF amplifier of claim 7, further comprising a second DC blocking capacitor coupling the drain terminal of the transistor to the first programmable resistor and the third programmable resistor.

11. The RF amplifier according to claim 3, wherein: The switch is disposed in the first feedback path.

12. The RF amplifier of claim 1, wherein: The first input signal is configured to be selected from a plurality of input signals based on a desired frequency band.

13. The RF amplifier of claim 12, further comprising a series switch in the first feedback path, wherein: The series switch is configured to switch the first programmable resistor on and off, and The series switch is disposed closer to the drain terminal of the transistor, or closer to the source terminal of the first transistor.

14. The RF amplifier of claim 1, further comprising: one or more additional transistors connected in series, wherein a first additional transistor of the plurality of additional transistors is configured to receive a second input signal from a second input terminal; and a second feedback path including a second programmable resistor, the second feedback path coupling a drain terminal of an additional transistor of the plurality of additional transistors to a source terminal of the first additional transistor, wherein the drain terminal of the transistor is connected to the drain terminal of the additional transistor, and wherein the source terminal of the first transistor is connected to the source terminal of the first additional transistor.

15. The RF amplifier of claim 14, wherein: The first feedback path and the second feedback path are configured to be selectively switched on and off.

16. The RF amplifier of claim 1, further comprising: an additional transistor configured to receive a second input signal from a second input terminal; as well as a second feedback path including a second programmable resistor, the second feedback path coupling the drain terminal of the second transistor to the source terminal of the first transistor, wherein the drain terminal of the first transistor is connected to the drain terminal of the additional transistor, and wherein the source terminal of the first transistor is connected to the source terminal of the additional transistor.

17. The RF amplifier of claim 16, wherein: The first feedback path and the second feedback path are configured to be selectively switched on and off.

18. The RF amplifier of claim 1, further comprising: one or more additional transistors connected in series, wherein a first additional transistor of the one or more additional transistors is configured to receive a second input signal from a second input terminal, wherein the drain terminal of the transistor is connected to a drain terminal of an additional transistor of the one or more additional transistors, and wherein the source terminal of the first transistor is connected to a source terminal of the first additional transistor. The RF amplifier of claim 18 , wherein the first feedback path is configured to be selectively switched on and off.

20. A radio frequency (RF) amplifier comprising: one or more transistors connected in series, wherein a first transistor of the one or more transistors is configured to receive a first input signal from a first input terminal; and A first feedback path including a first programmable resistor couples a gate terminal of the first transistor to a source terminal of the first transistor.

21. The RF amplifier of claim 20, further comprising: i) one or more additional transistors connected in series, wherein: a first additional transistor of the one or more additional transistors configured to receive a second input signal from a second input terminal; the drain terminal of the transistor being connected to a drain terminal of an additional transistor of the one or more additional transistors, and the source terminal of the first transistor being connected to a source terminal of the first additional transistor; ii) The second feedback path, The second feedback path couples the source terminal of the first transistor to the gate terminal of the first additional transistor via a second switch.

22. The RF amplifier of claim 21, wherein In a first state when the first input terminal is activated, the first switch is closed and the second switch is open, and In a second state when the second input terminal is activated, the first switch is open and the second switch is closed.

23. The RF amplifier of claim 1, wherein: The RF amplifier is a low noise amplifier (LNA).

24. A method of reducing gain in a radio frequency (RF) amplifier, the method comprising: providing one or more transistors connected in series; applying an input signal to a gate terminal of a first transistor of the one or more transistors; providing a first feedback path including a first programmable resistor, the first feedback path coupling a drain terminal of a transistor of the one or more transistors to the gate terminal of the first transistor; providing a second feedback path including a second programmable resistor, the second feedback path coupling the drain terminal of the transistor to the source terminal of the first transistor; providing a third feedback path including a third programmable resistor, the third feedback path coupling the gate terminal of the first transistor of the one or more transistors to the source terminal of the first transistor of the one or more transistors; selectively switching on and off one or more of the first feedback path, the second feedback path, and the third feedback path based on set requirements, and The gain is also adjusted by varying one or more of the first programmable resistor, the second programmable resistor, and the third programmable resistor.

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