Fan control circuit, method and equipment

Abstract

The invention provides a fan control circuit, method and equipment, and relates to the technical field of fan management and fault monitoring. And the fan control circuit comprises a CPLD (Complex Programmable Logic Device), a watchdog and a multiplexer. In the fan control method, a CPLD firstly sends a dog feeding signal to a watchdog according to a first preset duration, and if the watchdog does not receive the dog feeding signal within a second preset duration, a first control signal is sent to a multiplexer. Wherein the first preset duration is greater than or equal to the second preset duration. And then, the multiplexer adjusts the second control signal to a high level according to the first control signal, and sends the high-level second control signal used for controlling the fan to work to the fan to be controlled. According to the method, flexible control over the fan is improved, and the application scene of controlling the fan through the CPLD is expanded.

Description

Technical Field

[0001] The present application relates to the technical field of fan management and fault monitoring, and in particular to a fan control circuit, method and device. Background Art

[0002] Complex Programmable Logic Device (CPLD) is between simple programmable logic devices and more complex field programmable gate arrays, and is used to implement complex digital circuit functions. CPLD has sufficient flexibility and programmability, making it very suitable for implementing various control tasks, including fan control.

[0003] In traditional data service products, fans are monitored by CPLD. However, once the CPLD fails, the fans will lose control or stop running, which will not only cause the machine to overheat rapidly, but also cause the failure to spread and eventually lead to forced service interruption.

[0004] Since the existing technology does not have a solution for rapid fault isolation and fan takeover, the business system's control of the fan is not flexible enough, and the application scenarios of CPLD controlling the fan are also subject to certain restrictions. Summary of the invention

[0005] The present application provides a fan control circuit, method and device to solve the problems in the prior art that the control of the fan by the business system is not flexible enough and the application scenarios of the CPLD controlling the fan are limited.

[0006] In a first aspect, the present application provides a fan control circuit, comprising:

[0007] CPLD, watchdog, and multiplexer;

[0008] Wherein, the input end of the watchdog is connected to the first output end of the CPLD, the first output end of the watchdog is connected to the input end of the multiplexer, and the output end of the multiplexer is connected to the first input end of the fan to be controlled;

[0009] The CPLD is used to send a dog feeding signal to the watchdog according to a first preset duration;

[0010] When the watchdog does not receive the dog feeding signal within the second preset time length, the watchdog is used to send a first control signal to the multiplexer, the first control signal is used to adjust the level of the second control signal to a high level, the high-level second control signal is used to control the fan to be controlled to work, and the second preset time length is greater than or equal to the first preset time length;

[0011] The multiplexer is used for adjusting the second control signal to a high level according to the first control signal, and sending the second control signal of the high level to the fan to be controlled.

[0012] In one possible design, the fan control circuit further includes a BMC;

[0013] The first output end of the BMC is connected to the input end of the CPLD, and the second output end of the CPLD is also connected to the second input end of the fan to be controlled;

[0014] The CPLD is further used to control the fan to be controlled according to the PWM signal of the BMC or the write register value of the BMC.

[0015] In one possible design, the fan control circuit further includes an Efuse;

[0016] The first input end of the Efuse is connected to the second output end of the BMC, and the second input end of the Efuse is connected to the second output end of the watchdog;

[0017] When the watchdog does not receive the dog feeding signal within the second preset time period, the watchdog is further used to send a third control signal to the Efuse, and the third control signal is used to control the Efuse to be enabled;

[0018] When the CPLD fails, the CPLD is further used to send a fourth control signal to the Efuse, and the fourth control signal is used to control the Efuse to be disabled.

[0019] In a second aspect, the present application provides a fan control method, applied to the fan control circuit as described in any one of the first aspects, the method comprising:

[0020] The CPLD sends a feeding signal to the watchdog according to the first preset duration;

[0021] When the watchdog does not receive the dog feeding signal within the second preset time period, the watchdog sends a first control signal to the multiplexer, the first control signal is used to adjust the level of the second control signal to a high level, the high-level second control signal is used to control the fan to be controlled to work, and the second preset time period is greater than or equal to the first preset time period;

[0022] The multiplexer adjusts the second control signal to a high level according to the first control signal, and sends the second control signal of the high level to the fan to be controlled.

[0023] In one possible design, the method further includes:

[0024] When the watchdog receives the dog feeding signal within the second preset time period, the CPLD obtains the working status of the BMC;

[0025] The CPLD controls the fan to be controlled according to the working state of the BMC.

[0026] In a possible design, the CPLD controls the fan to be controlled according to the working state of the BMC, including:

[0027] If the working state of the BMC is not working, the CPLD controls the fan to be controlled to keep working;

[0028] If the working state of the BMC is working, the fan to be controlled is controlled according to the PWM signal of the BMC or the write register value of the BMC.

[0029] In a possible design, when the watchdog does not receive the dog feeding signal within the second preset time period, the method further includes:

[0030] The watchdog sends a third control signal to the Efuse, where the third control signal is used to control the Efuse to be enabled;

[0031] The Efuse sets the enable pin to a high level according to the third control signal.

[0032] In one possible design, the method further includes:

[0033] When the watchdog receives the dog feeding signal, the accumulated duration of the timer is reset to zero and the time is restarted;

[0034] If the accumulated time length obtained by re-timing is greater than or equal to the second preset time length, it is determined that the watchdog has not received the dog feeding signal within the second preset time length.

[0035] In one possible design, the method further includes:

[0036] When the CPLD fails, the CPLD is further used to send a fourth control signal to the Efuse, and the fourth control signal is used to control the Efuse to be disabled.

[0037] In a third aspect, an embodiment of the present application provides an electronic device, comprising the fan control circuit as described in the first aspect and various possible designs.

[0038] The present application provides a fan control circuit, method and device, wherein the fan control circuit includes a watchdog, and a CPLD and a multiplexer that communicate with the watchdog. Among them, the CPLD and the multiplexer can also communicate with the fan to be controlled. In the process of controlling the fan, the CPLD first sends a dog feeding signal to the watchdog according to a first preset time length. If the watchdog does not receive the dog feeding signal within a second preset time length, a first control signal is sent to the multiplexer. Next, the multiplexer adjusts the second control signal to a high level according to the first control signal, and sends a high-level second control signal for controlling the operation of the fan to the fan to be controlled. It can be seen that when it is detected that the CPLD fails within the set time and cannot control the fan, the control of the fan is flexibly taken over by the watchdog and the multiplexer, and the fault is isolated to restore the operation of the fan, thereby ensuring that the business is not affected. This flexible fan control method means that the technology of CPLD controlling the fan can be applied to more fields and more diverse scenarios, further expanding the application scenarios of CPLD controlling the fan. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0040] Figure 1 A schematic diagram of the structure of a fan control circuit provided in an embodiment of the present application;

[0041] Figure 2 The structure of the fan control method applicable to the embodiment of the present application is shown in FIG. Figure 1 ;

[0042] Figure 3 The structure of the fan control method applicable to the embodiment of the present application is shown in FIG. Figure 2 ;

[0043] Figure 4 A schematic diagram of a flow chart of a fan control method provided in an embodiment of the present application;

[0044] Figure 5 A schematic diagram of the watchdog operation of the fan control method provided in an embodiment of the present application.

[0045] The above drawings have shown clear embodiments of the present application, which will be described in more detail later. These drawings and text descriptions are not intended to limit the scope of the present application in any way, but to illustrate the concept of the present application to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0046] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0047] In the technical solution of this application, the collection, storage, use, processing, transmission, provision and disclosure of information such as financial data or user data involved shall comply with the provisions of relevant laws and regulations and shall not violate public order and good morals.

[0048] It should be noted that in the embodiments of the present application, certain software, components, models and other existing solutions in the industry may be mentioned, and they should be regarded as exemplary. Their purpose is only to illustrate the feasibility of implementing the technical solution of the present application, but it does not mean that the applicant has or will necessarily use the solution.

[0049] Terminology explanation:

[0050] CPLD: A digital integrated circuit that users can construct logic functions according to their own needs. It uses Electrically Erasable Programmable Read-Only Memory (EEPROM), Static Random-Access Memory (SRAM) and flash memory to form a high-density, high-speed and low-power programmable logic device.

[0051] Watchdog: The full name is WatchDog, which is mainly used to monitor and protect the normal operation of the system to prevent the system from freezing or falling into an infinite loop due to software or hardware errors. The watchdog mentioned in this application refers to a hardware watchdog, which is a timer circuit that usually has an input (called "feeding dog") and an output, and the output is connected to the reset terminal of the system.

[0052] Multiplexer: The full name is Multiplexer, which is a digital circuit component used to select an output signal from multiple input signals. It has multiple input terminals, one output terminal and some control signal lines, and is widely used in computer systems, communication systems and various digital circuits.

[0053] Baseboard Management Controller (BMC): A dedicated microcontroller that uses sensors to monitor the status of a computer, network service, or other hardware device, and communicates with the system administrator through independent connection lines. In the fan control circuit, the main role of the BMC is to detect fan failures, manage fan redundancy, record event logs, and allow the system administrator to configure fan control policies.

[0054] Since CPLD can be programmed to implement various logic functions that are more complex than programmable logic devices but not as complex as programmable gate arrays, it has high flexibility and programmability and is very suitable for implementing various control tasks including fan control.

[0055] In traditional data services, fans are usually monitored by CPLD. Specifically, CPLD can monitor the operating status of the fan, such as speed, temperature, etc. Then, CPLD can control the start and stop and speed of the fan according to the monitored fan operating status and preset logic to ensure the heat dissipation requirements of the system.

[0056] However, once the CPLD fails, the fan will lose control or stop, resulting in insufficient heat dissipation in the system and a rapid rise in device temperature. Excessive temperatures can cause other components to overheat, leading to more failures. Ultimately, the system may be forced to shut down due to overheating, resulting in business interruption.

[0057] It can be seen that when the CPLD fails, there is no backup controller or redundant design to take over the fan control, resulting in the fan losing control or stopping. Since the system lacks a mechanism to quickly isolate the fault, it cannot quickly switch to the backup fan control solution, and the business system's control of the fan is not flexible enough.

[0058] However, due to the above problems, the application scenarios of CPLD fan control are subject to certain restrictions. For example, in application scenarios that require high reliability and high availability (such as data centers, servers, etc.), the CPLD fan control method may not be reliable enough to meet the high reliability requirements. In application scenarios that require flexible adjustment of fan control strategies (such as intelligent cooling systems), the existing CPLD fan control method may not provide sufficient flexibility and adaptability.

[0059] In response to the above technical problems, the inventors found that when studying the process of CPLD controlling the fan, redundant CPLD or backup controller can be introduced to take over the fan control when the CPLD fails. Considering the economy and feasibility of the specific implementation process, the inventors chose to use a watchdog to monitor the working status of the CPLD and provide a backup control solution when the CPLD fails. The watchdog does not require complex hardware or software design, and can reliably detect system failures and quickly trigger the backup control solution to ensure the normal operation of the fan, thereby improving the flexible control of the fan by the business system. In addition, the implementation of the watchdog is relatively simple and low-cost, and has a high use value.

[0060] The technical solution of the present application and how the technical solution of the present application solves the above-mentioned technical problems are described in detail below with specific embodiments. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of the present application will be described below in conjunction with the accompanying drawings.

[0061] An embodiment of the present application provides a fan control circuit. Figure 1 This is a schematic diagram of the structure of the fan control circuit provided in the embodiment of the present application. Figure 1 As shown, the fan control circuit includes a CPLD, a watchdog, a multiplexer, a BMC and an Efuse.

[0062] Among them, CPLD receives control signals from BMC and generates corresponding output signals according to these control signals to control the working status of watchdog and fan. Watchdog is used to monitor the operating status of the system to prevent the system from falling into a fault state; if an abnormal situation is detected, it can send output signals to the multiplexer and Efuse through its output end. The multiplexer receives the output signal from the watchdog and passes it to the fan to control the operation of the fan. Efuse is an electronic fuse used to protect the circuit; it receives output signals from BMC and watchdog to ensure that the circuit can be cut off and the system can be protected under abnormal conditions.

[0063] Specifically, the input end of the watchdog is connected to the first output end of the CPLD, the first output end of the watchdog is connected to the input end of the multiplexer, and the output end of the multiplexer is connected to the first input end of the fan to be controlled. The fan control circuit also includes a BMC and an Efuse, the first output end of the BMC is connected to the input end of the CPLD, and the second output end of the CPLD is connected to the second input end of the fan to be controlled. The first input end of the Efuse is connected to the second output end of the BMC, and the second input end of the Efuse is connected to the second output end of the watchdog.

[0064] In one possible implementation, Figure 2The structure of the fan control circuit applicable to the embodiment of the present application is shown in FIG. Figure 1 , Figure 3 The structure of the fan control circuit applicable to the embodiment of the present application is shown in FIG. Figure 2 It should be noted that Figure 2 and Figure 3 The difference lies in the different operating voltages, among which, Figure 1 The circuit shown operates at 12V. Figure 2 The circuit shown operates at 54V. Figure 1 and Figure 2 As shown, the fan control circuit is implemented by CPLD, watchdog, and multiplexer.

[0065] First, we will Figure 2 and Figure 3 A brief description of the component pins included.

[0066] exist Figure 2 or Figure 3 In the example, the VCC pin of the watchdog module is the power pin, which is used to provide the working voltage; the MR pin is the manual reset pin, which is used to manually reset the timer; the WDI is the watchdog input pin, which is used to receive the periodic pulse signal; the PFI is the power fault input pin, which is used to monitor the power supply voltage; the PFO is the power fault output pin, which outputs the power fault signal; and the WDO is the watchdog output pin, which is used to output the watchdog timeout signal.

[0067] The A pin and B pin of the multiplexer are usually input pins for receiving input signals; the S pin is a selection pin for selecting which input signal will be transmitted to the output end; and the Y pin is an output pin for outputting the selected input signal.

[0068] Next, we will Figure 2 and Figure 3 The meaning of the signals included is briefly explained.

[0069] Exemplarily, the motherboard standby power signal may be P3V3_STBY_MB or P3V3_STBY_PSU, indicating a 3.3V standby power signal on the motherboard; wherein P3V3_STBY_MB may be used as Figure 2 The motherboard standby power signal, P3V3_STBY_PSU can be used as Figure 3 The standby power signal of the motherboard can be P3V3_STBY, which means a 3.3V standby power signal.

[0070] The power signal can be P12V_PSU, which indicates a 12V power signal provided by a power supply unit (PSU); or P54V_PSU, which indicates a 54V power signal provided by a PSU. Figure 2 The power signal of P54V_PSU can be used as Figure 3 power signal.

[0071] The enable signal may be EFUSE_EN, indicating an enable signal corresponding to Efuse; the control enable signal may be CPLD_EFUSE_EN, indicating an Efuse enable signal controlled by CPLD.

[0072] The fan power signal can be P12V_FAN[0…N], which indicates a 12V power signal for the fan, where [0…N] indicates multiple fans; or P54V_FAN[0…N], which indicates a 54V power signal for the fan. Figure 2 The fan power signal, P54V_FAN[0…N] can be used as Figure 3 The fan power signal.

[0073] The fan modulation signal may be FAN[0…N]_CPLD_PWM, which indicates a fan pulse width modulation (PWM) signal controlled by a CPLD; the fan PWM signal may be FAN[0…N]_PWM.

[0074] The speed signal may be FAN[0...N]_TACH, indicating a signal for determining speed information of a plurality of fans; the occupancy signal may be FAN[0...N]_PRENSENT_N, indicating a signal for determining occupancy information of a plurality of fans.

[0075] In addition, the heartbeat signal sent by the CPLD is the dog feeding signal, which is used to monitor whether the CPLD is working properly. The fuse is a protective device used to prevent overcurrent or short circuit from damaging the circuit. When the CPLD power supply is short-circuited, the fuse will melt and cut off the current.

[0076] exist Figure 2 and Figure 3In the fan control circuit shown, watchdog monitoring is used as a low-cost exception handling solution. When a CPLD fails due to software upgrades or abnormal operation damage, it will not only cause service interruptions and data loss in servers or switches, but also cause abnormal operation of the fan module. The watchdog can take over the control of the fan in the first place, isolate the fault to restore the fan operation, control the impact range, and reserve enough time to resolve the abnormality.

[0077] based on Figure 2 and Figure 3 The fan control circuit shown, the embodiment of the present application also provides a fan control method. Figure 4 A flow chart of a fan control method provided in an embodiment of the present application is shown in FIG. Figure 4 As shown, the fan control method includes:

[0078] S401. The CPLD sends a dog feeding signal to the watchdog according to a first preset duration.

[0079] It is understandable that when the CPLD is working normally, it will send a dog-feeding signal to the input end of the watchdog according to the first preset duration to reset the timer and restart the timing. After the timing is restarted, if the CPLD fails, it will not be able to continue to send the dog-feeding signal to the watchdog. Determine the cumulative duration obtained by retiming. If the cumulative duration is greater than or equal to the second preset duration, it is determined that the watchdog has not received the dog-feeding signal within the second preset duration, wherein the second preset duration is greater than or equal to the first preset duration. If the watchdog does not receive the dog-feeding signal within the second preset duration, the timer will continue to count until it times out.

[0080] Explanatory, the watchdog of this embodiment is a hardware mechanism for monitoring the operating status of the system, and its main purpose is to prevent the system from failing to respond when a fault occurs or falls into an infinite loop. The watchdog usually waits for the feeding signal within a preset time interval, that is, a second preset time length.

[0081] If the CPLD does not send a feeding signal to the watchdog within the first preset time, the watchdog will not take action immediately, but the timer will continue to count. If the timer reaches its set timeout period, that is, the second preset time, during the process of continuing to count, the watchdog will determine that there is a problem with the system and take corresponding measures, such as restarting the system or triggering an interrupt.

[0082] For example, assuming that the first preset time is 5 seconds and the second preset time is 8 seconds, the CPLD needs to send a feeding signal to the watchdog every 5 seconds. If the CPLD does not send a feeding signal within a 5-second period, the watchdog timer will continue to count. If the timer counts for more than 8 seconds (i.e., timeout), the watchdog will think that there is a problem with the system.

[0083] S402: When the watchdog does not receive a dog feeding signal within a second preset time period, the watchdog sends a first control signal to the multiplexer.

[0084] in, Figure 5 The watchdog operation diagram of the fan control method provided in the embodiment of the present application is as follows: Figure 5 As shown, the watchdog needs to be started first, and the watchdog starts to monitor the system and perform its functions through software or hardware configuration. Specifically, the watchdog enabling usually includes setting the timeout time of the timer (i.e., the second preset duration), reset behavior and other parameters, and starting the timer to time and monitor by writing a specific register or executing a specific instruction.

[0085] Once the timer times out, it will trigger a predefined action, such as outputting a reset signal or an interrupt signal. The reset signal usually restarts the system to try to resume normal operation; the interrupt signal may be used to notify the processor or other system components to perform corresponding error handling.

[0086] In this embodiment, when the watchdog does not receive the dog feeding signal within the second preset time, the watchdog sends a first control signal that can be used as an interrupt signal to the multiplexer. The first control signal is used to control the multiplexer to adjust the level of the second control signal to a high level, that is, to select the high-level second control signal through the selection pin of the multiplexer. The high-level second control signal is used to control the operation of the fan to be controlled.

[0087] S403: The multiplexer adjusts the second control signal to a high level according to the first control signal, and sends the high-level second control signal to the fan to be controlled.

[0088] The second control signal is actually a control signal sent by the CPLD to the fan to be controlled. The fan works when the second control signal is at a high level and stops working when the control signal is at a low level. When the multiplexer adjusts the second control signal to a high level according to the first control signal, it means that the fan will receive a continuous high level signal and will run at the maximum speed.

[0089] Specifically, the second control signal may be generated by the CPLD itself, or may be sent by the BMC to the CPLD.

[0090] In a possible implementation, when the CPLD works normally, that is, when the watchdog receives a feeding signal within the second preset time, the CPLD obtains the working state of the BMC, and the CPLD controls the fan to be controlled according to the working state of the BMC. Specifically, if the working state of the BMC is not working, the CPLD itself generates a second control signal to directly control the fan to keep working. If the working state of the BMC is working, the CPLD uses the PWM signal of the BMC or the write register value of the BMC as the corresponding second control signal, and controls the fan to be controlled by transparently transmitting the second control signal.

[0091] Explanatory, when the BMC is not working, in order to ensure that the fan can keep working, the CPLD itself should generate a fixed high-level second control signal. When the BMC is working normally and the CPLD uses the BMC's PWM signal as the second control signal, the fan speed can be accurately controlled by adjusting the duty cycle of the PWM signal. Specifically, the rapid switching between the high and low levels of the PWM signal generates an average voltage, and the fan speed is proportional to the average voltage, that is, the higher the average voltage received by the fan, the faster the speed.

[0092] Whether the CPLD controls the fan to be controlled according to the second control signal generated by itself, or uses the PWM signal of the BMC or the write register value as the second control signal to control the fan to be controlled, Efuse is indispensable. It should be understood that Efuse is used to monitor the power supply and isolation protection of the fan. It is not enabled by default. The CPLD can enable Efuse power supply according to the timing requirements. Usually, the CPLD is powered on first, and then outputs the corresponding enable signal to control the power supply of the Efuse-related circuit.

[0093] Specifically, Efuse can monitor the power supply status of the fan to ensure that the fan can obtain a stable power supply when it is working normally, wherein monitoring the power supply may include detecting parameters such as voltage and current. In addition, when a CPLD fails, isolation technology can be used to isolate the failed CPLD from the fan and other circuit parts.

[0094] In a possible implementation, when the CPLD is working normally, a high-level enable signal can be continuously sent to the Efuse to control the power supply of the Efuse-related circuits. However, as can be seen from the above, the watchdog will monitor the working status of the CPLD. When the CPLD fails, that is, the watchdog does not receive the feeding signal within the second preset time, the watchdog will take over the sending of the enable signal to ensure the normal operation of the Efuse.

[0095] It is understandable that after the PSU is powered on, the CPLD and the watchdog are powered on at the same time. Before the CPLD works normally and the watchdog setting times out, the Efuse is not enabled. When the CPLD does not work all the time, the watchdog timer times out, and the watchdog outputs the corresponding control signal, the Efuse power supply is enabled and the PWM output is controlled, so that the fan can operate normally.

[0096] Specifically, when a CPLD fails, the enable signal sent to the Efuse includes a high level state, a low level state, and a high impedance state. For example, when a short circuit occurs in the CPLD, the enable signal sent to the Efuse is in a high level state; when the CPLD burns out, the enable signal sent to the Efuse is in a high impedance state. When the CPLD fails such as an internal logic error, a partial function failure, or a power problem, the enable signal sent to the Efuse is in a low level state.

[0097] Explanatory, when CPLD fails, if the enable signal sent to Efuse is in a low level state or high impedance state, the enable signal will be cut off by the Metal Oxide Semiconductor (MOS) tube, and the watchdog will send a low level control signal to Efuse. If the enable signal sent to Efuse is in a high level state when CPLD fails, and the watchdog cannot receive the feeding signal within the second preset time, it will still take over the control of Efuse from CPLD.

[0098] In a possible implementation, when the CPLD fails, that is, the watchdog does not receive the feeding signal within the second preset time, the watchdog sends a third control signal for controlling the Efuse to be enabled, or a fourth control signal for controlling the Efuse to be disabled, to the Efuse. The third control signal is used to control the Efuse to set the enable pin to a high level.

[0099] In summary, if the CPLD fails or fails during normal operation of the device, the fan power supply is cut off or the fan stops. After the watchdog timer times out, the second control signal of the CPLD is switched to a high level, and the corresponding enable signal is forced to be sent to the Efuse to power the fan. The fan isolates the CPLD within the watchdog setting time and maintains its normal operation to prevent the device from overheating.

[0100] It should be understood that the CPLD has higher control over the fan than the watchdog. That is, when the CPLD returns to normal, it continues to send a feeding signal to the watchdog, the watchdog's interrupt is released, and the CPLD takes over control of the fan again.

[0101] The present application provides a fan control circuit and method, and the fan control circuit includes a CPLD, a watchdog and a multiplexer. In the process of controlling the fan, the CPLD first sends a dog feeding signal to the watchdog according to the first preset time length. When the watchdog receives the dog feeding signal within the second preset time length, the second control signal for controlling the fan to be controlled is determined according to the working state of the BMC. When the watchdog does not receive the dog feeding signal within the second preset time length, the first control signal is sent to the multiplexer. Next, the multiplexer adjusts the second control signal to a high level according to the first control signal, and sends the high-level second control signal to the fan to be controlled. In addition, the normally operating CPLD can also control the fan to be controlled by sending an enable signal to Efuse. When the CPLD fails, the watchdog takes over the control of Efuse. It can be seen that when the CPLD fails within the set time and cannot control the fan, the control of the fan is flexibly taken over by the watchdog and the multiplexer, and the fault is isolated to restore the operation of the fan, thereby ensuring that the business is not affected. This flexible fan control method means that the CPLD fan control technology can be applied to more fields and more diverse scenarios, further expanding the application scenarios of CPLD fan control.

[0102] The electronic device provided in the embodiment of the present application includes the technical solution of the fan control circuit in the above embodiment.

[0103] In the several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic, for example, the division of modules is only a logical function division, and there may be other division methods in actual implementation, such as multiple modules can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or modules, which can be electrical, mechanical or other forms.

[0104] The modules described as separate components may or may not be physically separated, and the components shown as modules may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the modules may be selected according to actual needs to implement the solution of this embodiment.

[0105] In addition, each functional module in each embodiment of the present application can be integrated into one processing unit, or each module can exist physically separately, or two or more modules can be integrated into one unit. The above-mentioned module-composed unit can be implemented in the form of hardware or in the form of hardware plus software functional units.

[0106] The above-mentioned integrated module implemented in the form of a software function module can be stored in a computer-readable storage medium. The above-mentioned software function module is stored in a storage medium, including a number of instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) or a processor to perform some steps of the methods of various embodiments of the present application.

[0107] It should be understood that the processor may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), etc. A general-purpose processor may be a microprocessor or any conventional processor. The steps of the method disclosed in the invention may be directly implemented as being executed by a hardware processor, or may be implemented by a combination of hardware and software modules in the processor.

[0108] The memory may include a high-speed RAM memory, and may also include a non-volatile storage NVM, such as at least one disk memory, and may also be a USB flash drive, a mobile hard disk, a read-only memory, a magnetic disk or an optical disk, etc.

[0109] The bus may be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. The bus may be divided into an address bus, a data bus, a control bus, etc. For ease of representation, the bus in the drawings of the present application is not limited to only one bus or one type of bus.

[0110] The above storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk. The storage medium can be any available medium that can be accessed by a general or special purpose computer.

[0111] An exemplary storage medium is coupled to a processor so that the processor can read information from the storage medium and write information to the storage medium. Of course, the storage medium can also be a component of the processor. The processor and the storage medium can be located in an application specific integrated circuit (ASIC). Of course, the processor and the storage medium can also exist as discrete components in an electronic control unit or a main control device.

[0112] Those skilled in the art can understand that all or part of the steps of implementing the above-mentioned method embodiments can be completed by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When the program is executed, the steps of the above-mentioned method embodiments are executed; and the aforementioned storage medium includes: ROM, RAM, disk or optical disk and other media that can store program codes.

[0113] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A fan control circuit, characterized in that: include: Complex programmable logic devices (CPLDs), watchdogs, and multiplexers; Wherein, the input end of the watchdog is connected to the first output end of the CPLD, the first output end of the watchdog is connected to the input end of the multiplexer, and the output end of the multiplexer is connected to the first input end of the fan to be controlled; The CPLD is used to send a dog feeding signal to the watchdog according to a first preset duration; When the watchdog does not receive the dog feeding signal within the second preset time length, the watchdog is used to send a first control signal to the multiplexer, the first control signal is used to adjust the level of the second control signal to a high level, the high-level second control signal is used to control the fan to be controlled to work, and the second preset time length is greater than or equal to the first preset time length; The multiplexer is used for adjusting the second control signal to a high level according to the first control signal, and sending the second control signal of the high level to the fan to be controlled.

2. The fan control circuit according to claim 1, characterized in that: The fan control circuit also includes a baseboard management controller BMC; The first output end of the BMC is connected to the input end of the CPLD, and the second output end of the CPLD is also connected to the second input end of the fan to be controlled; The CPLD is also used to control the fan to be controlled according to the pulse width modulation (PWM) signal of the BMC or the write register value of the BMC.

3. The fan control circuit according to claim 2, characterized in that: The fan control circuit also includes an electronic fuse Efuse; The first input end of the Efuse is connected to the second output end of the BMC, and the second input end of the Efuse is connected to the second output end of the watchdog; When the watchdog does not receive the dog feeding signal within the second preset time period, the watchdog is further used to send a third control signal to the Efuse, and the third control signal is used to control the Efuse to be enabled; When the CPLD fails, the CPLD is further used to send a fourth control signal to the Efuse, and the fourth control signal is used to control the Efuse to be disabled.

4. A fan control method, characterized in that: Applied to the fan control circuit according to any one of claims 1 to 3, the method comprises: The complex programmable logic device CPLD sends a dog feeding signal to the watchdog according to a first preset duration; When the watchdog does not receive the dog feeding signal within the second preset time period, the watchdog sends a first control signal to the multiplexer, the first control signal is used to adjust the level of the second control signal to a high level, the high-level second control signal is used to control the fan to be controlled to work, and the second preset time period is greater than or equal to the first preset time period; The multiplexer adjusts the second control signal to a high level according to the first control signal, and sends the second control signal of the high level to the fan to be controlled.

5. The method according to claim 4, characterized in that The method further comprises: When the watchdog receives the dog feeding signal within the second preset time period, the CPLD obtains the working state of the baseboard management controller BMC; The CPLD controls the fan to be controlled according to the working state of the BMC.

6. The method according to claim 5, characterized in that The CPLD controls the fan to be controlled according to the working state of the BMC, including: If the working state of the BMC is not working, the CPLD controls the fan to be controlled to keep working; If the working state of the BMC is working, the fan to be controlled is controlled according to the pulse width modulation (PWM) signal of the BMC or the write register value of the BMC.

7. The method according to any one of claims 4 to 6, characterized in that: When the watchdog does not receive the dog feeding signal within the second preset time period, the method further includes: The watchdog sends a third control signal to the electronic fuse Efuse, wherein the third control signal is used to control the Efuse to be enabled; The Efuse sets the enable pin to a high level according to the third control signal.

8. The method according to any one of claims 4 to 6, characterized in that: The method further comprises: When the watchdog receives the dog feeding signal, the accumulated duration of the timer is reset to zero and the time is restarted; If the accumulated time length obtained by re-timing is greater than or equal to the second preset time length, it is determined that the watchdog has not received the dog feeding signal within the second preset time length.

9. The method according to claim 7, characterized in that: The method further comprises: When the CPLD fails, the CPLD is further used to send a fourth control signal to the Efuse, and the fourth control signal is used to control the Efuse to be disabled.

10. An electronic device, characterized in that: The invention comprises a fan control circuit as described in any one of claims 1 to 3.

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