Chip life evaluation method and system and storage medium

Abstract

The invention discloses a chip life evaluation method and system and a storage medium, and the method comprises the steps: obtaining chip operation information and a chip temperature distribution diagram of a current time period; based on the chip temperature distribution diagram, obtaining a chip aging rate and a current fault probability; obtaining a current damage rate based on the current fault probability and the chip operation information; and evaluating the residual life of the chip based on the current damage rate and the chip aging rate. The damage rate and the chip aging rate can better represent the damage degree of the chip, and the damage degree of the chip is highly related to the service life of the chip, so that the residual service life of the chip is evaluated from the damage degree of the chip as an evaluation angle; therefore, the problem that a large amount of resource cost, time cost and labor cost are consumed due to the fact that the chip is comprehensively tested through various testing instruments and a complex testing process can be avoided, and the service life evaluation efficiency of the chip can be effectively improved.

Description

Technical Field

[0001] The present invention relates to the field of artificial intelligence and semiconductor life test technology, and in particular to a chip life assessment method, system and storage medium. Background Art

[0002] With the continuous upgrading of chip hardware, the chip's anti-interference ability, computing efficiency, service life, and scope of application are constantly improving. However, due to the diversity of the external environment and the richness of operating conditions, the application frequency of chips is increasing, and long-term operation under high voltage and high current is accompanied by frequent opening and closing actions, which puts higher requirements on the reliability of chips. In order to avoid chip failures during actual application, which may lead to the failure of running tasks and delay the execution of normal tasks, it is often necessary to estimate the service life of the chip to ensure timely replacement of the chip. Therefore, how to accurately estimate the life of the chip is the current research focus.

[0003] The traditional method of estimating chip life is to perform various functional tests on the chip and conduct comprehensive manual analysis of the test results to identify the current remaining life of the chip. However, this method requires a variety of test instruments and complex test processes for comprehensive testing, which consumes a lot of resource costs and manpower costs. In addition, the entire test process and manual analysis process are time-consuming, resulting in low chip life estimation efficiency. Summary of the invention

[0004] The present invention provides a chip life assessment method, system and storage medium to solve the above technical problems and effectively improve the chip life assessment efficiency.

[0005] In order to solve the above technical problems, the present invention provides a chip life assessment method, comprising:

[0006] Obtain chip operation information and chip temperature distribution diagram for the current period;

[0007] Based on the chip temperature distribution diagram, obtaining the chip aging rate and current failure probability;

[0008] Based on the current failure probability and the chip operation information, a current damage rate is obtained;

[0009] The remaining life of the chip is evaluated based on the current damage rate and the chip aging rate.

[0010] The beneficial effects of the present invention are:

[0011] The present invention obtains the current damage rate and the chip aging rate by acquiring the chip operation information and the chip temperature distribution diagram, and evaluates the remaining life of the chip based on the current damage rate and the chip aging rate, wherein the damage rate and the chip aging rate can better characterize the degree of damage of the chip, and the degree of damage of the chip is highly correlated with the life of the chip. The present invention evaluates the remaining life of the chip from the perspective of the degree of damage of the chip, which can avoid the problem of comprehensive testing of the chip through multiple testing instruments and complex testing processes, which consumes a lot of resource costs, time costs and manpower costs, thereby effectively improving the efficiency of chip life evaluation.

[0012] As a preferred solution, the chip aging rate and current failure probability are obtained based on the chip temperature distribution map, including:

[0013] Determine each chip structure of the chip and the connection position of each chip structure of the chip;

[0014] Based on the chip temperature distribution diagram, a heating rate of each chip structure, a temperature range change rate of each chip structure, and a temperature conductivity of each chip structure are obtained;

[0015] Based on the heating rate of each chip structure and the temperature range change rate of each chip structure, the chip aging rate and the first failure probability of each chip structure are calculated;

[0016] Based on the temperature conductivity of each chip structure, a second failure probability of a connection position of each chip structure is obtained;

[0017] According to the first preset weight value of each chip structure and the second preset weight value of each chip structure connection position, the first failure probability of all chip structures and the second failure probability of all chip structure connection positions are weighted summed to obtain the current failure probability.

[0018] As a preferred solution, the method of obtaining the heating rate of each chip structure, the temperature range change rate of each chip structure and the temperature conductivity of each chip structure based on the chip temperature distribution diagram includes:

[0019] Based on the chip temperature distribution diagram, obtaining a temperature position change trend and a temperature range change trend;

[0020] Based on the temperature range change trend, the heating rate and temperature range change rate of each chip structure are obtained;

[0021] Based on the temperature position change trend, the temperature conductivity of each chip structure is obtained.

[0022] As a preferred solution, the temperature position change trend and the temperature range change trend are obtained based on the chip temperature distribution map, including:

[0023] For the chip temperature distribution map at each moment, the chip temperature distribution map is divided into a number of temperature unit maps, the position information of each temperature unit map is obtained, and the average temperature data of each temperature unit map is calculated;

[0024] The average temperature data of each temperature unit graph at each moment is sorted in chronological order to obtain the sub-temperature change information of each temperature unit graph;

[0025] Based on the position information of each temperature unit graph and the sub-temperature change information of each temperature unit graph, the temperature position change trend and the temperature range change trend are obtained.

[0026] As a preferred solution, obtaining the current damage rate based on the current failure probability and the chip operation information includes:

[0027] Based on the chip operation information, generate operation status distribution information;

[0028] Based on the operation status distribution information, obtaining chip stability evaluation information and chip trend evaluation information;

[0029] Based on the chip stability evaluation information, obtaining the chip stability degree;

[0030] Based on the chip trend evaluation information, obtaining the chip trend amplitude and the chip abnormal trend degree;

[0031] Based on the current failure probability and the duration of the current period, the failure probability change rate is calculated;

[0032] The chip stability, the chip trend amplitude, the chip abnormal trend degree and the failure probability change rate are input into a preset life assessment network to obtain the current damage rate.

[0033] As a preferred solution, the generating of the operation status distribution information based on the chip operation information includes:

[0034] Based on the chip operation information, obtaining operation data corresponding to each moment;

[0035] In the preset operation database, obtain the data range to which each operation data belongs;

[0036] Determine the operation status corresponding to each operation data based on the data range to which each operation data belongs;

[0037] Based on the operating status corresponding to each operating data at each moment, the target operating status at each moment is obtained;

[0038] The target operating status at each moment is sorted according to the time sequence to generate operating status distribution information.

[0039] As a preferred solution, the chip stability evaluation information and the chip trend evaluation information are obtained based on the operation status distribution information, including:

[0040] Based on the operation status distribution information, a chip operation status trend, a chip operation status fluctuation range, and a chip status fluctuation range trend are obtained;

[0041] Obtain chip trend evaluation information based on the chip operation status trend through a preset status trend indicator evaluation strategy;

[0042] Through a preset state stability index evaluation strategy, chip stability evaluation information is obtained based on the chip operating state fluctuation range and the chip state fluctuation range trend.

[0043] As a preferred solution, the evaluating the remaining life of the chip based on the current damage rate and the chip aging rate includes:

[0044] Obtain the life span corresponding to different damage rates and the life attenuation ratio corresponding to different aging rates;

[0045] Based on the current damage rate and the chip aging rate, the current life span and the current life attenuation ratio are obtained from the life spans corresponding to the different damage rates and the life attenuation ratios corresponding to the different aging rates;

[0046] Based on the current life span and the current life decay ratio, the remaining life of the chip is evaluated.

[0047] Accordingly, in order to solve the above technical problems, the present invention also provides a chip life assessment system, comprising: a data acquisition module, a data calculation module, a damage rate acquisition module and a life assessment module;

[0048] Wherein, the data acquisition module is used to obtain the chip operation information and chip temperature distribution diagram of the current period;

[0049] The data calculation module is used to obtain the chip aging rate and current failure probability based on the chip temperature distribution map;

[0050] The damage rate acquisition module is used to obtain the current damage rate based on the current failure probability and the chip operation information;

[0051] The life evaluation module is used to evaluate the remaining life of the chip based on the current damage rate and the chip aging rate. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] Figure 1: A schematic diagram of a flow chart of an embodiment of a chip life assessment method provided by the present invention;

[0053] Figure 2 : A schematic diagram of the structure of an embodiment of a chip life assessment system provided by the present invention;

[0054] Figure 3 : A structural diagram of an embodiment of a computer device provided by the present invention. DETAILED DESCRIPTION

[0055] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0056] The traditional method of estimating chip life is to perform various functional tests on the chip and conduct comprehensive manual analysis of the test results to identify the current remaining life of the chip. However, this method requires a variety of test instruments and complex test processes for comprehensive testing, which consumes a lot of resource costs and manpower costs. In addition, the entire test process and manual analysis process are time-consuming, resulting in low chip life estimation efficiency.

[0057] Embodiment 1

[0058] In order to solve the above technical problems, the present invention provides a chip life assessment method, system and storage medium to solve the above technical problems and effectively improve the chip life assessment efficiency.

[0059] Please refer to Figure 1 , which is a flow chart of an embodiment of a chip life assessment method provided in an embodiment of the present invention.

[0060] like Figure 1 As shown, the chip life assessment method includes steps 101 to 104, specifically:

[0061] Step 101: Obtain chip operation information and chip temperature distribution diagram of the current period;

[0062] Step 102: Based on the chip temperature distribution diagram, obtain the chip aging rate and current failure probability;

[0063] Step 103: obtaining a current damage rate based on the current failure probability and the chip operation information;

[0064] Step 104: Evaluate the remaining life of the chip based on the current damage rate and the chip aging rate.

[0065] The present invention obtains the current damage rate and the chip aging rate by acquiring the chip operation information and the chip temperature distribution diagram, and evaluates the remaining life of the chip based on the current damage rate and the chip aging rate, wherein the damage rate and the chip aging rate can better characterize the degree of damage of the chip, and the degree of damage of the chip is highly correlated with the life of the chip. The present invention evaluates the remaining life of the chip from the perspective of the degree of damage of the chip, which can avoid the problem of comprehensive testing of the chip through multiple testing instruments and complex testing processes, which consumes a lot of resource costs, time costs and manpower costs, thereby effectively improving the efficiency of chip life evaluation.

[0066] Furthermore, in step 101, the present invention collects the sub-chip operation information of the chip in real time through the operation detection program preset in the chip, and after each collection of the sub-chip operation information of the preset time length, transmits the sub-chip operation information of the preset time length to the terminal to obtain the chip operation information of the chip in the current period, and the preset period is the period preset in the terminal by the staff, which can change with the adjustment of the staff. Then, the chip temperature distribution map of the chip surface in the current period is collected through the infrared temperature sensor image monitoring device set outside the chip.

[0067] Further, in step 102, the chip aging rate and current failure probability are obtained based on the chip temperature distribution map, including:

[0068] Determine each chip structure of the chip and the connection position of each chip structure of the chip;

[0069] Based on the chip temperature distribution diagram, a heating rate of each chip structure, a temperature range change rate of each chip structure, and a temperature conductivity of each chip structure are obtained;

[0070] Based on the heating rate of each chip structure and the temperature range change rate of each chip structure, the chip aging rate and the first failure probability of each chip structure are calculated;

[0071] Based on the temperature conductivity of each chip structure, a second failure probability of a connection position of each chip structure is obtained;

[0072] According to the first preset weight value of each chip structure and the second preset weight value of each chip structure connection position, the first failure probability of all chip structures and the second failure probability of all chip structure connection positions are weighted summed to obtain the current failure probability.

[0073] In this embodiment, the aging rate of the chip is calculated based on the heating rate of each chip structure and the temperature range change rate of each chip structure. Based on the heating rate of each chip structure and the temperature range change rate of each chip structure, the temperature damage rate of each chip structure to the chip is identified in the database corresponding to each chip structure; the temperature damage rates of all chip structures to the chip are summed and calculated to obtain the chip aging rate.

[0074] In this embodiment, the present invention presets a first ratio value between the heating rate, the temperature range change rate and the failure probability; the heating rate of each chip structure and the temperature range change rate of each chip structure are divided by the first ratio value respectively to obtain the first failure probability of each chip structure.

[0075] In this embodiment, the present invention presets a second ratio value between the temperature conductivity and the failure probability; each temperature conductivity is divided by the second ratio value to obtain a second failure probability of each chip structure connection position.

[0076] The present invention improves the accuracy of calculating the current failure probability of the chip by respectively calculating the first failure probability of different chip structures and the second failure probability of different chip structure connection positions, and then performing weighted summation to obtain the current failure probability.

[0077] Furthermore, based on the chip temperature distribution diagram, the heating rate of each chip structure, the temperature range change rate of each chip structure and the temperature conductivity of each chip structure are obtained, including:

[0078] Based on the chip temperature distribution diagram, obtaining a temperature position change trend and a temperature range change trend;

[0079] Based on the temperature range change trend, the heating rate and temperature range change rate of each chip structure are obtained;

[0080] Based on the temperature position change trend, the temperature conductivity of each chip structure is obtained.

[0081] Further, based on the temperature range change trend, the heating rate and the temperature range change rate of each chip structure are obtained; based on the temperature position change trend, the temperature conductivity of each chip structure is obtained, including:

[0082] Obtain the location range of each chip structure;

[0083] Determine a temperature unit map corresponding to each chip structure based on the position range of each chip structure and the position information of each temperature unit map;

[0084] Based on the temperature range change trend, the temperature position change trend and the temperature unit diagram corresponding to each chip structure, a sub-temperature range change trend of each chip structure and a sub-temperature position change trend of each chip structure are obtained;

[0085] Based on the sub-temperature range change trend of each chip structure, the heating rate of each chip structure and the temperature range change rate of each chip structure are obtained;

[0086] Based on the sub-temperature position variation trend of each chip structure, the temperature conductivity of each chip structure is obtained.

[0087] In this embodiment, the position range of each chip structure is preset, and based on the position information of each temperature unit diagram and the position range of each chip structure, the temperature unit diagrams corresponding to each chip structure are determined; based on the temperature range change trend, the temperature position change trend and the temperature unit diagrams corresponding to each chip structure, the sub-temperature range change trend of each chip structure and the sub-temperature position change trend of each chip structure are identified; based on each sub-temperature position change trend, the temperature position change amount corresponding to each chip structure per unit time length is identified, and the temperature position change amount corresponding to the unit time length is used as the temperature conductivity of each chip structure.

[0088] In this embodiment, based on the sub-temperature range change trend of each chip structure, the temperature increase value per unit time and the temperature range extension time per unit time are identified to obtain the heating rate of each chip structure and the temperature range change rate of each chip structure.

[0089] Further, the temperature position change trend and the temperature range change trend are obtained based on the chip temperature distribution diagram, including:

[0090] For the chip temperature distribution map at each moment, the chip temperature distribution map is divided into a number of temperature unit maps, the position information of each temperature unit map is obtained, and the average temperature data of each temperature unit map is calculated;

[0091] The average temperature data of each temperature unit graph at each moment is sorted in chronological order to obtain the sub-temperature change information of each temperature unit graph;

[0092] Based on the position information of each temperature unit graph and the sub-temperature change information of each temperature unit graph, the temperature position change trend and the temperature range change trend are obtained.

[0093] In this embodiment, the temperature position change trend and the temperature range change trend are used as the temperature distribution change information of the chip.

[0094] In this embodiment, the chip temperature distribution map is divided into a plurality of temperature unit maps, specifically: the chip temperature distribution map is divided into temperature unit maps of the same image size by performing equal grid splitting.

[0095] In this embodiment, each temperature unit diagram includes a temperature area ratio corresponding to each temperature data; the present invention calculates the average temperature data of each temperature unit diagram based on the temperature ratio corresponding to each temperature data and each temperature data.

[0096] In this embodiment, based on the position information of each temperature unit graph and the sub-temperature change information of each temperature unit graph, the temperature position change trend and the temperature range change trend are obtained, specifically: the sub-temperature change information of each unit unit graph is projected to the position information of each temperature unit graph to obtain the chip temperature distribution change graph of the chip; based on the temperature distribution change graph, the spread range trend of each temperature data and the range position movement trend of each temperature data are identified; the spread range trend of each temperature data is used as the temperature range change trend of the new product, and the range position movement trend of each temperature data is used as the temperature position change trend of the chip.

[0097] The present invention identifies the temperature position change trend and temperature range change trend of the chip, thereby judging the temperature transmission condition and temperature change condition of each chip structure, thereby improving the comprehensiveness and accuracy of the temperature change analysis of the chip.

[0098] Further, in step 103, obtaining a current damage rate based on the current failure probability and the chip operation information includes:

[0099] Based on the chip operation information, generate operation status distribution information;

[0100] Based on the operation status distribution information, obtaining chip stability evaluation information and chip trend evaluation information;

[0101] Based on the chip stability evaluation information, obtaining the chip stability degree;

[0102] Based on the chip trend evaluation information, obtaining the chip trend amplitude and the chip abnormal trend degree;

[0103] Based on the current failure probability and the duration of the current period, the failure probability change rate is calculated;

[0104] The chip stability, the chip trend amplitude, the chip abnormal trend degree and the failure probability change rate are input into a preset life assessment network to obtain the current damage rate.

[0105] In this embodiment, the operation status distribution information is the change distribution information of the operation status of the chip, and the operation status is determined by analyzing the chip operation information of the chip at each moment. The operation status of the chip is the status corresponding to different operation data ranges, and the operation data includes operation data of different data types, and the data types include but are not limited to operation rate type, error number type, average waiting time type, etc.

[0106] In this embodiment, the chip trend amplitude and the chip abnormal trend degree are obtained based on the chip trend evaluation information, specifically: based on the chip trend evaluation information, it is determined whether the chip is tending to an abnormal operating state, when the chip is not tending to an abnormal operating state, the chip abnormal trend degree is determined to be 0, and when the chip is tending to an abnormal operating state, the ratio of the chip trend amplitude to 90 degrees is used as the chip abnormal trend degree. The chip trend amplitude is the angle value corresponding to the trend slope of the chip.

[0107] In this embodiment, the failure probability change rate is calculated based on the current failure probability and the current time period length, specifically: the current failure probability is subtracted from the chip failure probability obtained in the last acquisition to obtain the chip failure probability growth value; the failure probability growth value is divided by the length of the current time period to obtain the failure probability change rate.

[0108] In this embodiment, the preset life assessment network is an artificial neural network based on a reinforcement learning neural network. After the initial artificial neural network is trained with the sample data of each chip and the sample damage rate corresponding to the sample data of each chip, the preset life assessment network is obtained.

[0109] The present invention obtains data information related to each life assessment of the chip by performing numerical analysis on the evaluation information, and then analyzes the current damage rate of the chip through a preset life assessment network, thereby improving the accuracy of calculating the current damage rate.

[0110] Further, generating the operation status distribution information based on the chip operation information includes:

[0111] Based on the chip operation information, obtaining operation data corresponding to each moment;

[0112] In the preset operation database, obtain the data range to which each operation data belongs;

[0113] Determine the operation status corresponding to each operation data based on the data range to which each operation data belongs;

[0114] Based on the operating status corresponding to each operating data at each moment, the target operating status at each moment is obtained;

[0115] The target operating status at each moment is sorted according to the time sequence to generate operating status distribution information.

[0116] In this embodiment, each operating data is operating data of each data type; the preset operating database includes each data range of each data type and the chip operating status corresponding to each data range.

[0117] In this embodiment, the target operating state at each moment is obtained based on the operating state corresponding to each operating data at each moment, specifically: identifying the operating state corresponding to the most operating data among the operating states corresponding to all the operating data as the target operating state at that moment.

[0118] The present invention determines the target operating state at each moment after respectively identifying the operating state corresponding to each operating data in the chip operating information at each moment, thereby distributing and arranging the operating state distribution information of the chip, thereby improving the accuracy of the operating state distribution information.

[0119] Further, the obtaining chip stability evaluation information and chip trend evaluation information based on the operating status distribution information includes:

[0120] Based on the operation status distribution information, a chip operation status trend, a chip operation status fluctuation range, and a chip status fluctuation range trend are obtained;

[0121] Obtain chip trend evaluation information based on the chip operation status trend through a preset status trend indicator evaluation strategy;

[0122] Through a preset state stability index evaluation strategy, chip stability evaluation information is obtained based on the chip operating state fluctuation range and the chip state fluctuation range trend.

[0123] In this embodiment, the chip operating state fluctuation range is the average state fluctuation range of the chip.

[0124] In this embodiment, the operating status of the chip ranges from good to bad: good status, normal status, stuck status, faulty status, abnormal status, etc.

[0125] In this embodiment, the state stability index evaluation strategy and the state trend index evaluation strategy are both chip index evaluation strategies. The state stability index evaluation strategy is used to evaluate the stability of the chip's operating state, and the state trend index evaluation strategy is used to evaluate the state trend of the chip to characterize the direction of the chip's trend.

[0126] In this embodiment, the chip trend evaluation information is obtained based on the chip operation state trend through the preset state trend indicator evaluation strategy, specifically: identifying the trend angle of the chip operation state trend and the current operation state trend; based on the trend angle, calculating the state change rate of the chip; based on the preset state trend indicator evaluation strategy, identifying the first evaluation value corresponding to the current operation state trend and the second evaluation value corresponding to the state change rate. In the first evaluation value range and the second evaluation value range corresponding to each evaluation information of the state trend indicator evaluation strategy, identify the target first evaluation value range corresponding to the first evaluation value and the target second evaluation value range corresponding to the second evaluation value. Finally, based on the above correspondence, identify the target evaluation information corresponding to the target first evaluation value range and the target second evaluation value range to obtain the chip trend evaluation information of the chip.

[0127] In this embodiment, the state trend indicator parity strategy includes the correspondence between the operating state trend of each chip and the first evaluation value, the correspondence between each state change rate and the second evaluation value, and the correspondence between the first evaluation value range and the second evaluation value range corresponding to each evaluation information.

[0128] In this embodiment, the state stability index evaluation strategy includes the fluctuation range of the operating state of each chip, and the correspondence between the trend range corresponding to the trend of the state fluctuation range of each chip and the stability evaluation information. By querying the above correspondence, the chip operating state fluctuation range and the chip stability evaluation information corresponding to the chip state fluctuation range trend can be identified.

[0129] The present invention evaluates chip trend evaluation information and chip stability evaluation information respectively through a state stability index evaluation strategy and a state trend index evaluation strategy, thereby ensuring the efficiency and accuracy of the chip stability evaluation information and chip trend evaluation information of the identified chip.

[0130] Furthermore, in step 104, the evaluating the remaining life of the chip based on the current damage rate and the chip aging rate includes:

[0131] Obtain the life span corresponding to different damage rates and the life attenuation ratio corresponding to different aging rates;

[0132] Based on the current damage rate and the chip aging rate, the current life span and the current life attenuation ratio are obtained from the life spans corresponding to the different damage rates and the life attenuation ratios corresponding to the different aging rates;

[0133] Based on the current life span and the current life decay ratio, the remaining life of the chip is evaluated.

[0134] The present invention calculates the remaining life of the chip after comprehensively analyzing the damage rate and aging rate of each chip, thereby improving the accuracy of evaluating the remaining life of the chip.

[0135] The chip life assessment method provided in the embodiment of the present application can be applied in different application environments. The method can be applied to a terminal, a server, or a system including a terminal and a server, and implemented through the interaction between the terminal and the server. The terminal can be, but is not limited to, various personal computers, laptops, smart phones, tablet computers, etc.

[0136] Accordingly, in order to solve the above technical problems, the present invention also provides a chip life assessment system. Figure 2 , Figure 2 A schematic structural diagram of an embodiment of a chip life assessment system provided by the present invention.

[0137] like Figure 2 As shown, the chip life assessment system 20 includes: a data acquisition module 201, a data calculation module 202, a damage rate acquisition module 203 and a life assessment module 204;

[0138] The data acquisition module 201 is used to acquire chip operation information and chip temperature distribution diagram in the current period;

[0139] The data calculation module 202 is used to obtain the chip aging rate and current failure probability based on the chip temperature distribution map;

[0140] The damage rate acquisition module 203 is used to obtain the current damage rate based on the current failure probability and the chip operation information;

[0141] The lifespan assessment module 204 is used to assess the remaining lifespan of the chip based on the current damage rate and the chip aging rate.

[0142] Each module in the above chip life assessment system can be implemented in whole or in part by software, hardware, or a combination thereof. Each module can be embedded in or independent of a processor in a computer device in the form of hardware, or can be stored in a memory in a computer device in the form of software, so that the processor can call and execute operations corresponding to each module.

[0143] In one embodiment, a computer device is provided. The computer device may be a terminal, and its internal structure diagram may be as follows: Figure 3As shown. The computer device includes a processor, a memory, a communication interface, a display screen and an input system connected through a system bus. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The communication interface of the computer device is used to communicate with an external terminal in a wired or wireless manner, and the wireless manner can be achieved through WIFI, a mobile cellular network, NFC (near field communication) or other technologies. When the computer program is executed by the processor, a chip life assessment method is implemented. The display screen of the computer device can be a liquid crystal display screen or an electronic ink display screen, and the input system of the computer device can be a touch layer covered on the display screen, or a button, trackball or touchpad set on the computer device housing, or an external keyboard, touchpad or mouse, etc.

[0144] Those skilled in the art will understand that Figure 3 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0145] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties.

[0146] An embodiment of the present invention further provides a storage medium on which a computer program is stored. When the computer program is executed by a processor, the steps of the chip life assessment method as described in any one of the above items are implemented.

[0147] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to the memory, database or other medium used in the embodiments provided in the present application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The database involved in each embodiment provided in this application may include at least one of a relational database and a non-relational database. Non-relational databases may include distributed databases based on blockchains, etc., but are not limited to this. The processor involved in each embodiment provided in this application may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, etc., but are not limited to this.

[0148] Compared with the prior art, the embodiments of the present invention have the following beneficial effects:

[0149] The present invention obtains the current damage rate and chip aging rate through the acquired chip operation information and chip temperature distribution diagram, and evaluates the remaining life of the chip based on the current damage rate and the chip aging rate, wherein the damage rate and chip aging rate can better characterize the degree of damage of the chip, and the degree of damage of the chip is highly correlated with the life of the chip. The present invention evaluates the remaining life of the chip from the perspective of the degree of damage of the chip, which can avoid the problem of comprehensive testing of the chip through multiple test instruments and complex test processes, which consumes a lot of resource costs, time costs and manpower costs, thereby effectively improving the efficiency of chip life evaluation. In addition, the present invention evaluates the remaining life of the chip from the perspective of the degree of damage of the chip through temperature distribution recognition and operation status recognition, which improves the efficiency of evaluating the chip life while ensuring the accuracy of identifying the chip life.

[0150] The specific embodiments described above further describe the purpose, technical scheme and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the scope of protection of the present invention. It should be understood that although the steps in the flowcharts involved in the above embodiments are displayed in sequence according to the instructions of the arrows, these steps are not necessarily executed in sequence in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction on the execution of these steps, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above embodiments may include multiple steps or multiple stages, and these steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps. The technical features of the above embodiments can be combined arbitrarily. In order to make the description concise, all possible combinations of the technical features in the above embodiments are not described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification. It is particularly pointed out that for those skilled in the art, any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A chip life assessment method, characterized in that: include: Obtain chip operation information and chip temperature distribution diagram for the current period; Based on the chip temperature distribution diagram, obtaining the chip aging rate and current failure probability; Based on the current failure probability and the chip operation information, a current damage rate is obtained; The remaining life of the chip is evaluated based on the current damage rate and the chip aging rate.

2. A chip life assessment method as claimed in claim 1, characterized in that: The obtaining of the chip aging rate and the current failure probability based on the chip temperature distribution diagram includes: Determine each chip structure of the chip and the connection position of each chip structure of the chip; Based on the chip temperature distribution diagram, a heating rate of each chip structure, a temperature range change rate of each chip structure, and a temperature conductivity of each chip structure are obtained; Based on the heating rate of each chip structure and the temperature range change rate of each chip structure, the chip aging rate and the first failure probability of each chip structure are calculated; Based on the temperature conductivity of each chip structure, a second failure probability of a connection position of each chip structure is obtained; According to the first preset weight value of each chip structure and the second preset weight value of each chip structure connection position, the first failure probability of all chip structures and the second failure probability of all chip structure connection positions are weighted summed to obtain the current failure probability.

3. A chip life assessment method as claimed in claim 2, characterized in that: The method of obtaining the heating rate of each chip structure, the temperature range change rate of each chip structure and the temperature conductivity of each chip structure based on the chip temperature distribution diagram includes: Based on the chip temperature distribution diagram, obtaining a temperature position change trend and a temperature range change trend; Based on the temperature range change trend, the heating rate and temperature range change rate of each chip structure are obtained; Based on the temperature position change trend, the temperature conductivity of each chip structure is obtained.

4. A chip life assessment method as claimed in claim 3, characterized in that: The step of obtaining a temperature position change trend and a temperature range change trend based on the chip temperature distribution diagram includes: For the chip temperature distribution map at each moment, the chip temperature distribution map is divided into a number of temperature unit maps, the position information of each temperature unit map is obtained, and the average temperature data of each temperature unit map is calculated; The average temperature data of each temperature unit graph at each moment is sorted in chronological order to obtain the sub-temperature change information of each temperature unit graph; Based on the position information of each temperature unit graph and the sub-temperature change information of each temperature unit graph, the temperature position change trend and the temperature range change trend are obtained.

5. A chip life assessment method as claimed in claim 1, characterized in that: The obtaining of the current damage rate based on the current failure probability and the chip operation information includes: Based on the chip operation information, generate operation status distribution information; Based on the operating status distribution information, obtaining chip stability evaluation information and chip trend evaluation information; Based on the chip stability evaluation information, obtaining the chip stability degree; Based on the chip trend evaluation information, obtaining the chip trend amplitude and the chip abnormal trend degree; Based on the current failure probability and the duration of the current period, the failure probability change rate is calculated; The chip stability, the chip trend amplitude, the chip abnormal trend degree and the failure probability change rate are input into a preset life assessment network to obtain the current damage rate.

6. A chip life assessment method as claimed in claim 5, characterized in that: The generating the operation status distribution information based on the chip operation information includes: Based on the chip operation information, obtaining operation data corresponding to each moment; In the preset operation database, obtain the data range to which each operation data belongs; Determine the operation status corresponding to each operation data based on the data range to which each operation data belongs; Based on the operating status corresponding to each operating data at each moment, the target operating status at each moment is obtained; The target operating status at each moment is sorted according to the time sequence to generate operating status distribution information.

7. A chip life assessment method as claimed in claim 5, characterized in that: The obtaining chip stability evaluation information and chip trend evaluation information based on the operation status distribution information includes: Based on the operation status distribution information, a chip operation status trend, a chip operation status fluctuation range, and a chip status fluctuation range trend are obtained; Obtain chip trend evaluation information based on the chip operation status trend through a preset status trend indicator evaluation strategy; Through a preset state stability index evaluation strategy, chip stability evaluation information is obtained based on the chip operating state fluctuation range and the chip state fluctuation range trend.

8. A chip life assessment method as claimed in claim 1, characterized in that: The evaluating the remaining life of the chip based on the current damage rate and the chip aging rate includes: Obtain the life span corresponding to different damage rates and the life attenuation ratio corresponding to different aging rates; Based on the current damage rate and the chip aging rate, the current life span and the current life attenuation ratio are obtained from the life spans corresponding to the different damage rates and the life attenuation ratios corresponding to the different aging rates; Based on the current life span and the current life decay ratio, the remaining life of the chip is evaluated.

9. A chip life assessment system, characterized in that: include: Data acquisition module, data calculation module, damage rate acquisition module and life assessment module; Wherein, the data acquisition module is used to obtain the chip operation information and chip temperature distribution diagram of the current period; The data calculation module is used to obtain the chip aging rate and current failure probability based on the chip temperature distribution map; The damage rate acquisition module is used to obtain the current damage rate based on the current failure probability and the chip operation information; The life evaluation module is used to evaluate the remaining life of the chip based on the current damage rate and the chip aging rate.

10. A storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the chip life assessment method according to any one of claims 1 to 8 are implemented.

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