Chip life evaluation method, system and storage medium

Abstract

The application discloses a kind of chip life evaluation method, system and storage medium, the chip life evaluation method, comprising: obtaining the chip operating information and chip temperature distribution of current period;Based on the chip temperature distribution, obtain chip aging rate and current failure probability;Based on the current failure probability and the chip operating information, obtain current damage rate;Based on the current damage rate and the chip aging rate evaluation chip's remaining life.Damage rate and chip aging rate can better characterize the damage degree of chip, and the damage degree of chip is highly related to the life of chip, the remaining life of chip is evaluated from the damage degree of chip as evaluation angle in the application, can avoid the problem that chip is tested by a variety of test instruments and complex test process, and a large amount of resource cost, time cost and manpower cost problem, and then the life evaluation efficiency of chip can be effectively improved.

Description

Technical Field

[0001] This invention relates to the fields of artificial intelligence and semiconductor lifespan testing technology, and in particular to a chip lifespan assessment method, system, and storage medium. Background Technology

[0002] With the continuous upgrading of chip hardware, the anti-interference capability, computing efficiency, lifespan, and application range of chips are constantly improving. However, due to the diversity of external environments and the richness of operating conditions, the application frequency of chips is constantly increasing, and they operate under high voltage and high current for extended periods, accompanied by frequent turn-on and turn-off operations, which places higher demands on chip reliability. To avoid chip failures during practical applications, which could lead to task failures and delays in normal task execution, it is often necessary to estimate the chip's lifespan to ensure timely replacement. Therefore, how to accurately estimate chip lifespan is a current research focus.

[0003] Traditional chip lifespan prediction methods involve performing various functional tests on the chip and then manually analyzing the test results to determine its remaining lifespan. However, this method requires multiple testing instruments and complex testing procedures, consuming significant resources and manpower. Furthermore, the entire testing and manual analysis process is time-consuming, resulting in low efficiency in chip lifespan prediction. Summary of the Invention

[0004] This invention provides a chip lifetime assessment method, system, and storage medium to solve the above-mentioned technical problems and effectively improve the efficiency of chip lifetime assessment.

[0005] To address the aforementioned technical problems, this invention provides a chip lifetime assessment method, comprising:

[0006] Obtain chip operating information and chip temperature distribution map for the current time period;

[0007] Based on the chip temperature distribution map, the chip aging rate and current failure probability are obtained;

[0008] Based on the current failure probability and the chip operating information, the current damage rate is obtained;

[0009] The remaining lifespan of the chip is assessed based on the current damage rate and the chip aging rate.

[0010] The beneficial effects of this invention are as follows:

[0011] This invention obtains the current damage rate and chip aging rate by acquiring chip operating information and chip temperature distribution maps, and evaluates the remaining lifespan of the chip based on the current damage rate and chip aging rate. The damage rate and chip aging rate can effectively characterize the degree of chip damage, and the degree of chip damage is highly correlated with the chip's lifespan. This invention evaluates the remaining lifespan of the chip from the perspective of the degree of chip damage, which avoids the problem of consuming a lot of resources, time, and manpower costs by conducting comprehensive testing of the chip through multiple testing instruments and complex testing procedures. Thus, it can effectively improve the efficiency of chip lifespan evaluation.

[0012] As a preferred embodiment, obtaining the chip aging rate and current failure probability based on the chip temperature distribution map includes:

[0013] Determine the structure of each chip and the connection points of each chip structure;

[0014] Based on the chip temperature distribution map, the heating rate of each chip structure, the rate of change of the temperature range of each chip structure, and the temperature conductivity of each chip structure are obtained.

[0015] Based on the heating rate and temperature range change rate of each chip structure, the chip aging rate and the first failure probability of each chip structure are calculated.

[0016] Based on the temperature conductivity of each chip structure, the second failure probability of the connection position of each chip structure is obtained.

[0017] Based on the first preset weight value of each chip structure and the second preset weight value of each chip structure connection position, the first failure probability of all chip structures and the second failure probability of all chip structure connection positions are weighted and summed to obtain the current failure probability.

[0018] As a preferred embodiment, the step of obtaining the heating rate, the rate of change of temperature range of each chip structure, and the temperature conductivity of each chip structure based on the chip temperature distribution map includes:

[0019] Based on the chip temperature distribution map, the temperature location change trend and temperature range change trend are obtained;

[0020] Based on the temperature range change trend, the heating rate and temperature range change rate of each chip structure are obtained;

[0021] Based on the temperature location change trend, the temperature conductivity of each chip structure is obtained.

[0022] As a preferred embodiment, obtaining the temperature location change trend and temperature range change trend based on the chip temperature distribution map includes:

[0023] For each moment of the chip temperature distribution map, the chip temperature distribution map is divided into several temperature unit maps, the location information of each temperature unit map is obtained, and the average temperature data of each temperature unit map is calculated.

[0024] The average temperature data of each temperature cell at each time point are sorted in chronological order to obtain the sub-temperature change information of each temperature cell.

[0025] Based on the location information of each temperature unit diagram and the sub-temperature change information of each temperature unit diagram, the temperature location change trend and the temperature range change trend are obtained.

[0026] As a preferred embodiment, obtaining the current damage rate based on the current failure probability and the chip operating information includes:

[0027] Based on the chip's operating information, operating status distribution information is generated;

[0028] Based on the operating state distribution information, chip stability evaluation information and chip trend evaluation information are obtained;

[0029] Based on the chip stability evaluation information, the chip stability level is obtained;

[0030] Based on the chip trend evaluation information, the chip trend magnitude and the degree of chip abnormal trend are obtained;

[0031] The rate of change of the failure probability is calculated based on the current failure probability and the duration of the current time period.

[0032] The chip stability, chip trend magnitude, chip anomaly trend degree, and failure probability change rate are input into a preset lifetime assessment network to obtain the current damage rate.

[0033] As a preferred embodiment, generating operating status distribution information based on the chip operating information includes:

[0034] Based on the chip's operating information, obtain the operating data corresponding to each moment;

[0035] In the preset running database, obtain the data range to which each running data belongs;

[0036] Based on the data range to which each piece of running data belongs, determine the running status corresponding to each piece of running data;

[0037] Based on the running status corresponding to each running data at each time moment, the target running status at each time moment is obtained;

[0038] The target running status at each moment is sorted according to time sequence to generate running status distribution information.

[0039] As a preferred embodiment, obtaining chip stability evaluation information and chip trend evaluation information based on the operating state distribution information includes:

[0040] Based on the operating state distribution information, the chip operating state trend, the chip operating state fluctuation range, and the chip state fluctuation range trend are obtained.

[0041] By using a preset state trend index evaluation strategy, chip trend evaluation information is obtained based on the chip's operating state trend.

[0042] By using a preset state stability index evaluation strategy, chip stability evaluation information is obtained based on the fluctuation range of the chip's operating state and the trend of the chip's state fluctuation range.

[0043] As a preferred embodiment, assessing the remaining lifespan of the chip based on the current damage rate and the chip aging rate includes:

[0044] Obtain the lifespan corresponding to different damage rates and the lifespan decay ratio corresponding to different aging rates;

[0045] Based on the current damage rate and the chip aging rate, the current lifespan and the current lifespan decay ratio are obtained from the lifespan corresponding to different damage rates and the lifespan decay ratio corresponding to different aging rates.

[0046] The remaining lifespan of the chip is assessed based on the current lifespan duration and the current lifespan decay rate.

[0047] Accordingly, in order to solve the above-mentioned technical problems, the present invention also provides a chip lifetime assessment system, including: a data acquisition module, a data calculation module, a damage rate acquisition module and a lifetime assessment module;

[0048] The data acquisition module is used to acquire chip operating information and chip temperature distribution map for the current time period;

[0049] The data calculation module is used to obtain the chip aging rate and current failure probability based on the chip temperature distribution map;

[0050] The damage rate acquisition module is used to obtain the current damage rate based on the current failure probability and the chip operating information;

[0051] The lifespan assessment module is used to assess the remaining lifespan of the chip based on the current damage rate and the chip aging rate. Attached Figure Description

[0052] Figure 1: A schematic flowchart of an embodiment of a chip lifetime assessment method provided by the present invention;

[0053] Figure 2 : A schematic diagram of the structure of an embodiment of a chip lifetime assessment system provided by the present invention;

[0054] Figure 3 : A schematic diagram of the structure of an embodiment of a computer device provided by the present invention. Detailed Implementation

[0055] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0056] Traditional chip lifespan prediction methods involve performing various functional tests on the chip and then manually analyzing the test results to determine its remaining lifespan. However, this method requires multiple testing instruments and complex testing procedures, consuming significant resources and manpower. Furthermore, the entire testing and manual analysis process is time-consuming, resulting in low efficiency in chip lifespan prediction.

[0057] Example 1

[0058] To address the aforementioned technical problems, this invention provides a chip lifetime assessment method, system, and storage medium, thereby effectively improving the efficiency of chip lifetime assessment.

[0059] Please refer to Figure 1 This is a flowchart illustrating one embodiment of a chip lifetime assessment method provided by this invention.

[0060] like Figure 1 As shown, the chip lifetime assessment method includes steps 101 to 104, specifically:

[0061] Step 101: Obtain the chip operating information and chip temperature distribution map for the current time period;

[0062] Step 102: Based on the chip temperature distribution map, obtain the chip aging rate and current failure probability;

[0063] Step 103: Based on the current failure probability and the chip operating information, obtain the current damage rate;

[0064] Step 104: Evaluate the remaining lifespan of the chip based on the current damage rate and the chip aging rate.

[0065] This invention obtains the current damage rate and chip aging rate by acquiring chip operating information and chip temperature distribution maps, and evaluates the remaining lifespan of the chip based on the current damage rate and chip aging rate. The damage rate and chip aging rate can effectively characterize the degree of chip damage, and the degree of chip damage is highly correlated with the chip's lifespan. This invention evaluates the remaining lifespan of the chip from the perspective of the degree of chip damage, which avoids the problem of consuming a lot of resources, time, and manpower costs by conducting comprehensive testing of the chip through multiple testing instruments and complex testing procedures. Thus, it can effectively improve the efficiency of chip lifespan evaluation.

[0066] Further, in step 101, the present invention collects sub-chip operation information in real time through a pre-set operation detection program on the chip, and transmits the pre-set duration of sub-chip operation information to the terminal after each collection, thus obtaining the chip operation information for the current time period. This pre-set time period is a time period preset by the operator on the terminal and can be changed as the operator adjusts it. Then, an infrared temperature sensing image monitoring device set on the outside of the chip is used to collect the chip temperature distribution map on the chip surface during the current time period.

[0067] Further, in step 102, obtaining the chip aging rate and current failure probability based on the chip temperature distribution map includes:

[0068] Determine the structure of each chip and the connection points of each chip structure;

[0069] Based on the chip temperature distribution map, the heating rate of each chip structure, the rate of change of the temperature range of each chip structure, and the temperature conductivity of each chip structure are obtained.

[0070] Based on the heating rate and temperature range change rate of each chip structure, the chip aging rate and the first failure probability of each chip structure are calculated.

[0071] Based on the temperature conductivity of each chip structure, the second failure probability of the connection position of each chip structure is obtained.

[0072] Based on the first preset weight value of each chip structure and the second preset weight value of each chip structure connection position, the first failure probability of all chip structures and the second failure probability of all chip structure connection positions are weighted and summed to obtain the current failure probability.

[0073] In this embodiment, the aging rate of the chip is calculated based on the heating rate and the temperature range change rate of each chip structure. Specifically, based on the heating rate and temperature range change rate of each chip structure, the temperature damage rate of each chip structure to the chip is identified in the database corresponding to each chip structure; the temperature damage rates of all chip structures to the chip are summed to obtain the chip aging rate.

[0074] In this embodiment, the present invention presets a first ratio value between the heating rate, the temperature range change rate, and the failure probability; the heating rate of each chip structure and the temperature range change rate of each chip structure are divided by the first ratio value to obtain the first failure probability of each chip structure.

[0075] In this embodiment, the present invention presets a second ratio value between temperature conductivity and failure probability; by dividing each temperature conductivity by the second ratio value, the second failure probability of each chip structure connection position is obtained.

[0076] This invention improves the accuracy of calculating the current failure probability of a chip by separately calculating the first failure probability of different chip structures and the second failure probability of different chip structure connection positions, and then weighted summing them to obtain the current failure probability.

[0077] Furthermore, the step of obtaining the heating rate, the rate of change of temperature range of each chip structure, and the temperature conductivity of each chip structure based on the chip temperature distribution map includes:

[0078] Based on the chip temperature distribution map, the temperature location change trend and temperature range change trend are obtained;

[0079] Based on the temperature range change trend, the heating rate and temperature range change rate of each chip structure are obtained;

[0080] Based on the temperature location change trend, the temperature conductivity of each chip structure is obtained.

[0081] Furthermore, the step of obtaining the heating rate and temperature range change rate of each chip structure based on the temperature range change trend; and the step of obtaining the temperature conductivity of each chip structure based on the temperature position change trend, including:

[0082] Obtain the location range of each chip structure;

[0083] Based on the location range of each chip structure and the location information of each temperature unit diagram, the temperature unit diagram corresponding to each chip structure is determined.

[0084] Based on the temperature range variation trend, the temperature position variation trend, and the temperature unit diagram corresponding to each chip structure, the sub-temperature range variation trend and the sub-temperature position variation trend of each chip structure are obtained.

[0085] The heating rate and the temperature range change rate of each chip structure are obtained based on the sub-temperature range change trend of each chip structure.

[0086] The temperature conductivity of each chip structure is obtained based on the temperature change trend of each chip structure's sub-temperature location.

[0087] In this embodiment, the position range of each chip structure is preset, and based on the position information of each temperature unit map and the position range of each chip structure, the temperature unit map corresponding to each chip structure is determined; based on the temperature range change trend, the temperature position change trend, and the temperature unit map corresponding to each chip structure, the sub-temperature range change trend and the sub-temperature position change trend of each chip structure are identified; based on the sub-temperature position change trend, the temperature position change amount corresponding to each chip structure per unit time is identified, and the temperature position change amount corresponding to the unit time is used as the temperature conductivity of each chip structure.

[0088] In this embodiment, based on the sub-temperature range change trend of each chip structure, the temperature increase value per unit time and the temperature range extension time per unit time are identified to obtain the heating rate of each chip structure and the temperature range change rate of each chip structure.

[0089] Furthermore, obtaining the temperature location change trend and temperature range change trend based on the chip temperature distribution map includes:

[0090] For the chip temperature distribution map at each time point, the chip temperature distribution map is divided into several temperature unit maps, the location information of each temperature unit map is obtained, and the average temperature data of each temperature unit map is calculated.

[0091] The average temperature data of each temperature cell at each time point are sorted in chronological order to obtain the sub-temperature change information of each temperature cell.

[0092] Based on the location information of each temperature unit diagram and the sub-temperature change information of each temperature unit diagram, the temperature location change trend and the temperature range change trend are obtained.

[0093] In this embodiment, the temperature location change trend and the temperature range change trend are used as the temperature distribution change information of the chip.

[0094] In this embodiment, dividing the chip temperature distribution map into several temperature unit maps specifically involves: dividing the chip temperature distribution map into equal grids, resulting in temperature unit maps of the same image size.

[0095] In this embodiment, each temperature cell map contains the temperature area percentage corresponding to each temperature data; the present invention calculates the average temperature data of each temperature cell map based on the temperature percentage corresponding to each temperature data and each temperature data.

[0096] In this embodiment, obtaining the temperature position change trend and temperature range change trend based on the position information of each temperature unit map and the sub-temperature change information of each temperature unit map specifically involves: projecting the sub-temperature change information of each unit map onto the position information of each temperature unit map to obtain the chip temperature distribution change map; based on the temperature distribution change map, identifying the spread range trend of each temperature data and the range position movement trend of each temperature data; using the spread range trend of each temperature data as the temperature range change trend of the new product, and using the range position movement trend of each temperature data as the temperature position change trend of the chip.

[0097] This invention improves the comprehensiveness and accuracy of temperature change analysis of chips by identifying the temperature location change trend and temperature range change trend of the chip.

[0098] Further, in step 103, obtaining the current damage rate based on the current failure probability and the chip operating information includes:

[0099] Based on the chip's operating information, operating status distribution information is generated;

[0100] Based on the operating state distribution information, chip stability evaluation information and chip trend evaluation information are obtained;

[0101] Based on the chip stability evaluation information, the chip stability level is obtained;

[0102] Based on the chip trend evaluation information, the chip trend magnitude and the degree of chip abnormal trend are obtained;

[0103] The rate of change of the failure probability is calculated based on the current failure probability and the duration of the current time period.

[0104] The chip stability, chip trend magnitude, chip anomaly trend degree, and failure probability change rate are input into a preset lifetime assessment network to obtain the current damage rate.

[0105] In this embodiment, the operating state distribution information refers to the distribution information of changes in the chip's operating state. This operating state is determined by analyzing the chip's operating information at various times. The chip's operating state corresponds to different ranges of operating data, which includes operating data of different data types, including but not limited to, operating rate type, error count type, and average waiting time type.

[0106] In this embodiment, obtaining the chip trend amplitude and the degree of chip abnormal trend based on the chip trend evaluation information specifically involves: determining whether the chip is trending towards an abnormal operating state based on the chip trend evaluation information; when the chip is not trending towards an abnormal operating state, determining the degree of chip abnormal trend as 0; when the chip is trending towards an abnormal operating state, using the proportion of the chip trend amplitude to 90 degrees as the degree of chip abnormal trend. The chip trend amplitude is the angle value corresponding to the chip's trend slope.

[0107] In this embodiment, the calculation of the fault probability change rate based on the current fault probability and the current time period duration specifically involves: subtracting the chip fault probability obtained in the previous collection from the current fault probability to obtain the chip fault probability growth value; and dividing the fault probability growth value by the current time period duration to obtain the fault probability change rate.

[0108] In this embodiment, the preset lifetime assessment network is an artificial neural network based on reinforcement learning. The preset lifetime assessment network is obtained by training the initial artificial neural network using sample data from each chip and the corresponding sample damage rate for each chip.

[0109] This invention obtains data related to chip lifespan assessment by performing numerical analysis on evaluation information, and then analyzes the chip's current damage rate through a preset lifespan assessment network, thereby improving the accuracy of calculating the current damage rate.

[0110] Furthermore, generating operating status distribution information based on the chip's operating information includes:

[0111] Based on the chip's operating information, obtain the operating data corresponding to each moment;

[0112] In the preset running database, obtain the data range to which each running data belongs;

[0113] Based on the data range to which each piece of running data belongs, determine the running status corresponding to each piece of running data;

[0114] Based on the running status corresponding to each running data at each time moment, the target running status at each time moment is obtained;

[0115] The target running status at each moment is sorted according to time sequence to generate running status distribution information.

[0116] In this embodiment, each running data is running data of a different data type; the preset running database includes the data range of each data type and the chip running status corresponding to each data range.

[0117] In this embodiment, obtaining the target running state at each time based on the running state corresponding to each running data at each time specifically involves: identifying the running state corresponding to the most running data among all running states and using it as the target running state at that time.

[0118] This invention identifies the operating state corresponding to each operating data in the chip's operating information at each moment, determines the target operating state at each moment, and then distributes and arranges the chip's operating state distribution information, thereby improving the accuracy of the operating state distribution information.

[0119] Furthermore, obtaining chip stability evaluation information and chip trend evaluation information based on the operating state distribution information includes:

[0120] Based on the operating state distribution information, the chip operating state trend, the chip operating state fluctuation range, and the chip state fluctuation range trend are obtained.

[0121] By using a preset state trend index evaluation strategy, chip trend evaluation information is obtained based on the chip's operating state trend.

[0122] By using a preset state stability index evaluation strategy, chip stability evaluation information is obtained based on the fluctuation range of the chip's operating state and the trend of the chip's state fluctuation range.

[0123] In this embodiment, the fluctuation range of the chip's operating state is the average fluctuation range of the chip's state.

[0124] In this embodiment, the chip's operating state range from good to bad is as follows: good state, normal state, stuck state, faulty state, abnormal state, etc.

[0125] In this embodiment, both the state stability index evaluation strategy and the state trend index evaluation strategy are chip index evaluation strategies. The state stability index evaluation strategy is used to evaluate the stability of the chip's operating state, while the state trend index evaluation strategy is used to evaluate the quality of the chip's state trend tendency, thus characterizing the direction of the chip's trend.

[0126] In this embodiment, the step of obtaining chip trend evaluation information based on the chip's operating state trend using a preset state trend indicator evaluation strategy specifically involves: identifying the trend angle of the chip's operating state trend and the current operating state trend; calculating the chip's state change rate based on the trend angle; and identifying a first evaluation value corresponding to the current operating state trend and a second evaluation value corresponding to the state change rate based on the preset state trend indicator evaluation strategy. Within the first and second evaluation value ranges corresponding to each evaluation information in the state trend indicator evaluation strategy, a target first evaluation value range corresponding to the first evaluation value and a target second evaluation value range corresponding to the second evaluation value are identified. Finally, based on the above correspondence, target evaluation information corresponding to the target first and target second evaluation value ranges is identified to obtain the chip's chip trend evaluation information.

[0127] In this embodiment, the state trend index parity strategy includes the correspondence between the operating state trend of each chip and the first evaluation value, the correspondence between the rate of change of each state and the second evaluation value, and the correspondence between the first evaluation value range and the second evaluation value range corresponding to each evaluation information.

[0128] In this embodiment, the state stability index evaluation strategy includes the fluctuation range of each chip's operating state, and the correspondence between the trend range corresponding to the fluctuation range of each chip's state and the stability evaluation information. By querying the above correspondence, the fluctuation range of the chip's operating state and the chip stability evaluation information corresponding to the fluctuation range trend of the chip's state can be identified.

[0129] This invention evaluates chip trend evaluation information and chip stability evaluation information respectively through a state stability index evaluation strategy and a state trend index evaluation strategy, ensuring the efficiency and accuracy of the identified chip stability evaluation information and chip trend evaluation information.

[0130] Further, in step 104, assessing the remaining lifespan of the chip based on the current damage rate and the chip aging rate includes:

[0131] Obtain the lifespan corresponding to different damage rates and the lifespan decay ratio corresponding to different aging rates;

[0132] Based on the current damage rate and the chip aging rate, the current lifespan and the current lifespan decay ratio are obtained from the lifespan corresponding to different damage rates and the lifespan decay ratio corresponding to different aging rates.

[0133] The remaining lifespan of the chip is assessed based on the current lifespan duration and the current lifespan decay rate.

[0134] This invention improves the accuracy of assessing the remaining lifespan of chips by comprehensively analyzing the damage rate and aging rate of each chip.

[0135] The chip lifetime assessment method provided in this application can be applied to different application environments. This method can be applied to terminals, servers, and systems including both terminals and servers, and is implemented through interaction between the terminal and the server. The terminal can be, but is not limited to, various personal computers, laptops, smartphones, tablets, etc.

[0136] Accordingly, to address the aforementioned technical problems, this invention also provides a chip lifetime assessment system. Please refer to... Figure 2 , Figure 2 This is a schematic diagram of one embodiment of a chip lifetime assessment system provided by the present invention.

[0137] like Figure 2 As shown, the chip life assessment system 20 includes: a data acquisition module 201, a data calculation module 202, a damage rate acquisition module 203, and a life assessment module 204.

[0138] The data acquisition module 201 is used to acquire chip operating information and chip temperature distribution map for the current time period;

[0139] The data calculation module 202 is used to obtain the chip aging rate and current failure probability based on the chip temperature distribution map;

[0140] The damage rate acquisition module 203 is used to obtain the current damage rate based on the current failure probability and the chip operating information;

[0141] The lifespan assessment module 204 is used to assess the remaining lifespan of the chip based on the current damage rate and the chip aging rate.

[0142] Each module in the aforementioned chip lifetime assessment system can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in the processor of a computer device in hardware form or independent of it, or stored in the memory of the computer device in software form, so that the processor can call and execute the corresponding operations of each module.

[0143] In one embodiment, a computer device is provided, which may be a terminal, and its internal structure diagram may be as follows: Figure 3As shown, the computer device includes a processor, memory, communication interface, display screen, and input system connected via a system bus. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The communication interface is used for wired or wireless communication with external terminals; wireless communication can be achieved through Wi-Fi, mobile cellular networks, NFC (Near Field Communication), or other technologies. When executed by the processor, the computer program implements a chip lifetime assessment method. The display screen can be an LCD screen or an e-ink display screen. The input system can be a touch layer covering the display screen, buttons, a trackball, or a touchpad on the computer device's casing, or an external keyboard, touchpad, or mouse.

[0144] Those skilled in the art will understand that Figure 3 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0145] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties.

[0146] This invention also provides a storage medium storing a computer program thereon, which, when executed by a processor, implements the steps of the chip lifetime assessment method as described in any of the above embodiments.

[0147] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, etc., and are not limited to these.

[0148] Compared with the prior art, the embodiments of the present invention have the following beneficial effects:

[0149] This invention obtains the current damage rate and chip aging rate by acquiring chip operating information and chip temperature distribution maps, and evaluates the chip's remaining lifespan based on the current damage rate and chip aging rate. The damage rate and chip aging rate can effectively characterize the degree of chip damage, and the degree of chip damage is highly correlated with chip lifespan. This invention evaluates the chip's remaining lifespan from the perspective of chip damage degree, avoiding the problem of consuming significant resource, time, and manpower costs associated with comprehensive testing of chips using multiple testing instruments and complex testing procedures, thus effectively improving the efficiency of chip lifespan evaluation. Furthermore, this invention evaluates the chip's remaining lifespan from the perspective of chip damage degree by identifying temperature distribution and operating status, improving the efficiency of chip lifespan evaluation while ensuring the accuracy of chip lifespan identification.

[0150] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the scope of protection of the present invention. It should be understood that although the steps in the flowcharts involved in the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts involved in the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least a portion of the steps or stages in other steps. The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as the combination of these technical features does not contradict each other, it should be considered within the scope of this specification. It should be noted that any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this invention should be included within the scope of protection of this invention for those skilled in the art.

Claims

1. A method of chip lifetime assessment, characterized by, The method comprises the following steps: obtaining chip running information and a chip temperature distribution map of a current period; based on the chip temperature distribution map, obtaining a chip aging rate and a current failure probability; Specifically: determining each chip structure of the chip and the connection position of each chip structure of the chip; based on the chip temperature distribution map, obtaining the temperature rise rate of each chip structure, the temperature range change rate of each chip structure and the temperature conductivity of each chip structure; based on the temperature rise rate of each chip structure and the temperature range change rate of each chip structure, the chip aging rate and the first failure probability of each chip structure are calculated; based on the temperature conductivity of each chip structure, the second failure probability of the connection position of each chip structure is obtained; according to the first preset weight value of each chip structure and the second preset weight value of the connection position of each chip structure, the first failure probability of all chip structures and the second failure probability of all chip structure connection positions are weighted and summed to obtain the current failure probability; based on the current failure probability and the chip running information, the current damage rate is obtained; based on the current damage rate and the chip aging rate, the remaining life of the chip is evaluated.

2. The method of claim 1, wherein the step of determining the chip life is performed by a method comprising: Based on the chip temperature distribution map, the temperature rise rate of each chip structure, the temperature range change rate of each chip structure and the temperature conductivity of each chip structure are obtained, which comprises: based on the chip temperature distribution map, the temperature position change trend and the temperature range change trend are obtained; based on the temperature range change trend, the temperature rise rate and the temperature range change rate of each chip structure are obtained; based on the temperature position change trend, the temperature conductivity of each chip structure is obtained.

3. The method of claim 2, wherein the step of determining the chip life is performed by: determining a chip life of the chip based on the number of times the chip has been used and the number of times the chip has been used in the past. Based on the chip temperature distribution map, the temperature position change trend and the temperature range change trend are obtained, which comprises: for each chip temperature distribution map at each time, the chip temperature distribution map is divided into a plurality of temperature unit maps, the position information of each temperature unit map is obtained and the average temperature data of each temperature unit map is calculated; the average temperature data of each temperature unit map at each time is sorted in time sequence to obtain the sub-temperature change information of each temperature unit map; based on the position information of each temperature unit map and the sub-temperature change information of each temperature unit map, the temperature position change trend and the temperature range change trend are obtained.

4. The method of claim 1, wherein the step of determining the chip life is performed by a method comprising: Based on the current failure probability and the chip running information, the current damage rate is obtained, which comprises: ​ based on the chip running information, generating running state distribution information; based on the running state distribution information, obtaining chip stability evaluation information and chip trend evaluation information; based on the chip stability evaluation information, obtaining the chip stability degree; based on the chip trend evaluation information, obtaining the chip trend amplitude and the chip abnormal trend degree; based on the current failure probability and the current period length, the failure probability change rate is calculated; the chip stability degree, the chip trend amplitude, the chip abnormal trend degree and the failure probability change rate are input into a preset life evaluation network to obtain the current damage rate.

5. The method of claim 4, wherein the step of determining the chip life is performed by: determining a chip life of the chip based on the number of times the chip has been used and the number of times the chip has been used in the past. Based on the chip running information, the running state distribution information is generated, which comprises: based on the chip running information, obtaining running data corresponding to each time; In the preset operation database, the data range to which each operation data belongs is obtained; Based on the data range to which each operation data belongs, the running state corresponding to each operation data is determined; Based on the running state corresponding to each operation data at each time, the target running state at each time is obtained; According to the time sequence, the target running state at each time is sorted to generate running state distribution information.

6. The method of claim 4, wherein the step of determining the chip life is performed by the steps of: determining a number of times the chip has been powered on; and determining a number of times the chip has been powered off. Based on the running state distribution information, chip stability evaluation information and chip trend evaluation information are obtained, including: Based on the running state distribution information, the chip running state trend, the chip running state fluctuation range and the chip state fluctuation range trend are obtained; Through a preset state trend index evaluation strategy, based on the chip running state trend, the chip trend evaluation information is obtained; Through a preset state stability index evaluation strategy, based on the chip running state fluctuation range and the chip state fluctuation range trend, the chip stability evaluation information is obtained.

7. The method of claim 1, wherein the step of determining the chip life is performed by a method comprising: determining a chip life of the chip based on a comparison of the chip life data with a chip life model. Based on the current damage rate and the chip aging rate, the remaining life of the chip is evaluated, including: Obtain the life duration corresponding to different damage rates and the life attenuation ratio corresponding to different aging rates; Based on the current damage rate and the chip aging rate, the current life duration and the current life attenuation ratio are obtained in the life duration corresponding to the different damage rates and the life attenuation ratio corresponding to the different aging rates; Based on the current life duration and the current life attenuation ratio, the remaining life of the chip is evaluated.

8. A chip lifetime evaluation system characterized by comprising: It includes: Data acquisition module, data calculation module, damage rate acquisition module and life evaluation module; The data acquisition module is used to obtain the chip running information and the chip temperature distribution diagram of the current period; The data calculation module is used to obtain the chip aging rate and the current failure probability based on the chip temperature distribution diagram; Specifically: Determine the chip structure of the chip and the connection position of the chip structure of the chip; Based on the chip temperature distribution diagram, the temperature rise rate of each chip structure, the temperature range change rate of each chip structure and the temperature conductivity of each chip structure are obtained; Based on the temperature rise rate of each chip structure and the temperature range change rate of each chip structure, the chip aging rate and the first failure probability of each chip structure are calculated; Based on the temperature conductivity of each chip structure, the second failure probability of each chip structure connection position is obtained; According to the first preset weight value of each chip structure and the second preset weight value of each chip structure connection position, the first failure probability of all chip structures and the second failure probability of all chip structure connection positions are weighted and summed to obtain the current failure probability; The damage rate acquisition module is used to obtain the current damage rate based on the current failure probability and the chip running information; The life evaluation module is used to evaluate the remaining life of the chip based on the current damage rate and the chip aging rate.

9. A storage medium having stored thereon a computer program, characterized in that The computer program is executed by the processor to realize the steps of the chip life evaluation method in any one of claims 1 to 7.

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