Load detection circuit and driving device

Abstract

The application discloses a load detection circuit, comprising a first detection port for receiving a detection current, a first end of a load being coupled to the first detection port, the first end of the load having a first potential; a first resistor, a first end of the first resistor receiving the detection current; a first switch, a first end of the first switch being coupled to a second end of the first resistor; a second detection port, a second end of the first switch being coupled to the second detection port, a second end of the load being coupled to the second detection port, the second end of the load having a second potential; the first switch being closed, the first potential and the second potential being related to the detection current and the first resistor; the first switch being opened, a difference between the first potential and the second potential being less than a first preset value when the load is short-circuited, the difference between the first potential and the second potential being greater than a second preset value when the load is open-circuited; wherein a first current value is greater than a second current value. The application can quickly establish the difference between the first potential and the second potential to realize voltage boosting, thereby reducing the time for voltage establishment. Subsequently, the state of the load is determined by the voltage value of the load.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of load detection, and in particular to a load detection circuit and a driving device. BACKGROUND

[0002] With the rapid development of electronic technology, terminal devices such as audio amplifiers, power amplifiers and various high-precision electronic devices are increasingly widely used. These devices often need to run under high power or specific load conditions to achieve their designed specific functions, such as providing high-quality audio output, driving high-power loads, etc. In order to achieve these functions, the traditional driving method mainly relies on stable power supply and amplifies the signal through an amplifier circuit.

[0003] When the device power is large or a multi-stage amplification structure is adopted (such as connecting another amplifier in the rear stage to achieve linear amplification), the load impedance faced by the system often increases significantly. High-impedance loads put higher requirements on the stability and driving capacity of the power supply, and also bring great challenges to the testing work.

[0004] Traditional load testing methods, such as current-through voltage measurement, can reflect the electrical characteristics of the load to some extent, but have obvious shortcomings when facing high-impedance loads. Since the charging time of high-impedance loads is relatively long, when testing by using the current-through voltage measurement method, a lot of time is spent waiting for the load voltage to reach a stable state, which not only reduces the testing efficiency, but also increases the uncertainty in the testing process. In addition, due to the difficulty in accurately controlling the current charging process, especially under high current and high voltage conditions, overcharging may occur, which not only may damage the testing equipment, but also may cause irreversible damage to the measured load. SUMMARY

[0005] The present application aims to provide a load detection circuit and a driving device to solve the technical problem that in the prior art, when testing the load, it often needs to work for tens of times the working time under normal conditions to detect the open / short circuit state of the load.

[0006] To achieve the above-mentioned one of the purposes of the application, an embodiment of the present application provides a load detection circuit, the load detection circuit comprising: a first detection port configured to receive a detection current, and configured to be coupled to a first end of a load, the first end of the load having a first potential; a first resistor having a first end and a second end, the first end of the first resistor being configured to receive the detection current; a first switch having a first end and a second end, the first end of the first switch being coupled to the second end of the first resistor; a second detection port coupled to the second end of the first switch, and configured to be coupled to a second end of the load, the second end of the load having a second potential; in a first state, the first switch is closed, the detection current represents a first current value, and the first potential and the second potential are both related to the detection current and the first resistor; in a second state, the first switch is opened, the detection current represents a second current value, and when the load is short-circuited, the difference between the first potential and the second potential is less than a first preset value, and when the load is open-circuited, the difference between the first potential and the second potential is greater than a second preset value; wherein the first current value is greater than the second current value, and the load detection circuit operates in the first state and the second state in sequence.

[0007] To achieve the above-mentioned one of the purposes of the application, an embodiment of the present application provides a load detection circuit, the load detection circuit comprising: a first detection port configured to receive a detection current, and configured to be coupled to a first end of a load, the first end of the load having a first potential; a first resistor having a first end and a second end, the first end of the first resistor being configured to receive the detection current; a first switch having a first end and a second end, the first end of the first switch being coupled to the second end of the first resistor; a second detection port coupled to the second end of the first switch, and configured to be coupled to a second end of the load, the second end of the load having a second potential; in a first state, the first switch is closed, the detection current represents a first current value, and the first potential and the second potential are both related to the detection current and the first resistor; in a second state, the first switch is opened, the detection current represents a second current value, and when the load is short-circuited, the difference between the first potential and the second potential is less than a first preset value, and when the load is open-circuited, the difference between the first potential and the second potential is greater than a second preset value; wherein the first current value is greater than the second current value, and the load detection circuit operates in the first state and the second state in sequence.

[0008] An embodiment of the present application further provides a driving device, the D-class amplifier comprising the load detection circuit in the above embodiment, and the D-class amplifier having an output end configured to be coupled to the load through the first detection port and the second detection port.

[0009] Compared with the prior art, the application has the following beneficial effects: the detection current with the first current value is used in the first state, so that the difference between the first potential and the second potential is generated according to the first resistance and the detection current, and the difference between the first potential and the second potential can be quickly established due to the size of the first current value being greater than the second current value, thereby achieving the purpose of fast voltage rise, and further reducing the time of voltage establishment. Then the difference between the first potential and the second potential is adjusted to the voltage value of the related load by the detection current with the second current value, and the state of the load can be determined by the size of the voltage value. BRIEF DESCRIPTION OF DRAWINGS

[0010] Figure 1 A structure schematic diagram of a load detection circuit 100 of an embodiment of the application is given.

[0011] Figure 2 A structure schematic diagram of a load detection circuit 200 of an embodiment of the application is given.

[0012] Figure 3 A structure schematic diagram of a voltage detector 2 of an embodiment of the application is given. DETAILED DESCRIPTION

[0013] The application will be described in detail below with reference to the specific embodiments shown in the drawings. However, these embodiments do not limit the application, and the changes in structure, method or function made by those of ordinary skill in the art based on these embodiments are included in the protection scope of the application.

[0014] It should be noted that the term "comprising" or any other variant thereof is intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or equipment. In addition, the terms "first", "second", "third", etc. are only used for description purposes and cannot be understood as indicating or implying relative importance.

[0015] The phrases "one embodiment", "an embodiment", "one example", "an example" appearing in various places throughout the specification are not necessarily all referring to the same embodiment or example. Those of ordinary skill in the art should understand that various specific features, structures or parameters, steps, etc. disclosed in one or more embodiments of the present disclosure can be combined in any suitable manner.

[0016] Figure 1A structure diagram of a load detection circuit 100 in an embodiment of the present application is shown. The load detection circuit 100 includes a first detection port P1, a first resistor R1, a first switch K1 and a second detection port P2. The first detection port P1 is configured to receive a detection current I1, and is configured to be coupled to a first end of a load Rk, which has a first voltage U1. The first resistor R1 has a first end and a second end, and the first end is configured to receive the detection current I1. The first switch K1 has a first end and a second end, and the first end is configured to be coupled to the second end of the first resistor R1. The second detection port P2 is configured to be coupled to the second end of the first switch K1, and is configured to be coupled to a second end of the load Rk, which has a second voltage U2. In an embodiment, when the load detection circuit 100 is in a first state, the first switch K1 is closed, the detection current I1 represents a first current value, and the first voltage U1 and the second voltage U2 are related to the detection current I1 and the first resistor R1. In an embodiment, U1-U2=I1*R1. In an embodiment, when the load detection circuit 100 is in a second state, the first switch K1 is opened, and the detection current I1 represents a second current value. The load detection circuit 100 works in the first state and the second state in turn. The first current value is greater than the second current value. When the load Rk is short-circuited, the difference between the first voltage U1 and the second voltage U2 is less than a first preset value VTH1, i.e., U1-U2<VTH1. When the load Rk is open-circuited, the difference between the first voltage U1 and the second voltage U2 is greater than a second preset value VTH2, i.e., U1-U2>VTH2. In an embodiment, the first preset value VTH1 is equal to the second preset value VTH2.

[0017] Thus, Figure 1 The load detection circuit 100 shown above is configured as follows. First, the detection current I1 with the first current value is used to make the voltage difference between the first detection port P1 and the second detection port P2 reach a preset voltage value according to the set first resistor R1 and the detection current I1. Since the first current value is greater than the second current value, the difference between the first voltage U1 and the second voltage U2 can quickly reach the preset voltage value, thereby achieving the purpose of fast voltage rise, and further reducing the time for voltage establishment. Subsequently, the detection current I1 with the second current value is used to make the voltage difference between the first detection port P1 and the second detection port P2 reach the real voltage value of the load according to the resistance value of the load Rk and the detection current I1, and the state (open-circuit, short-circuit or stable) of the load Rk is determined by the size of the real voltage value.

[0018] Continuing Figure 1In the first state, the load detection circuit 100 detects the first potential U1 and the second potential U2 difference according to the detection current I1 and the first resistor R1, i.e. U1-U2=I1*R1. In the second state, the load detection circuit 100 detects the first potential U1 and the second potential U2 difference according to the detection current I1 and the load Rk, i.e. U1-U2=I1*RLO, where RLO is the resistance of the load Rk. In one embodiment, RLO is 10 kΩ.

[0019] Continuing Figure 1 In one embodiment, the load detection circuit 100 further comprises a gain amplifier A. The gain amplifier A has a first input, a second input and an output. The first input of the gain amplifier A receives a reference voltage Vref, and the second input of the gain amplifier A is coupled to the output. The output of the gain amplifier A is coupled to the second terminal of the first switch K1. The gain amplifier A is configured to absorb the detection current I1 when the load detection circuit 100 is in the first state and the second state.

[0020] In Figure 1 In one embodiment, when the load detection circuit 100 is in the first state, the detection current I1 flows through the first resistor R1 and the first switch K1 to the gain amplifier A, and the gain amplifier A absorbs the detection current I1. The first potential U1 and the second potential U2 are raised, and the first potential U1 and the second potential U2 difference (voltage difference between the first detection port P1 and the second detection port P2) is generated according to the detection current I1 and the first resistor R1, i.e. U1-U2=I1*R1.

[0021] In Figure 1 In one embodiment, when the load detection circuit 100 is in the second state, based on the first potential U1 and the second potential U2 difference in the first state, the detection current I1 is output from the first detection port P1, flows through the load Rk, and is input from the second detection port P2 to the gain amplifier A, and the gain amplifier A absorbs the detection current I1. The first potential U1 and the second potential U2 difference is generated according to the detection current I1 and the load Rk. That is, the value of the first potential U1 and the second potential U2 difference is adjusted so that U1-U2=I1*RLO. In one embodiment, if the value of the first potential U1 and the second potential U2 difference in the first state is less than I1*RLO, the value of the first potential U1 and the second potential U2 difference is increased. In one embodiment, if the value of the first potential U1 and the second potential U2 difference in the first state is greater than I1*RLO, the value of the first potential U1 and the second potential U2 difference is decreased.

[0022] In Figure 1In one embodiment, the gain amplifier A is a unity gain driver, and the benefit effect of the gain amplifier A is 1. In one embodiment, the first input terminal of the gain amplifier A is a non-inverting input terminal, and the second input terminal of the gain amplifier A is a negative phase input terminal. In this way, the detection current I1 flows into the gain amplifier A from the negative phase input terminal, and the second input terminal of the gain amplifier A is coupled to the output terminal to achieve the output current consistent with the input current, i.e. the output current follows the input current. The detection current I1 is circulated inside the gain amplifier A, achieving the effect of being "absorbed" by the gain amplifier A. Further, through a current path provided by the gain amplifier A, the detection current I1 can maintain its constant current output.

[0023] Continuing Figure 1 As described above, the load detection circuit 100 further comprises a voltage detector 2. The voltage detector 2 has a first input terminal and a second input terminal, the first input terminal of the voltage detector 2 is coupled to the first detection port P1, and the second input terminal of the voltage detector 2 is coupled to the second detection port P2. The voltage detector 2 is configured to detect the difference between the first potential U1 and the second potential U2 and compare the difference with the first preset value VTH1 and the second preset value VTH2 when the load detection circuit 100 is in the second state.

[0024] Figure 2A structure diagram of a load detection circuit 200 in an embodiment of the present application is shown. The load detection circuit 200 comprises a first detection port P1, a first resistor R1, a first switch K1, a second detection port P2, a second switch K2 and a gain amplifier A. The first detection port P1 is configured to receive a detection current I1, and is configured to be coupled to a first end of a load Rk, the first end of the load Rk having a first voltage U1. The first resistor R1 has a first end and a second end, and the first end of the first resistor R1 is configured to receive the detection current I1. The first switch K1 has a first end and a second end, and the first end of the first switch K1 is configured to be coupled to the second end of the first resistor R1. The second detection port P2 is configured to be coupled to the second end of the first switch K1, and is configured to be coupled to a second end of the load Rk, the second end of the load Rk having a second voltage U2. The second switch K2 has a first end and a second end, and the first end of the second switch K2 is configured to be coupled to the first detection port P1, and the second end of the second switch K2 is configured to be coupled to the second detection port P2. The gain amplifier A has a first input end, a second input end and an output end, the first input end of the gain amplifier A is configured to receive a reference voltage Vref, the second input end of the gain amplifier A is configured to be coupled to the output end, and the output end of the gain amplifier A is configured to be coupled to the second end of the first switch K1 and the second end of the second switch K2 respectively. In an embodiment, when the load detection circuit 200 is in a first state, the second switch K2 is closed, the gain amplifier A outputs a driving current I2, and the first voltage U1 and the second voltage U2 are related to the load Rk. In an embodiment, when the load detection circuit 200 is in a second state, the first switch K1 is closed, the detection current I1 represents a first current value, and the first voltage U1 and the second voltage U2 are related to the detection current I1 and the first resistor R1. In an embodiment, U1-U2=I1*R1. In an embodiment, when the load detection circuit 200 is in a third state, the first switch K1 is opened, and the detection current I1 represents a second current value. The load detection circuit 200 works in the first state, the second state and the third state in turn. The first current value is greater than the second current value. When the load Rk is short-circuited, the difference between the first voltage U1 and the second voltage U2 is less than a first preset value VTH1, i.e. U1-U2

[0025] In Figure 2In one embodiment, the load Rk includes an amplifier 11, a first filter 12, and a second filter 13. The amplifier 11 has a first input terminal and a second input terminal. The first filter 12 is coupled to a first detection port P1 and the first input terminal of the amplifier 11. The second filter 13 is coupled to a second detection port P2 and the second input terminal of the amplifier 11. Thus, the detection current I1 is input to the amplifier 11 through the first filter 12 and the second filter 13, enabling the amplifier 11 to operate more stably and preventing damage to the load Rk.

[0026] exist Figure 2 In one embodiment, in the first state, the load detection circuit 200 outputs a drive current I2 from the gain amplifier A. This drive current I2 flows through the first filter 12 and the second filter 13, charging them. The value of the first potential U1 is related to the first filter 12, and the value of the second potential U2 is related to the second filter 13. Specifically, the first potential U1 and the second potential U2 are the same, meaning the potentials at the first detection port P1 and the second detection port P2 are the same. In one embodiment, the magnitude of the drive current I2 output by the gain amplifier A is related to the value of the reference voltage VREF. Thus, in the first state, the load detection circuit 200 charges the potentials at the first filter 12 and the second filter 13 to a preset common-mode voltage using the drive current I2. This avoids the problem of negative differential voltages at the two input terminals of the load Rk in the second state, where the voltage at the first input terminal representing the positive inverting input is less than the voltage at the second input terminal representing the negative inverting input. Furthermore, by preferentially charging the first potential U1 and the second potential U2 to higher potentials using the drive current I2, the speed can be significantly improved.

[0027] exist Figure 2 In one embodiment, the load detection circuit 200, in the second state, detects a current I1 flowing through the first resistor R1 based on the potential values ​​of the first potential U1 and the second potential U2 in the first state. The difference between the first potential U1 and the second potential U2 (the voltage difference between the first detection port P1 and the second detection port P2) is generated based on the detection current I1 and the first resistor R1. That is, the values ​​of the first potential U1 and the second potential U2 are adjusted so that U1 - U2 = I1 * R1. In one embodiment, the first potential U1 increases and the second potential U2 decreases, such that U1 - U2 = I1 * R1. In another embodiment, the voltage increase of the first potential U1 is greater than the voltage increase of the second potential U2, such that U1 - U2 = I1 * R1. In yet another embodiment, the voltage decrease of the first potential U1 is less than the voltage decrease of the second potential U2, such that U1 - U2 = I1 * R1.

[0028] exist Figure 2In an embodiment of the load detection circuit 200, when the load detection circuit 200 is in the third state, the load detection circuit 200 detects the current II flowing through the amplifier 11 based on a difference between the first potential Ul and the second potential U2, the difference between the first potential Ul and the second potential U2 being generated according to the current II and the amplifier 11. That is, the difference between the first potential Ul and the second potential U2 is adjusted such that Ul-U2=II*RLO, where RLO is the impedance of the amplifier 11. In an embodiment, if the difference between the first potential Ul and the second potential U2 is less than II*RLO when the load detection circuit 200 is in the second state, the difference between the first potential Ul and the second potential U2 is increased. In an embodiment, if the difference between the first potential Ul and the second potential U2 is greater than II*RLO when the load detection circuit 200 is in the second state, the difference between the first potential Ul and the second potential U2 is decreased. In an embodiment, the impedance RLO of the amplifier 11 is 10 kΩ.

[0029] In Figure 2 an embodiment of the load detection circuit 200, the gain amplifier A is the same as the gain amplifier A in the load detection circuit 200, which will not be described herein. Figure 1

[0030] In Figure 2 an embodiment of the load detection circuit 200, the load detection circuit 200 further comprises a voltage detector 2. The voltage detector 2 has a first input and a second input, the first input of the voltage detector 2 being coupled to the first detection port PI, and the second input of the voltage detector 2 being coupled to the second detection port P2. The voltage detector 2 is configured to, when the load detection circuit 200 is in the third state, detect the difference between the first potential Ul and the second potential U2 and compare the difference between the first potential Ul and the second potential U2 with the first preset value VTH1 and the second preset value VTH2. In an embodiment, the voltage detector 2 is an analog-to-digital converter.

[0031] In Figure 2 ​In an embodiment, the first filter 12 comprises a first inductor LI and a first capacitor CI. The first inductor LI has a first end and a second end, the first end of the first inductor LI is coupled to the first input of the amplifier 11, and the second detection port PI is configured to couple to the second end of the first inductor LI. The first capacitor CI has a first end and a second end, the first end of the first capacitor CI is coupled to the first end of the first inductor LI, and the second end of the first capacitor CI is coupled to the reference ground GND. In this way, when the load detection circuit 200 is in the first state, the drive current I2 outputted by the gain amplifier A charges the first capacitor CI. In an embodiment, the capacitance of the first capacitor CI is between 1 uF and 4.7 uF. The second filter 13 comprises a second inductor L2 and a second capacitor C2. The second inductor L2 has a first end and a second end, the first end of the second inductor L2 is coupled to the second input of the amplifier 11, and the second detection port P2 is configured to couple to the second end of the second inductor L2. The second capacitor C2 has a first end and a second end, the first end of the second capacitor C2 is coupled to the first end of the second inductor L2, and the second end of the second capacitor C2 is coupled to the reference ground GND. In this way, when the load detection circuit 200 is in the first state, the drive current I2 outputted by the gain amplifier A charges the second capacitor C2. In an embodiment, the capacitance of the first capacitor CI and the second capacitor C2 is the same. In an embodiment, the capacitance of the second capacitor C2 is between 1 uF and 4.7 uF.

[0032] Figure 3 A schematic diagram of a voltage detector 2 according to an embodiment of the present application is shown. The voltage detector 2 comprises a voltage acquisition circuit 21 and an analog-to-digital converter 22. In this embodiment, the voltage acquisition circuit 21 and the analog-to-digital converter 22 are coupled, the first input of the voltage acquisition circuit 21 is coupled to the first detection port PI, and the second input of the voltage acquisition circuit 21 is coupled to the second detection port P2. The analog-to-digital converter 22 receives the difference between the first potential Ul and the second potential U2 acquired by the voltage acquisition circuit 21 and converts the difference between the first potential Ul and the second potential U2 into a digital signal. In a specific embodiment, the analog-to-digital converter 22 is a successive approximation analog-to-digital converter. In a specific embodiment, the analog-to-digital converter 22 is a delta-sigma analog-to-digital converter.

[0033] An embodiment of the present application also provides a driving device. The driving device comprises Figure 1 the load detection circuit 100 in any of the embodiments shown or Figure 2 the load detection circuit 200 in any of the embodiments shown, and a class-D amplifier, the output of which is configured to be coupled to the load Rk via the first detection port and the second detection port.

[0034] In summary, the application adopts a load detection circuit 100, which comprises a first resistor R1 and a first switch K1 arranged in series, and adjusts the potentials at a first detection port P1 and a second detection port P2 by means of the detection current I1 flowing through the first resistor R1 and the first switch K1. When the first switch K1 is turned on, the load detection circuit 100 is in a first state, and the first potential U1 and the second potential U2 are adjusted by means of the first resistor R1 and the detection current I1, so that the voltage difference between the first potential U1 and the second potential U2 is R1*I1. When the first switch K1 is turned off, the load detection circuit 100 is in a second state, and the voltage difference between the first potential U1 and the second potential U2 is adjusted by means of the load Rk and the detection current I1, so that the voltage difference is RLO*I1. Since the current value of the detection current I1 in the first state is greater than that in the second state, the voltage difference between the first potential U1 and the second potential U2 can quickly reach the value of R1*I1, so that the value of R1*I1 is adjusted to the value of RLO*I1 more quickly in the second state.

[0035] The application also adopts a load detection circuit 200, which adjusts the potentials at a first detection port P1 and a second detection port P2 by means of a first resistor R1 and a first switch K1 arranged in series, and a second switch K2 connected in parallel with the first resistor R1 and the first switch K1. When the second switch K2 is turned on, the load detection circuit 200 is in a first state, and the potentials at the first detection port P1 and the second detection port P2 are in the same potential by means of the output driving current I2 of a gain amplifier A charging the filter at the end of the load Rk, so as to avoid the problem of negative differential voltage between the two input ends of the load Rk in the second state of the load detection circuit 200. When the second switch K2 is turned off and the first switch K1 is turned on, the load detection circuit 200 is in a second state, and the potentials at the first detection port P1 and the second detection port P2 are adjusted by means of the first resistor R1 and the detection current I1, so that the voltage difference between the first detection port P1 and the second detection port P2 is R1*I1. In this state, the first potential U1 and the second potential U2 are preprocessed in the first state, and the detection current I1 with a large current flows through the first resistor R1, so that the voltage difference between the first potential U1 and the second potential U2 can be quickly adjusted to the value of R1*I1. When the first switch K1 is turned off, the load detection circuit 200 is in a third state, and the voltage difference between the first potential U1 and the second potential U2 is adjusted by means of the load Rk and the detection current I1, so that the voltage difference is RLO*I1, thereby ensuring that the voltage difference between the first potential U1 and the second potential U2 is adjusted from the value of R1*I1 to the value of RLO*I1 more quickly.

[0036] It should be understood that although the present specification describes only a single embodiment, the description herein of the embodiment by no means limits the scope of the application, and the skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can be combined appropriately to form other embodiments which can be understood by the skilled in the art.

[0037] The above detailed description of a series of embodiments is merely specific to the feasible embodiments of the present application, and is not intended to limit the protection scope of the present application, and any equivalent embodiments or changes made without departing from the spirit of the present application should be included in the protection scope of the present application.

Claims

1. A load detection circuit, characterized by, comprising: a first detection port for receiving a detection current, for coupling a first end of a load, the first end of the load having a first potential; a first resistor having a first end and a second end, the first end of the first resistor receiving the detection current; a first switch having a first end and a second end, the first end of the first switch being coupled to the second end of the first resistor; a second detection port coupled to the second end of the first switch, for coupling a second end of the load, the second end of the load having a second potential; a first state in which the first switch is closed, the detection current representing a first current value, the first potential and the second potential both being related to the detection current and the first resistor; a second state in which the first switch is open, the detection current representing a second current value, a difference between the first potential and the second potential being less than a first preset value when the load is short-circuited, and the difference between the first potential and the second potential being greater than a second preset value when the load is open-circuited; wherein the first current value is greater than the second current value, and the load detection circuit operates in the first state and the second state in turn; wherein the load comprises: an amplifier having a first input and a second input; a first filter coupled to the first detection port and the first input of the amplifier; a second filter coupled to the second detection port and the second input of the amplifier.

2. The load detection circuit of claim 1, wherein in the first state, the difference between the first potential and the second potential is generated according to the detection current and the first resistor when the detection current flows through the first resistor; and in the second state, the difference between the first potential and the second potential is generated according to the detection current and the load when the detection current flows through the load.

3. The load detection circuit of claim 1, further comprising: a gain amplifier having a first input, a second input and an output, the first input of the gain amplifier receiving a reference voltage, the second input of the gain amplifier being coupled to the output, the output of the gain amplifier being coupled to the second end of the first switch; the gain amplifier being configured to absorb the detection current in the first state and the second state.

4. The load detection circuit of claim 1, further comprising: a voltage detector having a first input and a second input, the first input of the voltage detector being coupled to the first detection port, the second input of the voltage detector being coupled to the second detection port; the voltage detector being configured to detect the difference between the first potential and the second potential and compare the difference with the first preset value and the second preset value in the second state.

5. The load detection circuit of claim 1, wherein the first preset value is equal to the second preset value. comprising:

6. A load detection circuit, characterized by, a first detection port for receiving a detection current, for coupling a first end of a load, the first end of the load having a first potential; a first resistor having a first end and a second end, the first end of the first resistor receiving the detection current; a first switch having a first end and a second end, the first end of the first switch being coupled to the second end of the first resistor; a second detection port coupled to the second end of the first switch, for coupling a second end of the load, the second end of the load having a second potential; a second switch having a first end and a second end, the first end of the second switch being coupled to the first detection port, the second end of the second switch being coupled to the second detection port; and a third switch having a first end and a second end, the first end of the third switch being coupled to the second end of the first switch, the second end of the third switch being coupled to the second end of the second switch. ​ The gain amplifier has a first input terminal, a second input terminal and an output terminal, the first input terminal receives a reference voltage, the second input terminal is coupled to the output terminal, and the output terminal is coupled to the second terminal of the first switch and the second terminal of the second switch, respectively; In the first state, the second switch is closed, the gain amplifier outputs a driving current, and the first potential and the second potential are related to the load; In the second state, the first switch is closed, the detection current represents a first current value, and the first potential and the second potential are related to the detection current and the first resistor; In the third state, the first switch is open, the detection current represents a second current value, and the difference between the first potential and the second potential is less than a first preset value when the load is short-circuited, and the difference between the first potential and the second potential is greater than a second preset value when the load is open-circuited; The first current value is greater than the second current value, and the load detection circuit works in the first state, the second state and the third state in turn; The load includes: An amplifier has a first input terminal and a second input terminal; A first filter is coupled to the first detection port and the first input terminal of the amplifier; A second filter is coupled to the second detection port and the second input terminal of the amplifier.

7. The load detection circuit of claim 6, wherein the gain amplifier is configured to sink the detection current in the second state and the third state.

8. The load detection circuit of claim 6, wherein in the first state, the drive current flows through the first filter and the second filter, the value of the first potential is related to the first filter, and the value of the second potential is related to the second filter, wherein, The first potential is equal to the second potential; In the second state, when the detection current flows through the first resistor, the difference between the first potential and the second potential is generated according to the detection current and the first resistor; In the third state, when the detection current flows through the amplifier, the difference between the first potential and the second potential is generated according to the detection current and the amplifier.

9. The load detection circuit of claim 6, further comprising: A voltage detector has a first input terminal and a second input terminal, the first input terminal is coupled to the first detection port, and the second input terminal is coupled to the second detection port; The voltage detector is configured to detect the difference between the first potential and the second potential in the third state and compare the difference with the first preset value and the second preset value.

10. The load detection circuit of claim 6, wherein the first preset value is equal to the second preset value.

11. A drive apparatus characterized by comprising: The load detection circuit of any one of claims 1-5 or the load detection circuit of any one of claims 6-10; and A class-D amplifier has an output terminal for coupling to the load through the first detection port and the second detection port. ​ ​

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