Etching deviation acquisition method of multiple exposure technology
By using optical proximity correction model and multiple exposure technology, the etching deviation is obtained and corrected, and the problem of low line-end pitch etching deviation accuracy in semiconductor technology is solved, and the stability of the process and device is improved.
Patent Information
- Application Number
- CN202310842962.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-07-10
- Publication Date
- 2025-01-10
- Estimated Expiration
- 2043-07-10
AI Technical Summary
In semiconductor technology, the etching deviation of the multiple exposure technology has a low accuracy in the length direction, resulting in unstable process windows and device functions. It is difficult for the prior art to effectively improve the accuracy of line-end pitch etching deviations.
By providing the first and second photomasks, simulated development and actual lithography are performed using an optical proximity correction model, the line end spacing after simulation development and the line end spacing after etching are obtained, and the etching deviation is calculated and corrected to improve the Etching deviation accuracy of line end spacing.
It effectively improves the accuracy of line-end etching deviation in multiple exposure technology, ensuring process stability and device function reliability.
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Figure CN119292000A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor technology, and in particular to a method for obtaining etching deviations using a multiple exposure technology. Background Art
[0002] As semiconductor technology nodes develop to below 10 nanometers, etching bias needs to be very precise to ensure process windows and device functions. Generally speaking, two masks of the multiple exposure technology (LELE: litho-etch-litho-etch) process can share the same etching bias table, which is summarized from the measured deviations between thousands of post-development inspection (ADI: AfterDevelopment Inspection) and post-etching inspection (AEI: AfterEtch Inspection) data through the key dimensions / spacing / length of the mask pattern.
[0003] For line spacing layers, the accuracy of line end etch deviation in the length direction is usually worse than that in the width direction. An inevitable reason is the metrological instability of ADI and AEI critical dimension measurement for longer length patterns. However, errors of several nanometers in the etch deviation table can lead to unhealthy processes and wafer pattern defects.
[0004] Therefore, it is necessary to provide a more effective and reliable technical solution to make the etching deviation of the line end spacing more accurate in the length direction. Summary of the invention
[0005] The present application provides an etching deviation acquisition method of a multiple exposure technology, which can make the etching deviation of the line end spacing more accurate in the length direction.
[0006] The present application provides an etching deviation acquisition method of a multiple exposure technology, including: providing a first mask and a second mask, the first mask including a first pattern and a second pattern, the second mask including a third pattern, the second pattern and the third pattern being superimposed to form a fourth pattern; acquiring a line end spacing after simulated development of the first pattern and the fourth pattern; performing a first photolithography process, copying the first pattern and the second pattern onto a wafer, and acquiring a line end spacing after development of the first pattern; performing a second photolithography process, copying the third pattern onto the wafer, the third pattern and the second pattern being superimposed on the wafer to form a fourth pattern, and acquiring a line end spacing after etching of the fourth pattern; acquiring an etching deviation based on the line end spacing after simulated development of the first pattern and the fourth pattern, the line end spacing after development of the first pattern, and the line end spacing of the fourth pattern after etching.
[0007] In some embodiments of the present application, a method for obtaining the line end spacing of the first and fourth graphics after simulated development includes: importing the first mask and the second mask into an optical proximity correction model; performing multiple exposure technology to simulate lithography on the first mask and the second mask through the optical proximity correction model; and obtaining the line end spacing of the first and fourth graphics after simulated development.
[0008] In some embodiments of the present application, a method for obtaining an etching deviation based on the line end spacing after simulated development of the first and fourth graphics, the line end spacing after development of the first graphic, and the line end spacing after etching of the fourth graphic includes: obtaining a model error based on the line end spacing after development of the first graphic and the line end spacing after simulated development of the first graphic; obtaining an actual line end spacing after development of the fourth graphic based on the model error and the line end spacing after simulated development of the fourth graphic; and obtaining an etching deviation based on the actual line end spacing after development of the fourth graphic and the line end spacing after etching of the fourth graphic.
[0009] In some embodiments of the present application, a method for obtaining an etching deviation based on the line end spacing after simulated development of the first and fourth graphics, the line end spacing after development of the first graphics, and the line end spacing after etching of the fourth graphics includes: performing multiple tests to obtain multiple groups of line end spacings after simulated development of the first and fourth graphics, the line end spacings after development of the first graphics, and the line end spacings after etching of the fourth graphics.
[0010] In some embodiments of the present application, a method for obtaining a model error based on a line end spacing of the first graphic after development and a line end spacing of the first graphic after simulated development includes:
[0011]
[0012] Among them, Model_error is the model error, A_ADI m() A_ADI is the line end spacing after development of the first graphic. s() is the line end spacing after simulated development of the first graphic, i is the test number, and n is the number of tests.
[0013] In some embodiments of the present application, a method for obtaining the actual developed line end spacing of the fourth graphic based on the model error and the simulated developed line end spacing of the fourth graphic includes:
[0014] B_ADI m() =B_ADI s() +Model_error;
[0015] Among them, Model_error is the model error, B_ADI m() is the line end spacing of the fourth pattern after development, B_ADI s() is the line end spacing after simulated development of the fourth graphic, and i is a test number.
[0016] In some embodiments of the present application, a method for obtaining an etching deviation based on the line end spacing of the fourth pattern after actual development and the line end spacing of the fourth pattern after etching includes:
[0017]
[0018] Among them, Etch_Bias is the etching bias, B_AEI m() is the line end spacing of the fourth pattern after etching, B_ADI m() is the line end spacing of the fourth pattern after development, i is the test number, and n is the number of tests.
[0019] In some embodiments of the present application, the first figure includes a plurality of rectangles distributed in an array, the rectangles include a long side along the horizontal direction and a short side along the vertical direction, the length of the long side is greater than the length of the short side, and the line end spacing is the spacing of the rectangles in the long side direction.
[0020] In some embodiments of the present application, the second figure includes a plurality of rectangles distributed in an array, the rectangles include long sides along the horizontal direction and short sides along the vertical direction, the length of the long sides is greater than the length of the short sides, and the line end spacing of the second figure is greater than the line end spacing of the first figure.
[0021] In some embodiments of the present application, the third figure includes a plurality of rectangles distributed in an array, the rectangles include long sides along the horizontal direction and short sides along the vertical direction, the length of the long sides is greater than the length of the short sides, and after the second figure and the third figure are superimposed, the third figure is located at the interval in the long side direction of adjacent rectangles of the second figure.
[0022] The present application provides an etching deviation acquisition method of a multiple exposure technology, which can make the etching deviation of the line end spacing more accurate in the length direction. BRIEF DESCRIPTION OF THE DRAWINGS
[0023] The following figures describe in detail the exemplary embodiments disclosed in this application. The same reference numerals represent similar structures in several views of the drawings. Those skilled in the art will understand that these embodiments are non-limiting, exemplary embodiments, and the drawings are only for the purpose of illustration and description, and are not intended to limit the scope of this application. Other embodiments may also accomplish the inventive intent in this application. It should be understood that the drawings are not drawn to scale.
[0024] in:
[0025] Figure 1 A flowchart of a method for obtaining etching deviations using the multiple exposure technology described in an embodiment of the present application;
[0026] Figure 2 A schematic diagram of the structure of a first mask in the etching deviation acquisition method of the multiple exposure technology described in an embodiment of the present application;
[0027] Figure 3 A schematic diagram of the structure of a second mask in the etching deviation acquisition method of the multiple exposure technology described in an embodiment of the present application;
[0028] Figure 4 This is a schematic diagram of the structure after the first mask and the second mask overlap in the etching deviation acquisition method of the multiple exposure technology described in an embodiment of the present application. DETAILED DESCRIPTION
[0029] The following description provides specific application scenarios and requirements of the present application, with the purpose of enabling those skilled in the art to make and use the content in the present application. It will be apparent to those skilled in the art that various local modifications to the disclosed embodiments are apparent, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the present application. Therefore, the present application is not limited to the embodiments shown, but to the widest scope consistent with the claims.
[0030] The technical solution of the present invention is described in detail below in conjunction with the embodiments and drawings.
[0031] In some etching deviation acquisition methods of multiple exposure technology, after multiple exposure etching, the etching deviation is calculated by measuring the difference between the length of the pattern after development and the length of the pattern after etching. However, the FOV (field of view) of the critical dimension scanning electron microscope (CDSEM) is a limitation, and longer patterns outside the FOV cannot be applied by this method.
[0032] In other etching deviation acquisition methods of multiple exposure technology, after multiple exposure etching, the etching deviation is calculated by measuring the line end spacing of the pattern after development and the line end spacing of the pattern after etching. Although not limited by FOV, due to the lithography capability, the line end spacing is usually as high as hundreds of nanometers, which is still too large for the etching deviation accuracy requirement.
[0033] Based on this, the technical solution of the present application provides a method for obtaining etching deviation of multiple exposure technology, which can effectively improve the line end etching deviation accuracy of multiple exposure technology.
[0034] Figure 1 This is a flow chart of the etching deviation acquisition method of the multiple exposure technology described in an embodiment of the present application.
[0035] This application provides a method for obtaining etching deviation of multiple exposure technology, referring to Figure 1 As shown, including:
[0036] Step S1: providing a first light mask and a second light mask, wherein the first light mask includes a first pattern and a second pattern, and the second light mask includes a third pattern, and the second pattern and the third pattern are superimposed to form a fourth pattern;
[0037] Step S2: obtaining the line end spacing of the first pattern and the fourth pattern after simulated development;
[0038] Step S3: performing a first photolithography process to copy the first pattern and the second pattern onto a wafer, and obtaining a line end spacing of the first pattern after development;
[0039] Step S4: performing a second photolithography process to copy the third pattern onto the wafer, superimposing the third pattern and the second pattern on the wafer to form a fourth pattern, and obtaining the line end spacing of the fourth pattern after etching;
[0040] Step S5: obtaining an etching deviation based on the line end spacings of the first and fourth graphics after simulated development, the line end spacing of the first graphics after development, and the line end spacing of the fourth graphics after etching.
[0041] Figure 2 It is a schematic structural diagram of the first mask in the etching deviation acquisition method of the multiple exposure technology described in an embodiment of the present application. Figure 3 It is a schematic structural diagram of the second mask in the etching deviation acquisition method of the multiple exposure technology described in an embodiment of the present application. Figure 4 The schematic diagram of the structure after the first mask and the second mask overlap in the etching deviation acquisition method of the multiple exposure technology according to the embodiment of the present application is shown in FIG. The etching deviation acquisition method of the multiple exposure technology according to the embodiment of the present application is described in detail below with reference to the accompanying drawings.
[0042] refer to Figure 1 , Figure 2 , Figure 3 and Figure 4 As shown, in step S1, a first mask 100 and a second mask 200 are provided, wherein the first mask 100 includes a first pattern 101 and a second pattern 102, and the second mask 200 includes a third pattern 103, and the second pattern 102 and the third pattern 103 are superimposed to form a fourth pattern 104.
[0043] refer to Figure 2 As shown, in some embodiments of the present application, the first graphic 101 includes a plurality of rectangles distributed in an array, the rectangles include a long side along the horizontal direction and a short side along the vertical direction, the length of the long side is greater than the length of the short side, and the line end gap is the gap between the rectangles in the long side direction. It should be noted that the horizontal direction and vertical direction described in the present application are all based on the directions in the accompanying drawings.
[0044] In some embodiments of the present application, the line end spacing in the first graphic 101 is 50 to 500 nanometers, for example, 100 to 200 nanometers.
[0045] Continue to refer Figure 2 As shown, in some embodiments of the present application, the second graphic 102 includes a plurality of rectangles distributed in an array, the rectangles include long sides along the horizontal direction and short sides along the vertical direction, the length of the long sides is greater than the length of the short sides, and the line end spacing of the second graphic 102 is greater than the line end spacing of the first graphic 102. Except for the line end spacing, other parameters of the first graphic 101 and the second graphic 102 are the same, such as the long side size (length) and short side size (width) of the rectangles, and the spacing of the rectangles in the short side direction.
[0046] refer to Figure 3 As shown, in some embodiments of the present application, the third graphic 103 includes a plurality of rectangles distributed in an array, the rectangles including a long side in the horizontal direction and a short side in the vertical direction, and the length of the long side is greater than the length of the short side. The rectangles in the third graphic 103 are the same as the rectangles in the first graphic 101 and the second graphic 102. And the third graphic 103 and the second graphic 102 are configured such that when the second graphic 102 and the third graphic 103 are superimposed, the third graphic 103 is located at the interval in the long side direction of the adjacent rectangles of the second graphic 102.
[0047] refer to Figure 4As shown, the first mask 100 and the second mask 200 are overlapped so that the third figure 103 is located at the interval in the long side direction of the adjacent rectangles of the second figure 102, and the second figure 102 and the third figure 103 overlap to form a fourth figure 104.
[0048] In some embodiments of the present application, the line end spacing in the fourth graphic 104 is 10 to 200 nanometers, for example, 30 to 60 nanometers. Except for the line end spacing, other parameters in the fourth graphic 104 are the same as those in the first graphic 101, such as the length and width of the rectangle.
[0049] It should be noted that Figure 2 , Figure 3 and Figure 4 Only the graphic structures on the first photomask 100 and the second photomask 200 are shown. However, in the subsequent simulation photolithography and actual photolithography process, the pattern transferred to the photoresist after development and the pattern transferred to the wafer after etching are the same as the pattern on the corresponding photomask. Therefore, although the present application does not provide the patterns after the photolithography of the first photomask 100 and the second photomask 200 for the purpose of simplicity, those skilled in the art will be able to understand the patterns of the first photomask 100 and the second photomask 200 in combination with the above. Figure 2 , Figure 3 and Figure 4 The displayed mask pattern can obtain the corresponding pattern after light development and etching. That is to say, when the patterns after the first mask 100 and the second mask 200 are developed and etched in the future, you can directly refer to Figure 2 , Figure 3 and Figure 4 .
[0050] Continue to refer Figure 1 As shown, in step S2, the line end spacing of the first graphic 101 and the fourth graphic 104 after simulated development is obtained.
[0051] In some embodiments of the present application, a method for obtaining the line end spacing after simulated development of the first graphic 101 and the fourth graphic 104 includes: importing the first mask 100 and the second mask 200 into an optical proximity correction (OPC: Optical Proximity Correction) model; performing multiple exposure technology simulated lithography on the first mask 100 and the second mask 200 through the optical proximity correction model; and obtaining the line end spacing after simulated development of the first graphic 101 and the fourth graphic 104.
[0052] The simulation lithography includes: performing a first simulation lithography to simulate a pattern after the first and second graphics are lithographically formed; and performing a second simulation lithography directly on the pattern of the first simulation lithography to simulate a lithographic pattern after the third and second graphics are overlapped.
[0053] The simulated photolithography includes a whole set of simulated exposure, simulated development and simulated etching processes. In the simulated photolithography process, the line end spacing after the simulated development of the first graphic 101 and the fourth graphic 104 can be directly obtained through the optical proximity correction model. The line end spacing after the simulated development of the first graphic 101 is marked as A_ADI s(i) The line end spacing after the simulated development of the fourth graphic 104 is marked as B_ADI s(i) . In order to improve the accuracy of the data, the simulated lithography can be performed multiple times to obtain multiple sets of corresponding data, and i is the test number. For example, i is 1 in the data obtained by the first simulated lithography; i is 2 in the data obtained by the second simulated lithography; and i is 3 in the data obtained by the third simulated lithography. The data obtained subsequently can also be obtained in multiple sets and marked by i, which will not be repeated.
[0054] Continue to refer Figure 1 As shown, in step S3, a first photolithography process is performed using a first mask 100 to copy the first pattern 101 and the second pattern 102 onto a wafer, and obtain the line end spacing of the first pattern 101 after development.
[0055] Photolithography includes the processes of exposure, development and etching. After exposure and development, the first pattern 101 and the second pattern 102 on the first mask 100 are copied to the photoresist. At this time, the line end spacing of the first pattern 101 copied to the photoresist after development can be directly measured. The line end spacing of the first pattern 101 after development is marked as A_ADI m() .
[0056] Continue to refer Figure 1 As shown, step S4, a second photolithography process is continued to be performed on the wafer that has undergone the first photolithography process using a second mask 200, the third graphic 103 is copied to the wafer, the third graphic 103 and the second graphic 102 are superimposed on the wafer to form a fourth graphic 104, and the line end spacing of the fourth graphic 104 after etching is obtained.
[0057] Photolithography includes the processes of exposure, development and etching. After etching, the patterns on the first photomask 100 and the second photomask 200 are copied to the wafer. At this time, the line end spacing of the fourth pattern 104 after the second pattern 102 and the third pattern 103 copied to the wafer after etching can be directly measured. The line end spacing of the fourth pattern 104 after etching is marked as B_AEI m() .
[0058] Continue to refer Figure 1 As shown, in step S5, based on the line end spacing (A_ADI) after the simulated development of the first graphic 101 and the fourth graphic 104s() and B_ADI a() ), the line end spacing A_ADI of the first graphic 101 after development m() and the line end spacing B_AEI of the fourth pattern 104 after etching m() Get the etch bias.
[0059] In some embodiments of the present application, a method for obtaining an etching deviation based on the line end spacing after simulated development of the first graphic 101 and the fourth graphic 104, the line end spacing after development of the first graphic 101, and the line end spacing after etching of the fourth graphic 104 includes: obtaining a model error based on the line end spacing after development of the first graphic 101 and the line end spacing after simulated development of the first graphic 101; obtaining an actual line end spacing after development of the fourth graphic 104 based on the model error and the line end spacing after simulated development of the fourth graphic 104; and obtaining an etching deviation based on the actual line end spacing after development of the fourth graphic 104 and the line end spacing after etching of the fourth graphic 104.
[0060] In some embodiments of the present application, a method for obtaining an etching deviation based on the line end spacing after simulated development of the first graphic 101 and the fourth graphic 104, the line end spacing after development of the first graphic 101, and the line end spacing after etching of the fourth graphic 104 includes: performing multiple tests to obtain multiple groups of line end spacings after simulated development of the first graphic 101 and the fourth graphic 104, the line end spacings after development of the first graphic 101, and the line end spacings after etching of the fourth graphic 104.
[0061] In some embodiments of the present application, a method for obtaining a model error based on the line end spacing of the first graphic 101 after development and the line end spacing of the first graphic 101 after simulated development includes:
[0062]
[0063] Among them, Model_error is the model error, A_ADI m() A_ADI is the line end spacing after development of the first graphic. s() is the line end spacing after simulated development of the first graphic, i is the test number, and n is the number of tests.
[0064] In some embodiments of the present application, a method for obtaining the actual developed line end spacing of the fourth graphic 104 based on the model error and the simulated developed line end spacing of the fourth graphic 104 includes:
[0065] B_ADI m() =B_ADI s()+Model_error;
[0066] Among them, Model_error is the model error, B_ADI m() is the line end spacing of the fourth pattern after development, B_ADI s() is the line end spacing after simulated development of the fourth graphic, and i is a test number.
[0067] In some embodiments of the present application, a method for obtaining an etching deviation based on the line end spacing of the fourth pattern 104 after actual development and the line end spacing of the fourth pattern 104 after etching includes:
[0068]
[0069] Among them, Etch_Bias is the etching bias, B_AEI m() is the line end spacing of the fourth pattern after etching, B_ADI m() is the line end spacing of the fourth pattern after development, i is the test number, and n is the number of tests.
[0070] The technical solution of the present application provides a method for obtaining etching deviation of a multiple exposure technology, which can effectively improve the line end etching deviation accuracy of the multiple exposure technology.
[0071] The technical solution of the present application provides a first photomask and a second photomask with specific design patterns. The model error, that is, the line end spacing error value between the simulated photolithography and the actual photolithography, is obtained by using the line end spacing after development and the simulated line end spacing after development of the first pattern in the first photomask. The simulated line end spacing after development and the line end spacing after etching of the fourth pattern are obtained by using the fourth pattern formed by superimposing the second pattern in the first photomask and the third pattern in the second photomask. The line end spacing after development of the fourth pattern is then obtained by using the model error and the simulated line end spacing after development of the fourth pattern. The etching error is then obtained by using the line end spacing after development and the line end spacing after etching of the fourth pattern, that is, the error value between the line end spacing before and after and the line end spacing after etching of the fourth pattern.
[0072] The present application provides an etching deviation acquisition method of a multiple exposure technology, which can make the etching deviation of the line end spacing more accurate in the length direction.
[0073] In summary, after reading the contents of this application, those skilled in the art will appreciate that the aforementioned application contents may be presented only in an exemplary manner and may not be restrictive. Although not explicitly stated herein, those skilled in the art will appreciate that this application is intended to encompass various reasonable changes, improvements and modifications to the embodiments. These changes, improvements and modifications are within the spirit and scope of the exemplary embodiments of this application.
[0074] It should be understood that the term "and / or" used in this embodiment includes any or all combinations of one or more of the associated listed items. It should also be understood that the terms "comprise", "comprising", "including" or "comprising", when used in this application document, indicate the existence of the recorded features, wholes, steps, operations, elements and / or components, but do not exclude the existence or addition of one or more other features, wholes, steps, operations, elements, components and / or their groups.
[0075] It should also be understood that although the terms first, second, third, etc. can be used to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Therefore, without departing from the teachings of the present application, the first element in some embodiments can be referred to as the second element in other embodiments. The same reference numerals or the same reference signs represent the same elements throughout the specification.
[0076] In addition, the present specification describes exemplary embodiments by reference to idealized exemplary cross-sectional views and / or plan views and / or stereograms. Therefore, differences from the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are foreseeable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but should include deviations in shapes caused by, for example, manufacturing. For example, an etched region shown as a rectangle will typically have circular or curved features. Therefore, the region shown in the figure is schematic in nature, and its shape is not intended to illustrate the actual shape of the region of the device nor to limit the scope of the exemplary embodiments.
Claims
1. A method for obtaining etching deviation of multiple exposure technology, characterized in that: include: Providing a first light mask and a second light mask, wherein the first light mask includes a first pattern and a second pattern, and the second light mask includes a third pattern, and the second pattern and the third pattern are superimposed to form a fourth pattern; Obtaining the line end spacing of the first graphic and the fourth graphic after simulated development; Performing a first photolithography process to copy the first pattern and the second pattern onto a wafer, and obtaining a line end spacing of the first pattern after development; Performing a second photolithography process to copy the third pattern onto the wafer, superimposing the third pattern and the second pattern on the wafer to form a fourth pattern, and obtaining a line end spacing of the fourth pattern after etching; The etching deviation is obtained based on the line end spacings of the first and fourth patterns after simulated development, the line end spacing of the first pattern after development, and the line end spacing of the fourth pattern after etching.
2. The etching deviation acquisition method according to claim 1, characterized in that: The method for obtaining the line end spacing after simulated development of the first and fourth graphics includes: importing the first and second masks into an optical proximity correction model; performing multiple exposure technology simulation lithography on the first and second masks through the optical proximity correction model; and obtaining the line end spacing after simulated development of the first and fourth graphics.
3. The etching deviation acquisition method according to claim 1, characterized in that: The method for obtaining etching deviation based on the line end spacing after simulated development of the first and fourth graphics, the line end spacing after development of the first graphics, and the line end spacing after etching of the fourth graphics includes: Acquire a model error based on a line end spacing of the first graphic after development and a line end spacing of the first graphic after simulated development; Obtaining an actual line end spacing of the fourth graphic after development based on the model error and a line end spacing of the fourth graphic after simulated development; The etching deviation is obtained based on the line end spacing of the fourth pattern after actual development and the line end spacing of the fourth pattern after etching.
4. The etching deviation acquisition method according to claim 1, characterized in that: The method for obtaining etching deviation based on the line end spacing after simulated development of the first and fourth graphics, the line end spacing after development of the first graphics, and the line end spacing after etching of the fourth graphics includes: performing multiple tests to obtain multiple groups of line end spacings after simulated development of the first and fourth graphics, the line end spacings after development of the first graphics, and the line end spacings after etching of the fourth graphics.
5. The etching deviation acquisition method according to claim 4, characterized in that: The method for obtaining the model error based on the line end spacing of the first graphic after development and the line end spacing of the first graphic after simulated development includes: Among them, Model_error is the model error, A_ADI m() A_ADI is the line end spacing after development of the first graphic. s() is the line end spacing after simulated development of the first graphic, i is the test number, and n is the number of tests.
6. The etching deviation acquisition method according to claim 4, characterized in that: The method for obtaining the actual developed line end spacing of the fourth graphic based on the model error and the line end spacing of the fourth graphic after simulated development includes: B_ADI m() =B_ADI s() +Model_error; Among them, Model_error is the model error, B_ADI m() is the line end spacing of the fourth pattern after development, B_ADI s() is the line end spacing after simulated development of the fourth graphic, and i is a test number.
7. The etching deviation acquisition method according to claim 4, characterized in that: The method for obtaining the etching deviation based on the line end spacing of the fourth pattern after actual development and the line end spacing of the fourth pattern after etching includes: Among them, Etch_Bias is the etching bias, B_AEI m() is the line end spacing of the fourth pattern after etching, B_ADI m() is the line end spacing of the fourth pattern after development, i is the test number, and n is the number of tests.
8. The etching deviation acquisition method according to claim 1, characterized in that: The first figure includes a plurality of rectangles distributed in an array, wherein the rectangles include long sides along the horizontal direction and short sides along the vertical direction, the length of the long sides is greater than the length of the short sides, and the line end spacing is the spacing of the rectangles in the long side direction.
9. The etching deviation acquisition method according to claim 8, characterized in that: The second figure includes a plurality of rectangles distributed in an array, wherein the rectangles include long sides along the horizontal direction and short sides along the vertical direction, the length of the long sides is greater than the length of the short sides, and the line end spacing of the second figure is greater than the line end spacing of the first figure.
10. The etching deviation acquisition method according to claim 9, characterized in that: The third figure includes a plurality of rectangles distributed in an array, wherein the rectangles include long sides along the horizontal direction and short sides along the vertical direction, the length of the long sides is greater than the length of the short sides, and after the second figure and the third figure are superimposed, the third figure is located at the interval in the long side direction of adjacent rectangles of the second figure.
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