Linear voltage regulator applied to three-dimensional memory

Abstract

The invention provides a linear voltage regulator applied to a three-dimensional memory. The linear voltage regulator comprises an LDO (Low Dropout Regulator) main circuit module and a bias module, the LDO main circuit module is used for generating an output voltage; the bias module is connected to the output of the LDO main circuit module and is used for generating bias voltage for the LDO main circuit module; wherein when the output voltage of the LDO main circuit module is increased or decreased, the LDO main circuit module can restore the output voltage to a static stable value. The transient response performance is improved, and the size area of the power tube is reduced.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuits, and in particular to a linear voltage regulator applied to a three-dimensional memory. Background Art

[0002] With the continuous improvement of integrated circuit technology, traditional non-volatile memory, such as flash memory, has serious reliability problems as the feature size decreases. New memory, including phase-change memory, resistive random access memory, and magnetic random access memory, has obvious advantages in speed, power consumption, and three-dimensional integration. Chips such as three-dimensional phase-change memory (3D-PCM) and three-dimensional resistive random access memory (3D-RRAM) have achieved 4F with their three-dimensional structure. 2 Ultra-high density has become a hot research direction to break through the bottleneck of Moore's Law, and has broad application prospects in the fields of replacing traditional non-volatile memory, in-memory computing, information security, etc. Since the gating devices used in three-dimensional memory, such as bidirectional threshold switch devices, are bidirectional conduction devices, special bias methods such as V / 2 are required to achieve correct read and write operations in three-dimensional memory. V / 2 bias methods such as Figure 1 As shown, taking the read operation as an example, when the memory performs a read operation, all bit lines and word lines are biased at V before the read pulse arrives. read / 2, when the read pulse arrives, the selected bit line or word line is quickly switched to V read or 0, the unselected word line and bit line bias remain unchanged. To ensure faster reading speed and higher reading accuracy, V read Circuit modules with a / 2 bias voltage must have good transient characteristics when facing extremely fast load current switching speeds.

[0003] Low-dropout linear regulator (LDO) has the advantages of low ripple, low noise, and small area, and is suitable for implementing special bias for three-dimensional memory. At present, traditional LDO is mainly divided into two categories: with off-chip capacitors and without off-chip capacitors. Although the former has good transient characteristics, it needs to reserve additional pins in the SOC chip to connect to the external capacitor device, which greatly reduces the integration of the chip; LDO without off-chip capacitors is a hot research direction at present, but the traditional LDO structure will produce a large overshoot when the load current changes rapidly, which is difficult to adapt to the transient characteristics requirements of three-dimensional memory. In order to improve the transient characteristics of LDO, FVF (Flipped Voltage Follower) structure without off-chip capacitor LDO circuits have been proposed one after another. Many of these circuits use large on-chip capacitors of several hundred picofarads to use the output node as the main pole to achieve loop stability and high transient characteristics, which seriously deteriorates the area of ​​the chip and its load capacitance range is severely limited. Some other FVFs set the output end as the non-main pole of the loop. Although a large amount of on-chip capacitor area is saved, the load capacitance is weak and the transient characteristics are poor. That is, when the prior art provides a V / 2 bias for a three-dimensional vertical memory, there are problems such as poor transient characteristics, inability to integrate on-chip, large area, and poor load capacitance capability.

[0004] In view of this, it is necessary to provide a novel linear regulator applied to a three-dimensional memory to solve the above problems in the prior art. Summary of the invention

[0005] The purpose of the present invention is to provide a linear voltage regulator applied to a three-dimensional memory, so as to solve the problems of poor transient characteristics, inability to integrate on chip, large area and the like in the prior art.

[0006] In order to achieve the above object, the present invention provides a linear regulator applied to a three-dimensional memory, comprising:

[0007] LDO main circuit module and bias module;

[0008] The LDO main circuit module is used to generate an output voltage;

[0009] The bias module is connected to the output of the LDO main circuit module and is used to generate a bias voltage for the LDO main circuit module;

[0010] When the output voltage of the LDO main circuit module increases or decreases, the LDO main circuit module can restore the output voltage to a static stable value.

[0011] In an optional solution, the LDO main circuit module includes: a first MOS tube, a second MOS tube, a third MOS tube, a fourth MOS tube, a fifth MOS tube, a sixth MOS tube, a seventh MOS tube, an eighth MOS tube, a ninth MOS tube, a tenth MOS tube, an eleventh MOS tube, a twelfth MOS tube, a first resistor, a second resistor, a third resistor, a first capacitor, a second capacitor and a third capacitor;

[0012] Wherein, the source terminal of the first MOS tube is connected to the set voltage, the gate terminal is connected to its own drain terminal, and is also connected to the gate terminal of the second MOS tube and the gate terminal of the third MOS tube; the gate terminal of the third MOS tube is connected to the second bias voltage of the bias module, and the source terminal is connected to the drain terminal of the fourth MOS tube; the gate terminal of the fourth MOS tube is connected to the first bias voltage of the bias module, and the source terminal is grounded; the source terminal of the second MOS tube is connected to the source terminal of the twelfth MOS tube MP, and is also connected to one end of the third resistor, which is used as the output terminal of the LDO main circuit module; the drain terminal of the second MOS tube is connected to the drain terminal of the tenth MOS tube, which is used as the feedback terminal of the LDO main circuit module; the other end of the third resistor is connected to one end of the third capacitor; the other end of the third capacitor is connected to the ground;

[0013] The gate terminal of the tenth MOS transistor is connected to the second bias voltage of the bias module, and the source terminal is connected to the drain terminal of the eleventh MOS transistor; the gate terminal of the eleventh MOS transistor is connected to the first bias voltage of the bias module, and the source terminal is connected to the ground;

[0014] The drain terminal of the twelfth MOS transistor is connected to the input voltage, the gate terminal is connected to one end of the second resistor, and is also connected to the drain terminal of the fifth MOS transistor, the drain terminal of the sixth MOS transistor, and the drain terminal of the ninth MOS transistor; the other end of the second resistor is connected to one end of the second capacitor, and the other end of the second capacitor is connected to the ground;

[0015] The source terminal of the fifth MOS tube is connected to the input voltage, and the gate terminal is connected to one end of the first resistor and one end of the first capacitor; the other end of the first resistor is connected to the third bias voltage of the bias module; the other end of the first capacitor is connected to the output end of the LDO main circuit module; the gate terminal of the sixth MOS tube is connected to the feedback end of the LDO main circuit module, the source terminal is connected to the gate terminal of the ninth MOS tube, and is also connected to the drain terminal of the seventh MOS tube; the gate terminal of the seventh MOS tube is connected to the second bias voltage of the bias module, and the source terminal is connected to the drain terminal of the eighth MOS tube; the gate terminal of the eighth MOS tube is connected to the first bias voltage of the bias module, and the source terminal is connected to the ground; the source terminal of the ninth MOS tube is connected to the ground;

[0016] The first MOS tube, the second MOS tube, and the fifth MOS tube are all PMOS tubes; the third MOS tube, the fourth MOS tube, the sixth MOS tube, the seventh MOS tube, the eighth MOS tube, the ninth MOS tube, the tenth MOS tube, the eleventh MOS tube, and the twelfth MOS tube are all NMOS tubes.

[0017] In an optional solution, the setting voltage V SET The generating circuit comprises: a low power amplifier and a thirteenth MOS tube; the negative input terminal of the low power amplifier is connected to the reference voltage, the positive input terminal is connected to the drain terminal of the thirteenth MOS tube, which point is the set voltage, the output terminal of the low power amplifier is connected to the gate terminal of the thirteenth MOS tube; the source terminal of the thirteenth MOS tube is connected to the input voltage; the thirteenth MOS tube is a PMOS tube.

[0018] In an optional solution, the bias circuit module includes: a fourteenth MOS tube, a fifteenth MOS tube, a sixteenth MOS tube, a seventeenth MOS tube, an eighteenth MOS tube, a first current source and a fourth capacitor;

[0019] Wherein, the source terminal of the fourteenth MOS tube is connected to the input voltage, the gate terminal is recorded as the third bias voltage of the bias module, the point is connected to its own source terminal, and is also connected to the drain terminal and gate terminal of the fifteenth MOS tube; the source terminal of the fifteenth MOS tube is connected to the drain terminal and gate terminal of the sixteenth MOS tube; the drain terminal and gate terminal of the sixteenth MOS tube are recorded as the second bias voltage of the bias module; the source terminal of the sixteenth MOS tube is connected to the drain terminal of the seventeenth MOS tube; the gate terminal of the seventeenth MOS tube is recorded as the first bias voltage of the bias module, the point is connected to one end of the fourth capacitor, and is also connected to the gate terminal, drain terminal and output terminal of the eighteenth MOS tube and the first current source; the other end of the fourth capacitor is connected to the output terminal of the LDO main circuit module; the source terminal of the eighteenth MOS tube is connected to the ground; the input terminal of the first current source is connected to the input voltage;

[0020] The fourteenth MOS tube is a PMOS tube; the fifteenth MOS tube, the sixteenth MOS tube, the seventeenth MOS tube and the eighteenth MOS tube are all NMOS tubes.

[0021] The beneficial effects of the present invention are:

[0022] 1) The present invention improves transient response performance and reduces the size and area of ​​the power tube.

[0023] 2) The LDO circuit of the present invention has excellent transient characteristics and can achieve a smaller overshoot voltage and a shorter recovery time within an extremely short load switching time.

[0024] 3) The LDO circuit of the present invention does not require an off-chip capacitor and can be fully integrated on a chip.

[0025] 4) The LDO circuit of the present invention has a good load capacitance capability and can drive a wide range of load capacitance. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The above and other objects, features and advantages of the present invention will become more apparent through a more detailed description of exemplary embodiments of the present invention in conjunction with the accompanying drawings, in which like reference numerals generally represent like components.

[0027] Figure 1 Schematic diagram of the V / 2 bias method of a three-dimensional memory in the prior art.

[0028] Figure 2 FIG. 4 is a circuit schematic diagram of a linear regulator applied to a three-dimensional memory according to an embodiment of the present invention.

[0029] Figure 3 FIG. 4 is a circuit diagram of a voltage generating circuit according to an embodiment of the present invention.

[0030] Figure 4 1 is a simulation curve of amplitude-frequency characteristics at different load currents in one embodiment of the present invention.

[0031] Figure 5 1 is a phase margin simulation curve under different load capacitances in one embodiment of the present invention.

[0032] Figure 6 FIG. 4 is a transient characteristic response simulation curve in one embodiment of the present invention. DETAILED DESCRIPTION

[0033] The present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. According to the following description and drawings, the advantages and features of the present invention will become clearer. However, it should be noted that the concept of the technical solution of the present invention can be implemented in a variety of different forms and is not limited to the specific embodiments described herein. The drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0034] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there may be no intervening elements or layers. It should be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer or part discussed below may be represented as a second element, component, region, layer or part.

[0035] Spatially relative terms such as "under," "below," "below," "under," "above," "above," etc., may be used herein for ease of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, then the elements or features described as "under other elements" or "under" or "under" will be oriented as "on" the other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0036] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present invention. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0037] Example 1

[0038] Reference Figures 1 to 6 , this embodiment provides a linear regulator applied to a three-dimensional memory, including:

[0039] LDO main circuit module 1 and bias module 2;

[0040] The LDO main circuit module 1 is used to generate a stable output voltage VOUT with good transient response characteristics;

[0041] The bias module 2 is connected to the output of the LDO main circuit module 2 and is used to generate a bias voltage for the LDO main circuit module 1;

[0042] When the output voltage of the LDO main circuit module 1 increases or decreases, the LDO main circuit module 1 can restore the output voltage to a static stable value.

[0043] Specifically, in this embodiment, the LDO main circuit module includes: a first MOS tube M1, a second MOS tube M2, a third MOS tube M3, a fourth MOS tube M4, a fifth MOS tube M5, a sixth MOS tube M6, a seventh MOS tube M7, an eighth MOS tube M8, a ninth MOS tube M9, a tenth MOS tube M10, a second MOS tube M11, a third MOS tube M12, a fourth MOS tube M13, a fifth MOS tube M14, a sixth MOS tube M15, a seventh MOS tube M16, a eighth MOS tube M17, a ninth MOS tube M18, a tenth MOS tube M19, a fifth MOS tube M20, a sixth MOS tube M21, a seventh MOS tube M22, a fifth MOS tube M23, a sixth MOS tube M24, a seventh MOS tube M25, a sixth MOS tube M26, a seventh MOS tube M27, a eighth MOS tube 10 、Eleventh MOS tube M 11 12th MOS tube M P , a first resistor R1, a second resistor R2, a third resistor R3, a first capacitor C1, a second capacitor C2 and a third capacitor C3;

[0044] The source terminal of the first MOS tube M1 is connected to the setting voltage V SET The gate end is connected to its own drain end, and is also connected to the gate end of the second MOS tube M2 and the gate end of the third MOS tube M3; the gate end of the third MOS tube M3 is connected to the second bias voltage V of the bias module B2 , the source terminal is connected to the drain terminal of the fourth MOS tube M4; the gate terminal of the fourth MOS tube M4 is connected to the first bias voltage V of the bias module B1 , the source terminal is grounded; the source terminal of the second MOS tube M2 is connected to the twelfth MOS tube M P The source terminal is connected to one end of the third resistor R3, which serves as the output terminal V of the LDO main circuit module. OUT The drain terminal of the second MOS tube M2 is connected to the tenth MOS tube M 10 The drain terminal of the LDO main circuit module is used as the feedback terminal V F The other end of the third resistor R3 is connected to one end of the third capacitor C3; the other end of the third capacitor C3 is connected to ground; the tenth MOS tube M 10 The gate terminal is connected to the second bias voltage V of the bias module B2 The source terminal is connected to the eleventh MOS tube M 11 The drain terminal of the eleventh MOS tube M 11 The gate terminal is connected to the first bias voltage V of the bias module B1 , the source terminal is connected to the ground; the twelfth MOS tube M P The drain terminal is connected to the input voltage V IN , the gate terminal is recorded as the power tube gate voltage V GThe gate end is connected to one end of the second resistor R2, and is also connected to the drain end of the fifth MOS tube M5, the drain end of the sixth MOS tube M6, and the drain end of the ninth MOS tube M9; the other end of the second resistor R2 is connected to one end of the second capacitor C2, and the other end of the second capacitor C2 is connected to the ground; the source end of the fifth MOS tube M5 is connected to the input voltage V IN , the gate end is connected to one end of the first resistor R1 and one end of the first capacitor C1; the other end of the first resistor R1 is connected to the third bias voltage V of the bias module B3 The other end of the first capacitor C1 is connected to the output end V of the LDO main circuit module OUT The gate terminal of the sixth MOS tube M6 is connected to the feedback terminal V of the LDO main circuit module F The source terminal is connected to the gate terminal of the ninth MOS tube M9 and is also connected to the drain terminal of the seventh MOS tube M7; the gate terminal of the seventh MOS tube M7 is connected to the second bias voltage V of the bias module B2 , the source terminal is connected to the drain terminal of the eighth MOS tube M8; the gate terminal of the eighth MOS tube M8 is connected to the first bias voltage V of the bias module B1 , the source end is connected to the ground; the source end of the ninth MOS tube M9 is connected to the ground; the first MOS tube M1, the second MOS tube M2, and the fifth MOS tube M5 are all PMOS tubes; the third MOS tube M3, the fourth MOS tube M4, the sixth MOS tube M6, the seventh MOS tube M7, the eighth MOS tube M8, the ninth MOS tube M9, and the tenth MOS tube M 10 、Eleventh MOS tube M 11 And the twelfth MOS tube M P All are NMOS tubes.

[0045] In this embodiment, the bias circuit module includes: a fourteenth MOS tube M B1 、15th MOS tube M B2 16th MOS tube M B3 、17th MOS tube M B4 , Eighteenth MOS tube M B5 , the first current source I BIAS , a fourth capacitor C4; wherein the fourteenth MOS tube M B1 The source terminal is connected to the input voltage V IN , the gate terminal is recorded as the third bias voltage V of the bias module B3 , which is connected to its own source terminal and is also connected to the fifteenth MOS tube M B2 The drain terminal and the gate terminal of the fifteenth MOS tube M B2The source terminal is connected to the sixteenth MOS tube M B3 The drain terminal and the gate terminal of the sixteenth MOS tube M B3 The drain terminal and the gate terminal of the bias module are recorded as the second bias voltage V B2 The sixteenth MOS tube M B3 The source terminal is connected to the seventeenth MOS tube M B4 The drain terminal of the seventeenth MOS tube M B4 The gate terminal is recorded as the first bias voltage V of the bias module B1 , which is connected to one end of the fourth capacitor C4 and is also connected to the eighteenth MOS tube M B5 The gate terminal, the drain terminal and the first current source I BIAS The other end of the fourth capacitor C4 is connected to the output end V of the LDO main circuit module OUT The eighteenth MOS tube M B5 The source terminal of the first current source I BIAS The input terminal is connected to the input voltage V IN The fourteenth MOS tube M B1 is a PMOS tube; the fifteenth MOS tube M B2 16th MOS tube M B3 、17th MOS tube M B4 And the eighteenth MOS tube M B5 All are NMOS tubes.

[0046] In this embodiment, the setting voltage V SET The generating circuit includes: a low power amplifier EA and a thirteenth MOS tube M SET The negative input terminal of the low power amplifier EA is connected to the reference voltage V REF The positive input terminal is connected to the thirteenth MOS tube M SET The drain terminal is the setting voltage V SET The output end of the low power amplifier EA is connected to the gate end of the thirteenth MOS tube; the thirteenth MOS tube M SET The source terminal is connected to the input voltage V IN The thirteenth MOS tube is a PMOS tube. The setting voltage V SET The power consumption of the generating circuit is very low. Since only a few microamperes of driving current are required, the size of the PMOS tube does not need to be set very large.

[0047] The input voltage V IN and output voltage V OUT The difference is large, the input voltage V IN When V is recorded, the output voltage VOUT The value is usually between 1 / 3V and 2 / 3V, with a typical value of 1 / 2V.

[0048] In this embodiment, the first capacitor C1 and the fourth capacitor C4 enhance the transient characteristics of the circuit by means of capacitive coupling. In static state, the first capacitor C1 and the fourth capacitor C4 are not conducting, and the fifth MOS transistor M5 and the fourteenth MOS transistor M B1 , the seventeenth MOS tube M B4 And the eighteenth MOS tube M B5 The current mirror structure works normally. When the output current is instantly converted from a small current load to a large current load, the gate voltage of the power tube does not change immediately due to its large size, and the output voltage V OUT When the capacitor is coupled, the voltage at both ends follows the output voltage to decrease, increasing the current flowing through both ends of the fifth MOS tube M5 and reducing the current flowing through the eighth MOS tube M8 and the eleventh MOS tube M 11 The voltage at both ends accelerates the twelfth MOS tube M P The gate voltage V G The charging makes the output voltage V OUT Quickly recover to static stable value.

[0049] In this embodiment, the second resistor R2 and the second capacitor C2 are used to compensate for the loop stability of the circuit; the third resistor R3 and the third capacitor C3 are used to enhance the transient characteristics of the circuit and improve the loop stability. The second resistor R2 and the second capacitor C2 generate a left half plane zero point for compensating the phase margin of the loop; the third resistor R3 and the third capacitor C3 are used not only to improve the transient characteristics of the circuit, but also to compensate for the phase margin of the loop under heavy load conditions.

[0050] The output resistance of the output end of the LDO main circuit module of this embodiment is very small, has a good load capacitance capability, and can drive a wide range of load capacitance.

[0051] The working process of the LDO circuit applied to the three-dimensional memory is as follows: when the output voltage increases, the drain voltage of the second MOS tube M2 increases, and the fifth MOS tube M5, the sixth MOS tube M6, the seventh MOS tube M7, the eighth MOS tube M8 and the ninth MOS tube M9 form a high output resistance and high bandwidth reverse amplifier to convert the output voltage V OUT The change is reversely amplified and fed back to the twelfth MOS tube M P gate terminal, thus forming negative feedback so that the output voltage returns to the static stable value.

[0052] Figure 4The simulation curve of the amplitude-frequency characteristic at 10mA and 0 load current in the embodiment of the present invention. It can be seen that under heavy load conditions, the low-frequency loop gain is 40dB, the GBW is 400MHz, and the phase margin is 109°; under heavy load conditions, the low-frequency loop gain is 38dB, the GBW is 10MHz, and the phase margin is 91°. The simulation results show that the LDO circuit applied to the three-dimensional memory can achieve good switching stability under various load conditions and has a large loop bandwidth under heavy load conditions.

[0053] Figure 5 The phase margin simulation curve under different load capacitances in the embodiment of the present invention. The resistance of the output node of the LDO circuit is very low, so it has a good load resistance capability. It can be seen that in the wide range of load capacitance of 0-10nF, the phase margin of the LDO circuit in both light load and heavy load scenarios is above 50°, meeting the loop stability requirements. The simulation results show that the LDO circuit applied to the three-dimensional memory has the ability to drive a wide range of load capacitance.

[0054] Figure 6 It is a transient characteristic response simulation curve in the embodiment of the present invention. It can be seen that the simulation condition is set that the load current jumps in the range of 0 to 10mA with an edge time of 10ps. Without load capacitance, when the load current switches from light load to heavy load, the maximum undershoot voltage at the output end is 144mV, and the recovery time is about 50ns; when the load current switches from heavy load to light load, the maximum overshoot voltage at the output end is 121mV, and the recovery time is about 400ns. With 100pF load capacitance, when the load current switches from light load to heavy load, the maximum undershoot voltage at the output end is 102mV, and the recovery time is about 55ns; when the load current switches from heavy load to light load, the maximum overshoot voltage at the output end is 76mV, and the recovery time is about 1μs. The simulation results show that the LDO circuit applied to the three-dimensional memory has good transient characteristics.

[0055] It can be seen that the LDO circuit applied to the three-dimensional memory described in the present invention has the following beneficial effects: 1) The present invention improves the transient response performance and reduces the size and area of ​​the power tube; 2) The LDO circuit described in the present invention has excellent transient characteristics, and can achieve a smaller overshoot voltage and a shorter recovery time in an extremely short load switching time; 3) The LDO circuit described in the present invention does not require an off-chip capacitor and can achieve full on-chip integration. 4) The present invention uses a 5-picofarad compensation capacitor and a 40-picofarad output capacitor, which has a smaller area than the traditional FVF-LDO circuit. 5) The LDO circuit described in the present invention has a good load capacitance capability and can drive a wide range of load capacitance. The present invention adopts the SMIC 110nm process. The simulation results show that the input voltage of the LDO circuit of the present invention is 3.3V, the output voltage is 1.65V, the static current is 70μA when unloaded, and the load switching range is 0-10mA. In the load switching time of 10ps, the overshoot voltage of the output voltage is 144mV and the recovery time is 50ns. In addition, this LDO circuit can drive a load capacitance of 0-10nF.

[0056] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A linear regulator for a three-dimensional memory, characterized in that: include: LDO main circuit module and bias module; The LDO main circuit module is used to generate an output voltage; The bias module is connected to the output of the LDO main circuit module and is used to generate a bias voltage for the LDO main circuit module; When the output voltage of the LDO main circuit module increases or decreases, the LDO main circuit module can restore the output voltage to a static stable value.

2. The linear regulator for three-dimensional memory according to claim 1, characterized in that: The LDO main circuit module includes: a first MOS tube, a second MOS tube, a third MOS tube, a fourth MOS tube, a fifth MOS tube, a sixth MOS tube, a seventh MOS tube, an eighth MOS tube, a ninth MOS tube, a tenth MOS tube, an eleventh MOS tube, a twelfth MOS tube, a first resistor, a second resistor, a third resistor, a first capacitor, a second capacitor and a third capacitor; Wherein, the source terminal of the first MOS tube is connected to the set voltage, the gate terminal is connected to its own drain terminal, and is also connected to the gate terminal of the second MOS tube and the gate terminal of the third MOS tube; the gate terminal of the third MOS tube is connected to the second bias voltage of the bias module, and the source terminal is connected to the drain terminal of the fourth MOS tube; the gate terminal of the fourth MOS tube is connected to the first bias voltage of the bias module, and the source terminal is grounded; the source terminal of the second MOS tube is connected to the source terminal of the twelfth MOS tube MP, and is also connected to one end of the third resistor, which is used as the output terminal of the LDO main circuit module; the drain terminal of the second MOS tube is connected to the drain terminal of the tenth MOS tube, which is used as the feedback terminal of the LDO main circuit module; the other end of the third resistor is connected to one end of the third capacitor; the other end of the third capacitor is connected to the ground; The gate terminal of the tenth MOS transistor is connected to the second bias voltage of the bias module, and the source terminal is connected to the drain terminal of the eleventh MOS transistor; the gate terminal of the eleventh MOS transistor is connected to the first bias voltage of the bias module, and the source terminal is connected to the ground; The drain terminal of the twelfth MOS transistor is connected to the input voltage, the gate terminal is connected to one end of the second resistor, and is also connected to the drain terminal of the fifth MOS transistor, the drain terminal of the sixth MOS transistor, and the drain terminal of the ninth MOS transistor; the other end of the second resistor is connected to one end of the second capacitor, and the other end of the second capacitor is connected to the ground; The source terminal of the fifth MOS tube is connected to the input voltage, and the gate terminal is connected to one end of the first resistor and one end of the first capacitor; the other end of the first resistor is connected to the third bias voltage of the bias module; the other end of the first capacitor is connected to the output end of the LDO main circuit module; the gate terminal of the sixth MOS tube is connected to the feedback end of the LDO main circuit module, the source terminal is connected to the gate terminal of the ninth MOS tube, and is also connected to the drain terminal of the seventh MOS tube; the gate terminal of the seventh MOS tube is connected to the second bias voltage of the bias module, and the source terminal is connected to the drain terminal of the eighth MOS tube; the gate terminal of the eighth MOS tube is connected to the first bias voltage of the bias module, and the source terminal is connected to the ground; the source terminal of the ninth MOS tube is connected to the ground; The first MOS tube, the second MOS tube, and the fifth MOS tube are all PMOS tubes; the third MOS tube, the fourth MOS tube, the sixth MOS tube, the seventh MOS tube, the eighth MOS tube, the ninth MOS tube, the tenth MOS tube, the eleventh MOS tube, and the twelfth MOS tube are all NMOS tubes.

3. The linear regulator for three-dimensional memory according to claim 2, characterized in that: The setting voltage V SET The generating circuit includes: A low-power amplifier and a thirteenth MOS tube; the negative input terminal of the low-power amplifier is connected to the reference voltage, the positive input terminal is connected to the drain terminal of the thirteenth MOS tube, which point is the set voltage, the output terminal of the low-power amplifier is connected to the gate terminal of the thirteenth MOS tube; the source terminal of the thirteenth MOS tube is connected to the input voltage; the thirteenth MOS tube is a PMOS tube.

4. The linear regulator for three-dimensional memory according to claim 2, characterized in that: The bias circuit module includes: a fourteenth MOS tube, a fifteenth MOS tube, a sixteenth MOS tube, a seventeenth MOS tube, an eighteenth MOS tube, a first current source and a fourth capacitor; Wherein, the source terminal of the fourteenth MOS tube is connected to the input voltage, the gate terminal is recorded as the third bias voltage of the bias module, the point is connected to its own source terminal, and is also connected to the drain terminal and gate terminal of the fifteenth MOS tube; the source terminal of the fifteenth MOS tube is connected to the drain terminal and gate terminal of the sixteenth MOS tube; the drain terminal and gate terminal of the sixteenth MOS tube are recorded as the second bias voltage of the bias module; the source terminal of the sixteenth MOS tube is connected to the drain terminal of the seventeenth MOS tube; the gate terminal of the seventeenth MOS tube is recorded as the first bias voltage of the bias module, the point is connected to one end of the fourth capacitor, and is also connected to the gate terminal, drain terminal and output terminal of the eighteenth MOS tube and the first current source; the other end of the fourth capacitor is connected to the output terminal of the LDO main circuit module; the source terminal of the eighteenth MOS tube is connected to the ground; the input terminal of the first current source is connected to the input voltage; The fourteenth MOS tube is a PMOS tube; the fifteenth MOS tube, the sixteenth MOS tube, the seventeenth MOS tube and the eighteenth MOS tube are all NMOS tubes.

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