Power management device and electronic device including the same

Abstract

A power management device and an electronic apparatus including the same are provided. The power management device includes: a primary power management integrated circuit (PMIC); and at least one sub PMIC, wherein the at least one sub PMIC is communicated with the main PMIC through a special pin. The main PMIC includes a first pin that, during a standby period before generating a first output voltage based on a battery voltage, enables a first function associated with a first initial operation based on the battery voltage, and, after completing the first initial operation, enables a second function associated with a second initial operation based on the battery voltage. A first sub-enable signal is applied to the at least one sub-PMIC through the first pin based on a power-on signal. The at least one sub-PMIC includes a second pin, receives the first sub-enable signal through the second pin, and enables a second function associated with a second initial operation based on the battery voltage in response to activation of the first sub-enable signal.

Description

Technical Field

[0001] Example embodiments relate to semiconductor devices, and more particularly, to a power management device including a plurality of power management integrated circuits (PMICs) and an electronic apparatus including the power management device. Background Art

[0002] System on chip (SoC) indicates a technology that integrates various functional blocks such as a central processing unit (CPU), a memory, a digital signal processing circuit, and / or an analog signal processing circuit into one semiconductor integrated circuit or one integrated circuit integrated according to the technology. SoC is developed as a more complex system including a processor, multimedia, graphics, security, etc. In response to the increase in power necessary for various functions of mobile devices and the demand for efficient power management, SoC embedded in mobile devices such as smart phones and tablet PCs includes a PMIC. The PMIC performs a power conversion function and a power sequence function to output various output voltages to a voltage rail.

[0003] When the circuits in the PMIC are too large, the increased physical footprint size can result in high operating costs due to reasons such as circuit layout challenges, crowded external component placement, thermal density challenges, and / or increased PMIC design complexity. When the physical size limit of the PMIC is reached, the SoC can employ multiple PMICs. Multiple PMICs can spread the thermal load and enable external components to be easily placed. Summary of the invention

[0004] Example embodiments provide a power management device capable of reducing current consumption in a standby period.

[0005] Example embodiments provide an electronic apparatus including a power management device capable of reducing current consumption in a standby period.

[0006] According to some example embodiments, a power management device includes: a main power management integrated circuit (PMIC); and at least one sub-PMIC, the at least one sub-PMIC configured to communicate with the main PMIC through a dedicated pin. The main PMIC includes a first pin and is configured to: enable a first function associated with a first initial operation based on a battery voltage during a standby period before generating a first output voltage based on a battery voltage; and after completing the first initial operation, apply a first sub-enable signal to the at least one sub-PMIC through the first pin based on a power-on signal. The at least one sub-PMIC each includes a second pin and is configured to: receive the first sub-enable signal through the second pin; and in response to activation of the first sub-enable signal, enable a second function associated with a second initial operation based on the battery voltage.

[0007] According to some example embodiments, an electronic device includes: a main processor, the main processor including a plurality of first power domains; and a power management device, the power management device being configured to: generate a plurality of output voltages in association with power sequences of the plurality of first power domains, and provide the plurality of output voltages to the plurality of first power domains through a voltage rail. The power management device includes: a main power management integrated circuit (PMIC), the main PMIC being configured to communicate with the main processor through a system bus; and at least one sub-PMIC, the at least one sub-PMIC being configured to communicate with the main PMIC through a dedicated pin. The main PMIC includes a first pin and is configured to: enable a first function associated with a first initial operation based on a battery voltage during a standby period before generating a first output voltage based on a battery voltage; and after completing the first initial operation, apply a first sub-enable signal to the at least one sub-PMIC through the first pin based on a power-on signal. The at least one sub-PMIC each includes a second pin and is configured to: receive the first sub-enable signal through the second pin; and enable a second function associated with a second initial operation based on the battery voltage in response to activation of the first sub-enable signal.

[0008] According to some example embodiments, a power management device includes: a main power management integrated circuit (PMIC); and at least one sub-PMIC, the at least one sub-PMIC configured to communicate with the main PMIC through a dedicated pin. The main PMIC includes a first pin and is configured to: enable a first function associated with a first initial operation based on a battery voltage during a standby period before generating a first output voltage based on a battery voltage; and after completing the first initial operation, apply a sub-enable signal to the at least one sub-PMIC through the first pin based on a power-on signal. The at least one sub-PMIC each includes a second pin and is configured to: receive the sub-enable signal through the second pin; and in response to activation of the sub-enable signal, enable a second function associated with a second initial operation based on the battery voltage. The main PMIC is also configured to: generate a reference voltage based on the battery voltage in response to the battery voltage reaching a reference level; activate the sub-enable signal in response to the reference voltage reaching a target level and activation of the power-on signal; and apply the sub-enable signal to the at least one sub-PMIC through the first pin.

[0009] Therefore, in some example embodiments, in the power management device including the main PMIC and the plurality of sub-PMICs, the main PMIC activates a sub-enable signal after enabling a function associated with an initial operation, and applies the activated sub-enable signal to the plurality of sub-PMICs to concurrently or sequentially enable the functions associated with the initial operation of the plurality of sub-PMICs. Therefore, the power management device can reduce the current consumed during the standby mode. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other features of the present inventive concept will become more apparent by describing some example embodiments of the present inventive concept with reference to the attached drawings.

[0011] Figure 1 is a block diagram illustrating an example of an electronic device according to some example embodiments.

[0012] Figure 2 FIG. 1 illustrates a method for transmitting a signal to a user according to some example embodiments. Figure 1 Configuration associated with transmitting power to components in an electronic device.

[0013] Figure 3 is a block diagram illustrating an example of an electronic device according to some example embodiments.

[0014] Figure 4 and Figure 5 The following diagrams respectively illustrate the Figure 3 The status of the main PMIC 200 and multiple sub-PMICs in the electronic device.

[0015] Figure 6 is an illustration of some example embodiments Figure 3 A block diagram of an example of a main PMIC and a first sub-PMIC in an electronic device.

[0016] Figure 7 is an illustration of some example embodiments Figure 3 A timing diagram of a turn-on scenario of multiple PMICs in an electronic device.

[0017] Figure 8 is an illustration of some example embodiments Figure 3 A timing diagram of shutdown scenarios of multiple PMICs in an electronic device.

[0018] Fig. 9 is a timing diagram illustrating a turn-on scenario of multiple PMICs when the multiple PMICs do not use a sub-enable signal according to some example embodiments.

[0019] Fig.10is a timing diagram illustrating a shutdown scenario of multiple PMICs when the multiple PMICs do not use a sub-enable signal according to some example embodiments.

[0020] Fig.11 is an illustration of some example embodiments Figure 3 A block diagram of an example of a first sub-PMIC in an electronic device.

[0021] Fig. 12A is an illustration of some example embodiments Fig.11 A circuit diagram of an example of a power switching circuit in FIG.

[0022] Fig. 12B is an illustration of some example embodiments Fig.11 A circuit diagram of an example of a power switching circuit in FIG.

[0023] Fig.13A is an illustration of some example embodiments Fig.11 A circuit diagram of an example of a power switching circuit in FIG.

[0024] Fig. 13B is an illustration of some example embodiments Fig.11 A circuit diagram of an example of a power switching circuit in FIG.

[0025] Fig.14A is an illustration of some example embodiments Fig.11 A circuit diagram of an example of a power switching circuit in FIG.

[0026] Fig. 14B is an illustration of some example embodiments Fig.11 A circuit diagram of an example of a power switching circuit in FIG.

[0027] Fig.15 is a block diagram illustrating an example of an electronic device according to an example embodiment.

[0028] Fig.16 is a block diagram illustrating an example of an electronic device according to some example embodiments.

[0029] Fig.17 is a block diagram illustrating a portion of an electronic device according to some example embodiments.

[0030] Fig.18 is an illustration of some example embodiments Fig.17 A block diagram of an example of a main processor in an electronic device in FIG.

[0031] Fig.19 is an illustration of some example embodiments Fig.17 Block diagram of one of the DC-DC converters in the PMIC.

[0032] Fig. 20 is an illustration of some example embodiments Fig.17 Block diagram of one of the LDO regulators in the main PMIC in FIG.

[0033] Fig.21 is a diagram illustrating the operation according to some example embodiments Figure 3 Flow chart of a method for a main PMIC and multiple sub-PMICs in FIG.

[0034] Fig. 22 is a block diagram illustrating a mobile device according to some example embodiments.

[0035] Fig.23 and Fig.24 is a diagram illustrating an autonomous driving system according to some example embodiments. DETAILED DESCRIPTION

[0036] Example embodiments of the inventive concept will be described more fully hereinafter with reference to the accompanying drawings.Like reference numerals may refer to like elements throughout the drawings.

[0037] It should be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on the other element, or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements. It should also be understood that when an element is referred to as being "on" another element, it can be above or below the other element or adjacent to the other element (e.g., horizontally adjacent).

[0038] It should be understood that elements and / or properties thereof described herein as being "substantially" the same and / or identical include elements and / or properties thereof having a relative difference in magnitude equal to or less than 10%. Furthermore, regardless of whether an element and / or property thereof is qualified as "substantially", it should be understood that these elements and / or properties thereof should be interpreted as including manufacturing or operating tolerances (e.g., ±10%) around the stated element and / or property thereof.

[0039] Figure 1 is a block diagram illustrating an example of an electronic device according to some example embodiments.

[0040] refer to Figure 1 , the electronic device 1000 may include various electronic circuits. For example, the electronic circuits of the electronic device 1000 may include an image processing block 1100, a communication block 1200, an audio processing block 1300, a buffer memory 1400, a non-volatile memory 1500, a user interface 1600, a main processor 1800, a power management device 1900, and a charger circuit 1910.

[0041] The electronic device 1000 may be implemented with any computing device or any mobile / portable device such as a mobile phone, a smart phone, a tablet computer, a laptop computer, a personal digital assistant (PDA), an enterprise digital assistant (EDA), a portable multimedia player (PMP), a digital camera, a portable game console, a music player, a video player, a navigation device, a wearable device, an Internet of Things (IoT) device, an Internet of Everything (IoE) device, an e-book, a virtual reality (VR) device, an augmented reality (AR) device, a robotic device, etc., but example embodiments are not limited thereto.

[0042] For example, the electronic device 1000 may be connected to the battery 1920, and the battery 1920 may supply power for operation of the electronic device 1000. However, the inventive concept is not limited thereto. For example, the power supplied to the electronic device 1000 may be provided from a power source other than the battery 1920.

[0043] The image processing block 1100 may receive light through the lens 1110. The image sensor 1120 and the image signal processor 1130 included in the image processing block 1100 may generate image information associated with an external object based on the received light.

[0044] The communication module 1200 may exchange signals with an external device / system through an antenna 1210. The transceiver 1220 and the modem (modulator / demodulator) 1230 of the communication block 1200 may process signals exchanged with the external device / system according to one or more of various wired / wireless communication protocols.

[0045] The audio processing block 1300 may process sound information by using the audio signal processor 1310. The audio processing block 1300 may receive an audio input through a microphone 1320, or may output audio through a speaker 1330.

[0046] The buffer memory 1400 may store data used for the operation of the electronic device 1000. For example, the buffer memory 1400 may temporarily store data processed by or to be processed by the main processor 1800. For example, the buffer memory 1400 may include a volatile memory such as a static random access memory (SRAM), a dynamic RAM (DRAM), or a synchronous DRAM (SDRAM), and / or a nonvolatile memory such as a phase change RAM (PRAM), a magnetoresistive RAM (MRAM), a resistive RAM (ReRAM), or a ferroelectric RAM (FRAM).

[0047] The nonvolatile memory 1500 can store data regardless of whether power is supplied. For example, the nonvolatile memory 1500 may include at least one of various nonvolatile memories such as flash memory, PRAM, MRAM, ReRAM, and FRAM. For example, the nonvolatile memory 1500 may include a removable memory such as a secure digital (SD) card or a solid state drive (SSD), and / or an embedded memory such as an embedded multimedia card (eMMC).

[0048] The user interface 1600 may enable communication between a user and the electronic device 1000. For example, the user interface 1600 may include an input interface for receiving an input from a user and an output interface for providing information to the user.

[0049] The main processor 1800 may control the overall operation of the components of the electronic device 1000. The main processor 1800 may perform various operations in order to operate the electronic device 1000. For example, the main processor 1800 may be implemented with an operation processing device / circuit that may include one or more processor cores such as a general-purpose processor, a dedicated processor, an application processor, or a microprocessor, but example embodiments are not limited thereto.

[0050] The power management device 1900 and the charger circuit 1910 may supply power for operating the electronic device 1000. For example, the power management device 1900 may be implemented with a plurality of power management integrated circuits (PMICs) 1900a, 1900b, ..., 1900n. Figure 2 Here, n may be a natural number greater than 2.

[0051] Figure 2 FIG. 1 illustrates a method for transmitting a signal to a user according to some example embodiments. Figure 1 Configuration associated with transmitting power to components in an electronic device.

[0052] The power management device 1900 can supply power to the components 1100 to 1800 of the electronic device 1000 through a voltage rail (e.g., a power rail). For example, the charger circuit 1910 can charge the battery 1920 based on the power PWR received from the outside, and the battery 1920 can provide the power management device 1900 with a battery voltage VBAT based on the charged voltage. The power management device 1900 can output power to be supplied to the components 1100 to 1600 and 1800 of the electronic device 1000 based on the battery voltage VBAT. The power management device 1900 can supply power obtained by appropriately converting the battery voltage VBAT to the components 1100 to 1600 and 1800 of the electronic device 1000. The components 1100 to 1600 other than the main processor 1800 can be referred to as a load system 1005.

[0053] In some example embodiments, the power management device 1900 may include a plurality of PMICs 1900a, 1900b, ..., 1900n, each of which may supply power to at least one component of the electronic device 1000. For example, a voltage output from each PMIC may be transmitted to at least one of the image processing block 1100, the communication block 1200, the audio processing block 1300, the buffer memory 1400, the nonvolatile memory 1500, the user interface 1600 (e.g., an input / output interface such as a display device 1610 and a touch processing integrated circuit (IC) 1690), and the main processor 1800, but example embodiments are not limited thereto. Each component of the electronic device 1000 may operate based on the transmitted voltage.

[0054] The voltages generated from the plurality of PMICs 1900a, 1900b, ..., 1900n may be transmitted to the components 1100 to 1800 of the electronic device 1000 in a predetermined or preferred order, or may be blocked in a predetermined or preferred order. To this end, the plurality of PMICs 1900a, 1900b, ..., 1900n may be synchronized with each other during a power-on sequence and a power-off sequence.

[0055] In some example embodiments, before executing a power-on sequence, the main PMIC (one of PMICs 1900a, 1900b, ..., 1900n) may enable a first function associated with a first initial operation based on a battery voltage VBAT during a standby period before generating a first output voltage based on a battery voltage VBAT, and may apply a sub-enable signal to at least one sub-PMIC (at least one sub-PMIC may correspond to PMICs 1900a, 1900b, ..., 1900n other than the main PMIC) through a first pin based on a power-on signal received from the outside after completing the first initial operation. Each sub-PMIC may receive the first sub-enable signal through a second pin, and may enable a second function associated with a second initial operation based on a battery voltage in response to activation of the sub-enable signal. Therefore, the power management device 1900 may reduce the standby current consumed during the standby period.

[0056] In some example embodiments, before executing the power-on sequence, the main PMIC deactivates the sub-enable signal in response to the deactivation of the power-on signal, and applies the deactivated sub-enable signal to the sub-PMIC through the first pin. Each sub-PMIC receives the deactivated sub-enable signal through the second pin and disables the second function. The main PMIC applies the activated sub-enable signal to the sub-PMIC, deactivates the first function after a predetermined or preferred time has passed since the activated sub-enable signal was applied to the sub-PMIC, and enters the off state.

[0057] Figure 3 is a block diagram illustrating an example of an electronic device according to some example embodiments.

[0058] refer to Figure 3 , the electronic device 10 may include a power management device 50 and a load system 600. The load system 600 may correspond to Figure 2 The load system 1005 is shown in FIG.

[0059] The power management device 50 may include a main PMIC 200 and a plurality of sub-PMICs 300a, 300b, ..., 300n. The plurality of sub-PMICs 300a, 300b, ..., 300n may be referred to as first to nth sub-PMICs.

[0060] The battery voltage VBAT may be commonly supplied to the main PMIC 200 and the plurality of sub-PMICs 300a, 300b, . . . , 300n, and the main PMIC 200 may be supplied from the outside (eg, Figure 2 The main processor 1800 in receives a power-on signal PRON.

[0061] The master PMIC 200 may include a control logic 210, an undervoltage lockout (UVLO) circuit 220, a reference voltage (BGR) generator 230, an internal low voltage dropout (ILDO) regulator 240, and a first pin 201. The UVLO circuit 220, the BGR generator 230, and the ILDO regulator 240 may perform a first function associated with a first initial operation. The first pin 201 may be referred to as a first dedicated pin.

[0062] The sub-PMIC 300a may include a control logic 310a, a UVLO circuit 320a, a BGR generator 330a, an ILDO regulator 340a, and a second pin 301a. The UVLO circuit 320a, the BGR generator 330a, and the ILDO regulator 340a may perform a second function associated with a second initial operation.

[0063] The sub-PMIC 300b may include a control logic 310b, a UVLO circuit 320b, a BGR generator 330b, an ILDO regulator 340b, and a second pin 301b. The UVLO circuit 320b, the BGR generator 330b, and the ILDO regulator 340b may perform a second function associated with a second initial operation.

[0064] The sub-PMIC 300n may include a control logic 310n, a UVLO circuit 320n, a BGR generator 330n, an ILDO regulator 340n, and a second pin 301n. The UVLO circuit 320n, the BGR generator 330n, and the ILDO regulator 340n may perform a second function associated with a second initial operation.

[0065] The second pins 301a, 301b, ..., 301n may all be referred to as second dedicated pins.

[0066] Each of the main PMIC 200 and the plurality of sub-PMICs 300 a , 300 b , . . . , 300 n may provide a corresponding output voltage to the load system 600 through a corresponding one of the voltage rails V-RAILS 12 , 14 , 16 , . . . , 18 .

[0067] The main PMIC 200 may apply a sub-enable signal EN_SUB to the plurality of sub-PMICs 300a, 300b, ..., 300n through the first pin 201. Each of the plurality of sub-PMICs 300a, 300b, ..., 300n may commonly receive the sub-enable signal EN_SUB through a corresponding one of the second pins 301a, 301b, ..., 301n, and may concurrently perform a second function associated with a second initial operation in response to activation of the sub-enable signal EN_SUB.

[0068] Figure 4 and Figure 5 The following diagrams respectively illustrate the Figure 3 The status of the main PMIC 200 and the plurality of sub-PMICs 300a, 300b, ..., 300n in the electronic device.

[0069] refer to Figure 4, when the battery voltage VBAT is commonly supplied to the main PMIC 200 and the plurality of sub-PMICs 300a, 300b, ..., 300n, the UVLO circuit 220, the BGR generator 230, and the ILDO regulator 240 in the main PMIC 200 that perform the first function associated with the first initial operation are activated, enter the on state, and perform the first function. According to some example embodiments, because the power-on signal PRON is in the deactivated state, the control logic 210 in the main PMIC 200 deactivates the sub-enable signal EN_SUB at a logic low level (e.g., "L"), and applies the deactivated sub-enable signal EN_SUB to the plurality of sub-PMICs 300a, 300b, ..., 300n. Because the sub enable signal EN_SUB has a logic low level, the UVLO circuits 320a, 320b, ..., 320n, the BGR generators 330a, 330b, ..., 330n, and the ILDO regulators 340a, 340b, ..., 340n in the plurality of sub-PMICs 300a, 300b, ..., 300n are in a turned-off state.

[0070] refer to Figure 5 , the UVLO circuit 220, the BGR generator 230, and the ILDO regulator 240 that perform the first function associated with the first initial operation in the master PMIC 200 are in an on state and perform the first function. According to some example embodiments, because the power-on signal PRON is in an activated state, the control logic 210 in the master PMIC 200 activates the sub-enable signal EN_SUB at a logic high level (e.g., “H”), and applies the activated sub-enable signal EN_SUB to the plurality of sub-PMICs 300a, 300b, . . . , 300n. Because the sub-enable signal EN_SUB has a logic high level, the UVLO circuits 320a, 320b, ..., 320n, the BGR generators 330a, 330b, ..., 330n, and the ILDO regulators 340a, 340b, ..., 340n in the plurality of sub-PMICs 300a, 300b, ..., 300n transition to an on state and concurrently perform a second function associated with the second initial operation.

[0071] Figure 6 is an illustration of some example embodiments Figure 3 A block diagram of an example of a main PMIC and a first sub-PMIC in an electronic device.

[0072] refer to Figure 6 , the master PMIC 200 may include a control logic 210 , a UVLO circuit 220 , a BGR generator 230 , an ILDO regulator 240 , and a first pin 201 .

[0073] The UVLO circuit 220 may receive the battery voltage VBAT, may compare the battery voltage VBAT with a reference level, may generate a voltage level detection signal VLDS_M activated in response to the battery voltage VBAT reaching the reference level, and may provide the voltage level detection signal VLDS_M to the BGR generator 230 and the control logic 210 .

[0074] The BGR generator 230 may generate a reference voltage VREF_M based on the battery voltage VBAT in response to activation of the voltage level detection signal VLDS_M, and may provide the reference voltage VREF_M to the ILDO regulator 240 .

[0075] The ILDO regulator 240 may receive the battery voltage VBAT and may generate an internal voltage VINT_M based on the reference voltage VREF_M and the battery voltage VBAT. The ILDO regulator 240 may generate the internal voltage VINT_M in response to the reference voltage VREF_M reaching a first target level, may provide the internal voltage VINT_M to the control logic 210, and may provide an OK signal INT_OK_M in response to the reference voltage VREF_M reaching a second target level.

[0076] The control logic 210 can receive the internal voltage VINT_M, can operate based on the internal voltage VINT_M, can receive the voltage level detection signal VLDS_M and the OK signal INT_OK_M, can activate the sub-enable signal EN_SUB in response to the activation of the voltage level detection signal VLDS_M and the activation of the OK signal INT_OK_M and the power-on signal PRON, and can apply the sub-enable signal EN_SUB to the first sub-PMIC 300a through the first pin 201.

[0077] The first sub-PMIC 300 a may include a control logic 310 a , a UVLO circuit 320 a , a BGR generator 330 a , an ILDO regulator 340 a , and a second pin 301 a .

[0078] The control logic 310 a may receive the sub enable signal EN_SUB through the second pin 301 a and may operate the UVLO circuit 320 a , the BGR generator 330 a , the ILDO regulator 340 a , and the second pin 301 a in response to activation of the sub enable signal EN_SUB.

[0079] The UVLO circuit 320a may receive the battery voltage VBAT, may compare the battery voltage VBAT with a reference level, may generate a voltage level detection signal VLDS_a activated in response to the battery voltage VBAT reaching the reference level, and may provide the voltage level detection signal VLDS_a to the BGR generator 330a and the control logic 310a.

[0080] The BGR generator 330 a may generate a reference voltage VREF_a based on the battery voltage VBAT in response to activation of the voltage level detection signal VLDS_a, and may provide the reference voltage VREF_a to the ILDO regulator 340 a .

[0081] The ILDO regulator 340a may receive the battery voltage VBAT and may generate an internal voltage VINT_a based on the reference voltage VREF_a and the battery voltage VBAT. The ILDO regulator 340a may generate the internal voltage VINT_a in response to the reference voltage VREF_a reaching a first target level, may provide the internal voltage VINT_a to the control logic 310a, and may provide an OK signal INT_OK_a in response to the reference voltage VREF_a reaching a second target level.

[0082] The control logic 310a may receive the internal voltage VINT_a, may operate based on the internal voltage VINT_a, may receive the voltage level detection signal VLDS_a and the OK signal INT_OK_a, and may execute a power-on sequence associated with generating multiple supply voltages by controlling multiple DC-DC converters in response to activation of the voltage level detection signal VLDS_a and the OK signal INT_OK_a.

[0083] Each configuration of the second to nth sub-PMICs 300b, ..., 300n may be the same as Figure 6 The configuration of the first sub-PMIC 300a in FIG.

[0084] Figure 7 is an illustration of some example embodiments Figure 3 A timing diagram of a “turn on” scenario for multiple PMICs in an electronic device.

[0085] refer to Figures 3 to 7When the battery voltage VBAT starts to be commonly supplied to the main PMIC 200 and multiple sub-PMICs 300a, 300b, ..., 300n in the electronic device 50, the UVLO circuit 220 can generate a voltage level detection signal VLDS_M that is activated in response to the battery voltage VBAT reaching the reference level VL_REF at time point t11, and the voltage level detection signal VLDS_M can be provided to the BGR generator 230 and the control logic 210.

[0086] At a time point t11 ​​, the BGR generator 230 generates a reference voltage VREF_M based on the battery voltage VBAT in response to activation of the voltage level detection signal VLDS_M, and may provide the voltage level detection signal VLDS_M to the ILDO regulator 240 .

[0087] ILDO regulator 240 receives battery voltage VBAT and may generate internal voltage VINT_M in response to reference voltage VREF_M reaching a first target level at time point t12 and may provide internal voltage VINT_M to control logic 210. Internal voltage VINT_M may reach a second target level at a second time point t13.

[0088] In response to activation of the power-on signal PRON at the time point t14 , the control logic 210 activates the sub enable signal EN_SUB at the time point t15 , and may provide the activated sub enable signal EN_SUB to the first sub-PMIC 300 a and the plurality of sub-PMICs 300 b , . . . , 300 n .

[0089] The first sub-PMIC 300a receives the activated sub-enable signal EN_SUB through the second pin 301a, and the UVLO circuit 320a generates a voltage level detection signal VLDS_a activated at a time point t15 and may provide the voltage level detection signal VLDS_a to the BGR generator 330a and the control logic 310a.

[0090] At a time point t15 , the BGR generator 330 a generates a reference voltage VREF_a based on the battery voltage VBAT in response to activation of the voltage level detection signal VLDS_a, and may provide the voltage level detection signal VLDS_a to the ILDO regulator 340 a .

[0091] The ILDO regulator 340a receives the battery voltage VBAT and may generate an internal voltage VINT_a in response to the reference voltage VREF_a reaching the first target level and may provide the internal voltage VINT_a to the control logic 310a. The internal voltage VINT_a may reach a second target level at time point t16.

[0092] The main PMIC 200 is in the off state until time point t14 and transits to the on state from time point t14. The first sub-PMIC 300a and the plurality of sub-PMICs 300b, ..., 300n are in the off state until time point t15 and transits to the on state from time point t15.

[0093] Therefore, in some example embodiments, the standby mode (eg, standby state) of the main PMIC 200 and the plurality of sub-PMICs 300 a , 300 b , . . . , 300 n of the electronic device 50 corresponds to a time interval from the time point t11 ​​to the time point t15 .

[0094] Figure 8 is an illustration of some example embodiments Figure 3 A timing diagram of a “shutdown” scenario for multiple PMICs in an electronic device.

[0095] refer to Figures 3 to 6 and Figure 8 , the control logic 210 in the main PMIC 200 deactivates the sub-enable signal EN_SUB at a logic low level in response to the deactivation of the power-on signal PRON at the time point t21. The UVLO circuit 320a, the BGR generator 330a, and the ILDO regulator 340a in the first sub-PMIC 300a are deactivated at the first time point t21, the voltage level detection signal VLDS_a is deactivated at a logic low level, and the voltage levels of the reference voltage VREF_a and the internal voltage VINT_a are reduced.

[0096] In some example embodiments, when the battery voltage VBAT becomes equal to or less than the reference level VL_REF at the time point t22, the UVLO circuit 220 deactivates the voltage level detection signal VLDS_M at a logic low level, the BGR generator 230 suspends generating the reference voltage VREF_M in response to the deactivated voltage level detection signal VLDS_M, and the ILDO regulator 240 suspends generating the internal voltage VINT_M at the time point t22.

[0097] The main PMIC 200 , the first sub-PMIC 300 a , and the plurality of sub-PMICs 300 b , . . . , 300 n are in an “on” state until a time point t21 , and transition to an “off” state from the time point t21 .

[0098] Therefore, in some example embodiments, the standby mode (eg, standby state) before the power-off sequence of the main PMIC 200 and the plurality of sub-PMICs 300a, 300b, . . . , 300n of the electronic device 50 corresponds to a time interval from time point t21 to time point t22.

[0099] Fig. 9 is a timing diagram illustrating an “on” scenario of multiple PMICs when the multiple PMICs do not use a sub-enable signal according to some example embodiments.

[0100] exist Fig. 9 In the embodiment, for example, each of the plurality of PMICs includes a control logic, a UVLO circuit, a BGR generator, and an ILDO regulator.

[0101] refer to Fig. 9 In some example embodiments, when the battery voltage VBAT starts to be commonly supplied to the plurality of PMICs, the UVLO circuit generates a voltage level detection signal VLDS activated in response to the battery voltage VBAT reaching the reference level VL_REF at a time point t31, and provides the voltage level detection signal VLDS to the BGR generator.

[0102] At a time point t31 , the BGR generator generates a reference voltage VREF based on the battery voltage VBAT in response to activation of the voltage level detection signal VLDS, and provides the voltage level detection signal VLDS to the ILDO regulator.

[0103] The ILDO regulator receives the battery voltage VBAT and generates an internal voltage VINT in response to the reference voltage VREF reaching a first target level at time point t32 and may provide the internal voltage VINT to the control logic. The internal voltage VINT may reach a second target level at a second time point t33.

[0104] In response to the activation of the power-on signal PRON at the time point t34 , the plurality of PMICs transition from the “off” state to the “on” state.

[0105] Therefore, in some example embodiments, Fig. 9 The standby mode (eg, standby state) of the plurality of sub-PMICs in corresponds to a time interval from a time point t31 to a time point t34.

[0106] When with Figure 7 In comparison, because Fig. 9 All control logics, UVLO circuits, BGR generators, and ILDO regulators in the multiple PMICs are operated during the standby mode, so the standby current consumed during the standby mode increases.

[0107] Fig.10 is a timing diagram illustrating a “shutdown” scenario for multiple PMICs when the multiple PMICs do not use a sub-enable signal.

[0108] refer to Fig.10, when the power-on signal PRON is deactivated at a logic low level in each of the plurality of PMICs at time point t41, and when the battery voltage VBAT becomes equal to or less than the reference level VL_REF at time point t42, the UVLO circuit deactivates the voltage level detection signal VLDS at a logic low level, the BGR generator suspends generation of the reference voltage VREF in response to the deactivated voltage level detection signal VLDS, and the ILDO regulator suspends generation of the internal voltage VINT at time point t42.

[0109] The plurality of PMICs are in the “ON” state until the time point t41 , and transition to the “OFF” state from the time point t41 .

[0110] Therefore, in some example embodiments, Fig.10 The standby mode (eg, standby state) before the power-off sequence of the plurality of PMICs in FIG. 4 corresponds to a time interval from a time point t41 to a time point t42 .

[0111] When with Figure 8 In comparison, because Fig.10 The control logic, UVLO circuit, BGR generator, and ILDO regulator in all the multiple PMICs operate during the standby mode, so the standby current consumed during the standby mode increases.

[0112] Fig.11 is an illustration of some example embodiments Figure 3 A block diagram of an example of a first sub-PMIC in an electronic device.

[0113] refer to Fig.11 , the first sub-PMIC 300 a_1 may include a control logic 310 a , a UVLO circuit 320 a , a BGR generator 330 a , an ILDO regulator 340 a , a power switch circuit 350 , and a second pin 301 a .

[0114] The power switch circuit 350 may selectively transmit the battery voltage VBAT to the UVLO circuit 320a and the BGR generator 330a based on the sub-enable signal EN_SUB received through the second pin 301a. The power switch circuit 350 may provide the battery voltage VBAT to the UVLO circuit 320a and the BGR generator 330a in response to activation of the sub-enable signal EN_SUB.

[0115] The control logic 310 a may receive the sub enable signal EN_SUB through the second pin 301 a and may operate the UVLO circuit 320 a , the BGR generator 330 a , the ILDO regulator 340 a , and the second pin 301 a in response to activation of the sub enable signal EN_SUB.

[0116] The UVLO circuit 320a may receive the battery voltage VBAT through the power switching circuit 350, may compare the battery voltage VBAT with a reference level, may generate a voltage level detection signal VLDS_a that is activated in response to the battery voltage VBAT reaching the reference level, and may provide the voltage level detection signal VLDS_a to the BGR generator 330a and the control logic 310a.

[0117] The BGR generator 330 a may receive the battery voltage VBAT through the power switching circuit 350 , may generate a reference voltage VREF_a based on the battery voltage VBAT in response to activation of the voltage level detection signal VLDS_a, and may provide the voltage level detection signal VLDS_a to the ILDO regulator 340 a .

[0118] The ILDO regulator 340a may receive the battery voltage VBAT and may generate an internal voltage VINT_a based on the reference voltage VREF_a and the battery voltage VBAT. The ILDO regulator 340a may generate the internal voltage VINT_a in response to the reference voltage VREF_a reaching a first target level, may provide the internal voltage VINT_a to the control logic 310a, and may provide an OK signal INT_OK_a in response to the reference voltage VREF_a reaching a second target level.

[0119] The control logic 310a may receive the internal voltage VINT_a, may operate based on the internal voltage VINT_a, may receive the voltage level detection signal VLDS_a and the OK signal INT_OK_a, and may execute a power-on sequence associated with generating multiple supply voltages by controlling multiple DC-DC converters in response to activation of the voltage level detection signal VLDS_a and the OK signal INT_OK_a.

[0120] According to some example embodiments, each configuration of the second to nth sub-PMICs 300b, . . . , 300n may be the same as Fig.11 The configuration of the first sub-PMIC 300a_1 in FIG.

[0121] Fig. 12A is an illustration of some example embodiments Fig.11 A circuit diagram of an example of a power switching circuit in FIG.

[0122] refer to Fig. 12A The power switching circuit 350 a may include a first p-channel metal oxide semiconductor (PMOS) transistor 351 , a second PMOS transistor 352 , and an inverter 353 .

[0123] The inverter 353 may generate an inverted sub-enable signal EN_SUB_B by inverting the sub-enable signal EN_SUB.

[0124] The first PMOS transistor 351 may have a source receiving the battery voltage VBAT, a drain connected to the UVLO circuit 320 a , and a gate receiving the inverted sub enable signal EN_SUB_B, and may selectively transfer the battery voltage VBAT to the UVLO circuit 320 a based on the inverted sub enable signal EN_SUB_B.

[0125] The second PMOS transistor 352 may have a source receiving the battery voltage VBAT, a drain connected to the BGR generator 330 a , and a gate receiving the inverted sub enable signal EN_SUB_B, and may selectively transfer the battery voltage VBAT to the BGR generator 330 a based on the inverted sub enable signal EN_SUB_B.

[0126] Fig. 12B is an illustration of some example embodiments Fig.11 A circuit diagram of an example of a power switching circuit in FIG.

[0127] refer to Fig. 12B , the power switch circuit 350a_1 may include a PMOS transistor 351a and an inverter 353a.

[0128] The inverter 353 a may generate an inverted sub-enable signal EN_SUB_B by inverting the sub-enable signal EN_SUB.

[0129] The PMOS transistor 351a may have a source receiving the battery voltage VBAT, a drain connected to the UVLO circuit 320a and the BGR generator 330a, and a gate receiving the inverted sub-enable signal EN_SUB_B, and may selectively transfer the battery voltage VBAT to the UVLO circuit 320a and the BGR generator 330a based on the inverted sub-enable signal EN_SUB_B.

[0130] Fig.13A is an illustration of some example embodiments Fig.11 A circuit diagram of an example of a power switching circuit in FIG.

[0131] refer to Fig.13A The power switching circuit 350 b may include a first n-channel metal oxide semiconductor (NMOS) transistor 354 and a second NMOS transistor 355 .

[0132] The first NMOS transistor 354 may have a drain receiving the battery voltage VBAT, a source connected to the UVLO circuit 320 a , and a gate receiving the sub enable signal EN_SUB, and may selectively transfer the battery voltage VBAT to the UVLO circuit 320 a based on the sub enable signal EN_SUB.

[0133] The second NMOS transistor 355 may have a drain receiving the battery voltage VBAT, a source connected to the BGR generator 330 a , and a gate receiving the sub enable signal EN_SUB, and may selectively transfer the battery voltage VBAT to the BGR generator 330 a based on the sub enable signal EN_SUB_B.

[0134] Fig. 13B is an illustration of some example embodiments Fig.11 A circuit diagram of an example of a power switching circuit in FIG.

[0135] refer to Fig. 13B , the power switching circuit 350b_1 may include an NMOS transistor 354a.

[0136] The NMOS transistor 354a may have a drain receiving the battery voltage VBAT, a source connected to the UVLO circuit 320a and the BGR generator 330a, and a gate receiving the sub-enable signal EN_SUB, and may selectively transfer the battery voltage VBAT to the UVLO circuit 320a and the BGR generator 330a based on the sub-enable signal EN_SUB.

[0137] Fig.14A is an illustration of some example embodiments Fig.11 A circuit diagram of an example of a power switching circuit in FIG.

[0138] refer to Fig.14A The power switching circuit 350 c may include a first transmission gate 356 , a second transmission gate 357 , and an inverter 358 .

[0139] The inverter 358 may generate an inverted sub-enable signal EN_SUB_B by inverting the sub-enable signal EN_SUB.

[0140] The first transmission gate 356 may have a first terminal receiving the battery voltage VBAT, a second terminal connected to the UVLO circuit 320 a, and a control terminal receiving the sub-enable signal EN_SUB and the inverted sub-enable signal EN_SUB_B, and may selectively transmit the battery voltage VBAT to the UVLO circuit 320 a based on the sub-enable signal EN_SUB and the inverted sub-enable signal EN_SUB_B.

[0141] The second transmission gate 357 may have a first terminal receiving the battery voltage VBAT, a second terminal connected to the BGR generator 330 a, and a control terminal receiving the sub-enable signal EN_SUB and the inverted sub-enable signal EN_SUB_B, and may selectively transmit the battery voltage VBAT to the BGR generator 330 a based on the sub-enable signal EN_SUB and the inverted sub-enable signal EN_SUB_B.

[0142] Fig. 14B is an illustration of some example embodiments Fig.11 A circuit diagram of an example of a power switching circuit in FIG.

[0143] refer to Fig. 14B , the power switch circuit 350c_1 may include a transmission gate 356a and an inverter 358a.

[0144] The inverter 358 a may generate an inverted sub-enable signal EN_SUB_B by inverting the sub-enable signal EN_SUB.

[0145] The transmission gate 356a may have a first terminal receiving the battery voltage VBAT, a second terminal connected to the UVLO circuit 320a and the BGR generator 330a, and a control terminal receiving the sub-enable signal EN_SUB and the inverted sub-enable signal EN_SUB_B, and may selectively transmit the battery voltage VBAT to the UVLO circuit 320a and the BGR generator 330a based on the sub-enable signal EN_SUB and the inverted sub-enable signal EN_SUB_B.

[0146] Therefore, in some example embodiments, Fig.11 The power switch circuit 350 in the embodiment may include one of a pair including a first PMOS transistor 351 and a second PMOS transistor 352 , a pair including a first NMOS transistor 354 and a second NMOS transistor 355 , and a pair including a first transmission gate 356 and a second transmission gate 357 .

[0147] Or, in some example embodiments, Fig.11 The power switch circuit 350 in the embodiment may include one of a PMOS transistor 351 a , an NMOS transistor 354 a , and a transmission gate 356 a .

[0148] Fig.15 is a block diagram illustrating an example of an electronic device according to some example embodiments.

[0149] refer to Fig.15 , the electronic device 10a may include a power management device 50a and a load system 600. According to some example embodiments, the load system 600 may correspond to Figure 2The load system 1005 in.

[0150] The power management device 50a may include a main PMIC 200a and a plurality of sub-PMICs 300aa, 300ba, ..., 300na. The plurality of sub-PMICs 300aa, 300ba, ..., 300na may be referred to as first to nth sub-PMICs.

[0151] The battery voltage VBAT may be commonly supplied to the main PMIC 200a and the plurality of sub-PMICs 300aa, 300ba, . . . , 300na, and the main PMIC 200a may be supplied from the outside (eg, Figure 2 The main processor 1800 in receives a power-on signal PRON.

[0152] According to some example embodiments, each configuration of the main PMIC 200a and the plurality of sub-PMICs 300aa, 300ba, . . . , 300na may be configured with Figure 3 The configurations of the main PMIC 200 and the plurality of sub-PMICs 300a, 300b, . . . , 300n are substantially similar.

[0153] Each of the plurality of sub-PMICs 300aa, 300ba, ..., 300na may include a corresponding one of the second pins 301a, 301b, ..., 301n and a corresponding one of the third pins 302a, 302b, ..., 302n.

[0154] The main PMIC 200 a performs a first function associated with a first initial operation and may apply a first sub enable signal EN_SUB1 to a first sub PMIC 300 aa among a plurality of sub PMICs 300 aa , 300 ba , . . . , 300 na through a first pin 201 in response to activation of a power-on signal PRON.

[0155] The first sub-PMIC 300aa may receive the activated first sub enable signal EN_SUB1 through the second pin 301a , may activate the second sub enable signal EN_SUB2 in response to the activation of the first sub enable signal EN_SUB1 , and may provide the activated second sub enable signal EN_SUB2 to the second sub-PMIC 300ba through the third pin 302a .

[0156] The second sub-PMIC 300ba receives the activated second sub enable signal EN_SUB2 through the second pin 301b, may activate the third sub enable signal EN_SUB3 in response to the activation of the second sub enable signal EN_SUB2, and may provide the activated third sub enable signal EN_SUB3 to an adjacent sub-PMIC through the third pin 302b.

[0157] The nth sub-PMIC 300na may receive the activated nth sub-enabling signal EN_SUBn through the second pin 301n.

[0158] The first to nth sub-PMICs 300aa, 300ba, ..., 300na may be connected to (or communicate with) the main PMIC 200a through the second pins 301a, 301b, ..., 301n and the third pins 302a, 302b, ..., 302n in, for example, a daisy chain configuration, may be provided with an activated first sub-enable signal EN_SUB1 through the second pins 301a, 301b, ..., 301n and the third pins 302a, 302b, ..., 302n, and may sequentially enable the second functions based on the battery voltage VBAT.

[0159] Fig.16 is a block diagram illustrating an example of an electronic device according to some example embodiments.

[0160] refer to Fig.16 , the electronic device 10b may include a power management device 50b and a load system 600. According to some example embodiments, the load system 600 may correspond to Figure 2 The load system 1005 in.

[0161] The power management device 50b may include a main PMIC 200b and a plurality of sub-PMICs 300ab, 300bb, ..., 300nb. The plurality of sub-PMICs 300ab, 300bb, ..., 300nb may be referred to as first to nth sub-PMICs.

[0162] The battery voltage VBAT may be commonly supplied to the main PMIC 200b and the plurality of sub-PMICs 300ab, 300bb, . . . , 300nb, and the main PMIC 200b may be supplied from the outside (eg, Figure 2 The main processor 1800 in receives a power-on signal PRON.

[0163] According to some example embodiments, each configuration of the main PMIC 200b and the plurality of sub-PMICs 300ab, 300bb, ..., 300nb may be configured with Figure 3 The configurations of the main PMIC 200 and the plurality of sub-PMICs 300a, 300b, . . . , 300n are substantially similar.

[0164] Each of the plurality of sub-PMICs 300ab, 300bb, ..., 300nb may include a corresponding one of the second pins 301a, 301b, ..., 301n, and the sub-PMIC 300ab may further include a third pin 302a.

[0165] The main PMIC 200 b performs a first function associated with a first initial operation and may apply a first sub enable signal EN_SUB1 to a first sub PMIC 300 ab among the plurality of sub PMICs 300 ab, 300 bb, . . . , 300 nb through a first pin 201 in response to activation of a power on signal PRON.

[0166] The first sub-PMIC 300ab receives the activated first sub enable signal EN_SUB1 through the second pin 301a, activates the second sub enable signal EN_SUB22 in response to the activation of the first sub enable signal EN_SUB1, and can provide the activated second sub enable signal EN_SUB22 to the second to nth sub-PMICs 300bb, ..., 300nb through the third pin 302a.

[0167] The first sub-PMIC 300ab may enable functions associated with the second initial operation in response to activation of the first sub-enable signal EN_SUB1, and the second to nth sub-PMICs 300bb, . . . , 300nb may each enable functions associated with the second initial operation in response to activation of the second sub-enable signal EN_SUB22.

[0168] The nth sub-PMIC 300nb may receive the activated nth sub-enabling signal EN_SUBn through the second pin 301n.

[0169] The first to nth sub-PMICs 300ab, 300bb, ..., 300nb may be connected to (or communicate with) the main PMIC 200b through the second pins 301a, 301b, ..., 301n in, for example, a daisy chain configuration, and the third pin 302a may be provided with an activated first sub-enable signal EN_SUB1 through the second pin 301a and the third pin 302a, and the second functions may be sequentially enabled based on the battery voltage VBAT.

[0170] Fig.17 is a block diagram illustrating a portion of an electronic device according to some example embodiments.

[0171] refer to Fig.17 , the electronic device 20 may include a main PMIC 200 and a main processor 500 .

[0172] Fig.17The present invention illustrates a method according to some example embodiments. Figure 3 The connection relationship between the main PMIC 200 and the main processor 500 in FIG. The main processor 500 may correspond to Figure 2 The main processor 1800 in.

[0173] The master PMIC 200 may include a control logic 210, a UVLO circuit 220, a BGR generator 230, an ILDO regulator 240, and a first pin 201. In some example embodiments, the master PMIC 200 may further include a communication interface 260, a converter block 270, a regulator block 400, and a plurality of pins (eg, terminals).

[0174] The description of the control logic 210, the UVLO circuit 220, the BGR generator 230, the ILDO regulator 240, and the first pin 201 may be the same as that corresponding to Figure 6 The descriptions are substantially the same and thus may be omitted.

[0175] The main PMIC 200 may receive a battery voltage VBAT through a terminal 202 , may be connected to a ground voltage VSS through a terminal 203 , may communicate with a main processor 500 or a host through terminals 205 and 206 , and may receive a power management control signal CTPRM from the main processor 500 through a terminal 204 .

[0176] The converter block 270 may include a plurality of DC-DC converters 270a, 270b, ..., 270k that generate a plurality of supply voltages VDD1, VDD2, ..., VDDk based on the battery voltage VBAT. Here, k may be a natural number greater than 2. The regulator block 400 may include a plurality of low dropout (LDO) regulators 400a, 400b, ..., 400k that generate a plurality of output voltages VOUT1, VOUT2, ..., VOUTk based on the plurality of supply voltages VDD1, VDD2, ..., VDDk.

[0177] The plurality of LDO regulators 400a, 400b, ..., 400k may provide a plurality of output voltages VOUT1, VOUT2, ..., VOUTk to the power domain PD in the main processor 500. The main processor 500 may include a dynamic voltage and frequency scaling (DVFS) controller 520. The DVFS controller 520 may perform DVFS on the power domain PD by adjusting the frequency of each clock signal or adjusting the voltage level of each of the output voltages VOUT1, VOUT2, ..., VOUTk.

[0178] The main processor 500 may provide a power management control signal CTRPM to the main PMIC 200 through a general purpose input / output (I / O) (GPIO) terminal 501 .

[0179] The control logic 210 may control activation / deactivation of each of the DC-DC converters 270a, 270b, ..., 270k in response to the power management control signal CTRPM. The control logic 210 may generate internal enable signals IEN1, IEN2, ..., IENk in response to the power management control signal CTRPM, and may provide the internal enable signals IEN1, IEN2, ..., IENk to the corresponding DC-DC converters 270a, 270b, ..., 270k to control activation / deactivation of the DC-DC converters 270a, 270b, ..., 270k.

[0180] The communication interface 260 may communicate with the main processor 500 through the terminals 205 and 206 , and may transfer data and signals differently from the control logic 210 .

[0181] According to some example embodiments, Figure 3 Each of the plurality of sub-PMICs 300a, 300b, ..., 300n in the embodiment may be configured with Fig.17 The configuration of the main PMIC 200 in FIG. 1 is basically similar.

[0182] According to some example embodiments, each of the plurality of sub-PMICs 300a, 300b, . . . , 300n may include a plurality of DC-DC converters generating a plurality of power supply voltages and a plurality of LDO regulators generating a plurality of output voltages based on the plurality of power supply voltages.

[0183] Fig.18 is an illustration of some example embodiments Fig.17 A block diagram of an example of a main processor in an electronic device in FIG.

[0184] exist Fig.18 For example, the main processor 500 includes a plurality of power domains PD1, PD2, ..., PD4.

[0185] refer to Fig.17 and Fig.18 In some example embodiments, the main processor 500 may include voltage terminals 511, 512, ..., 514, a GPIO terminal 501, a plurality of function blocks IP1, IP2, ..., IP4, and a DVFS controller 520. In some example embodiments, the main processor 500 may further include a clock management unit (CMU) 530, a power management unit (PMU) 540, a memory interface (MIF) 560, an I / O interface (I / O IF) 550, and a display controller 570.

[0186] In some example embodiments, the main processor 500 may be an application processor (AP), a mobile AP, etc., but example embodiments are not limited thereto.

[0187] The memory interface 560 may be connected to an external memory 580 , and the display controller 570 may be connected to an external display 590 .

[0188] In some example embodiments, each of the plurality of functional blocks IP1, IP2, ..., IP4 may belong to a corresponding one of different power domains PD1, PD2, ..., PD4. In some example embodiments, one or more functional blocks may belong to each of the power domains PD1, PD2, ..., PD4.

[0189] The output voltages VOUT1, VOUT2, ..., VOUT4 may be supplied to the corresponding one of the power domains PD1, PD2, ..., PD4 through the corresponding one of the voltage terminals 511, 512, ..., 514, and the clock signals CLK1 to CLK4 may be provided to the corresponding one of the power domains PD1, PD2, ..., PD4 from the CMU 530. Each of the function blocks IP1, IP2, ..., IP4 belonging to the corresponding one of the power domains PD1, PD2, ..., PD4 may operate based on the corresponding one of the output voltages VOUT1, VOUT2, ..., VOUT4 and the corresponding one of the clock signals CLK1 to CLK4.

[0190] The DVFS controller 520 may perform DVFS on the power domains PD1, PD2, ..., PD4 by adjusting the frequency of each of the clock signals CLK1 to CLK4 and / or the voltage level of each of the output voltages VOUT1, VOUT2, ..., VOUT4. According to some example embodiments, the DVFS technology refers to a technology that dynamically controls or adjusts the operating frequency and operating voltage of the main processor 500 to reduce power consumption.

[0191] The CMU 530 may generate clock signals CLK1 to CLK4 , and may increase, maintain, or decrease the frequency of each of the clock signals CLK1 to CLK4 based on a clock control signal CTR2 from the DVFS controller 520 .

[0192] The PMU 540 can monitor the current power consumption of the main processor 500, can store the permitted power consumption of the main processor 500, and can compare the current power consumption with the permitted power consumption. The PMU 540 can generate a power control management control signal CTRPM for controlling the main PMIC 200 based on the power control signal CTR1 and / or the result of the comparison operation, and can provide the power control management control signal CTRPM to the main PMIC 200 through the GPIO terminal 501.

[0193] The memory interface 560 may control or facilitate data transfer between the main processor 500 and the memory device 580. For example, the memory interface 560 may operate based on the clock signal CLK3 and the output voltage VOUT3. The memory interface 560 may belong to the third power domain.

[0194] The memory device 580 may be provided outside the main processor 500, and may exchange data with the main processor 500 via the memory interface 560. In some example embodiments, the memory device 580 may include at least one volatile memory such as a dynamic random access memory (DRAM), a synchronous DRAM (SDRAM), a static random access memory (SRAM), etc., and / or at least one non-volatile memory such as an electrically erasable programmable read-only memory (EEPROM), a flash memory, a phase change random access memory (PRAM), a resistive random access memory (RRAM), a magnetic random access memory (MRAM), a ferroelectric random access memory (FRAM), a nano floating gate memory (NFGM), or a polymer random access memory (PoRAM), etc., but example embodiments are not limited thereto. Alternatively, in some example embodiments, the memory device 580 may include a solid state drive or solid state disk (SSD), an embedded SSD (eSSD), a multimedia card (MMC), an embedded MMC (eMMC), a universal flash storage (UFS), etc., but example embodiments are not limited thereto.

[0195] The I / O interface 550 may control or facilitate data transfer between the main processor 500 and an external system (not shown). In some example embodiments, the I / O interface 550 may support Serial Advanced Technology Attachment (SATA), SATA Express (SATAe), SAS (Serial Attached Small Computer System Interface (SCSI)), Peripheral Component Interconnect Express (PCI), and SATA Express. Non-Volatile Memory Express (NVMe) or Mobile Industry Processor Interface (MIPI), but example embodiments are not limited thereto.

[0196] The display controller 570 may control or facilitate data transfer between the main processor 500 and the display 590. In some example embodiments, the display 590 may be provided outside the main processor 500 and may display image data from the main processor 500. For example, the display 590 may operate based on the clock signal CLK2 and the output voltage VOUT2. The display controller 570 may belong to the second power domain.

[0197] In some example embodiments, at least a portion of the DVFS controller 520, the CMU 530, and the PMU 540 may be implemented as hardware. For example, at least a portion of the DVFS controller 520, the CMU 530, and the PMU 540 may be implemented as instructions or program routines (e.g., software programs). For example, the instructions or program routines may be stored in an internal storage device (not shown) included in the main processor 500 or in a storage device 580 located outside the main processor 500, but example embodiments are not limited thereto.

[0198] Despite Fig.18 Although not shown in the figure, in some example embodiments, the main processor 500 may include a performance monitoring unit that measures or counts performance parameters of the functional blocks IP1, IP2, ..., IP4, the memory interface 560, and the display controller 570. For example, the performance parameters may include instruction cycles, workload, cache hits, cache misses, branch misses, etc., but example embodiments are not limited thereto. The DVFS controller 520 may control the DVFS based on the measurement results of the performance monitoring unit.

[0199] Fig.19 is an illustration of some example embodiments Fig.17 Block diagram of one of the DC-DC converters in the PMIC.

[0200] Fig.19 A configuration of the DC-DC converter 270 a according to some example embodiments is illustrated, and each configuration of the DC-DC converters 270 b , . . . , 270 k may be substantially the same as that of the DC-DC converter 270 a .

[0201] refer to Fig.19 The DC-DC converter 270 a may include a main driver 275 , a first power switch MP, a second power switch MN, a feedback circuit 280 , and a pulse width modulation (PWM) controller 285 .

[0202] The first power switch MP may be coupled between the battery voltage VBAT and the switch node SN connected to the output node N011, and may include a PMOS transistor having a source coupled to the battery voltage VBAT, a gate receiving the first drive control signal PD, and a drain coupled to the switch node SN. The second power switch MN may be coupled between the switch node SN and the ground voltage VSS. The second power switch MP may include an NMOS transistor having a drain coupled to the switch node SN, a gate receiving the second drive control signal ND, and a source coupled to the ground voltage VSS.

[0203] The PWM controller 285 may generate a PWM signal SPWM based on a feedback voltage VFB1 proportional to the power supply voltage VDD1. The PWM controller 285 may generate the PWM signal SPWM by performing PWM on the feedback voltage VFB1.

[0204] The feedback circuit 280 may generate a feedback voltage VFB1 proportional to the power supply voltage VDD1, and may provide the feedback voltage VFB1 to the PWM controller 285. The feedback circuit 280 may include voltage-dividing resistors R11 and R12 connected between the output node NO11 and the ground voltage VSS, and the voltage-dividing resistors R11 and R12 may be connected to each other at a feedback node FN.

[0205] For example, Fig.19 As illustrated, the feedback circuit 280 may generate the feedback voltage VFB1 corresponding to a ratio of resistance values ​​of the voltage-dividing resistors R11 and R12 , but example embodiments are not limited thereto.

[0206] like Fig.19 As shown, in some example embodiments, the DC-DC converters 270a, 270b, ..., 270k may each include a buck converter. The buck converter may receive the battery voltage VBAT and may generate a supply voltage having a level relatively lower than the battery voltage VBAT based on the battery voltage VBAT.

[0207] Fig. 20 is an illustration of some example embodiments Fig.17 Block diagram of one of the LDO regulators in the main PMIC in FIG.

[0208] Fig. 20 A configuration of the LDO regulator 400 a according to some example embodiments is illustrated, and each configuration of the LDO regulators 400 b , . . . , 400 k may be substantially the same as the configuration of the LDO regulator 400 a .

[0209] refer to Fig. 20In some example embodiments, the LDO regulator 400 a may include an error amplifier (EA) 410 , a buffer (BUF) 445 , a pass element 440 including a power transistor 441 , and a feedback circuit (FC) 450 .

[0210] In some example embodiments, the LDO regulator 400a may further include a compensation capacitor Cc. The compensation capacitor Cc is connected between an internal node of the error amplifier 410 and the output node N021.

[0211] exist Fig. 20 , a load 460 and a load capacitor CL connected between the output node N021 and the ground voltage VSS according to some example embodiments are also illustrated. The load capacitor CL is connected between the output node N021 and the ground voltage VSS in parallel with respect to the load capacitor CL. The load 460 may include a load resistor RL.

[0212] The error amplifier 410 can be connected between the power supply voltage VDD1 and the ground voltage VSS, can receive the reference voltage VREF1 and the feedback voltage VFB2, can compare the reference voltage VREF1 and the feedback voltage VFB2, can amplify the difference between the reference voltage VREF1 and the feedback voltage VFB2 based on the comparison to generate a first error voltage EV1 corresponding to the difference, and can output the first error voltage EV1 to the buffer 445.

[0213] In some example embodiments, the first error voltage EV1 may correspond to a difference between the reference voltage VREF1 and the feedback voltage VFB2. According to some example embodiments, the error amplifier 410 has a positive (+) input terminal for receiving the reference voltage VREF1 and a negative (-) input terminal for receiving the feedback voltage VFB2.

[0214] The buffer 445 may buffer the first error voltage EV1 and may output a second error voltage EV2 to the gate of the power transistor 441. The buffer 445 may have a gain of -1.

[0215] The power transistor 441 may have a gate receiving the second error voltage EV2 and may adjust the supply voltage VDD1 based on the second error voltage EV2 to provide an output voltage VOUT1 to the output node N021. A load current IL corresponding to the output voltage VOUT1 is provided to the load 460 from the output node N021.

[0216] According to some example embodiments, the power transistor 441 has a source coupled to the supply voltage VDD1, a gate receiving the second error voltage EV2, and a drain coupled to the output node N021. In some example embodiments, when the load current IL increases, the voltage level of the output voltage VOUT1 decreases, and the voltage level of the first error voltage EV1 increases. For example, the voltage level of the second error voltage EV2 decreases in response to an increase in the level of the first error voltage EV1. In some example embodiments, when the voltage level of the second error voltage EV2 decreases, the voltage level of the output voltage VOUT1 increases.

[0217] In some example embodiments, when the load current IL decreases, the voltage level of the output voltage VOUT1 increases and the voltage level of the first error voltage EV1 decreases. For example, the voltage level of the second error voltage EV2 increases in response to the decrease in the voltage level of the first error voltage EV1. In some example embodiments, when the voltage level of the second error voltage EV2 increases, the voltage level of the output voltage VOUT1 decreases.

[0218] Therefore, in some example embodiments, when the load current IL increases, the voltage level of the second error voltage EV2 decreases, and when the load current IL decreases, the voltage level of the second error voltage EV2 increases.

[0219] The feedback circuit 450 may be connected between the output node N021 and the ground voltage VSS, may generate a feedback voltage VFB2 by dividing the output voltage VOUT1 , and may provide the feedback voltage VFB2 to the error amplifier 410 .

[0220] Fig.21 is a diagram illustrating the operation according to some example embodiments Figure 3 Flow chart of a method for a main PMIC and multiple sub-PMICs in FIG.

[0221] refer to Figures 3 to 8 and Fig.21 , all PMICs (eg, the main PMIC 200 and the plurality of sub-PMICs 300 a , 300 b , . . . , 300 n ) are turned off (operation S110 ).

[0222] In some example embodiments, the UVLO circuit 220 in the master PMIC 200 determines whether the battery voltage VBAT reaches (e.g., is greater than or equal to) the reference level VL_REF (operation S120). In some example embodiments, when the battery voltage VBAT is less than the reference level VL_REF (No in operation S120), the process returns to operation S110 (e.g., all PMICs are turned off).

[0223] In some example embodiments, when the battery voltage VBAT reaches (eg, is greater than or equal to) the reference level VL_REF (Yes in operation S120), the master PMIC 200 enables an initial function of the master PMIC 200 while disabling the plurality of sub-PMICs 300a, 300b, . . . , 300n (operation S130).

[0224] In some example embodiments, the master PMIC 200 determines whether the power-on signal PRON is activated (operation S140 ). In some example embodiments, when the power-on signal PRON is not activated (NO in operation S140 ), the process returns to operation S130 .

[0225] In some example embodiments, when the power-on signal PRON is activated (Yes in operation S140), the main PMIC 200 is enabled (operation S150), and the main PMIC 200 (or the control logic 210) determines whether the sub-enable signal EN_SUB is activated (operation S160). In some example embodiments, when the sub-enable signal EN_SUB is not activated (No in operation S160), the process returns to operation S150.

[0226] In some example embodiments, when the sub-enable signal EN_SUB is activated (Yes in operation S160 ), the plurality of sub-PMICs 300 a , 300 b , . . . , 300 n are enabled, and a power-on sequence is performed (operation S170 ).

[0227] In some example embodiments, the UVLO circuit 220 in the main PMIC 200 determines whether the battery voltage VBAT drops below the reference level VL_REF (operation S180). In some example embodiments, when the battery voltage VBAT drops below the reference level VL_REF (yes in operation S180), all PMICs (e.g., the main PMIC 200 and the plurality of sub-PMICs 300a, 300b, ..., 300n) are turned off (operation S190).

[0228] In some example embodiments, when the battery voltage VBAT does not drop below the reference level VL_REF (No in operation S180), the master PMIC 200 determines whether the power-on signal PRON is deactivated (operation S210). In some example embodiments, when the power-on signal PRON is not deactivated (No in operation S210), the process returns to operation S170.

[0229] In some example embodiments, when the power-on signal PRON is deactivated (yes in operation S210), the sub-enable signal EN_SUB is deactivated, and all PMICs (e.g., the main PMIC 200 and the plurality of sub-PMICs 300a, 300b, . . . , 300n) are turned off, while the initial function of the main PMIC 200 is enabled (activated) (operation S220).

[0230] Fig. 22 is a block diagram illustrating a mobile device according to some example embodiments.

[0231] In some example embodiments, Fig. 22 The mobile device 30 shown in FIG. Figure 3 An electronic device 10.

[0232] According to some example embodiments, the mobile device 30 may include a printed circuit board (PCB) 110 a and a plurality of (electronic) components disposed on the PCB 110 a .

[0233] In some example embodiments, the PCB 110a may include an electrical (e.g., conductive) path along which at least one component mounted on and attached to the first side UF1 of the PCB 110a and at least one component mounted on and attached to the second side LF1 of the PCB 110a are electrically connected. For example, an operating voltage (e.g., a power voltage and / or a ground voltage) and a signal are transmitted along the electrical path.

[0234] According to some example embodiments, PCB 110a may refer to a circuit board or substrate capable of providing an electrical path (or electrical communication path) between at least one component mounted on and attached to a first side UF1 of the PCB 110a and at least one component mounted on and attached to a second side LF1 of the PCB 110a.

[0235] In some example embodiments, PCB 110a may include one or more dielectric material (e.g., insulation) layers, multiple metal (e.g., wiring) layers separated from each other by (one or more) dielectric material (e.g., insulation) layers, and conductive paths extending through (one or more) dielectric material layers and electrically connecting the metal (e.g., wiring) layers to each other, but example embodiments are not limited thereto.

[0236] refer to Fig. 22 In some example embodiments, the mobile device 30 may include a PCB 110a, a package substrate 150, a main PMIC 200_1, a sub-PMIC 300_1, passive components 31, 32, 33, 35, 36, and 37, LDO regulators 400a and 400b, and, for example Fig.17 The main processor 500 shown in FIG. Figure 2 The integrated circuit (SoC die) 500 corresponding to the main processor 1800 shown in FIG. 1 and the memory 590. The mobile device 30 may further include high-density capacitors 480 and 490 located between the second side LF2 of the package substrate 150 and the LDO regulators 400a and 400b, respectively.

[0237] The package substrate 150 may be attached to the first side UF1 of the PCB 110a through the first interconnects 140, 161, and 163. The package substrate 150 may have a first side UF2 and a second side LF2 opposite to the first side UF2.

[0238] According to some example embodiments, the first interconnects 140, 161, and 163 may each include at least one of a conductive pad or connection pad of a conductive material such as copper, a pin, and a solder bump (e.g., a ball of solder, etc.), but example embodiments are not limited thereto. The first interconnect 140 may include first balls 141, 142, and 143.

[0239] In some example embodiments, the SoC die 500 may be attached to the first side UF2 of the package substrate 150 through the third interconnects 170 and 180. The third interconnects 170 and 180 may include at least one of a conductive pad or connection pad of a conductive material such as copper, a pin, and a solder bump (e.g., a ball of solder, etc.), but example embodiments are not limited thereto. The third interconnect 170 may include balls 171, 172, and 173, and the third interconnect 180 may include balls 181, 182, and 183.

[0240] In some example embodiments, the memory 590 may be attached to the first side UF2 of the package substrate 150 through the fourth interconnects 191 and 193, and the memory 590 may be located above (e.g., overlapping) the SoC die 500. The fourth interconnects 191 and 193 may include at least one of a conductive pad or a connection pad of a conductive material.

[0241] In some example embodiments, the main PMIC 200_1 and the sub-PMIC 300_1 may be spaced apart in the first direction DR1. Fig. 22 One sub-PMIC 300_1 is illustrated in FIG. 1 , but in some example embodiments, a plurality of sub-PMICs may be distributed and mounted on the second side LF1 of the PCB 110a.

[0242] According to some example embodiments, the PCB 110 a and the package substrate 150 may each have a corresponding length extending in the first direction DR1 and a corresponding thickness extending in the second direction DR2 .

[0243] In some example embodiments, the corresponding passive components 31, 32, 33, 35, 36 and 37 may be variously mounted on the second side LF1 of the PCB 110a using pads and / or connection pads. The passive components 31, 32, 33, 35, 36 and 37 may include, for example: a first capacitor (C1) 31 and a first inductor (L1) 32 associated with the output of the main PMIC 200_1; a third capacitor (C3) 33 associated with the input of the LDO regulator 400a; and a second capacitor (C2) 35 and a second inductor (L2) 36 associated with the output of the sub-PMIC 300_1; and a fourth capacitor (C4) 37 associated with the input of the LDO regulator 400b.

[0244] In some example embodiments, the master PMIC 200_1 may be mounted on the second side LF1 of the PCB 110a using the second interconnect 120a. Here, the second interconnect 120a may include balls 121a, 122a, 123a, and 124a. The ball 121a may be coupled to the master PMIC 200_1 and the first inductor (L1) 32 through the first electrical path 135. Therefore, in some example embodiments, the supply voltage generated by the master PMIC 200_1 may be provided to the LDO regulator 400a through the first capacitor (C1) 31, the first inductor (L1) 32, the third capacitor (C3) 33, the first electrical paths 135 and 136, and the ball 141.

[0245] In some example embodiments, the sub-PMIC 300_1 may be mounted on the second side LF1 of the PCB 110a through the second interconnect 120b. Here, the second interconnect 120b may include balls 121b, 122b, 123b, and 124b. The ball 121b may be coupled to the sub-PMIC 300_1 and the second inductor (L2) 36 through the second electrical path 137. Therefore, in some example embodiments, the supply voltage generated by the sub-PMIC 300_1 may be provided to the LDO regulator 400b through the second capacitor (C2) 35, the second inductor (L2) 36, the fourth capacitor (C4) 37, the second electrical paths 137 and 138, and the ball 143.

[0246] In some example embodiments, the LDO regulator 400a may generate an output voltage in response to (or based on) the received supply voltage, and may provide the generated output voltage to a corresponding power domain of the SoC die 500 through the high-density capacitor 480, the electrical path 154, and the balls 171, 172, and 173. For example, the high-density capacitor 480 may operate as an output capacitor of the LDO regulator 400a.

[0247] In some example embodiments, the LDO regulator 400b may generate an output voltage in response to (or based on) the received supply voltage, and may provide the generated output voltage to a corresponding power domain of the SoC die 500 through the high-density capacitor 490, the electrical path 156, and the balls 181, 182, and 183. For example, the high-density capacitor 490 may operate as an output capacitor of the LDO regulator 400b.

[0248] According to some example embodiments, because the LDO regulators 400a and 400b are mounted on the second side LF2 of the package substrate 150, rather than the LDO regulators 400a and 400b being included in the main PMIC 200_1 and the sub-PMIC 300_1, the number of electrical paths (e.g., power rails) required to transmit the supply voltage from the main PMIC 200_1 and the sub-PMIC 300_1 to the LDO regulators 400a and 400b can be reduced relative to conventional designs.

[0249] In some example embodiments, because the LDO regulators 400a and 400b are mounted on the second side LF2 of the package substrate 150, instead of the LDO regulators 400a and 400b being included in the main PMIC 200_1 and the sub-PMIC 300_1, the LDO regulators 400a and 400b can both provide output voltages to corresponding power domains through a reduced number of balls 171, 172, 173, 181, 182 and 183 compared to conventional designs.

[0250] exist Fig. 22 In the embodiment, the LDO regulators 400 a and 400 b , the package substrate 150 , and the SoC die 500 may be combined in an IC package (eg, a SoC package or a SOC_PKG).

[0251] Fig.23 and Fig.24 is a diagram illustrating an autonomous driving system according to some example embodiments.

[0252] refer to Fig.23 In some example embodiments, the autonomous driving system 3000 may include a driver (e.g., including a circuit system) 3110, a sensor 3120, a storage device 3130, a controller (e.g., including a processing circuit system) 3140, a communication interface 3150, a main PMIC 3200, and sub-PMICs 3300a and 3300b.

[0253] Driver 3110 may be, for example, a configuration for driving autonomous driving system 3000, and may include various circuit systems. In some example embodiments, when autonomous driving system 3000 is implemented with an autonomous vehicle, driver 3110 may include various circuit systems and / or components, such as, for example, engine / motor 3111, steering unit 3112, brake unit 3113, etc., but example embodiments are not limited thereto.

[0254] The sensor 3120 may include a plurality of sensors configured to sense information related to the surrounding environment of the autonomous driving system 3000. For example, the sensor 3120 may include at least one of an image sensor 3121, a depth sensor 3122, a light detection and ranging (LIDAR) unit 3123, a radio detection and ranging (RADAR) unit 3124, an infrared sensor 3125, a global positioning system (GPS) 3126, a magnetic sensor 3127, and / or an accelerometer sensor 3128, but example embodiments are not limited thereto.

[0255] The controller 3140 may include a random access memory (RAM) 3141, a read-only memory (ROM) 3142, a central processing unit (CPU) 3143, a hardware interface device (HWIF) 3144, a plurality of intellectual property protection devices (IP) 3145 and 3146, and a bus 3147. The storage device 3130 may store data necessary for the controller 3140 to run various processes. The communication interface 3150 may include various communication circuits and may be configured to facilitate communication between the autonomous driving system 3000 and an external device.

[0256] The master PMIC 3200 may provide an output voltage VOUTs_1 to the controller 3140 .

[0257] The main PMIC 3200 may enable an initial function based on a battery voltage, may activate a sub-enable signal EN_SUB in response to activation of a power-on signal, and may apply the activated sub-enable signal EN_SUB to the sub-PMICs 3300a and 3300b. The sub-PMICs 3300a and 3300b may enable corresponding initial functions based on the activated sub-enable signal EN_SUB, and may perform a power-on sequence. The sub-PMIC 3300a may provide an output voltage VOUTs_2 to the sensor 3120, and the sub-PMIC 3300b may provide an output voltage VOUTs_3 to the communication interface 3150.

[0258] refer to Fig.24In some example embodiments, autonomous driving system 4010 may be installed in autonomous vehicle 4000. For example, autonomous driving system 4010 may detect a road 4200 including a fixed pattern and another vehicle 4100 moving in time by analyzing at least one image sequence 4300 received from at least one camera.

[0259] The present inventive concept may be applied to PMIC, SoC, and various devices and systems including PMIC and SoC, such as mobile phones, smart phones, PDAs, PMPs, digital cameras, digital televisions, set-top boxes, music players, portable game consoles, navigation devices, PCs, server computers, workstations, tablet computers, laptop computers, smart cards, printers, wearable devices, IoT devices, IoE devices, e-books, VR devices, AR devices, robotic devices, etc., but example embodiments are not limited thereto.

[0260] As described herein, one or more of the elements disclosed above may include or be implemented in one or more processing circuit systems such as: hardware including logic circuits; hardware / software combinations such as processors running software; or combinations thereof. For example, the processing circuit system may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on a chip (SoC), a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), etc.

[0261] As described herein, any device, electronic device, module, model, unit and / or portion thereof may include, may be included in, and / or may be implemented by: hardware including logic circuits; a hardware / software combination such as a processor running software; or a combination thereof. For example, the processing circuit system may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a graphics processing unit (CPU), an application processor (AP), a digital signal processor (DSP), a microcomputer, a field programmable gate array (FPGA) and a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), a neural network processing unit (NPU), an electronic control unit (ECU), etc. In some example embodiments, the processing circuit system may include a non-transitory computer-readable storage device (e.g., memory) (e.g., a solid-state drive (SSD)) and a processor (e.g., a CPU), the non-transitory computer-readable storage device storing a program of instructions, the processor being configured to execute the program of instructions to implement the functions and / or methods performed by some or all of any device, electronic device, module, unit and / or portion thereof according to any of the example embodiments.

[0262] Any of the memories described herein may be: a non-volatile memory such as flash memory, phase-change random access memory (PRAM), magnetoresistive RAM (MRAM), resistive RAM (ReRAM), or ferroelectric RAM (FRAM); or a volatile memory such as static RAM (SRAM), dynamic RAM (DRAM), or synchronous DRAM (SDRAM).

[0263] While the inventive concept has been shown and described with reference to certain example embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the inventive concept as defined by the following claims.

Claims

1. A power management device, comprising: Main power management integrated circuit; as well as at least one sub-power management integrated circuit, the at least one sub-power management integrated circuit being configured to communicate with the main power management integrated circuit through a dedicated pin, Wherein, the main power management integrated circuit includes a first pin and is configured as: During a standby period before generating a first output voltage based on a battery voltage, enabling a first function associated with a first initial operation based on the battery voltage; and After completing the first initial operation, applying a first sub-enabling signal to the at least one sub-power management integrated circuit through the first pin based on the power-on signal, and wherein the at least one sub-power management integrated circuit each includes a second pin and is configured as: receiving the first sub-enable signal through the second pin; and In response to activation of the first sub-enable signal, a second function associated with a second initial operation is enabled based on the battery voltage.

2. The power management device according to claim 1, wherein: The at least one sub-power management integrated circuit further includes first to n-th sub-power management integrated circuits, wherein a corresponding one of the first to n-th sub-power management integrated circuits is configured to: communicate with the main power management integrated circuit through the second pin, and n is a natural number greater than 2, The first to nth sub-power management integrated circuits are all configured to: receive the first sub-enabling signal through the second pin, and in response to activation of the first sub-enabling signal, concurrently enable the second function based on the battery voltage.

3. The power management device according to claim 1, wherein: The at least one sub-power management integrated circuit further includes first to nth sub-power management integrated circuits, wherein the first to nth sub-power management integrated circuits are configured to communicate with the main power management integrated circuit via a daisy chain configuration, Wherein, the first to nth sub-power management integrated circuits all further include a third pin, and The first to nth sub-power management integrated circuits are provided with the activated first sub-enabling signal through the second pin and the third pin, and sequentially enable the second function based on the battery voltage.

4. The power management device according to claim 1, wherein: The at least one sub-power management integrated circuit further includes first to nth sub-power management integrated circuits, The first sub-power management integrated circuit further includes a third pin and is configured as follows: in response to activation of the first sub-enablement signal, enabling the second function based on the battery voltage; and applying a second sub-enabling signal to the second to nth sub-power management integrated circuits through the third pin, and The second to nth sub-power management integrated circuits are each configured to concurrently enable the second function in response to activation of the second sub-enabling signal.

5. The power management device according to claim 1, wherein: The master power management integrated circuit further comprises: an under-voltage lockout circuit configured to compare the battery voltage with a reference level and generate a voltage level detection signal activated in response to the battery voltage reaching the reference level; a reference voltage generator configured to generate a reference voltage in response to activation of the voltage level detection signal; an internal low dropout regulator configured to generate an internal voltage based on the reference voltage and the battery voltage; and A control logic is configured to activate the first sub-enable signal based on the activation of the voltage level detection signal, the reference voltage reaching a target level and the activation of the power-on signal, and apply the first sub-enable signal to the at least one sub-power management integrated circuit through the first pin.

6. The power management device according to claim 5, wherein: The master power management integrated circuit is configured to transition from a standby state to an on state in response to activation of the power on signal.

7. The power management device according to claim 5, wherein: The internal low dropout regulator is configured to generate the internal voltage in response to the reference voltage reaching the target level.

8. The power management device according to claim 5, wherein: The master power management integrated circuit further comprises: a plurality of DC-to-DC converters configured to generate a plurality of supply voltages based on the battery voltage; and A plurality of low voltage dropout regulators are configured to generate a plurality of output voltages by regulating the plurality of supply voltages, and provide the plurality of output voltages to a load system.

9. The power management device according to claim 8, wherein: Each of the plurality of DC-to-DC converters includes a buck converter.

10. The power management device according to claim 1, wherein: The at least one sub-power management integrated circuit further comprises: an under-voltage lockout circuit configured to compare the battery voltage with a reference level in response to activation of the first sub-enable signal and to generate a voltage level detection signal configured to be activated in response to the battery voltage reaching the reference level; a reference voltage generator configured to generate a reference voltage in response to activation of the first sub-enable signal and activation of the voltage level detection signal; an internal low dropout regulator configured to generate an internal voltage based on the reference voltage and the battery voltage in response to activation of the first sub-enable signal; and A control logic is configured to perform a power-on sequence based on activation of the first sub-enable signal, activation of the voltage level detection signal, and the reference voltage reaching a target level.

11. The power management device according to claim 10, wherein: The at least one sub-power management integrated circuit is configured to transition from a standby state to an on state in response to activation of the first sub-enable signal.

12. The power management device according to claim 10, wherein: The at least one sub-power management integrated circuit further comprises: a plurality of DC-to-DC converters configured to generate a plurality of supply voltages based on the battery voltage; and A plurality of low voltage dropout regulators are configured to generate a plurality of output voltages by regulating the plurality of supply voltages, and provide the plurality of output voltages to a load system.

13. The power management device according to claim 10, wherein: The internal low dropout regulator is further configured to generate the internal voltage in response to the reference voltage reaching the target level.

14. The power management device according to claim 1, wherein: The at least one sub-power management integrated circuit further comprises: a power switch circuit configured to selectively pass the battery voltage based on the first sub-enable signal; an undervoltage lockout circuit connected to the power switch circuit and configured to compare the battery voltage with a reference level and generate a voltage level detection signal configured to be activated in response to the battery voltage reaching the reference level; a reference voltage generator connected to the power switching circuit and configured to generate a reference voltage in response to activation of the voltage level detection signal; an internal low dropout regulator configured to generate an internal voltage based on the reference voltage and the battery voltage in response to activation of the first sub-enable signal; and A control logic is configured to perform a power-on sequence based on activation of the first sub-enable signal, activation of the voltage level detection signal, and the reference voltage reaching a target level.

15. The power management device according to claim 14, wherein: The power switch circuit includes a pair of first and second p-channel metal oxide semiconductor transistors, first and second n-channel metal oxide semiconductor transistors, and first and second transmission gates. wherein the first p-channel metal oxide semiconductor transistor is configured to transmit the battery voltage to the undervoltage lockout circuit based on an inverted first sub-enable signal obtained by inverting the first sub-enable signal, and the second p-channel metal oxide semiconductor transistor is configured to transmit the battery voltage to the reference voltage generator based on the inverted first sub-enable signal, wherein the first n-channel metal oxide semiconductor transistor is configured to transmit the battery voltage to the undervoltage lockout circuit based on the first sub-enable signal, and the second n-channel metal oxide semiconductor transistor is configured to transmit the battery voltage to the reference voltage generator based on the first sub-enable signal, and Wherein, the first transmission gate is configured to transmit the battery voltage to the undervoltage lockout circuit based on the first sub-enable signal and the inverted first sub-enable signal, and the second transmission gate is configured to transmit the battery voltage to the reference voltage generator based on the first sub-enable signal and the inverted first sub-enable signal.

16. An electronic device, comprising: a main processor, the main processor comprising a plurality of first power domains; as well as a power management device configured to generate a plurality of output voltages in association with power sequences of the plurality of first power domains and to provide the plurality of output voltages to the plurality of first power domains through a voltage rail, Wherein, the power management device comprises: a master power management integrated circuit configured to communicate with the master processor via a system bus; and at least one sub-power management integrated circuit, the at least one sub-power management integrated circuit being configured to communicate with the main power management integrated circuit through a dedicated pin, wherein the main power management integrated circuit comprises a first pin and is configured to: During a standby period before generating a first output voltage based on a battery voltage, enabling a first function associated with a first initial operation based on the battery voltage; and After completing the first initial operation, applying a first sub-enabling signal to the at least one sub-power management integrated circuit through the first pin based on the power-on signal, and wherein the at least one sub-power management integrated circuit each includes a second pin and is configured as: receiving the first sub-enable signal through the second pin; and In response to activation of the first sub-enable signal, a second function associated with a second initial operation is enabled based on the battery voltage.

17. The electronic device according to claim 16, wherein: The at least one sub-power management integrated circuit further includes first to n-th sub-power management integrated circuits, wherein a corresponding one of the first to n-th sub-power management integrated circuits is configured to: communicate with the main power management integrated circuit through the second pin, and n is a natural number greater than 2, The first to nth sub-power management integrated circuits are all configured to: receive the first sub-enabling signal through the second pin, and in response to activation of the first sub-enabling signal, concurrently enable the second function based on the battery voltage.

18. The electronic device according to claim 16, wherein: The at least one sub-power management integrated circuit further includes first to nth sub-power management integrated circuits, wherein the first to nth sub-power management integrated circuits are configured to communicate with the main power management integrated circuit via a daisy chain configuration, Wherein, the first to nth sub-power management integrated circuits all further include a third pin, and The first to nth sub-power management integrated circuits are provided with the activated first sub-enabling signal through the second pin and the third pin, and sequentially enable the second function based on the battery voltage.

19. The electronic device according to claim 16, further comprising: a load system comprising a plurality of second power domains, and The power management device is further configured to provide the multiple output voltages to the multiple second power domains through the voltage rail.

20. A power management device, comprising: Main power management integrated circuit; as well as at least one sub-power management integrated circuit, the at least one sub-power management integrated circuit being configured to communicate with the main power management integrated circuit through a dedicated pin, Wherein, the main power management integrated circuit includes a first pin and is configured as: During a standby period before generating a first output voltage based on a battery voltage, enabling a first function associated with a first initial operation based on the battery voltage; and After completing the first initial operation, applying a sub-enable signal to the at least one sub-power management integrated circuit through the first pin based on a power-on signal, Wherein, the at least one sub-power management integrated circuit each includes a second pin and is configured as: receiving the sub-enable signal via the second pin; and in response to activation of the sub-enable signal, enabling a second function associated with a second initial operation based on the battery voltage, Wherein, the main power management integrated circuit is further configured as: generating a reference voltage based on the battery voltage in response to the battery voltage reaching a reference level; activating the sub-enable signal in response to the reference voltage reaching a target level and activation of the power-on signal; and The sub-enable signal is applied to the at least one sub-power management integrated circuit through the first pin.

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