Memory access popularity statistical method, related device and equipment

Abstract

The invention discloses a memory access heat statistical method, a controller, a chip, a memory, a mainboard and computer equipment, and relates to the field of computers. The method comprises the following steps: counting the access frequency of a processor accessing a data block in a memory according to the operation of an application program operated by the processor on the memory, and determining the access popularity of the data block according to the access frequency; the access frequency represents the frequency degree that the data block is accessed by the application program. The more the data blocks are accessed by the application program, the more frequent the data blocks are accessed by the application program, and the hotter the access heat of the data blocks is; the smaller the number of times that the data block is accessed by the application program is, the more frequent the data block is accessed by the application program, and the colder the access popularity of the data block is. Therefore, the hot data is migrated to the near-end memory, and the cold data is migrated to the far-end memory, so that the processor can obtain frequently accessed data from the near-end memory as quickly as possible, the data processing speed of the system is improved, the data processing time delay is reduced, and the access performance of the system is remarkably improved.

Description

[0001] This application is a divisional application of the Chinese application with application date of August 24, 2022 and application number 202211016161.0. This application and the Chinese application with application number 202211016161.0.5 both claim the priority of the Chinese patent application submitted to the State Intellectual Property Office on May 24, 2022, with application number 202210575022.5 and application name “A Data Migration Method”, all contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the computer field, and in particular to a memory access heat statistics method, a controller, a chip, a memory, a motherboard and a computer device. Background Art

[0003] At present, it is hoped that a memory with a fast access speed can store frequently accessed data, and a memory with a slow access speed can store infrequently accessed data. However, due to the low accuracy of the existing memory access heat statistics method, a memory with a fast access speed may store infrequently accessed data, or a memory with a slow access speed may store frequently accessed data, which affects the data processing speed and latency of the system. Summary of the invention

[0004] The present application provides a memory access heat statistics method, a controller, a chip, a memory, a motherboard and a computer device, thereby improving the data processing speed of the system and reducing the data processing delay.

[0005] In a first aspect, a memory access heat statistics method is provided, which is executed by a controller. The method includes counting the access frequency of a data block in the memory accessed by the processor according to the operation of the application program running on the memory of the computer device by the processor in the computer device, so as to determine the access heat of the data block according to the access frequency.

[0006] In this way, the access frequency intuitively indicates how frequently the data block is accessed by the application. The more times a data block is accessed by an application, the more frequently it is accessed by the application, and the hotter the access popularity of the data block; the fewer times a data block is accessed by an application, the less frequently it is accessed by the application, and the colder the access popularity of the data block. Therefore, when data migration is triggered based on the access popularity of the data block, hot data can be migrated to the near-end memory and cold data can be migrated to the far-end memory, so that the processor can obtain frequently accessed data from the near-end memory as quickly as possible, thereby increasing the data processing speed of the system and reducing the data processing latency, significantly improving the access performance of the system.

[0007] In a possible implementation, counting the access frequency of the data block where the first address is located includes: counting the access frequency of the data block where the unit storage space to which the first address belongs is located.

[0008] The size of the data block is a multiple of the unit storage space in the memory accessible to the processor. Since the computer device performs a read operation or a write operation on the storage space of the memory at the granularity of a cache line, the storage space of the memory is managed at the granularity of a page. A page may include multiple cache lines. The size of the data block is the size of a page in the memory accessible to the processor in the computer device. The size of the unit storage space may be the size of the cache line when the processor in the computer device accesses the memory. The operation of a cache line in the memory by the application program running on the processor in the computer device may be regarded as an operation on a page. In this way, the processor operates the memory at the granularity of a cache line, and the cache line belongs to a certain page under management. Then, the cache line in the memory is operated once, and the page to which the cache line belongs is also read and written once. The controller counts the access frequency of the page to which the cache line operated belongs, which effectively improves the recognition accuracy of the access heat of the page, and the page access frequency is counted at the granularity of the page, which is compatible with the page management method of the computer device for the memory, and the memory access heat statistics method is easy to use.

[0009] In addition, the interleaving method refers to the processor in the computer device distributing data to multiple memories for operation. The application program running on the processor in the computer device operates the memory of the computer device in an interleaving manner and processes data based on multiple memory channels to improve the memory bandwidth utilization and processing performance of the computer device. The size of the data block can also be the size of the interleaved data block in the memory accessible by the processor in the computer device in an interleaving manner.

[0010] In another possible implementation, the method further includes: identifying a second address according to the address of the data block where the first address is located and the address mapping relationship. The second address is used to indicate the location of the access frequency of the data block stored in the controller. The address mapping relationship is used to indicate the mapping relationship between the address of the data block and the address of the storage space storing the access frequency. Thus, the controller obtains the access frequency of the data block stored in the first storage medium according to the second address and updates the access frequency of the data block.

[0011] In another possible implementation, the memory includes a first storage medium, the first storage medium is used to store the access frequency of the data block in the memory, and the second address indicates a storage space in the first storage medium for storing the access frequency of the data block.

[0012] In another possible implementation, since the computer device pre-allocates the capacity of the memory particles in the memory, when the processor accesses the first storage medium, the computer device allocates the physical address space corresponding to the capacity of the first storage medium from the capacity of the memory particles in the memory, and the controller maps the physical address of the access to the first storage medium to the first storage medium, so that the corresponding capacity in the memory particles cannot be used, resulting in a waste of the storage space of the memory particles. For example, the total capacity of the memory particles in the memory is 64GB, the page size is 4KB, and the access frequency bit width for storing each data block is 4B, which wastes 64MB of memory storage space. The method also includes: identifying the second address according to the third address indicated by the processor and the address mapping relationship, obtaining the access frequency of the data block, and the third address is determined by the second address. Thereby, the storage space of the memory particles is saved and the utilization rate of the storage space of the memory particles is improved.

[0013] In another possible implementation, the method further includes: the controller determines the access heat of the data block according to the access frequency, and triggers data migration according to the access heat. For example, the controller feeds back the access heat of the data block to the processor, and the processor controls the data migration of data blocks with different access heats. For example, the processor stores cold data in the remote memory and stores hot data in the local memory. In this way, when the controller triggers data migration according to the access heat of the data block, the hot data can be migrated to the local memory and the cold data can be migrated to the remote memory, so that the processor can obtain data from the local memory as quickly as possible, thereby improving the data processing speed of the system, and reducing the data processing delay, thereby improving the overall processing performance of the system.

[0014] In a second aspect, a memory access heat statistics method is provided, which is executed by a processor and includes: receiving access frequencies of interleaved data blocks sent by multiple memories, merging the access frequencies of the interleaved data blocks, and obtaining the access frequency of a page. The access frequency of the interleaved data block indicates the access frequency of the processor to access a data block of a memory in the multiple memories in an interleaved manner.

[0015] In this way, when the application program running on the processor of the computer device operates the memory of the computer device in an interleaved manner and performs data processing based on multiple memory channels to improve the memory bandwidth utilization and processing performance of the computer device, the controller combines the access frequencies of the interleaved data blocks sent by multiple memories to obtain the access frequencies of the pages, so as to determine the access popularity of the pages according to the access frequencies of the pages. When data migration is triggered according to the access popularity of the pages, hot data can be migrated to the proximal memory and cold data can be migrated to the remote memory, so that the processor can obtain frequently accessed data from the proximal memory as quickly as possible, thereby improving the data processing speed of the system, reducing the data processing delay, and significantly improving the access performance of the system.

[0016] In a third aspect, a memory access heat statistics device is provided, which includes various modules for executing the memory access heat statistics method in the first aspect or any possible design of the first aspect, or executing various modules for executing the memory access heat statistics method in the second aspect or any possible design of the second aspect.

[0017] In a fourth aspect, a controller is provided, the controller comprising a processing unit and a storage unit, the storage unit being used to store a set of computer instructions; when the processing unit executes the set of computer instructions as the controller in the first aspect or any possible implementation of the first aspect, the operation steps of the memory access heat statistics method in the first aspect or any possible implementation of the first aspect are executed. The controller is a Register Clock Driver (RCD) or an extended controller in the memory of a computer device.

[0018] In a fifth aspect, a chip is provided, comprising: a processor and a power supply circuit; the power supply circuit is used to supply power to the processor; the processor is used to execute the operating steps of the memory access heat statistics method in the first aspect or any possible implementation of the first aspect.

[0019] In a sixth aspect, a memory is provided, comprising a storage device and a controller as described in the fourth aspect, wherein the storage device is used to store a set of computer instructions; when the controller executes the set of computer instructions, the operating steps of the memory access heat statistics method in the first aspect or any possible implementation of the first aspect are executed.

[0020] In a seventh aspect, a mainboard is provided, the mainboard comprising the controller as described in the fourth aspect, the controller executing the operating steps of the memory access heat statistics method in the first aspect or any possible implementation of the first aspect.

[0021] In an eighth aspect, a computer device is provided, the computer device comprising the mainboard as described in the seventh aspect.

[0022] In a ninth aspect, a computer-readable storage medium is provided, comprising: computer software instructions; when the computer software instructions are executed in a computing device, the computing device executes the operating steps of the method described in the first aspect or any possible implementation of the first aspect.

[0023] In a tenth aspect, a computer program product is provided. When the computer program product is run on a computer, the computing device executes the operating steps of the method described in the first aspect or any possible implementation of the first aspect.

[0024] Based on the implementations provided in the above aspects, this application can also be further combined to provide more implementations. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 A schematic diagram of the structure of a computer device provided for this application;

[0026] Figure 2 A flowchart of a memory access heat statistics method provided in this application;

[0027] Figure 3 A schematic diagram of the relationship between a cache line and a page provided for this application;

[0028] Figure 4 A schematic diagram of a storage structure of access frequency provided for this application;

[0029] Figure 5 A schematic diagram of an interleaving method provided for this application;

[0030] Figure 6 A schematic diagram of the structure of another computer device provided for this application;

[0031] Figure 7 A schematic diagram of a memory access heat statistics device provided in this application;

[0032] Figure 8 A schematic diagram of the structure of a controller provided in this application. DETAILED DESCRIPTION

[0033] For the convenience of description, the terms involved in this application are first briefly explained.

[0034] Memory is a memory device used to store programs and various data. Access speed refers to the data transmission speed when writing or reading data from the memory. Access speed can also be called read and write speed. According to the access speed of the memory, the main memory connected to the processor in the computer device can be divided into far memory and near memory. The main memory can be referred to as main memory or memory. The access speed of the near memory is greater than the access speed of the far memory. For example, the near memory can be a dynamic random access memory (DRAM) or a double data rate synchronous dynamic random access memory (doubledatarate SDRAM, DDR SDRAM). The far memory can be a storage-class-memory (SCM).

[0035] Hot data refers to data that is frequently accessed by the processor. If hot data is stored in the local memory, the processor can obtain the data as quickly as possible, which increases the data processing speed of the system and reduces the data processing delay, significantly improving the access performance of the system.

[0036] Cold data refers to data that is not frequently accessed by the processor. If cold data is stored in remote memory, data reliability can be improved, and more hot data can be stored in local memory, thereby improving local memory resource utilization and reducing system costs.

[0037] A cache line is a unit in which a computer device reads or writes memory. The size of a cache line can be 64 bytes (byte, B).

[0038] Page refers to the unit in which a computer device manages the storage space of memory. For example, the page size (pagesize) is 4 kilobytes (KB), 2 megabytes (MB), or other byte sizes. A 4KB page can be called a small page. A 2MB page can be called a large page. The smaller the page, the more resources the computer device needs to manage memory; the larger the page, the fewer resources the computer device needs to manage memory. A page can include multiple cache lines, that is, the page size is a multiple of the cache line size.

[0039] Interleaving refers to evenly distributing memory access data to multiple memory channels according to unit storage space (for example, cache lines). The interleaving method can be configured by the system administrator and can be interleaved between multiple memory channels connected to a processor or between multiple memory channels of multiple processors.

[0040] Memory channels refer to multiple memories connected to a processor in a computer device. The processor can use interleaving technology to operate the memory. For example, the processor evenly distributes the data to be written to the memory to multiple memory channels according to the size of the cache line. Then, the processor reads data from multiple memory channels according to the size of the cache line. Thus, data processing is performed based on multiple memory channels to improve the memory bandwidth utilization and processing performance of the computer device.

[0041] In order to improve the accuracy of memory access heat statistics, the present application provides a memory access heat statistics method, that is, according to the operation of the application program running on the memory of the computer device by the processor in the computer device, the access frequency of the processor accessing the data block in the memory is counted, so as to determine the access heat of the data block according to the access frequency, and trigger data migration according to the access heat. The access frequency intuitively represents the frequency of data block access by the application program. The more times a data block is accessed by the application program, the more frequently the data block is accessed by the application program, and the hotter the access heat of the data block; the fewer times a data block is accessed by the application program, the less frequently the data block is accessed by the application program, and the colder the access heat of the data block. Therefore, when data migration is triggered according to the access heat of the data block, hot data can be migrated to the proximal memory, and cold data can be migrated to the remote memory, so that the processor can obtain frequently accessed data from the proximal memory as quickly as possible, improve the data processing speed of the system, and reduce the data processing delay, significantly improving the access performance of the system.

[0042] The size of the data block is a multiple of a unit storage space in a memory accessible to a processor. For example, the size of the data block is a page size used by a computer device to manage memory. For another example, the size of the data block is a size of an interleaved data block in a memory accessible to a processor in a computer device using an interleaved manner.

[0043] The memory access heat statistics method provided by the present application is described in detail below with reference to the accompanying drawings.

[0044] Figure 1 This is a schematic diagram of the structure of a computer device provided in this application. Here, a computer device including a proximal memory is used as an example for explanation. Figure 1 As shown, the computer device 100 includes a processor 110 and a memory 120. The processor 110 and the memory 120 are connected via a bus 130.

[0045] The processor 110 may be a central processing unit (CPU), a graphics processing unit (GPU), a data processing unit (DPU), a neural processing unit (NPU), an embedded neural network processor (NPU), and the like for data processing. The processor 110 may also be other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA), systems on chip (SoC), or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, and the like. A general-purpose processor may be a microprocessor or any conventional processor, and the like. For ease of description, the following embodiments are described by taking the processor 110 as a CPU as an example.

[0046] Figure 1 The computer device 100 may include one or more processors. The processor may be a multi-core processor. The processor herein may refer to one or more devices, circuits, and / or computing units for processing data (e.g., computer program instructions).

[0047] The processor 110 is used to run an application program to perform a read operation or a write operation on the memory 120 , and to trigger data migration according to the access hotness or coldness of the memory 120 .

[0048] The bus 130 may include a path for transmitting data between the above components (such as the processor 110 and the memory 120). For example, the access request sent by the processor 110 to the memory 120, and the access frequency of the data block fed back by the memory 120 to the processor 110. In addition to the data bus, the bus 130 may also include a power bus, a control bus, and a status signal bus. For example, the bus 130 is a DDR bus. However, for the sake of clarity, various buses are labeled as bus 130 in the figure.

[0049] The memory 120 may be a volatile memory pool or a non-volatile memory pool, or may include both volatile and non-volatile memory. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), which is used as an external cache. By way of example but not limitation, many forms of RAM are available, such as static random access memory (SRAM), DRAM, synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous connection dynamic random access memory (SLDRAM) and direct rambus RAM (DR RAM).

[0050] The memory 120 includes a memory cell 121 , a data buffer (DB) 122 and a register clock driver (RCD) 123 . The DB 122 connects the memory cell 121 and the RCD 123 .

[0051] The memory cell 121 is used to store application data of the application program executed by the processor 110. For example, the memory cell 121 may be a DRAM.

[0052] DB 122 is used to drive the data signal generated by the memory controller in the processor 110 to write the data sent by the processor 110 into the memory particle 121, and transmit the application data stored in the memory particle 121 to the processor 110 or transmit the access frequency of the data block stored in the RCD 123 to the processor 110.

[0053] RCD 123 is used to drive the clock signal, address signal and command signal generated by the memory controller in the processor 110 to implement the operation on the multiple memory particles 121. RCD 123 is used to perform a read operation or a write operation on the memory particles 121 in the memory 120 according to the access request of the processor 110, and count the access frequency of the data block of the memory particles 121 in the memory 120 to store the access frequency of the data block. RCD 123 is also used to obtain the access frequency of the data block from the storage medium 124. Optionally, RCD 123 can determine the access heat of the data block according to the access frequency to trigger data migration.

[0054] Among them, RCD 123 includes a storage medium 124, and the storage medium 124 is used to store the access frequency of the data block. Thereby avoiding occupying the storage space of the memory particle 121 to store the access frequency of the data block, improving the resource utilization of the memory particle 121. The storage medium 124 can be a volatile memory pool or a non-volatile memory pool, or can include both volatile and non-volatile memories. For example, the storage medium 124 can be a RAM or a ROM. The storage capacity of the storage medium 124 is related to the size of the data block used to count the access frequency. The storage capacity of the storage medium 124 can be determined according to the following two methods.

[0055] Method 1: The capacity of the storage medium storing the access frequency of the page is determined according to the capacity of the memory, the page size and the bit width of the access frequency counter.

[0056] When counting the access frequency of a page, the capacity of the storage medium used to store the access frequency of the page can be determined by the capacity of the memory, the page size, and the bit width of the access frequency counter. The capacity of the storage medium is shown in the following formula (1).

[0057] n1 capacity =(n capacity / X page size )*W count Formula (1)

[0058] Among them, n1 capacity Indicates the capacity of the storage medium used to store the access frequency of the page, n capacity Indicates the capacity of the memory, X page size Indicates the page size, W count The counter bit width that indicates the access frequency. The counter bit width can be determined based on experience. The larger the counter bit width, the larger the value recorded by the counter; the smaller the counter bit width, the smaller the value recorded by the counter.

[0059] Example 1: Assume that the capacity of the memory is 64 GB, the page size is 4 KB, the counter bit width is 4 B, and the capacity of the storage medium is (64 GB / 4 KB)*4 B=64 MB.

[0060] Example 2: Assume that the capacity of the memory is 64 GB, the page size is 2 MB, the counter bit width is 4 B, and the capacity of the storage medium is (64 GB / 2 MB)*4 B=128 KB.

[0061] It can be seen that the larger the page size, the smaller the capacity of the storage medium, and the less data indicating the access frequency of the page that needs to be stored. The smaller the page size, the larger the capacity of the storage medium, and the more data indicating the access frequency of the page that needs to be stored.

[0062] In addition, when the computer device manages memory in 4KB pages, the storage space required by the storage medium 124 is relatively large. In some embodiments, the RCD 123 can be connected to an external storage medium to expand the access frequency capacity of the RCD 123 storage page. For example, Figure 1 As shown in , RCD 123 is also connected to storage medium 125. Storage medium 124 can be used to cache the access frequency of frequently accessed pages. Storage medium 125 is used to store the access frequency of pages. Optionally, when RCD 123 updates the access frequency of pages stored in storage medium 125, it involves two operations of storage medium 125. RCD 123 can meet the demand for storage access frequency by expanding the bandwidth of the storage medium or increasing the access frequency of the storage medium. For example, RCD123 can connect at least two storage media to expand the bandwidth of the storage medium and increase the access frequency of the storage medium.

[0063] Method 2: determining the capacity of the storage medium storing the access frequency of the interleaved data block according to the capacity of the memory, the page size, the bit width of the access frequency counter and the number of interleaved internal channels.

[0064] When counting the access frequency of the interleaved data block, the capacity of the storage medium for storing the access frequency of the interleaved data block can be determined by the capacity of the memory, the page size, the bit width of the access frequency counter and the number of interleaved internal channels.

[0065] Assume that the number of memory channels in a computer device is N channel , the page size is X page size Bytes, data is stored in N cache lines. channel The size of the interleaved data block (sub-page) distributed on each memory channel is X page size / N channel Bytes, that is, the controller of each memory channel is Xpage size / N channel Bytes manage memory units, and the controller of each memory channel records the X-based page size / N channel The access frequency of a data block of byte. The capacity of the storage medium is shown in the following formula (2).

[0066] n1 capacity = = (n capacity / (X page size / N channel )*W count ) Formula (2)

[0067] Among them, n1 capacity The capacity of the storage medium that represents the access frequency of the interleaved data blocks, n capacity Indicates the capacity of the memory, X page size Indicates the page size, W count The bit width of the counter indicating the access frequency. N channel Indicates the number of memory channels.

[0068] Example 1, assuming the page size is 2MB (X page size =2MB), data is interleaved across 8 memory channels at the granularity of cache lines (N channel =8), the size of the interleaved data block of each memory channel is 256KB, and the memory capacity is 64GB (n capacity =64GB), the access frequency counter bit width is 4B (W count =4B), the capacity of the storage medium is 1MB. The computer device needs to reserve 8MB of physical address space for the storage medium of 8 memory channels. The processor obtains the access frequency of 8 memory channels based on 256KB units, and can combine the access frequency of a complete 2MB page to perform data migration. For example, the processor can add these 8 data.

[0069] Example 2: Assume the page size is 4KB (X page size =4KB), data is interleaved across 8 memory channels at the granularity of cache lines (N channel =8), the size of the interleaved data block of each memory channel is 512B, and the memory capacity is 64GB (n capacity =64GB), the access frequency counter bit width is 4B (W count=4B), the capacity of the storage medium is 0.5GB. The RCD of each memory channel needs to record the access frequency based on 512B. The computer device needs to reserve 4GB of physical address space for the storage medium of 8 memory channels.

[0070] It should be understood that Figure 1 The components included in the computer device 100 are only for schematic illustration. In a specific embodiment, the number of components can be determined according to business requirements.

[0071] Next, combine Figure 2 A memory access heat statistics method provided by this application is introduced, as shown in the figure.

[0072] Step 210 : RCD 123 determines the storage space to be accessed by the access request sent by processor 110 .

[0073] RCD 123 receives the access request sent by processor 110 through memory bus (eg, DDR bus), decodes the access request, obtains physical address and operation instruction, and determines whether processor 110 accesses memory granule 121 or storage medium 124 in memory 120 according to the physical address.

[0074] If the physical address indicates the storage space of the memory cell 121, it means that the RCD 123 determines that the application program executed by the processor 110 accesses the memory cell 121, and determines to perform a read operation or a write operation on the memory cell 121 according to the operation instruction. Steps 220 and 230 are executed.

[0075] If the physical address indicates the storage space of the storage medium 124, it means that the RCD 123 determines the access frequency of the processor 110 accessing the storage medium 124 to obtain the data block, and determines to perform a read operation on the storage medium 124 according to the operation instruction. Steps 240 and 250 are executed.

[0076] Step 220 : RCD 123 operates the memory cell 121 in the memory 120 .

[0077] If the operation instruction indicates to perform a write operation on the storage space indicated by the physical address in the memory particle 121, the RCD 123 writes the data obtained through the DB 122 into the storage space indicated by the physical address.

[0078] If the operation instruction indicates to perform a read operation on the storage space indicated by the physical address in the memory particle 121 , the RCD 123 reads the data stored in the storage space indicated by the physical address and transmits the data to the processor 110 through the DB 122 .

[0079] Step 230: RCD 123 counts the access frequency of the data block where the first address is located.

[0080] Since the application program run by the processor 110 uses the cache line as the minimum granularity for the operation on the memory 120, the access request sent by the processor 110 indicates that the application program run by the processor 110 performs a read operation or a write operation on a cache line. RCD 123 performs a read operation or a write operation on a cache line indicated by the physical address. Once a cache line is read or written, the access frequency of the page to which the cache line belongs increases by one. RCD 123 can set a counter for each page to count the access frequency of the page. Each time the application program run by the processor 110 accesses a page, the counter corresponding to the page increases by one. Thus, the memory access heat statistics are performed at the granularity of the page of the storage space of the memory managed by the computer device to improve the accuracy of the memory access heat statistics.

[0081] For example, Figure 3 As shown in (a), the size of the physical address space of the memory is 2 N+1 , where the cache line size is 64 bytes. The page size can be 4KB or 2MB.

[0082] like Figure 3 As shown in (b), assume that the size of a cache line is 64 bytes and the page size is 4KB. A 4KB page contains 64 consecutive cache lines. Physical address 0x000 indicates the starting address of the first page. Physical address 0x1000 indicates the starting address of the second page. The first page contains 64 consecutive cache lines between physical addresses 0x000 and 0x1000. The second page contains 64 consecutive cache lines between physical addresses 0x1000 and 0x2000.

[0083] When RCD 123 counts the access frequency in pages, the address segment to be counted is determined based on the page size. For example, if the page size is 4KB, RCD 123 counts the access frequency of the pages contained in the address segment [N:12]. N represents the capacity of the memory 120. For example, if the capacity of the memory 120 is 64GB, N=35. Assuming that the capacity of the memory 120 is 64GB, the address segment [N:12] contains 64GB / 4KB=16MB pages, and RCD 123 counts the access frequency of the 16MB pages contained in the address segment [N:12].

[0084] For another example, the page size is 2MB, and RCD 123 counts the access frequency of the page included in address segment [N:21]. Assuming that the capacity of memory 120 is 64GB, address segment [N:21] includes 64GB / 2MB=32KB pages, and RCD 123 counts the access frequency of the 32KB pages included in address segment [N:21].

[0085] Assume that the physical address included in the access request indicates a first address, and the application program run by the processor 110 accesses the cache line indicated by the first address in the memory particle 121. The first address may be an address or an address segment of a cache line in the statistical address segment. The RCD 123 identifies the second address according to the address of the page where the first address is located and the address mapping relationship, reads the access frequency of the accessed page from the storage medium 124 according to the second address, updates the access frequency of the page, that is, adds one to the access frequency of the page, and writes the updated access frequency of the page back to the storage medium 124. The second address is used to indicate the location of the storage space where the access frequency of the page is stored. The second address may be the page number of the page or the address of the page. The address mapping relationship is used to indicate the mapping relationship between the address of the page and the address of the storage space where the access frequency is stored. For example, when the first address indicates an address, the RCD 123 determines the page number of the page where the cache line indicated by the first address is located according to the first address, and reads the access frequency of the accessed page from the storage medium 124 according to the page number of the page. When the first address indicates an address segment, the RCD 123 determines the page numbers of all pages where the cache line indicated by the address segment is located according to the first address, and then reads the access frequency of the accessed page from the storage medium 124 according to the page numbers of the pages.

[0086] Step 240 : RCD 123 operates the storage medium 124 in the memory 120 .

[0087] Since the computer device pre-allocates the capacity of the memory granule 121 in the memory 120, when the processor 110 accesses the storage medium 124, the computer device allocates the physical address space corresponding to the capacity of the storage medium 124 from the capacity of the memory granule 121 in the memory 120 to the storage medium 124, and the RCD 123 maps the physical address of the storage medium 124 to the storage medium 124, so that the corresponding capacity in the memory granule 121 cannot be used, resulting in a waste of the storage space of the memory granule 121. For example, if the page size is 4KB, 64MB of memory storage space is wasted.

[0088] The RCD 123 can determine the physical address of the storage medium 124 according to the page number (page address) of the page, and store the partial bits of the page number and the access frequency component field into the corresponding address space in the storage medium 124. Figure 4As shown, the bit width of the counter of each page is 4B (32 bits) and is divided into two parts, one part is used to record the access frequency of the page, and the other part records any 8 bits in the page number of the page. The position of recording the access frequency of the page and the position of recording any 8 bits in the page number of the page are not limited. Among them, bit23 to bit0 are used to record the access frequency of the page, and bit32 to bit24 are used to record any 8 bits in the page number of the page, for example, bit32 to bit24 represent the lower 8 bits in the page number of the page. Furthermore, the page number of the page is used to generate the corresponding address space for the processor 110 to access the access frequency of the page stored in the storage medium 124, and obtain the mapping relationship between the address of the data block and the address of the storage space for storing the access frequency, so that it can be used to save the address space reserved for the memory 120, and the purpose of mapping the address space of the storage medium to store the access frequency with a small amount of address space has been achieved, so that the RCD 123 can determine the physical address of the processor 110 to access the storage medium 124 according to the address mapping relationship, and improve the utilization rate of the storage space of the memory particle 121.

[0089] In some embodiments, some bits in the page number of a page are used to generate the corresponding address space of the access frequency of the processor 110 accessing the storage medium 124. For example, the remaining bits of any bit in the page number of the deleted page are used as the corresponding address space of the access frequency of the processor 110 accessing the storage medium 124. The more arbitrary bits in the page number of the deleted page, the smaller the corresponding address space of the access frequency of the processor 110 accessing the storage medium 124; conversely, the fewer arbitrary bits in the page number of the deleted page, the larger the corresponding address space of the access frequency of the processor 110 accessing the storage medium 124. For example, after the RCD 123 operates on the page in the memory granule 121, the lower 8 bits of the page number of the page are stored in the counter bit32 to bit24, and the access frequency recorded in bit23 to bit0 is increased by one.

[0090] The physical address obtained by RCD 123 indicates the storage space of the storage medium 124, indicating that RCD 123 determines the access frequency of the processor 110 accessing the storage medium 124 to obtain the data block, and determines to perform a read operation on the storage medium 124 according to the operation instruction. The physical address can be the remaining bits of any bit in the page number of the deleted page. For example, RCD 123 obtains the third address, determines the storage space of the storage medium 124 indicated by the third address, and after reading the 32-bit data, extracts the high 8 bits, adds the third address, and obtains the page number. The corresponding 24-bit data bits are the access frequency of the page with the corresponding page number.

[0091] Step 250 : RCD 123 determines the access popularity of the data block according to the access frequency.

[0092] If the access frequency is greater than or equal to the threshold, the data block is determined to be hot; if the cold access frequency is less than the threshold, the data block is determined to be cold. RCD 123 can feed back the page number and the access heat of the page indicated by the page number to processor 110 to trigger data migration.

[0093] In this way, the processor operates the memory at the granularity of cache line, and the cache line belongs to a certain page under management. Then, once the cache line in the memory is operated, the page to which the cache line belongs is also read and written once. The controller counts the access frequency of the page to which the cache line being operated belongs, effectively improving the accuracy of identifying the access heat of the page. Moreover, counting the access frequency of the page at the granularity of the page is compatible with the page management method of the computer device for the memory, and the memory access heat statistics method is easy to use. In addition, when data migration is triggered according to the access heat of the data block, hot data can be migrated to the proximal memory, and cold data can be migrated to the remote memory, so that the processor can obtain frequently accessed data from the proximal memory as quickly as possible, thereby improving the data processing speed of the system, and reducing the data processing delay, significantly improving the access performance of the system.

[0094] The above embodiment illustrates the memory access heat statistics method using 4KB pages (small pages) and 2MB pages (large pages).

[0095] In other embodiments, when the application program executed by the processor operates the memory of the computer device in an interleaved manner, the data accessing the memory is evenly distributed to multiple memory channels according to the unit storage space (e.g., cache line). When the controller of each memory channel performs memory access heat statistics, the access frequency of the interleaved data block is counted. The method for the controller of each memory channel to count the access frequency of the interleaved data block can refer to the above description of the access frequency of the page.

[0096] Compared with the non-interleaved scenario, the difference in counting the access frequency of the interleaved data block is that the size of the interleaved data block is smaller than the page size, and the corresponding address space of the access frequency of the processor 110 accessing the storage page in the storage medium 124 is generated according to some bits in the address of the interleaved data block.

[0097] For example, Figure 5 As shown in the figure, a 2MB page includes 512 4KB pages, a cache line size is 64B, and a 4KB page includes 64 cache lines. A 2MB page includes 512*64 cache lines evenly divided into less than 8 memory channels, and each memory channel is allocated 512*512B cache lines. Each memory channel contains a 256KB interleaved data block.

[0098] For example, the page size is 4KB (X page size =4KB), data is interleaved across 8 memory channels at the granularity of cache lines (N channel =8), then the size of the interleaved data block of each memory channel is 512B. Each in-memory controller records the access frequency of 64GB / 512B=128MB interleaved data blocks. The capacity of the storage medium for storing the access frequency of the interleaved data blocks in each in-memory controller is 0.5GB. The computer device needs to reserve 4GB of physical address space for the storage medium of 8 memory channels.

[0099] For example, the page size is 2MB (X page size =2MB), the memory capacity is 64GB, the counter width is 4B. The reserved address space for each memory is 1MB, there are 8 memory channels, and the reserved memory address space is 8MB.

[0100] In some embodiments, the controller can determine the address of the storage space in the controller for storing the access frequency of the interleaved data block, which is accessed by the processor, based on the mapping relationship between the address of the interleaved data block and the address of the storage space for storing the access frequency. That is, the controller stores any 8 bits of the address of the interleaved data block in bit32 to bit24 of the counter of the interleaved data block, and adds one to the access frequency of the interleaved data block recorded in bit23 to bit0. The remaining bits of the address of the interleaved data block serve as the physical address of the processor accessing the storage medium storing the access frequency of the interleaved data block.

[0101] For example, when the controller in the memory records the access frequency of 64GB / 512B=128MB of interleaved data blocks, the physical address space of the processor accessing the storage medium is reduced to 0.5GB / 256=2MB. At the same time, the access frequency counter bit width is 4B, and the minimum data granularity of the processor access frequency counter is 4B. The 2MB physical address space can be further reduced to 2MB / 4B=512KB. A total of 4MB of physical address space needs to be reserved for 8 memory channels, so only 4MB of memory capacity is wasted.

[0102] The controller determines the physical address of the access frequency of the page stored in the storage medium according to the physical address indicated by the processor accessing the storage medium. For example, for each memory, the processor periodically and continuously reads the access frequency of the interleaved data block stored in the controller in the memory, and the controller detects the corresponding 512KB address access, which is addressed as PA[18:0]. The controller implements an 8-bit address counter AddrCnt[7:0]. When the 512KB address is accessed continuously, the AddrCnt[7:0] counter is incremented, and the controller generates a physical address MAT_Addr={AddrCnt[7:0], PA[18:0]}. The controller accesses the access frequency of the interleaved data block stored in the controller based on the physical address MAT_Addr.

[0103] After the controller reads the 32-bit data, it extracts the upper 8 bits and adds them to PA[18:0], a total of 27 bits for the address of the interleaved data block (sub-page), and the corresponding lower 24 bits of the data bits are the access frequency of the corresponding interleaved data block. The processor obtains the 512B-based access frequency of the 8 memory channels and can combine a complete 4KB page for access frequency. For example, add the access frequencies of the 8 memory channels, or take the mean, variance, maximum value, etc. of the access frequencies of the 8 memory channels.

[0104] The above embodiment is a method for calculating memory access heat statistics by taking an access request as an example of the processor 110. If the application program running on the processor 110 sends multiple access requests to the memory operation of the computer device, statistics are collected for the data block where the physical address corresponding to each access request is located. The specific method can refer to the description of the above embodiment.

[0105] The above embodiments, in combination with the accompanying drawings, illustrate the connection relationship between the controller and the proximal memory included in the computer device and the scenario of the memory access heat statistics method of the proximal memory. As described in the above embodiments, the memory 120 may indicate the proximal memory (also referred to as the near memory), and the RCD 123 may refer to a controller that controls the proximal memory to perform memory access heat statistics.

[0106] In other embodiments, the computer device may include a remote memory (also referred to as far memory), and the controller counts the access frequency of the remote memory. The difference from the connection relationship between the near memory and the controller is that, relative to the memory controller in the processor, the controller that controls the remote memory to perform memory access heat statistics can be an extended controller.

[0107] Optionally, the computer device includes a remote memory and a near-end memory, and the access frequency of the near-end memory is counted by the RCD in the near-end memory, and the access frequency of the remote memory is counted by the extension controller connected to the remote memory.

[0108] Based on the application, the threshold of access frequency is determined, and data with access frequency greater than the threshold is judged as hot data and placed in the near-end memory, and data with access frequency less than the threshold is judged as cold data and placed in the far-end memory. Under the premise that the setting of the threshold does not affect the application performance, it is found that only a small amount of memory access data is hot data, and most of the memory access data is cold data. Computer equipment can be configured with a larger proportion of far-end memory to reduce system costs. The reduction in the proportion of hot data can reduce data migration between near-end memory and far-end memory, and reduce the system memory bandwidth usage and CPU overhead.

[0109] As a possible implementation, the present application also provides a schematic diagram of the structure of another computer device. Figure 6 As shown, on the basis that the computer device 100 includes a processor 110 and a memory 120, the computer device 100 also includes a memory 610. The memory 120 can be used as a near-end memory, and the memory 610 can be used as a far-end memory. The processor 110 and the memory 610 are connected via a bus 620.

[0110] The memory 610 includes an expansion controller 611, a memory particle 612, and a storage medium 613. The memory particle 612 includes a DRAM and a SCM. The storage medium 613 may be a DRAM.

[0111] The expansion controller 611 is used to perform a read operation or a write operation in the memory particle 612 according to the access request of the processor 110, and count the access frequency of the data block in the memory particle 612, and store the access frequency of the data block in the storage medium 613. The expansion controller 611 can also be connected to an external storage medium 614 to expand the storage capacity of the storage medium 613 and store the access frequency of the data block.

[0112] The expansion controller 611 is further used to obtain the access frequency of the data block from the storage medium 613 .

[0113] The functions of the extended controller 611 and the method of counting the access frequency of the data blocks of the memory particles 612 in the memory 610, as well as obtaining the access frequency of the data blocks from the storage medium 613 can refer to the relevant description of the controller counting the access frequency of the proximal memory.

[0114] Memory 610 may be a volatile memory pool or a non-volatile memory pool, or may include both volatile and non-volatile memory. Among them, the non-volatile memory may be ROM, PROM, EPROM, EEPROM, or flash memory. The volatile memory may be RAM. By way of example but not limitation, many forms of RAM are available, such as SRAM, DRAM, SDRAM, DDR SDRAM, ESDRAM, SLDRAM, and DR RAM.

[0115] The bus 620 may include a path for transmitting data between the above components (such as the processor 110 and the memory 610). For example, the access request sent by the processor 110 to the memory 610, and the access frequency of the data block fed back by the memory 610 to the processor 110. In addition to the data bus, the bus 620 may also include a power bus, a control bus, and a status signal bus. For example, the bus 620 is a DDR bus. However, for the sake of clarity, various buses are marked as bus 620 in the figure. The bus 620 may be a Peripheral Component Interconnect Express (PCIe) bus, or an extended industry standard architecture (EISA) bus, a unified bus (Ubus or UB), a computer express link (CXL), a cache coherent interconnect for accelerators (CCIX), etc. The bus 620 can be divided into an address bus, a data bus, a control bus, etc.

[0116] The embodiment of the present application describes the structure of the proximal memory and the remote memory included in the computer device. The method for counting the memory access heat of the proximal memory and the remote memory can refer to the above description of the memory access heat statistics of the proximal memory. The access frequency of the proximal memory is counted by the RCD in the proximal memory, and the access frequency of the remote memory is counted by the extended controller connected to the remote memory, which consumes almost no CPU performance, and the processor operates the memory with the cache line as the granularity, and the cache line belongs to a certain page of management, then the cache line in the memory is operated once, and the page to which the cache line belongs is also read and written once. The controller counts the access frequency of the page to which the cache line is operated, which effectively improves the recognition accuracy of the access heat of the page, and the page access frequency is counted with the page as the granularity, which is compatible with the page management method of the computer device for the memory, and the memory access heat statistics method has ease of use. In addition, based on the threshold value of the access frequency determined by the application, the data with an access frequency greater than the threshold is judged as hot data and placed in the proximal memory, and the data with an access frequency less than the threshold is judged as cold data and placed in the remote memory. Under the premise that the threshold setting does not affect the application performance, it is found that only a small amount of memory access data is hot data, and most of the memory access data is cold data. Computer equipment can be configured with a larger proportion of remote memory to reduce system costs. The reduction in the proportion of hot data can reduce data migration between local memory and remote memory, and reduce the system memory bandwidth usage and CPU overhead.

[0117] In order to implement the functions in the above-mentioned embodiments, the controller includes hardware structures and / or software modules corresponding to the execution of each function. It should be easily appreciated by those skilled in the art that, in combination with the units and method steps of each example described in the embodiments disclosed in this application, the present application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a function is executed in the form of hardware or computer software driving hardware depends on the specific application scenario and design constraints of the technical solution.

[0118] Combined with the above Figures 1 to 6 , describes in detail the memory access heat statistics method provided by this application, and will be combined with Figure 7 , describing the memory access heat statistics device provided by this application.

[0119] Figure 7 Schematic diagram of the structure of a possible memory access heat statistics device provided in the present application. These memory access heat statistics devices can be used to implement the functions of the controller in the above method embodiment, and thus can also achieve the beneficial effects possessed by the above method embodiment. In this embodiment, the memory access heat statistics device can be as follows: Figure 2 The controller shown may also be a module (such as a chip) applied to a computer device.

[0120] like Figure 7 As shown, the memory access heat statistics device 700 includes a communication module 710, a statistics module 720 and a storage module 730. The memory access heat statistics device 700 is used to implement the above Figure 2 The functions of the controller in the method embodiment shown in FIG.

[0121] The communication module 710 is used to determine a first address according to an obtained access request, wherein the access request is used to instruct an application program running on a processor in the computer device where the controller is located to operate on the memory of the computer device, and the first address is a physical address in the memory.

[0122] The statistical module 720 is used to count the access frequency of the data block where the first address is located, and the size of the data block is a multiple of the unit storage space in the memory accessible by the processor. For example, the statistical module 720 is used to execute Figure 2 Steps 210 to 250.

[0123] The statistical module 720 is specifically configured to count the access frequency of the data block where the unit storage space to which the first address belongs is located.

[0124] The storage module 730 is used to store the access frequency so that the statistical module 720 can determine the access popularity of the data block according to the access frequency and trigger data migration.

[0125] The memory access heat statistics device 700 of the embodiment of the present application can be implemented by an application-specific integrated circuit (ASIC) or a programmable logic device (PLD), and the PLD can be a complex programmable logical device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), a DPU, a SoC or any combination thereof. It can also be implemented by software. Figure 2 The memory access heat statistics method shown in the figure and its various modules may also be software modules, and the memory access heat statistics device 700 and its various modules may also be software modules.

[0126] The memory access heat statistics device 700 according to the embodiment of the present application may correspond to the method described in the embodiment of the present application, and the above and other operations and / or functions of each unit in the memory access heat statistics device 700 are respectively to implement Figure 2For the sake of brevity, the corresponding processes of each method in are not repeated here.

[0127] Figure 8 The present application provides a schematic diagram of the structure of a controller 800. As shown in the figure, the controller 800 includes a processing unit 810, a bus 820, a storage unit 830 and a communication interface 840. The processing unit 810, the storage unit 830 and the communication interface 840 are connected via the bus 820.

[0128] In this embodiment, the processing unit 810 may be a CPU, and the processing unit 810 may also be other general-purpose processors, digital signal processors (DSP), ASICs, FPGAs or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or any conventional processor, etc.

[0129] The communication interface 840 is used to implement the communication between the controller 800 and an external device or component. Figure 2 When the controller functions as shown, the communication interface 840 is used to obtain access requests.

[0130] The bus 820 may include a path for transmitting information between the above components (such as the processing unit 810 and the storage unit 830). In addition to the data bus, the bus 820 may also include a power bus, a control bus, and a status signal bus. However, for the sake of clarity, various buses are marked as bus 820 in the figure. The bus 820 may be a Peripheral Component Interconnect Express (PCIe) bus, or an extended industry standard architecture (EISA) bus, a unified bus (Ubus or UB), a computer express link (CXL), a cache coherent interconnect for accelerators (CCIX), etc. The bus 820 can be divided into an address bus, a data bus, a control bus, etc.

[0131] As an example, the controller 800 may include multiple processors. The processor may be a multi-core (multi-CPU) processor. The processor here may refer to one or more devices, circuits, and / or computing units for processing data (such as computer program instructions). In this embodiment, the controller 800 is used to implement Figure 2 When the controller functions as shown, the processing unit 810 counts the access frequency of the data block where the first address is located.

[0132] Optionally, a method for calculating the access frequency of the data block may also be burned into the processing unit 810, so that the processing unit 810 can calculate the access frequency of the data block.

[0133] Figure 8 In the example, the controller 800 includes one processing unit 810 and one storage unit 830. Here, the processing unit 810 and the storage unit 830 are respectively used to indicate a type of device or equipment. In a specific embodiment, the number of each type of device or equipment can be determined according to business requirements.

[0134] The storage unit 830 may be used to store information such as access frequency in the above method embodiment. The storage unit 830 may be a volatile memory pool or a non-volatile memory pool, or may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of RAM are available, such as static RAM (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM), and direct rambus RAM (DR RAM).

[0135] The storage unit 830 may also correspond to a storage medium for storing information such as computer instructions in the above method embodiments, for example, a disk such as a mechanical hard disk or a solid state disk.

[0136] The controller 800 may be a general device or a dedicated device. For example, the controller 800 may also be a server or other device with computing capabilities.

[0137] The controller 800 according to this embodiment may correspond to the memory access heat statistics device 700 in this embodiment, and may correspond to executing Figure 2 The corresponding subject in any method, and the above and other operations and / or functions of each module in the memory access heat statistics device 700 are respectively to realize Figure 2 For the sake of brevity, the corresponding processes of each method in are not repeated here.

[0138] The controller 800 described in the embodiment of the present application may be an RCD controller in the memory of the computer device, or the controller 800 may be an extended controller connected to the memory of the computer device.

[0139] An embodiment of the present application also provides a chip, including: a processor and a power supply circuit; the power supply circuit is used to supply power to the processor; the processor is used to execute the memory access heat statistics method described in the above embodiment.

[0140] An embodiment of the present application also provides a memory, which includes a storage device and a controller, and the storage device is used to store a group of computer instructions; when the controller executes a group of computer instructions, the memory access heat statistics method described in the above embodiment is executed.

[0141] An embodiment of the present application also provides a mainboard, which includes a controller, and the controller executes the memory access heat statistics method described in the above embodiment.

[0142] The method steps in this embodiment can be implemented by hardware or by a processor executing software instructions. The software instructions can be composed of corresponding software modules, which can be stored in random access memory (RAM), flash memory, read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, hard disks, mobile hard disks, CD-ROMs, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor so that the processor can read information from the storage medium and write information to the storage medium. Of course, the storage medium can also be a component of the processor. The processor and the storage medium can be located in an ASIC. In addition, the ASIC can be located in a computing device. Of course, the processor and the storage medium can also exist in a computing device as discrete components.

[0143] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented by software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer programs or instructions. When the computer program or instruction is loaded and executed on a computer, the process or function described in the embodiment of the present application is executed in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, a network device, a user device or other programmable device. The computer program or instruction may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer program or instruction may be transmitted from one website site, computer, server or data center to another website site, computer, server or data center by wired or wireless means. The computer-readable storage medium may be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available medium may be a magnetic medium, for example, a floppy disk, a hard disk, a tape; it may also be an optical medium, for example, a digital video disc (DVD); it may also be a semiconductor medium, for example, a solid state drive (SSD).

[0144] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed in the present application, and these modifications or replacements should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. A memory data migration method, characterized in that: include: The extended controller counts the access frequency of the first data block, wherein the first data block is located in the remote memory or the near-end memory; The expansion controller provides access heat to the processor, where the access heat is determined by the access frequency of the first data block; The processor migrates the data in the first data block between the remote memory and the local memory based on the access heat.

2. The method according to claim 1, characterized in that The first data block includes a plurality of sub-blocks, and the expansion controller counts the access frequency of the first data block, specifically including: The expansion controller counts the access frequency of each sub-block in the plurality of sub-blocks, wherein the access frequency of each sub-block indicates the frequency with which the processor accesses data in each sub-block; The access frequency of the first data block is determined by the access frequency of each sub-block.

3. The method according to claim 2, characterized in that The processor migrates the data in the first data block between the remote memory and the local memory, specifically including: Migrating hot data in the first data block from the remote memory to the local memory, or, Migrate cold data in the first data block from the near-end memory to the far-end memory.

4. The method according to claim 3, characterized in that At least one sub-block of the plurality of sub-blocks includes the hot data.

5. The method according to any one of claims 1 to 4, characterized in that: The access frequency of the first data block is stored in a first counter, and the method further comprises: After counting the access frequency of the first data block, the expansion controller updates the first counter using the counted access frequency of the first data block.

6. The method according to any one of claims 1 to 5, characterized in that The method further comprises: The processor sends a first access request, where the first access request includes a first address, where the first address indicates a storage location of the first data block; The expansion controller updates the access frequency of the first data block based on the first access request.

7. The method according to any one of claims 1 to 6, characterized in that The method further comprises: The processor sends a second request, wherein the second access request includes a second address, and the second address indicates a storage location of the access heat; The processor obtains the access heat based on the second request.

8. The method according to any one of claims 1 to 7, characterized in that The expansion controller is located in the remote memory.

9. The method according to any one of claims 1 to 7, characterized in that: The expansion controller is located in the proximal memory.

10. The method according to any one of claims 1 to 7, characterized in that: The expansion controller is integrated in the processor.

11. The method according to any one of claims 1 to 7, characterized in that: The expansion controller is connected to the proximal memory and / or the distal memory.

12. The method according to any one of claims 1 to 11, characterized in that The proximal memory and / or the remote memory is a volatile memory pool or a non-volatile memory pool.

13. The method according to any one of claims 1 to 12, characterized in that The processor accesses data blocks in the proximal memory and / or the remote memory via the expansion controller in an interleaving manner, wherein the interleaving manner indicates that there are multiple memory channels between the processor and the proximal memory and / or the remote memory.

14. A memory access heat statistics method, characterized in that: The method is executed by an extension controller and includes: Counting the access frequency of a first data block, wherein the first data block is located in a proximal memory or a remote memory; Access heat is provided to a processor so that the processor migrates data in the first data block between the remote memory and the near-end memory according to the access heat, wherein the access heat is determined by an access frequency of the first data block.

15. The method according to claim 14, characterized in that The first data block includes a plurality of sub-blocks, and the counting of access frequencies of the first data block specifically includes: Counting the access frequency of each sub-block in the plurality of sub-blocks, wherein the access frequency of each sub-block indicates the frequency with which the processor accesses data in each sub-block; The access frequency of the first data block is determined by the access frequency of each sub-block.

16. The method according to claim 15, characterized in that The processor migrates the data in the first data block between the remote memory and the local memory, specifically including: Migrating hot data in the first data block from the remote memory to the local memory, or, Migrate cold data in the first data block from the near-end memory to the far-end memory.

17. The method according to claim 16, characterized in that At least one sub-block of the plurality of sub-blocks includes the hot data.

18. The method according to any one of claims 14 to 17, characterized in that: The access frequency of the first data block is stored in a first counter. The method further includes: after counting the access frequency of the first data block, updating the first counter with the counted access frequency of the first data block, and the access heat is determined by the counted access frequency of the first data block.

19. The method according to any one of claims 14 to 18, characterized in that The method further comprises: receiving a first access request sent by the processor, wherein the first access request includes a first address, and the first address indicates a storage location of the first data block Based on the first access request, the access frequency of the first data block is updated.

20. The method according to any one of claims 14 to 19, characterized in that The method further comprises: receiving a second request sent by the processor, wherein the second access request includes a second address, and the second address indicates a storage location of the access heat; Based on the second request, the access temperature is provided to the processor.

21. The method according to any one of claims 14 to 20, characterized in that The expansion controller is located in the proximal memory.

22. The method according to any one of claims 14 to 20, characterized in that The expansion controller is located in the remote memory.

23. The method according to any one of claims 14 to 20, characterized in that: The expansion controller is integrated in the processor.

24. The method according to any one of claims 14 to 20, characterized in that The expansion controller is connected to the proximal memory and / or the distal memory.

25. The method according to any one of claims 14 to 24, characterized in that The proximal memory and / or the remote memory is a volatile memory pool or a non-volatile memory pool.

26. The method according to any one of claims 14 to 25, characterized in that The processor accesses data blocks in the proximal memory and / or the remote memory via the expansion controller in an interleaving manner, wherein the interleaving manner indicates that there are multiple memory channels between the processor and the proximal memory and / or the remote memory.

27. A memory access heat statistics device, characterized in that: include: A statistics module, configured to count the access frequency of a first data block, wherein the first data block is located in a proximal memory or a remote memory; A communication module is used to provide access heat to the processor so that the processor migrates data in the first data block between the remote memory and the proximal memory according to the access heat, wherein the access heat is determined by the access frequency of the first data block.

28. The device according to claim 27, characterized in that The first data block includes a plurality of sub-blocks, and the statistical module is further used for: The access frequency of each sub-block in the multiple sub-blocks is counted, and the access frequency of each sub-block indicates the frequency of the processor accessing the data in each sub-block, wherein the access frequency of the first data block is determined by the access frequency of each sub-block.

29. The device according to claim 27 or 28, characterized in that The statistics module is also used for: After counting the access frequency of the first data block, the first counter is updated with the counted access frequency of the first data block.

30. The device according to any one of claims 27 to 29, characterized in that The communication module is also used for: receiving a first access request sent by the processor, wherein the first access request includes a first address, and the first address indicates a storage location of the first data block Based on the first access request, the access frequency of the first data block is updated.

31. The device according to claim 29 or 30, characterized in that The communication module is also used for: receiving a second request sent by the processor, wherein the second access request includes a second address, and the second address indicates a storage location of the access heat; Based on the second request, the access temperature is provided to the processor.

32. The device according to any one of claims 27 to 29, characterized in that The device is located in the proximal memory.

33. The device according to any one of claims 27 to 29, characterized in that The device is located in the remote memory.

34. The device according to any one of claims 27 to 29, characterized in that The device is integrated in the processor.

35. The device according to any one of claims 27 to 29, characterized in that The device is connected to the proximal memory and / or the remote memory.

36. The device according to any one of claims 27 to 35, characterized in that The proximal memory and / or the remote memory is a volatile memory pool or a non-volatile memory pool.

37. The device according to any one of claims 27 to 36, characterized in that The statistics module is also used for: When the access frequency of the first data block is greater than or equal to a first threshold, it is determined that the data in the first data block is hot data, and the access heat indicates that the data in the first data block is hot data, so that the processor migrates the data in the first data block from the remote memory to the near memory based on the data in the first data block being hot data.

38. The device according to any one of claims 27 to 37, characterized in that The communication module is also used for: The processor accesses data blocks in the proximal memory and / or the remote memory via the communication module in an interleaving manner, wherein the interleaving manner indicates that there are multiple memory channels between the processor and the proximal memory and / or the remote memory.

39. A controller, characterized in that: The controller includes a storage unit and a processing unit, wherein the storage unit is used to store a set of computer instructions; when the processing unit executes the set of computer instructions, the method described in any one of claims 14-26 is executed.

40. The controller according to claim 39, characterized in that The controller is a registered clock driver RCD in the memory of the computer device.

41. The controller according to claim 39, characterized in that The controller is an expansion controller in the memory of the computer device.

42. A chip, characterized in that: include: A processor and a power supply circuit; wherein the power supply circuit is used to supply power to the processor; The processor is configured to execute the method of any one of claims 14 to 26.

43. A memory, characterized in that: The memory includes a storage device and a controller as described in any one of claims 39-41, wherein the storage device includes the first data block.

44. A motherboard, characterized in that: The mainboard includes a controller as described in any one of claims 39-41.

45. A computer device, characterized in that: The computer device comprises a chip as claimed in claim 42.

46. ​​A computer system, characterized in that: The computing system comprises a processor, an expansion controller, a proximal memory and a remote memory, wherein the processor is connected to the proximal memory and the remote memory via the expansion controller; Wherein, the expansion controller is used to execute the method described in any one of claims 14-26; The processor is used for migrating the data in the first data block between the remote memory and the local memory according to the access heat.

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