Table look-up interpolation circuit

Abstract

The invention provides a table lookup interpolation circuit. A lut lookup module generates two nbit output values according to an nbit input address index; the three universal multiplexers are respectively connected to a lut search module, and the three multiplexers are configured with different selection logic signals sel for selection; the left shifting module is connected with one of the three universal multiplexers and is used for shifting an input value leftwards by one bit; the 3-2 one-lacking addition compressor is connected with the left shift module and the other two of the three universal multiplexers, and the sum of two output values of the 3-2 one-lacking addition compressor is 1 less than the sum of the three input values in a complement operation environment; and the fixed-point adder is connected with the 3-2 one-lacking addition compressor and is a standard (n + 2) bit fixed-point adder. Compared with a traditional table look-up method, table entries can be greatly compressed and looked up, and the table entries can be compressed to 1 / 8 of the original table entries at most for table look-up functions with odd function or even function properties.

Description

Technical Field

[0001] The present invention relates to the technical field of digital circuit design, and in particular to a table lookup interpolation circuit. Background Art

[0002] In hardware design, LUT lookup table is a common design to solve nonlinear calculations and irregular mappings. However, due to the representation of standard floating-point numbers, traditional lookup table designs mostly use floating-point decimal original codes for calculations. When there is a need for a two's complement lookup table, it is generally necessary to add a two's complement original code conversion circuit before and after the lookup table, which has additional hardware overhead. And when the accuracy of the lookup table is required to be high, the number of entries and selection logic of the LUT lookup table unit will increase significantly. Summary of the invention

[0003] The purpose of the present invention is to provide a method and circuit design for table lookup and interpolation using complement code. The present invention mainly uses a 2-bit interpolation and table lookup tightly coupled mode, which can greatly compress the lookup table entries compared with the traditional table lookup. For the table lookup function with odd function or even function properties, the table entries can be compressed to 1 / 8 of the original at most.

[0004] To achieve the above-mentioned object of the invention, the present invention discloses a table lookup interpolation circuit, comprising:

[0005] lut search module, 3 general multiplexers, left shift module, 3-2 missing 1 adder compressor and fixed-point adder, among which,

[0006] The LUT lookup module generates two nbit output values ​​according to the nbit input address index ,in They are the current item value and the next item value of the lookup table item respectively;

[0007] The three general multiplexers are respectively connected to the lut search module, and the three multiplexers are configured with different selection logic signals sel for selection;

[0008] The left shift module is connected to one of the three universal multiplexers, and the universal multiplexer connected is a selector equipped with {X}[1] and a sign bit S XOR to generate a selection logic signal sel, which is used to shift the input value left by one bit, where {X}[1] represents a 2-bit interpolation bit The second item;

[0009] The 3-2 missing 1 adder compressor is connected to the left shift module and the other two of the three universal multiplexers. In a complement operation environment, the sum of the two output values ​​of the 3-2 missing 1 adder compressor is 1 less than the sum of the three input values.

[0010] The fixed-point adder is connected to the 3-2 missing 1 adder compressor and is a standard (n+2)-bit fixed-point adder.

[0011] The number of search index bits in the compressor circuit is n, which can be extended to any number of bits. Through configuration, the table lookup function can be extended to any function such as exponential, logarithmic, square root and other operations. However, the table lookup items can be further saved only when the table lookup function has the property of an odd function or an even function. When the table lookup number does not have the property of a complement code, the table lookup device can also be used. However, this will not save table lookup items. The present invention is applied to the implementation of a large-scale integrated circuit operation circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a search and interpolation circuit implementation diagram provided in one embodiment of the present invention;

[0013] Figure 2 This is an IO interface diagram of a single-bit 3-2 missing 1 compressor provided in one embodiment of the present disclosure;

[0014] Figure 3 is a circuit implementation diagram of a single-bit 3-2 missing-1 addition compressor CU1 provided in one embodiment of the present disclosure;

[0015] Figure 4 is a circuit implementation diagram of a multi-bit 3-2 missing 1 addition compressor provided in one embodiment of the present disclosure;

[0016] Figure 5 is a reciprocal lookup table and its interpolation relationship function diagram provided in one embodiment of the present disclosure;

[0017] Figure 6 is a circuit diagram of a LUT lookup table module provided in one embodiment of the present disclosure;

[0018] Figure 7 is a design idea diagram of an interpolation circuit provided in one embodiment of the present disclosure;

[0019] Figure 8 is a circuit diagram of an inplt interpolation module provided in one embodiment of the present disclosure;

[0020] Fig. 9 It is a fixed-floating-point mixed operation unit diagram provided in one embodiment of the present disclosure. DETAILED DESCRIPTION

[0021] The following is combined with Figures 1 to 9The embodiments of the present invention are described in detail. It should be clear that the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0022] Those skilled in the art should know that the following specific embodiments or specific implementations are a series of optimized settings listed by the present invention to further explain the specific content of the invention, and these settings can be combined or used in association with each other, unless the present invention clearly states that some or a specific embodiment or implementation cannot be associated or used together with other embodiments or implementations. At the same time, the following specific embodiments or implementations are only used as the most optimized settings, and are not to be understood as limiting the scope of protection of the present invention.

[0023] See also Figure 1 In one embodiment, the present invention discloses a table lookup interpolation circuit, comprising a LUT lookup module, 3 universal multiplexers, a left shift module, a 3-2 missing 1 adder compressor and a fixed-point adder, characterized in that,

[0024] The LUT lookup module generates two nbit output values ​​according to the nbit input address index ,in They are the current item value and the next item value of the lookup table item respectively;

[0025] The three general multiplexers are respectively connected to the lut search module, and the three multiplexers are configured with different selection logic signals sel for selection;

[0026] The left shift module is connected to one of the three universal multiplexers, and the universal multiplexer connected is a selector equipped with {X}[1] and a sign bit S XOR to generate a selection logic signal sel, which is used to shift the input value left by one bit, where {X}[1] represents a 2-bit interpolation bit The second item;

[0027] The 3-2 missing 1 adder compressor is connected to the left shift module and the other two of the three universal multiplexers. In a complement operation environment, the sum of the two output values ​​of the 3-2 missing 1 adder compressor is 1 less than the sum of the three input values.

[0028] The fixed-point adder is connected to the 3-2 missing 1 adder compressor and is a standard (n+2)-bit fixed-point adder.

[0029] In this embodiment, in the table lookup interpolation circuit, a 1-bit sign bit can be used. As control, nbit is used for lut table lookup, and 2bit is used for inplt interpolation. For table lookup functions with odd and even function properties, Compared with direct table lookup, the table entries can be compressed to 1 / 8 of the original.

[0030] The multiplexers can also be configured to have more than 3. The three multiplexers (mux) are configured with different selection logic (sel) signals and select according to the 2-bit interpolation number ({X}[0], {X}[1]) and S.

[0031] In another embodiment, the 3-2 missing 1 adder compressor is either a single-bit 3-2 missing 1 adder compressor or a multi-bit 3-2 missing 1 adder compressor obtained by connecting single-bit 3-2 missing 1 adder compressors in parallel.

[0032] For this embodiment, Figure 1 The "3-2(L1)" module in the example is a custom 3-2 missing 1 adder compressor that can quickly convert the addition of 3 numbers into the addition of 2 numbers. The "L1" in the brackets means missing 1, which means that the addition result of the 2 numbers output by this adder compressor will be fixedly 1 less than the addition result of the 3 numbers input.

[0033] The 3-2 missing 1 addition compressor of the present invention has a similar structure to the standard 4-2 addition compressor. In addition, the multi-bit compressor is composed of multiple identical single-bit compressors connected in parallel, and the design has excellent scalability.

[0034] In the two's complement operation, if an n-bit operation is performed, the fixed default 1 is equivalent to adding a number that is all ones. So the output range of a single-bit 3-2 missing 1 addition compressor is from [ 3:0] The change has arrived [4:1] , it is not possible to use 2 bits to output the result like the standard 3-2 compressor. The single-bit 3-2 missing 1 addition compressor has a similar structure to the standard 4-2 compressor, using 3 bits for output, and each single bit has a carry and .

[0035] In another embodiment, the input of the single-bit 3-2 missing 1 adder compressor is three addends and carry term , the output is two summands , carry term .

[0036] In this embodiment, if Figure 2As shown, the single-bit 3-2 missing 1 compressor is referred to as "CU1".

[0037] In another embodiment, the algebraic relationship between the output and input of the single-bit 3-2 missing 1 addition compressor satisfies

[0038]

[0039] For this embodiment, a truth table satisfying formula (1) is designed, namely Table 1, and simplified and corrected:

[0040]

[0041] Table 1

[0042] Table 1 will be formulated and Do decoupling and achieve and The logic expression generated according to Table 1 can achieve the smallest circuit area, but not necessarily the fastest speed.

[0043] According to Table 1, the Karnaugh map is simplified and the resulting logical expression is:

[0044]

[0045] Therefore, according to formula (2), the internal circuit implementation logic of the single-bit 3-2 missing 1 addition compressor CU1 can be obtained as follows: Figure 3 As shown. Figure 3 In and Decoupling can be done when When needed, the upper level Just generated.

[0046] By connecting multiple single-bit 3-2 missing 1 adder compressors in parallel, an n-bit 3-2 missing 1 adder compressor can be obtained. The circuit implementation of the parallel connection is as follows: Figure 4 As shown. For the nbit operation implemented in this example, Figure 4 The right part of the middle dashed line can be directly discarded, because we can estimate the range of the table lookup result and know in advance that it will not overflow. If this nbit3-2 missing 1 adder compressor is used for other purposes, such as calculating If the bitwise OR overflow is detected, the left part can be used.

[0047] In another embodiment, and Decouple the design so that the carry of the next item does not have to depend on the calculation result of the previous item.

[0048] As far as this embodiment is concerned, the design redundancy of the compressor can be used during design. and By decoupling the design, the carry of the next item does not have to depend on the calculation result of the previous item, thus achieving true parallel compression operation.

[0049] In another embodiment, the table lookup function in the LUT lookup module is an even function or an odd function.

[0050] As far as this embodiment is concerned, in this circuit, the lut table lookup module is tightly coupled with the inplt interpolation module, and the table lookup function is specially formulated for even functions or odd functions, which can significantly compress the number of items in the lookup table.

[0051] In another embodiment, when the input is a complement code, the input of the LUT search module is the bitwise XOR value of the sign bit S and the nbit addressing part [X] of the number to be looked up in the table, and the output is the two adjacent items found in the lookup table, represented by variables A and B respectively.

[0052] In terms of this embodiment, the present principle derivation takes an inverse proportional function with an odd function as an example to derive a circuit design that should be satisfied by the two's complement 2-bit interpolation.

[0053] The design features are: the input is required to be a complement code, and the positive and negative numbers can be used for collaborative lookup. In this example, the 8-bit LUT is used to achieve a lookup value with a precision close to 11 bits, which can compress the lookup table entries to 1 / 8 of the original.

[0054] Input: (n+3) bits of table number to be looked up .

[0055] The output is: two-item lookup table output number and . are both nbit numbers, The corresponding lookup table current item and next item.

[0056] The principle of the positive and negative multiplexing table of the complement code is derived as follows:

[0057] In this embodiment, LUT uses an inverse proportional reciprocal lookup table, and the interpolation method is proportional linear interpolation. The calculation is performed on the high (n+3) bits of the valid bits. The 1-bit sign bit is used As a control, nbit is used for LUT table lookup, and 2bit is used for INPLT interpolation. Taking the inverse proportional function as an example, the lookup function and its interpolation relationship are reflected on the coordinate axis as follows Figure 5 shown.

[0058] Figure 5 The two curves in the figure are inverse proportional functions. The lookup table implements the Obtain Here, The value of is determined by the sign bit and the nbit lookup table value. Represents a decimal less than 1, whose value is the value represented by the 2-bit interpolated binary number divided by ,Right now .

[0059] Scaled linear interpolation function It can be expressed as:

[0060]

[0061] Exact value of the inverse proportional function exist Figure 5 The position of point A in the graph is obtained by linear interpolation of the scale. At point B. This type of interpolation will produce system error.

[0062] To implement the interpolation process shown in formula (3), two multipliers and one adder are required. In this way, the interpolation calculation cannot be completed within one cycle. However, the symmetry of the inverse proportional function can be used to compress the number of lookup table entries.

[0063] The following is a derivation of the simplification principle of the lookup table and interpolation module. In order to obtain universality, the digit specification in this example is abandoned and the derivation is based on Bit complement input, use Bit integer lookup table, The scenario of interpolation of decimal places.

[0064] First, the agreement is: All bits are The binary number is defined as , . Indicates a Bit binary number, using express The truth value in decimal.

[0065] According to the complement property, the opposite operation is defined as:

[0066]

[0067] Note that when doing complement or negation operations, the number of bits of the data must be considered. The complement operation is a modulo remainder operation. Only when the number of bits of the operation is unified as n bits, the number in formula (4) Only then can it be considered .

[0068] The bitwise negation operation is defined as:

[0069]

[0070] [ X ] Indicates taking Integer digits, Indicates taking Decimal places. [ X ] t Indicates taking from a high position of Number of digits; Take from low of digits. Binary number Add a floating point to make it have bit integer, decimal places, get :

[0071]

[0072] when When it is considered to be a positive number (the highest bit is 0), the interpolation can be directly performed by looking up the table according to formula (3):

[0073]

[0074] The last one can be transformed:

[0075]

[0076] Because it is calculate, According to formula (8), the result of formula (7) can be rewritten as:

[0077]

[0078] when When it is larger, the last digit can be omitted Operations are performed to reduce hardware overhead and the simplified formula (9) is:

[0079]

[0080] The positive number lookup table error using equation (10) is:

[0081]

[0082] according to Figure 5As shown, the inverse proportional function is concave on the positive semi-axis, and the interpolated point B is above the exact value point A, which will produce a positive system error. This system error will offset the negative error generated by equation (11). When is larger, the calculation accuracy may be higher using formula (10).

[0083] According to the symmetry of the inverse proportional function, when the input is a negative number, the positive number lookup table can be reused to compress the lookup table entries. When it is considered to be a negative number (the highest bit is 1), use the standard method and first find Opposite number:

[0084]

[0085] Then, similarly to formula (6), Add a floating point to make it have bit integer

[0086]

[0087] like , there will be no forward The carry of the bit. Equation (13) can be rewritten as:

[0088]

[0089] at this time and are all considered to be positive numbers. According to formula (3), the positive interpolation table is used, and the result is:

[0090]

[0091] Simplify the last term:

[0092]

[0093] According to formula (16), formula (15) is simplified and the standard interpolation result is rewritten as:

[0094]

[0095] like ,but It still satisfies equation (17) and no classification discussion is needed. Similar to the positive interpolation method, when When it is larger, decimal places are omitted. The rough result is:

[0096]

[0097] The negative number lookup table error is:

[0098]

[0099] However, the result obtained by formula (17) or formula (18) is a positive number, and it is necessary to take the opposite number to get the final result. The final result should be or In other words, when performing negative number interpolation by using the method of multiplexing the positive number lookup table, a calculation circuit for negating the result and adding one needs to be added at the end of the interpolation module.

[0100] The above is the derivation of the principle of the complement code multiplexing lookup table.

[0101] According to the above derivation, the input of the inplt interpolation module is , the output is the two adjacent items found in the lookup table, and the variables A and B represent these two items respectively. When is considered to be a positive number, let , ;when When it is considered to be a negative number, let , . Figure 6 The circuit shown can realize the above functions.

[0102] Figure 6 Where S represents the sign bit; [X] represents the n-bit binary lookup table part. Their meanings and relationships are shown in Table 2. Figure 6 Can look up the table based on the input and output the corresponding item of the input value and next .

[0103]

[0104] Table 2

[0105] In another embodiment, when the input is a complement code, the universal multiplexer selects as the output value.

[0106] In this embodiment, the Intplt interpolation module combines the inverse values ​​of two adjacent points output by the lookup table and interpolates according to the weights of the input values ​​close to the two points, thereby obtaining the precise value of the interpolation of the lookup table function.

[0107] Input: Output of Lut lookup module ; Sign bit ; Interpolation mantissa X [1:0] ;

[0108] Output: The output result is the n+3bit interpolation value of the table .

[0109] The 2-bit complement interpolation principle is derived as follows:

[0110] According to the exact derivation of formula (9) (17) or the simplified formula (10) (18), two multipliers and one adder are still needed. Next, the interpolation process is further simplified according to the specific decimal interpolation digits, and the intplt interpolation module is designed.

[0111] According to Figure 5 Description, this interpolation module plans to use 2-bit decimals for interpolation, that is At this time, the decimal place If the value is small, using equations (10) and (18) will produce large errors. Therefore, the relationship between equations (9) and (17) is used to further simplify the relationship.

[0112] according to Figure 6 The output of the lut module in When is considered to be a positive number, let , Substituting into specific decimal places, formula (9) is rewritten as:

[0113]

[0114] At the same time, when When it is considered to be a negative number, let , . Rewrite formula (17) as:

[0115]

[0116] Among them, the combination , there are only 4 cases. So it was decided to use an adder compressor and an adder instead of a multiplier. The prototype of the interpolation circuit is shown in the figure. Figure 7 shown.

[0117] like Figure 7 The design idea is to convert the multiplication in the formulas (20) and (21) into multiple additions of terms and coefficients selected by the multiplexer mux. After the multiplication is converted into addition, a 3-2 adder compressor is used for fast compression, and finally the results are added together.

[0118] Figure 7 The mux selection signal in It is based on the 2-bit interpolation bit and sign bit The judgment logic should satisfy the common expression of formula (20) and (21). The conditions that should be satisfied are listed, and the truth table is shown in Table 3. Now summarize the Figure 7 The hardware logic provided satisfies formulas (20) and (21) Select the truth table. The control circuit derivation of mux is shown in Table 3:

[0119]

[0120] Table 3

[0121] Because Figure 7 The mux selection form shown has design redundancy, that is, there are multiple truth tables that satisfy equations (20) and (21). Table 3 is only one of the designs that satisfy equations (20) and (21). After analysis, it is the one that is most conducive to simplifying the mux selection mode. The formula expression of the selection signal of the three muxes is shown in the summary column at the end of Table 3.

[0122] It should be noted here that formula (17) uses the positive Lut table for the complement negative number, and the result is the lookup table result of the opposite number corresponding to the negative number. When the table function is an even function, it can be used directly, but the inverse proportional function used to find the reciprocal table here is an odd function, so It is necessary to add the inversion operation to the result of formula (17).

[0123] We don't want to Figure 7 We decided to change the front-end design to solve this problem. According to the operation rules of the complement code, using the expressions of formula (4) and formula (5), the result is The negation operation of can be transformed into formula (22):

[0124]

[0125] Analysis of the error points in the derivation: The negation operation here cannot be advanced to the end of the adder, attempting to use the carry item of the adder To achieve the purpose of adding one. If the last step of the adder performs the operation , then negating in advance will lead to the following derivation:

[0126]

[0127] That is to say , borrowing the carry bit of the adder The result is still off by one, which is a waste of effort. In order to solve the problem that adding an add-one module consumes extra resources, the standard 3-2 additive compressor is replaced with a custom 3-2 missing-one additive compressor using the form of formula (22). When the back-end adder The carry is filled with 1, and the end result is not negated; when When the back-end adder The carry is filled with 0 and the end result is inverted.

[0128] Therefore, according to the formula summary in the last column of Table 3 and the negative strategy of the result of formula (22), we can improve Figure 7 The design idea shown in the figure adds the control item of mux and replaces the custom 3-2 missing 1 adder compressor, and finally obtains the circuit design that can satisfy both equations (9) and (17) as shown in the figure. Figure 8 shown.

[0129] In the figure, for Figure 6 The output of lut module; for The highest bit is the sign bit; {X}[0] and {X}[1] represent The first and second items of . mux is a multiplexer, and its sel selection logic is designed by matching the coefficients according to the method in Table 2; "<<1" means shifting the data left by one bit; "3-2 (L1)" is a custom 3-2 missing 1 adder compressor; the plus sign "+" at the end indicates a 10-bit fixed-point adder.

[0130] In another embodiment, the circuit is used for fixed-point table lookup interpolation.

[0131] In this embodiment, the circuit of the present invention can be used for table lookup interpolation solution in a fixed-point environment. The specific operation is to determine the configuration of the device according to the requirements. The prerequisites that need to be determined are:

[0132] 1) Is the fixed-point number unsigned or two's complement?

[0133] 2) Use fixed point numbers to find the number of bits

[0134] 3) Check whether the table function has the properties of an odd function or an even function

[0135] Assume that the fixed-point number of the table to be looked up is n bits, and n>3

[0136] Steps:

[0137] S100: Determine the table lookup function and its properties, configure the LUT table lookup value and the corresponding index. If the table lookup function has an odd function or an even function property, LUT needs to configure the table entry corresponding to the n-3bit index. Otherwise, LUT needs to configure the table entry corresponding to the n-2bit index.

[0138] S200: Configure the device input. If the number to be looked up is unsigned or the lookup function is not an odd function, configure the sign bit input S=0. Otherwise, configure the sign bit of the fixed-point number to S. Configure the lower 2 bits of the fixed-point number as the interpolation control number. X [1:0] . Configure the number of points to be checked excluding the lower 2 bits and the sign bit as the table lookup number [ X ] . Table lookup number [ X ] The bit width should be consistent with the bit width of the LUT table entry index.

[0139] S300: Circuit operation, after the result is stable, the table lookup value lut_out is obtained.

[0140] In another embodiment, the circuit is used for table lookup interpolation of fixed-point and floating-point mixed precision operations.

[0141] In this embodiment, the fixed-floating point mixed precision computing device is designed to reuse fixed-point resources as much as possible for floating-point computing. The coarse-grained regularization method is used to improve the computing speed and save hardware resource consumption and computing power consumption at the cost of sacrificing a small amount of floating-point precision.

[0142] There are various designs of fixed-floating point mixed precision computing devices. When the mixed precision device has a circuit that approximates standard floating point numbers to complement codes or uses special types of floating point numbers with complement code computing properties, the complement code lookup table interpolation device of the present invention can be used to meet the table interpolation requirements.

[0143] The original intention of the present invention is to speed up table lookup operations and reduce resource overhead and power consumption. The fixed-floating point hybrid processing device allows floating point operations to reuse fixed-point resources, which is also the original intention of reducing resource overhead.

[0144] Fig. 9 The invention is a fixed-point and floating-point processing device. The lut_c and intplt modules below are the interpolation table lookup circuits of the invention. Fig. 9 The device distributes the table lookup and interpolation operations of the present invention to be executed in two clock cycles, so the present invention is represented in the form of two module blocks.

[0145] Steps:

[0146] S100: Configure a fixed-floating point mixed precision processing device to generate an input suitable for the present invention. The table lookup number preferably has a complement property, and the table lookup function preferably has an odd function and an even function property.

[0147] S200: Perform calculation according to the input to obtain the calculation result.

[0148] S300: Since a floating point number table lookup is performed, an exponent correction circuit matching the present invention is required to be provided outside the present invention to perform exponent correction.

[0149] S400: Combining the output table lookup interpolation number and the correction index to obtain a table lookup floating point number.

[0150] Although the embodiments of the present invention are described above in conjunction with the accompanying drawings, the present invention is not limited to the above specific embodiments and application fields, and the above specific embodiments are only illustrative and instructive, rather than restrictive. A person of ordinary skill in the art can also make many forms under the guidance of this specification and without departing from the scope of protection of the claims of the present invention, all of which belong to the protection of the present invention.

Claims

1. A table lookup interpolation circuit, comprising: lut search module, 3 general multiplexers, left shift module, 3-2 missing 1 adder compressor and fixed-point adder, among which, The LUT lookup module generates two nbit output values ​​according to the nbit input address index ,in They are the current item value and the next item value of the lookup table item respectively; The three general multiplexers are respectively connected to the lut search module, and the three multiplexers are configured with different selection logic signals sel for selection; The left shift module is connected to one of the three universal multiplexers, and the universal multiplexer connected is a selector equipped with {X}[1] and a sign bit S XOR to generate a selection logic signal sel, which is used to shift the input value left by one bit, where {X}[1] represents a 2-bit interpolation bit The second item; The 3-2 missing 1 adder compressor is connected to the left shift module and the other two of the three universal multiplexers. In a complement operation environment, the sum of the two output values ​​of the 3-2 missing 1 adder compressor is 1 less than the sum of the three input values. The fixed-point adder is connected to the 3-2 missing 1 adder compressor and is a standard (n+2)-bit fixed-point adder.

2. The circuit according to claim 1, wherein Preferably, the 3-2 missing 1 adder compressor is either a single-bit 3-2 missing 1 adder compressor or a multi-bit 3-2 missing 1 adder compressor obtained by connecting single-bit 3-2 missing 1 adder compressors in parallel.

3. The circuit according to claim 2, wherein: The input of the single-bit 3-2 missing 1 adder compressor is three addends and carry term , the output is two summands , carry term .

4. The circuit according to claim 3, wherein: The algebraic relationship between the output and input of the single-bit 3-2 missing 1 addition compressor satisfies: 。 5. The circuit according to claim 3, wherein: Will and Decouple the design so that the carry of the next item does not have to depend on the calculation result of the previous item.

6. The circuit according to claim 1, wherein: The table lookup function in the LUT lookup module is an even function or an odd function.

7. The circuit according to claim 1, when the input is a complement code, the input of the LUT search module is the value of the bitwise XOR of the sign bit S and the nbit addressing part [X] of the number to be looked up in the table, and the output is the two adjacent items found in the lookup table, represented by variables A and B respectively. The circuit according to claim 1 , wherein the circuit is used for fixed-point table lookup interpolation.

9. The circuit according to claim 1, wherein the circuit is used for table lookup interpolation of fixed-point and floating-point mixed precision operations.

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