Multi-processor data access control architecture and control method

Abstract

The embodiment of the invention discloses a multiprocessor data access control architecture and a control method, and relates to the technical field of computers. In the control architecture, a main processor and an accelerator access a shared cache memory, and a local cache memory is arranged in the main processor; the snoop filtering processing component stores the snoop label corresponding to the address in the local cache memory of the main processor; a shared tag is stored in the shared cache memory; the snoop filtering processing component receives the data access request of each accelerator, and queries a snoop tag and a shared tag according to the address of the current access memory of the accelerator; if the snoop tag is hit, the snoop filtering processing component sends a snoop request to the main processor; when the accelerator data access request is write operation, the main processor invalidates the data copy corresponding to the address of the current access memory in the local cache memory; dirty data and updated data of the accelerator are merged and written into a shared cache memory, and data consistency is guaranteed.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a data access control architecture and a control method for a multi-processor. Background Art

[0002] Heterogeneous many-core multiprocessor architecture is a design that integrates different types of processing units on the same chip. A multiprocessor usually includes a main processor and one or more accelerators. Heterogeneous many-core multiprocessor architecture can fully utilize the high-performance computing capabilities of accelerators to achieve parallel and fast computing. Therefore, heterogeneous many-core multiprocessor architecture is widely used in the fields of high-performance computing (HPC) and artificial intelligence (AI). It also plays an important role in scientific research in disciplines such as astronomy, physics, and biology.

[0003] In a heterogeneous multi-core multi-processor architecture, in addition to the main processor needing to access the main memory, other accelerators also need to read and write the main memory to obtain or temporarily store data during the calculation process. That is, the main processor and each accelerator can read or write to a single shared address. This access mechanism will cause the problem of cache data inconsistency in the heterogeneous multi-core multi-processor architecture.

[0004] For example, after the main processor has taken a copy of the data in the main memory, when the accelerator needs to update the data, the data cached by the main processor is out of date or invalid. Summary of the invention

[0005] The present invention provides a multi-processor data access control architecture and a control method to ensure consistency of data access in a heterogeneous multi-core multi-processor architecture.

[0006] According to one aspect of the present invention, a data access control architecture of a multiprocessor is provided, the data access control architecture of the multiprocessor comprising: a main processor, at least one accelerator, a main memory, and a snooping filter processing component, the main processor and the accelerator access a shared cache memory, and the main processor is provided with a local cache memory; wherein: The snoop filter processing component stores snooper tags corresponding to all memory addresses having copies stored in the local cache memory of the host processor; The shared cache memory stores shared tags corresponding to all memory addresses of which the host processor and / or accelerator has copies stored in the shared cache memory; The shared cache memory and the local cache memory are non-inclusive memories; The snoop filter processing component receives data access requests from each accelerator and queries the snoop tag and the shared tag according to the memory address currently accessed by the accelerator; If the snoop tag is hit, the snoop filter processing component sends a snoop request to the main processor; When the main processor determines that the data access request of the accelerator is a write operation according to the snoop request, the data copy corresponding to the memory address currently accessed by the accelerator in the local cache memory is invalidated; When the data of the main processor is dirty data, the dirty data is merged with the updated data of the accelerator and written into the shared cache memory.

[0007] According to another aspect of the present invention, a data access control method for a multiprocessor is provided. The data access control method for a multiprocessor is applied to a data access control architecture for a multiprocessor provided in any embodiment of the present invention. The data access control method for a multiprocessor comprises: Receive data access requests from each accelerator through a snoop filter processing component, and query the snoop tag and the shared tag according to the current memory address accessed by the accelerator; If the snooper tag is hit, a snoop request is sent to the main processor through the snoop filter processing component; When it is determined according to the snoop request that the data access request of the accelerator is a write operation, the data copy corresponding to the memory address currently accessed by the accelerator in the local cache memory is invalidated by the main processor; When the data in the main processor is dirty data, the dirty data is merged with the updated data of the accelerator and written into the shared cache memory.

[0008] According to another aspect of the present invention, a chip is provided, the chip comprising: a data access control architecture of a multi-processor provided by any embodiment of the present invention.

[0009] According to another aspect of the present invention, an electronic device is provided. The electronic device includes: a chip provided by any embodiment of the present invention.

[0010] The technical solution of the embodiment of the present invention is to set up a data access control architecture of a multi-processor including a main processor, at least one accelerator, a main memory, and a snooping filtering processing component, wherein the main processor and the accelerator access a shared cache memory, and the main processor is provided with a local cache memory; the snooping filtering processing component stores snooping tags corresponding to all memory addresses having copies stored in the local cache memory of the main processor; the shared cache memory stores shared tags corresponding to all memory addresses having copies stored in the shared cache memory by the main processor and / or the accelerator; the shared cache memory and the local cache memory are non-inclusive memories; the snooping filtering processing component receives data access requests from each accelerator, queries the snooping filtering processing component according to the memory address currently accessed by the accelerator, and checks the snooping filtering processing component for the data access request from each accelerator. tags and shared tags; if the snooper tag is hit, the snooping filter processing component sends a snooping request to the main processor; when the main processor determines that the data access request of the accelerator is a write operation according to the snooping request, the data copy corresponding to the memory address currently accessed by the accelerator in the local cache memory is invalidated; when the main processor data is dirty data, the dirty data is merged with the updated data of the accelerator and written into the shared cache memory, which solves the data inconsistency problem when multiple processors access data, especially solves the problem of data access inconsistency caused by the data in the main memory being taken away by the main processor and the accelerator needs to update the data. At this time, the data cached by the main processor is expired or invalid, which ensures that the main processor and the accelerator access data consistently, and improves the correctness and reliability of transaction processing.

[0011] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0013] Figure 1 It is a structural diagram of a data access control architecture of a multi-processor provided according to an embodiment of the present invention.

[0014] Figure 2 It is a structural diagram of another multi-processor data access control architecture provided according to an embodiment of the present invention.

[0015] Figure 3The present invention is a flowchart of a multi-processor data access control method provided in accordance with an embodiment of the present invention. DETAILED DESCRIPTION

[0016] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0017] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0018] Figure 1 1 is a schematic diagram of a data access control architecture of a multi-processor provided according to an embodiment of the present invention. This embodiment is applicable to the case of ensuring data access consistency in a heterogeneous multi-core multi-processor architecture. Figure 1 As shown, the data access control architecture of the multi-processor includes: a main processor, at least one accelerator, a main memory, and a snooping filter processing component, the main processor and the accelerator access a shared cache memory, and the main processor is provided with a local cache memory. The main processor and the accelerator can also access the main memory.

[0019] In the embodiment of the present invention, a high-speed cache memory may not be provided in the accelerator. Alternatively, a high-speed cache memory may be provided in the accelerator, but its data consistency is not maintained by a hardware structure but by software.

[0020] The cache memory may be a level 1 cache (L1 Cache), a level 2 cache (L2 Cache) and a level 3 cache (L3 Cache). In an application scenario of an embodiment of the present invention, L1 Cache and L2 Cache may be set in a main processor.

[0021] The snoop filter processing component stores snoop tags corresponding to all memory addresses with copies stored in the host processor's local cache memory. The shared cache memory stores shared tags corresponding to all memory addresses with copies stored in the shared cache memory by the host processor and / or accelerator.

[0022] In combination with the specific processing method in the data access control architecture of the multiprocessor provided in the embodiment of the present invention, only the tag value of the address is stored in the snooping filter processing component and the shared cache memory to ensure data access consistency. In the snooping filter processing component and the shared cache memory, there is no need to store information such as cache line status information and transaction processing source identification. The information that needs to be stored in the snooping filter processing component and the shared cache memory can be simplified, greatly reducing hardware overhead.

[0023] In the embodiment of the present invention, the shared cache memory and the local cache memory are non-inclusive memories. That is, the data corresponding to the storage address stored in the local cache memory is not stored in the shared cache memory. The data corresponding to the storage address stored in the shared cache memory is not stored in the local cache memory.

[0024] When the accelerator needs to access data, it can first send a data access request to the snooping filter processing component. The snooping filter processing component receives the data access requests of each accelerator, and queries the snooping tag and the shared tag according to the memory address currently accessed by the accelerator. If the snooping tag is hit, the snooping filter processing component sends a snooping request to the main processor. When the main processor determines that the data access request of the accelerator is a write operation based on the snooping request, the data copy corresponding to the memory address currently accessed by the accelerator in the local cache memory is invalidated. When the main processor data is dirty data, the dirty data is merged with the updated data of the accelerator and written into the shared cache memory.

[0025] Among them, when the memory address currently accessed by the accelerator hits the snooper tag, it indicates that the main processor has taken the data copy from the main memory and saved it in the local cache memory of the main processor. At this time, when the accelerator needs to write the data at the memory address, the data in the local cache memory of the main processor is expired data. Therefore, in an embodiment of the present invention, when the main processor determines that the data access request of the accelerator is a write operation according to the snooping request, the data copy corresponding to the memory address currently accessed by the accelerator in the local cache memory is invalidated, thereby avoiding the main processor from processing expired data, resulting in inconsistent data between the main processor and the accelerator.

[0026] In the local cache memory of the main processor, the data may be dirty or clean. Dirty data is data that is inconsistent with the corresponding data in the main memory, that is, the main processor has updated the data at this address. Clean data is data that is consistent with the corresponding data in the main memory, that is, the main processor has not updated the data at this address. In order to ensure data consistency, when the data in the main processor is dirty, a copy of the dirty data is returned, and the dirty data is merged with the updated data of the accelerator and written to the shared cache memory, so that the main processor can continue to process the data consistently. When the data in the main processor is clean, the accelerator updates the data in the main memory.

[0027] By returning the dirty data and merging it with the part of the data that the accelerator wants to update, and then storing it in the shared cache memory, the network pressure and performance loss caused by reading and writing the main memory can be reduced. When the data in the main processor is clean data, the data copy does not need to be returned, and the accelerator can directly update the data in the main memory. At this time, the data copy in the local cache memory of the main processor has been deleted, thereby ensuring data consistency. The above operation solves the problem of inconsistent data access caused by the data in the main memory being updated by another accelerator after the main processor has taken away the copy, and the data in the main processor cache is expired or invalid.

[0028] In an embodiment of the present invention, when the main processor determines that the data access request of the accelerator is a read operation according to the snoop request, it returns the data copy corresponding to the memory address currently accessed by the accelerator in the local cache memory and keeps the data copy valid.

[0029] Among them, when the memory address currently accessed by the accelerator hits the snooper tag, it indicates that the main processor has taken a copy of the data in the main memory and saved it in the local cache memory of the main processor. At this time, when the accelerator needs to perform a read operation on the memory address data, the main memory will no longer contain the latest data. Therefore, when the accelerator reads the data corresponding to the memory address in the main memory, it will obtain expired data. In an embodiment of the present invention, the main processor returns a copy of the data corresponding to the memory address currently accessed by the accelerator in the local cache memory, which can solve the problem of the accelerator obtaining expired data in the main memory and ensure the consistency of data access.

[0030] In the embodiment of the present invention, if the shared tag hits, the data access request of the accelerator is processed in the shared cache memory; if the snooper tag and the shared tag are not hit, the data access request of the accelerator is processed in the main memory.

[0031] By storing a snooper tag in a snooping filter processing component and storing a shared tag in a shared cache memory; when an accelerator needs to access data, the memory address currently accessed by the accelerator is compared with the snooper tag and the shared tag; and the memory accessed by the accelerator data is determined according to the hit situation, the problem of inconsistent data access caused by the data in the main memory being updated by another accelerator after the main processor has taken away a copy, and the data in the main processor cache is expired or invalid at this time, can be solved; and the problem of inconsistent data access caused by the main memory no longer containing the latest data when a copy of data is taken away from the main memory and stored in the local cache memory of the main processor when the accelerator needs to perform a read operation on the memory address data can be solved.

[0032] By storing the snooper tag in the snoop filter processing component and storing the shared tag in the shared cache memory, the storage information can be simplified, and there is no need to store cache line status information and transaction processing source identifiers, thereby reducing hardware overhead. When the accelerator is performing a write operation and the main processor returns dirty data, data is written to the shared cache memory instead of being written back to the main memory, which alleviates the transmission pressure on the system bus and network, and can also reduce the impact of consistency operations on the main memory performance.

[0033] Based on the above implementation, optionally, when the main processor receives a data access request to the main processor, it queries the shared tag in the shared cache memory according to the current access memory address of the main processor to determine whether it hits; if the current access memory address of the main processor hits the shared tag, the data of the main processor is accessed in the shared cache memory; otherwise, the data of the main processor is accessed through the main memory. Through this processing, the problem of inconsistent data access caused by the accelerator having taken away the data copy and accessing the data through the shared cache memory, and the main processor also needs to access the data at the address, can be solved.

[0034] Figure 2 FIG. 1 is a schematic diagram of a structure of a data access control architecture of a multiprocessor provided according to an embodiment of the present invention. Figure 2 As shown, the structure of the data access control architecture of the multi-processor includes a main processor, at least one accelerator, a main memory, and a snooping filter processing component; the main processor and the accelerator access a shared cache memory, and the main processor is provided with a local cache memory ( Figure 2The snoop filter processing component stores snoop tags corresponding to all memory addresses where copies are stored in the local cache memory of the main processor. The shared cache memory stores shared tags corresponding to all memory addresses where copies are stored in the shared cache memory of the main processor and / or the accelerator. The shared cache memory and the local cache memory are non-inclusive memories. The cache memory may not be set in the accelerator. Alternatively, the cache memory may be set in the accelerator, but its data consistency is not maintained by the hardware structure, but by software.

[0035] like Figure 2 As shown, optionally, the data access control architecture of the multiprocessor further includes: a consistency processing component; a snoop filter processing component, including: a pre-filter controller, a post-filter controller, a snoop filter controller, a snoop filter array, and a snoop request processing component. The snoop filter array stores snoop tags corresponding to all memory addresses that have copies stored in the local cache memory of the main processor.

[0036] Optionally, the main processor includes: a main processor request processing unit. The data access control architecture of the multi-processor also includes: a main memory access network and a main memory access controller.

[0037] In a specific implementation, when the main processor receives a data access request to the main processor, the main processor transmits the current access memory address of the main processor to the consistency processing component through the main processor request processing component; the consistency processing component queries the shared tag in the shared cache memory to determine whether it hits; if the current access memory address of the main processor hits the shared tag, data access to the main processor is performed in the shared cache memory; otherwise, the consistency processing component accesses the main memory access network through the main memory access controller, and accesses data to the main processor in the main memory.

[0038] Optionally, the pre-filter controller receives data access requests from each accelerator and sends the data access requests from each accelerator to a consistency processing component; the consistency processing component queries the snoop filter controller for a snoop tag stored in the snoop filter array and a shared tag in a shared cache memory according to the accelerator's current access memory address; when the consistency processing component determines that the accelerator's current access memory address hits the snoop tag, the hit information is sent to the snoop request processing component; the snoop request processing component sends a snoop request to the main processor.

[0039] Optionally, when the main processor determines that the data access request of the accelerator is a write operation according to the snoop request, the data copy corresponding to the memory address currently accessed by the accelerator in the local cache memory is invalidated; the main processor returns the corresponding dirty data to the consistency processing component through the snoop request processing component; the consistency processing component obtains the update data of the accelerator transmitted by the accelerator through the pre-filter controller, and merges the dirty data with the update data, and writes the merged result into the shared cache memory. When the data access request of the accelerator is a write operation and the main processor has clean data, a reply response is made through the snoop request processing component, and the reply response does not contain data; the snoop request processing component transmits the reply response to the consistency processing component; the consistency processing component accesses the main memory access network through the main memory access controller, and executes the update data write operation in the accelerator data access request in the main memory.

[0040] When the main processor determines that the data access request of the accelerator is a read operation based on the snoop request, the data copy corresponding to the memory address currently accessed by the accelerator in the local cache memory is returned to the shared cache memory through the snoop request processing component and the consistency processing component, so that the accelerator can read the data and keep the data copy in the local cache memory valid.

[0041] When determining that the memory address currently accessed by the accelerator misses the snooper tag and the shared tag, the consistency processing component sends the miss information to the post-filtering controller; the post-filtering controller accesses the main memory access network and processes the data access request of the accelerator in the main memory.

[0042] Through the above-mentioned multi-processor data access control architecture and hardware data access consistency maintenance, while simplifying the snooping filter processing components and the shared cache memory storage information and reducing hardware overhead, when the storage entries are cleared actively by the consistency operation rather than the main processor, the storage entries that need to be cleared can be stored in the shared cache memory instead of being written back to the main memory, thereby alleviating the transmission pressure of the system bus and the network, and also reducing the impact of the consistency operation on the main memory performance.

[0043] In addition, by Figure 2In the data access control architecture of the multi-processor shown, a first interface formed by a main memory access controller and a main memory access network, and a second interface formed by a post-filter controller and a main memory access network are provided, which can divert the access to the main memory, relieve the transmission pressure of the system bus and the network, and reduce the impact of consistency operations on the performance of the main processor core. Among them, the first interface can be used for read and write access of the main processor, and read and write access forwarding when the snoop command cannot obtain valid data. The second interface can be used for read and write operations from an accelerator, and the accessed memory address does not hit the tag in the snoop filtering processing component and the shared cache memory, which can filter out useless address accesses and reduce the impact of the accelerator's read and write data on the performance of the main processor.

[0044] Based on the above implementation, when the snooper tags stored in the snoop filter array reach the upper limit, the storage tags can be removed, such as using a first-in-first-out method to evict the victim entry, and sending an invalidation request to the main processor, and the data copy in the local cache memory of the main processor can be invalidated. The invalidated data copy can be taken out from the local cache memory of the main processor and stored in the shared cache memory. By writing the cleared entries into the shared cache memory instead of writing them back to the main memory, the transmission pressure on the system bus and network can be relieved, and the impact of consistency operations on the performance of the main memory can be reduced.

[0045] In such Figure 2 The data access control architecture of the multiprocessor shown may also include a shared high-speed cache memory controller. The shared high-speed cache memory controller is used to control the shared high-speed cache memory.

[0046] The technical solution of this embodiment is to store snoop tags corresponding to all memory addresses having copies stored in the local cache memory of the main processor in the snoop filtering processing component; store shared tags corresponding to all memory addresses having copies stored in the shared cache memory of the main processor and / or the accelerator in the shared cache memory in the shared cache memory; the shared cache memory and the local cache memory are non-inclusive memories; the shared cache memory and the local cache memory are non-inclusive memories; if the snoop tag is hit, the snoop filtering processing component sends a snoop request to the main processor; when the main processor determines that the data access request of the accelerator is a write operation according to the snoop request, the data copy corresponding to the current memory address accessed by the accelerator in the local cache memory is invalidated; when the data of the main processor is dirty data, the dirty data is merged with the updated data of the accelerator and written into the shared cache memory; when the data in the main processor is clean data, the accelerator updates the data in the main memory; the main processor determines that the data access request of the accelerator is a write operation according to the snoop request When it is determined that the data access request of the accelerator is a read operation, the data copy corresponding to the memory address currently accessed by the accelerator in the local cache memory is returned, and the data copy is kept valid; if the shared tag is hit, the data access request of the accelerator is processed in the shared cache memory; if the snooper tag and the shared tag are not hit, the data access request of the accelerator is processed in the main memory, which solves the problem that the data in the main memory is updated by another accelerator after the main processor has taken away the copy, and the data in the main processor cache will be expired or invalid at this time; and the main processor writes the copy in its cache, at this time the main memory will no longer contain the latest data, if the accelerator reads the same address in the main memory at this time, it will see expired data, the problem of inconsistent access of the two data can be achieved on the basis of simplifying the storage information and reducing the hardware overhead, and the data access consistency can be achieved, and the transmission pressure of the system bus and the network can be alleviated, and the impact of the consistency operation on the performance of the main processor core can also be reduced.

[0047] Figure 3 1 is a flow chart of a data access control method for a multiprocessor provided according to an embodiment of the present invention. The data access control method for a multiprocessor is applied to a data access control architecture for a multiprocessor provided in any embodiment of the present invention. Figure 3 As shown, the data access control method of the multiprocessor includes: Step 310: Receive data access requests from each accelerator through the snoop filter processing component, and query the snoop tag and the shared tag according to the memory address currently accessed by the accelerator.

[0048] Specifically, the snoop filter processing component includes: a pre-filter controller, a post-filter controller, a snoop filter controller, a snoop filter array, and a snoop request processing component. The snoop filter array stores snoop tags corresponding to all memory addresses with copies stored in the local cache memory of the main processor.

[0049] Optionally, a snoop filter processing component receives data access requests from each accelerator, and queries snoop tags and shared tags based on the memory address currently accessed by the accelerator, including: receiving data access requests from each accelerator through a pre-filter controller, and sending the data access requests from each accelerator to a consistency processing component; and querying, through the consistency processing component, the snoop filter controller, based on the memory address currently accessed by the accelerator, the snoop tags stored in the snoop filter array, and the shared tags in the shared cache memory.

[0050] Depending on the specific situation, execute step 320, step 330 and step 340; or, execute step 320, step 330 and step 350; or, execute step 320 and step 360; or, execute step 370; or, execute step 380.

[0051] Step 320: If the snooper tag is hit, a snoop request is sent to the main processor through the snoop filter processing component.

[0052] Optionally, if the snoop tag is hit, a snoop request is sent to the main processor through the snoop filter processing component, including: when the consistency processing component determines that the accelerator's current access memory address hits the snoop tag, the hit information is sent to the snoop request processing component; and the snoop request is sent to the main processor through the snoop request processing component.

[0053] Step 330: When it is determined according to the snoop request that the data access request of the accelerator is a write operation, the main processor invalidates the data copy in the local cache memory corresponding to the memory address currently accessed by the accelerator.

[0054] Optionally, the main processor includes: a main processor request processing component.

[0055] Step 340: When the data in the main processor is dirty data, merge the dirty data with the update data of the accelerator and write them into the shared cache memory.

[0056] Optionally, when the data in the main processor is dirty data, the dirty data is merged with the update data of the accelerator and written into the shared cache memory, including: returning the corresponding dirty data to the consistency processing component through the snoop request processing component by the main processor; obtaining the update data of the accelerator transmitted by the accelerator through the pre-filtering controller through the consistency processing component, merging the dirty data with the update data, and writing the merged result into the shared cache memory.

[0057] Step 350: When the data in the main processor is clean data, update the data of the accelerator's data access in the main memory by snooping the filter processing component.

[0058] Optionally, when the data in the main processor is clean data, the data access of the accelerator in the main memory is updated through the snooping filtering processing component, including: when the data access request of the accelerator is a write operation and the data in the main processor is clean data, a reply response is performed through the snooping request processing component, and the reply response does not contain data; the reply response is transmitted to the consistency processing component through the snooping request processing component; and the main memory access network is accessed through the main memory access controller through the consistency processing component, and the update data write operation in the accelerator data access request is executed in the main memory.

[0059] Step 360: When it is determined according to the snoop request that the data access request of the accelerator is a read operation, the main processor returns the data copy corresponding to the memory address currently accessed by the accelerator in the local cache memory, and keeps the data copy valid.

[0060] Specifically, when it is determined based on the snoop request that the data access request of the accelerator is a read operation, the main processor returns the data copy in the local cache memory corresponding to the memory address currently accessed by the accelerator to the shared cache memory through the snoop request processing component and the consistency processing component, and keeps the data copy in the local cache memory of the main processor valid.

[0061] Step 370: If the shared tag is hit, the accelerator's data access request is processed in the shared cache memory.

[0062] Specifically, when the consistency processing component determines that the memory address currently accessed by the accelerator hits the shared tag, the hit information is sent to the shared cache memory controller, and the shared cache memory controller controls the accelerator's data access request processing in the shared cache memory.

[0063] Step 380: If the snooper tag and the shared tag are not hit, the accelerator's data access request is processed in the main memory.

[0064] Optionally, if the snooper tag and the shared tag are missed, the data access request processing of the accelerator is performed in the main memory, including: when it is determined through the consistency processing component that the accelerator's current access memory address misses the snooper tag and the shared tag, the miss information is sent to the post-filtering controller; accessing the main memory access network through the post-filtering controller, and performing the data access request processing of the accelerator in the main memory.

[0065] Before step 310, or after step 380, the process may further include: when a data access request to the main processor is received through the main processor, querying the shared tag in the shared cache memory according to the current access memory address of the main processor to determine whether it hits; if the current access memory address of the main processor hits the shared tag, accessing the data of the main processor in the shared cache memory; otherwise, accessing the data of the main processor through the main memory.

[0066] Specifically, when the main processor receives a data access request to the main processor, the main processor's current access memory address is transmitted to the consistency processing component through the main processor request processing component; the shared tag in the shared cache memory is queried through the consistency processing component to determine whether it hits; if the current access memory address of the main processor hits the shared tag, data access to the main processor is performed in the shared cache memory; otherwise, the consistency processing component accesses the main memory access network through the main memory access controller, and accesses data to the main processor in the main memory.

[0067] The multi-processor data access control method provided by the embodiment of the present invention can achieve the same beneficial effects as the multi-processor data access control architecture.

[0068] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0069] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A data access control architecture for a multiprocessor, characterized in that: The data access control architecture of the multiprocessor includes: a main processor, at least one accelerator, a main memory, and a snoop filtering processing component, the main processor and the accelerator access a shared cache memory, and the main processor is provided with a local cache memory; wherein: The snoop filter processing component stores snooper tags corresponding to all memory addresses having copies stored in the local cache memory of the master processor; The shared cache memory stores shared tags corresponding to all memory addresses of which the host processor and / or accelerator has copies stored in the shared cache memory; The shared cache memory and the local cache memory are non-inclusive memories; The snoop filter processing component receives data access requests from each accelerator and queries the snoop tag and the shared tag according to the memory address currently accessed by the accelerator; If the snoop tag is hit, the snoop filter processing component sends a snoop request to the main processor; When the main processor determines that the data access request of the accelerator is a write operation according to the snoop request, the data copy corresponding to the memory address currently accessed by the accelerator in the local cache memory is invalidated; When the data of the main processor is dirty data, the dirty data is merged with the updated data of the accelerator and written into the shared cache memory.

2. The multiprocessor data access control architecture according to claim 1, characterized in that: Also includes: When the main processor determines that the data access request of the accelerator is a read operation according to the snoop request, the main processor returns the data copy corresponding to the memory address currently accessed by the accelerator in the local cache memory and keeps the data copy valid.

3. The multiprocessor data access control architecture according to claim 1, characterized in that: Also includes: When the data in the main processor is clean data, the accelerator updates the data in the main memory.

4. The multiprocessor data access control architecture according to claim 1, characterized in that: Also includes: If the shared tag is hit, the data access request of the accelerator is processed in the shared cache memory; If the snooper tag and the shared tag are not hit, the data access request processing of the accelerator is performed in the main memory.

5. The multiprocessor data access control architecture according to claim 1, characterized in that: Also includes: When receiving a data access request to the main processor, the main processor queries the shared tag in the shared cache memory according to the current access memory address of the main processor to determine whether it hits; If the current access memory address of the main processor hits the shared tag, data access to the main processor is performed in the shared cache memory; otherwise, data access to the main processor is performed through the main memory.

6. The multiprocessor data access control architecture according to claim 1, characterized in that: The data access control architecture of the multiprocessor further includes: a consistency processing component; A snoop filtering processing component includes: a pre-filtering controller, a post-filtering controller, a snoop filter controller, a snoop filter array, and a snoop request processing component; wherein: The snoop filter array stores snoop tags corresponding to all memory addresses having copies stored in the local cache memory of the master processor; The pre-filter controller receives the data access request of each accelerator and sends the data access request of each accelerator to the consistency processing component; The consistency processing component queries the snoop tag stored by the snoop filter controller through the snoop filter array and the shared tag in the shared cache memory according to the memory address currently accessed by the accelerator; The consistency processing component sends hit information to the snoop request processing component when determining that the memory address currently accessed by the accelerator hits the snoop tag; The snoop request processing component sends a snoop request to the main processor.

7. The multiprocessor data access control architecture according to claim 6, characterized in that: The main processor includes: A main processor request processing unit; When the main processor determines that the data access request of the accelerator is a write operation according to the snoop request, the data copy corresponding to the memory address currently accessed by the accelerator in the local cache memory is invalidated; The main processor returns the corresponding dirty data to the consistency processing component through the snoop request processing component; The consistency processing component obtains the update data of the accelerator transmitted by the accelerator through the pre-filtering controller, merges the dirty data with the update data, and writes the merged result into the shared high-speed cache memory.

8. The multiprocessor data access control architecture according to claim 7, characterized in that: The data access control architecture of the multiprocessor also includes: a main memory access network; When the data access request of the accelerator is a write operation and the data in the main processor is clean, a reply response is made through the snoop request processing component, and the reply response does not contain data; The snoop request processing component transmits the reply response to the consistency processing component; The consistency processing component accesses the main memory access network through the main memory access controller, and executes the update data write operation in the accelerator data access request in the main memory; or, The consistency processing component sends miss information to the post-filtering controller when determining that the memory address currently accessed by the accelerator misses the snooper tag and the shared tag; After filtering, the controller accesses the main memory access network and processes the data access request of the accelerator in the main memory.

9. The multiprocessor data access control architecture according to claim 8, characterized in that: The data access control architecture of the multiprocessor further includes: a main memory access controller; When receiving a data access request to the main processor, the main processor transmits the current access memory address of the main processor to the consistency processing component through the main processor request processing component; The consistency processing component queries the shared tag in the shared cache memory to determine whether it hits; If the current access memory address of the main processor hits the shared tag, data access to the main processor is performed in the shared cache memory; Otherwise, the consistency processing component accesses the main memory access network through the main memory access controller, and performs data access to the main processor in the main memory.

10. A data access control method for a multiprocessor, characterized in that: The data access control method for a multiprocessor is applied to the data access control architecture for a multiprocessor as claimed in any one of claims 1 to 9, and the data access control method for a multiprocessor comprises: Receive data access requests from each accelerator through a snoop filter processing component, and query the snoop tag and the shared tag according to the current memory address accessed by the accelerator; If the snooper tag is hit, a snoop request is sent to the main processor through the snoop filter processing component; When it is determined according to the snoop request that the data access request of the accelerator is a write operation, the data copy corresponding to the memory address currently accessed by the accelerator in the local cache memory is invalidated by the main processor; When the data in the main processor is dirty data, the dirty data is merged with the updated data of the accelerator and written into the shared cache memory.

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