A data playback control method and system for adaptive data caching

Abstract

The present invention discloses a data playback control method and system for adaptive data caching. When a start signal is detected, test data is generated to start DMA transmission to the corresponding DDR channel, and the transmission delay corresponding to the DDR channel is recorded when the test data is transmitted to the corresponding DDR channel; when a channel signal playback task request is detected, the minimum playback threshold for triggering playback data transmission corresponding to the DDR channel is obtained according to the sampling rate and transmission delay corresponding to the DDR channel; the amount of playback data cached in the DDR channel is detected in real time, and when the amount of playback data is greater than the minimum playback threshold, the playback data is sent to the playback device through an arbitration module. By reasonably setting the minimum playback threshold that can ensure the normal operation of the system, the delay of playback startup is reduced, and the orderly transmission of data is ensured.

Description

Technical Field

[0001] The present invention relates to the technical field of data signal processing, and in particular to a data playback control method and system for adaptive data caching. Background Art

[0002] In the existing data playback process, FPGA is used to process data playback, DDR cache data writing and reading, and data stream transmission. The CPU processor is responsible for sampling rate analysis and cache management, and transmits management information to FPGA through the data bus to dynamically adjust the cache size during playback. When the CPU starts the playback task, the CPU sends the data to the DDR of the corresponding channel. When the data cache reaches a threshold value, it starts to send data to the outside through the channel arbitration.

[0003] Currently, the threshold value is generally set in the following two ways:

[0004] 1. Set a relatively large value according to the sampling rate to ensure that the playback is not empty, but this will bring a problem, that is, the playback has a large delay.

[0005] 2. Set a relatively small value according to the sampling rate to ensure a small playback delay, but this will bring a problem. Occasionally, after a period of time at the start of playback, the cache data may be empty, resulting in discontinuous playback data. Summary of the invention

[0006] The object of the present invention is to provide a data playback control method and system for adaptive data caching, which can reduce the delay of playback startup and ensure orderly data transmission by reasonably setting the minimum playback threshold that can ensure the normal operation of the system.

[0007] To achieve the above objectives, this application provides the following solutions:

[0008] On the one hand, the present application provides a data playback control method for adaptive data caching, which specifically includes the following steps:

[0009] S1, when a start signal is detected, test data is generated and DMA is started to be transferred to the corresponding DDR channel, and the transmission delay corresponding to the DDR channel when the test data is transferred to the corresponding DDR channel is recorded;

[0010] S2, when a channel signal playback task request is detected, the minimum playback threshold for triggering playback data transmission corresponding to the DDR channel is obtained according to the sampling rate and transmission delay corresponding to the DDR channel;

[0011] S3. Detect the amount of playback data cached in the DDR channel in real time, and when the amount of playback data is greater than the minimum playback threshold, send the playback data to the playback device through the arbitration module.

[0012] In some specific implementations, when solving the minimum playback threshold corresponding to each DDR channel, the transmission delay includes an average delay, a maximum delay, and a minimum delay. The specific process of step S2 is:

[0013] S21, monitoring the sampling rate of the current DDR channel, and calculating a first minimum threshold according to the sampling rate and the average delay;

[0014] S22, according to the preset size of the data packet transmitted by DMA, aligning the first minimum threshold to the preset size to obtain a second minimum threshold;

[0015] S23. Calculate a minimum playback threshold according to the average delay, the maximum delay, the minimum delay and the second minimum threshold.

[0016] In some specific implementations, the first minimum threshold Dmin is calculated as follows:

[0017] Dmin = SampleRate * Size * Among them, SampleRate indicates the sampling rate of the current DDR channel, Size is the number of bytes per sampling, Indicates the average delay.

[0018] In some specific implementations, the second minimum threshold is obtained as follows:

[0019] D'min = * X

[0020] Among them, X represents the preset size, Indicates rounding up.

[0021] In some specific implementations, the calculation method for obtaining the minimum playback threshold D in step S23 is:

[0022] D = k * D'min

[0023] k = 1 + C *

[0024] Among them, C represents the historical experience statistical coefficient, Indicates the maximum delay, Indicates the minimum delay.

[0025] In some specific implementations, the steps are further included:

[0026] S4. Monitor the available memory size of the current DDR channel in real time and dynamically adjust the cache space of the current DDR channel.

[0027] In some specific implementations, the specific process of step S4 is:

[0028] S41, obtaining the initial total memory size of the DDR channel, dividing the total memory size into N equal parts to form N memory nodes;

[0029] S42. Calculate the minimum number of memory nodes required by the DDR channel according to the minimum playback threshold;

[0030] S43, real-time detection of the channel memory resource status combined with the memory size corresponding to the minimum number of memory nodes, calculating the instantaneous occupancy rate, and selecting the maximum occupancy rate within a preset time after the channel signal playback task is started from the instantaneous occupancy rate;

[0031] S44, calculating the maximum occupied memory according to the maximum occupancy rate, and calculating the remaining memory space according to the maximum occupied memory and the initial total memory size;

[0032] S45, calculating the expected total memory according to the ratio of the maximum occupied memory to the expected occupied ratio;

[0033] S46: Compare the expected total memory with the initial total memory size, and dynamically adjust the cache space of the DDR channel according to the comparison result.

[0034] In some specific implementations, the specific process of dynamic adjustment is:

[0035] When the expected total memory is equal to the initial total memory size, the current buffer space size remains unchanged;

[0036] When the expected total memory is larger than the initial total memory size, the current buffer space is replenished, and the replenished memory is the difference between the expected total memory and the initial total memory size;

[0037] When the expected total memory is less than the initial total memory size, the current buffer space is reclaimed, and the reclaimed memory is the difference between the initial total memory size and the expected total memory.

[0038] In some specific implementations, during recycling and replenishment, the difference is set to an integer multiple of the memory length of each memory node.

[0039] In a second aspect, the present application provides a data playback control system for adaptive data caching, comprising:

[0040] Communication connection between CPU processor and FPGA, where

[0041] The CPU processor is used to implement cache management and sampling rate analysis of each DDR channel of the FPGA; specifically, when a start signal is detected, it is used to generate test data to start DMA transmission to the corresponding DDR channel, and record the delay corresponding to the DDR channel when the test data is transmitted to the corresponding DDR channel;

[0042] When a channel signal playback task request is detected, the minimum playback threshold for triggering playback data transmission corresponding to the DDR channel is obtained according to the sampling rate and delay corresponding to the DDR channel and passed to the FPGA;

[0043] FPGA is used to process the data playback of each DDR channel, write and read the cached data, and detect the amount of cached playback data in the DDR channel in real time. When the amount of playback data is greater than the minimum playback threshold, the playback data is sent to the playback device through the arbitration module.

[0044] The present invention has the beneficial effects:

[0045] This application records the transmission delay from DMA to DDR channel and calculates the minimum playback threshold of the DDR channel while ensuring the normal operation of the system. The minimum threshold satisfies the transmission delay of DMA data from CPU memory to the corresponding DDR channel, and the cache of the DDR channel is not empty. After determining the minimum playback threshold, when the playback task is started, the playback data cached in the DDR channel can be sent when it reaches the data volume corresponding to the minimum playback threshold, which can reduce the delay of playback startup and ensure orderly data transmission. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1 A schematic diagram of a data playback control system for adaptive data caching;

[0047] Figure 2 A flow chart of a data playback control method for adaptive data caching;

[0048] Figure 3 A flow chart of a method for dynamically adjusting cache space;

[0049] Figure 4 A schematic diagram of a cache space of an exemplary DDR channel. DETAILED DESCRIPTION

[0050] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments. The following description of at least one exemplary embodiment is actually only illustrative and is by no means intended to limit the present invention and its application or use. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0051] The relative arrangement of components and steps, the numerical expressions and numerical values ​​set forth in these embodiments do not limit the scope of the present invention unless specifically stated otherwise.

[0052] At the same time, it should be understood that for the convenience of description, the sizes of the various parts shown in the drawings are not drawn according to the actual proportional relationship.

[0053] Additionally, descriptions of well-known structures, functions, and configurations may be omitted for clarity and conciseness.One of ordinary skill in the art will recognize that various changes and modifications may be made to the examples described herein without departing from the spirit and scope of the present disclosure.

[0054] Technologies, methods, and apparatus known to ordinary technicians in the relevant field may not be discussed in detail, but where appropriate, such technologies, methods, and apparatus should be considered part of the authorization specification.

[0055] In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limiting. Therefore, other examples of the exemplary embodiments may have different values.

[0056] Before introducing the specific implementation methods of this application, the concepts involved are first explained:

[0057] The system architecture of the playback system is as follows Figure 1 As shown in the figure, the system includes an FPGA chip and a CPU processing chip. Generally, the FPGA is responsible for processing data playback, DDR cache data writing and reading, and data stream transmission. The CPU processor is responsible for sampling rate analysis and cache management, and transmits management information to the FPGA through the data bus to dynamically adjust the cache size during playback. Figure 1 It can be seen that there are multiple DDR cache channels on the playback channel. When the CPU starts the playback task, the CPU sends the data to the DDR of the corresponding channel. When the data cache reaches a playback threshold, it starts to send data to the outside through the channel arbitration. There are two parameters that need to be set here: how to set the cache space size of each DDR channel and how much data must be cached in the current DDR channel before it can be sent, that is, how large the playback threshold should be set. The existing playback threshold setting method is:

[0058] 1. Give a relatively large value according to the sampling rate to ensure that the playback is not empty, but it will bring a problem, that is, the playback has a large delay.

[0059] 2. Give a relatively small value according to the sampling rate to ensure a small playback delay, but this will bring a problem. Occasionally, after a period of time at the start of playback, the cache data may be empty, resulting in discontinuous playback data.

[0060] The cache size of each DDR channel is set by estimating a size based on the sampling rate of each channel, such as caching 1 second or 2 seconds, but it is ultimately a fixed value, which leads to the following two problems:

[0061] 1. When processing high sampling rate data, the amount of data will increase significantly. If a fixed smaller buffer is used, it may cause a buffer overflow. Since the buffer capacity is insufficient to store the large amount of data generated by the high sampling rate, a buffer overflow may occur, resulting in data loss or audio jamming and jumping during playback.

[0062] 2. For low sampling rate data, the transmission rate is low. If a fixed large cache size is used, it will lead to memory waste: A fixed large cache may be too large for low sampling rate data and cannot effectively utilize memory resources. Although data is stored for a long time, in fact, this data does not need so much cache.

[0063] In view of the above problems, this application proposes the following solutions:

[0064] Example 1

[0065] like Figure 2 As shown, this embodiment provides a data playback control method for adaptive data caching, which specifically includes the following steps:

[0066] S1, when a start signal is detected, test data is generated and DMA is started to be transferred to the corresponding DDR channel, and the transmission delay corresponding to the DDR channel when the test data is transferred to the corresponding DDR channel is recorded;

[0067] S2, when a channel signal playback task request is detected, the minimum playback threshold for triggering playback data transmission corresponding to the DDR channel is obtained according to the sampling rate and transmission delay corresponding to the DDR channel;

[0068] Specifically, when solving the minimum playback threshold corresponding to each DDR channel, the transmission delay includes the average delay, the maximum delay and the minimum delay. The specific process of step S2 is:

[0069] S21, monitoring the sampling rate of the current DDR channel, and calculating a first minimum threshold according to the sampling rate and the average delay;

[0070] The calculation method of the first minimum threshold Dmin is:

[0071] Dmin = SampleRate * Size *

[0072] Among them, SampleRate indicates the sampling rate of the current DDR channel, Size is the number of bytes per sampling, Indicates the average delay.

[0073] S22, according to the preset size of the data packet transmitted by DMA, aligning the first minimum threshold to the preset size to obtain a second minimum threshold;

[0074] The second minimum threshold is obtained as follows:

[0075] D'min = * X

[0076] Among them, X represents the preset size, Indicates rounding up.

[0077] S23. Calculate a minimum playback threshold according to the average delay, the maximum delay, the minimum delay and the second minimum threshold.

[0078] The calculation method for obtaining the minimum playback threshold D in step S23 is:

[0079] D = k * D'min

[0080] k = 1 + C *

[0081] Among them, C represents the historical experience statistical coefficient, Indicates the maximum delay Indicates the minimum delay.

[0082] S3. Detect the amount of playback data cached in the DDR channel in real time, and when the amount of playback data is greater than the minimum playback threshold, send the playback data to the playback device through the arbitration module.

[0083] It is understandable that the calculation and setting of the minimum playback threshold must ensure the normal operation of the system. Therefore, when setting the minimum playback threshold, the setting goals must meet the following requirements:

[0084] 1) Ensure that the cache is not empty during the TDMA transmission delay. (TDMA is the time required for a segment of DMA data to be transferred from the CPU's memory to the corresponding DDR channel cache of the FPGA)

[0085] 2) Reduce the delay in starting playback and ensure orderly data transmission.

[0086] In order to achieve the above goals, the implementation steps are:

[0087] 1. Calculate the time required to generate test data and transfer it from the CPU-side DMA to the FPGA's DDR memory when the playback task start signal is detected for the first time.

[0088] For example, assuming that the length of a single DMA is set to L, a pseudo-random data segment is generated in the memory as test data to fill the memory address of this segment with a length of L, the high-precision timer is started, and then the DMA transfer is started. N DMA transfers are tested, and the transfer time TDMA_i of each DMA is counted. The following transmission delay can be obtained:

[0089] Average delay:

[0090] Maximum delay:

[0091] Minimum delay:

[0092] Before detecting the channel signal playback task request, the DMA link will continuously count the transmission time of each DMA, and continuously update the average delay and maximum delay. When the channel signal playback task is detected to be started, the latest parameters (maximum delay, minimum delay and average delay) obtained before will be used in subsequent operations.

[0093] 2. According to the sampling rate SampleRate and Calculate the first minimum threshold for maintaining continuous playback of data:

[0094] Dmin = SampleRate * Size *

[0095] Size is the number of bytes per sample;

[0096] In order to meet the data alignment requirements of DMA, assuming that the preset size of the data packet transferred by DMA is X (KB), Dmin is aligned upward and rounded to the integer:

[0097] D'min = * X

[0098] The minimum playback threshold is: D = k * D'min

[0099] Among them, k is the safety factor. The selection of the safety factor k has an important impact on system performance. It is mainly used to ensure that the cache can continue to support playback in the case of transmission delays, system load changes, etc. The estimated safety factor 𝑘 is mainly in the case of high-load transmission. DMA transmission may fluctuate. Therefore, based on the above characteristics, the following expression can be introduced to express this characteristic:

[0100] k=1 + C *

[0101] The starting point of the formula is 1, which is the most basic safety factor, indicating that in an ideal situation, the system can operate normally without any additional buffering, when the DMA delay fluctuation is small, that is, near , the incremental part of the formula approaches 0, so 1k≈1. - Indicates the fluctuation range of DMA transmission delay. The larger the difference, the greater the change of DMA delay under different loads, and the system may need more buffers to cope with these fluctuations; C is the historical experience statistical coefficient, and users can fine-tune this coefficient based on historical engineering experience. The default value is 1.

[0102] Example 2

[0103] Based on Example 1, this implementation proposes to dynamically adjust the cache space size of each DDR channel to ensure that the system works normally without wasting the cache. Based on Example 1, the following steps are also included:

[0104] S4. Monitor the available memory size of the current DDR channel in real time and dynamically adjust the cache space of the current DDR channel.

[0105] Specifically, Figure 3 As shown, the specific process of step S4 is:

[0106] S41, obtaining the initial total memory size of the DDR channel, dividing the total memory size into N equal parts to form N memory nodes;

[0107] S42. Calculate the minimum number of memory nodes required by the DDR channel according to the minimum playback threshold;

[0108] S43, real-time detection of the channel memory resource status combined with the memory size corresponding to the minimum number of memory nodes, calculating the instantaneous occupancy rate, and selecting the maximum occupancy rate within a preset time after the channel signal playback task is started from the instantaneous occupancy rate;

[0109] S44, calculating the maximum occupied memory according to the maximum occupancy rate, and calculating the remaining memory space according to the maximum occupied memory and the initial total memory size;

[0110] S45, calculating the expected total memory according to the ratio of the maximum occupied memory to the expected occupied ratio;

[0111] S46: Compare the expected total memory with the initial total memory size, and dynamically adjust the cache space of the DDR channel according to the comparison result.

[0112] In some specific implementations, the specific process of dynamic adjustment is:

[0113] When the expected total memory is equal to the initial total memory size, the current buffer space size remains unchanged;

[0114] When the expected total memory is larger than the initial total memory size, the current buffer space is replenished, and the replenished memory is the difference between the expected total memory and the initial total memory size;

[0115] When the expected total memory is less than the initial total memory size, the current buffer space is reclaimed, and the reclaimed memory is the difference between the initial total memory size and the expected total memory.

[0116] In some specific implementations, during recycling and replenishment, the difference is set to an integer multiple of the memory length of each memory node.

[0117] It is understandable that in order to ensure that the cache space of each DDR channel can work normally without wasting cache resources, the cache space of the DDR channel is dynamically adjusted. Specifically, the CPU-side software can obtain the initial total memory size Total of the FPGA's DDR, divide the memory area into N equal parts, form N memory nodes, and hang the node information in the linked list list_free. The memory length NodeSIze of each node is:

[0118] NodeSIze = Total / N

[0119] When the channel signal playback task is started, the number of nodes P required when the amount of playback data cached in the DDR channel reaches the minimum playback threshold D can be calculated based on the minimum playback threshold D of the DDR channel. The calculation process is as follows:

[0120] Calculate D / NodeSIze

[0121] Determine whether D / NodeSIze is an integer. If it is an integer, then P = D / NodeSIze;

[0122] If D / NodeSIze contains a decimal, then P = [D / NodeSIze] + 1. [D / NodeSIze] indicates rounding calculation, so that P ≥ 1. The calculation result needs to allocate at least one data.

[0123] After calculating that P data blocks are needed on a certain channel when the task starts, the CPU informs the FPGA of the address information (starting address and length) of the P blocks through the data bus. The FPGA caches the information in the FIFO space and uses the information when playing back the data.

[0124] When the FPGA starts channel playback, the data space occupancy rate of each channel is counted in real time (the time can be very small because it can be done in real time in the FPGA), and the instantaneous occupancy rate can be obtained as follows:

[0125] Dpercent = DCacheData / (NodeSIze * P)

[0126] Among them, DcacheData represents the amount of playback data cached in the DDR channel counted in real time. During the working process, the maximum occupancy rate Dpercent_max can be obtained in real time from the instantaneous occupancy rate;

[0127] Assume that the current DDR channel transmission tends to be stable after the playback task time T is started. At this time, it can be considered that the maximum occupancy rate has tended to be stable, such as Figure 4 As shown in the figure, assuming that the initial total memory size of a channel is Total, after stabilization, the maximum occupied memory is M according to the maximum occupancy rate Dpercent_max at this time, then the remaining space of the channel R = Total – M. In order to achieve better anti-jitter performance, a safe expected ratio is set so that the ratio of the maximum occupied memory M to the remaining space R is X:Y = 7:3. According to the maximum occupied memory M and the expected occupied ratio, the expected total memory can be calculated. and the expected remaining memory

[0128]

[0129]

[0130] if No recycling or replenishment is required;

[0131] if Then the memory needs to be replenished. The size of the replenished memory is

[0132] if Then the memory needs to be reclaimed, and the size of the reclaimed memory is

[0133] In particular: during actual recycling and replenishment, the values ​​of D1 and D2 are constrained to be integer multiples of NodeSIze.

[0134] Example 3

[0135] This embodiment is used to implement the method of embodiment 1 or embodiment 2, and provides a data playback control system for adaptive data caching, including:

[0136] Communication connection between CPU processor and FPGA, where

[0137] The CPU processor is used to implement cache management and sampling rate analysis of each DDR channel of the FPGA; specifically, when a start signal is detected, it is used to generate test data to start DMA transmission to the corresponding DDR channel, and record the delay corresponding to the DDR channel when the test data is transmitted to the corresponding DDR channel;

[0138] When a channel signal playback task request is detected, the minimum playback threshold for triggering playback data transmission corresponding to the DDR channel is obtained according to the sampling rate and delay corresponding to the DDR channel and passed to the FPGA;

[0139] FPGA is used to process the data playback, cache data writing and reading of each DDR channel, and detect the amount of cached playback data in the DDR channel in real time. When the amount of playback data is greater than the minimum playback threshold, the playback data is sent to the playback device through the arbitration module. It also monitors the available memory size of the current DDR channel in real time and dynamically adjusts the cache space of the current DDR channel.

[0140] The above description is only a preferred embodiment of the present invention and does not limit the present invention in any form. According to the technical essence of the present invention, within the spirit and principles of the present invention, any simple modification, equivalent replacement and improvement made to the above embodiment still falls within the protection scope of the technical solution of the present invention.

Claims

1. A data playback control method for adaptive data caching, characterized in that: The specific steps include: S1, when a start signal is detected, test data is generated and DMA is started to be transferred to the corresponding DDR channel, and the transmission delay corresponding to the DDR channel when the test data is transferred to the corresponding DDR channel is recorded; S2, when a channel signal playback task request is detected, the minimum playback threshold for triggering playback data transmission corresponding to the DDR channel is obtained according to the sampling rate and transmission delay corresponding to the DDR channel; When solving the minimum playback threshold corresponding to each DDR channel, the transmission delay includes the average delay, the maximum delay and the minimum delay. The specific process of step S2 is: S21, monitoring the sampling rate of the current DDR channel, and calculating a first minimum threshold according to the sampling rate and the average delay; S22, according to the preset size of the data packet transmitted by DMA, aligning the first minimum threshold to the preset size to obtain a second minimum threshold; S23, calculating a minimum playback threshold according to the average delay, the maximum delay, the minimum delay and the second minimum threshold; S3. Detect the amount of playback data cached in the DDR channel in real time, and when the amount of playback data is greater than the minimum playback threshold, send the playback data to the playback device through the arbitration module.

2. The data playback control method of the adaptive data cache according to claim 1, characterized in that: The calculation method of the first minimum threshold Dmin is: Dmin = SampleRate * Size * ; Among them, SampleRate indicates the sampling rate of the current DDR channel, Size is the number of bytes per sampling, Indicates the average delay.

3. The data playback control method of the adaptive data cache according to claim 2, characterized in that: The second minimum threshold is obtained as follows: D'min = * X ; Among them, X represents the preset size, Indicates rounding up.

4. The data playback control method of the adaptive data cache according to claim 3, characterized in that: The calculation method for obtaining the minimum playback threshold D in step S23 is: D = k * D'min; k = 1 + C * ; Among them, k represents the safety factor, C represents the historical experience statistical coefficient, Indicates the maximum delay, Indicates the minimum delay.

5. The data playback control method of the adaptive data cache according to claim 4, characterized in that: Also includes the steps: S4. Monitor the available memory size of the current DDR channel in real time and dynamically adjust the cache space of the current DDR channel.

6. The data playback control method of the adaptive data cache according to claim 5, characterized in that: The specific process of step S4 is: S41, obtaining the initial total memory size of the DDR channel, dividing the total memory size into N equal parts to form N memory nodes; S42. Calculate the minimum number of memory nodes required by the DDR channel according to the minimum playback threshold; S43, real-time detection of the channel memory resource status combined with the memory size corresponding to the minimum number of memory nodes, calculating the instantaneous occupancy rate, and selecting the maximum occupancy rate within a preset time after the channel signal playback task is started from the instantaneous occupancy rate; S44, calculating the maximum occupied memory according to the maximum occupancy rate, and calculating the remaining memory space according to the maximum occupied memory and the initial total memory size; S45, calculating the expected total memory according to the ratio of the maximum occupied memory to the expected occupied ratio; S46: Compare the expected total memory with the initial total memory size, and dynamically adjust the cache space of the DDR channel according to the comparison result.

7. The data playback control method of adaptive data caching according to claim 6, characterized in that: The specific process of dynamic adjustment is as follows: When the expected total memory is equal to the initial total memory size, the current buffer space size remains unchanged; When the expected total memory is larger than the initial total memory size, the current buffer space is replenished, and the replenished memory is the difference between the expected total memory and the initial total memory size; When the expected total memory is less than the initial total memory size, the current buffer space is reclaimed, and the reclaimed memory is the difference between the initial total memory size and the expected total memory.

8. The data playback control method of adaptive data caching according to claim 7, characterized in that: When recycling and replenishing, the difference is set to an integer multiple of the memory length of each memory node.

9. A data playback control system for adaptive data caching, using the data playback control method for adaptive data caching as claimed in claim 1, characterized in that: include: Communication connection between CPU processor and FPGA, where The CPU processor is used to implement cache management and sampling rate analysis of each DDR channel of the FPGA; specifically, when a start signal is detected, it is used to generate test data to start DMA transmission to the corresponding DDR channel, and record the delay corresponding to the DDR channel when the test data is transmitted to the corresponding DDR channel; When a channel signal playback task request is detected, the minimum playback threshold for triggering playback data transmission corresponding to the DDR channel is obtained according to the sampling rate and delay corresponding to the DDR channel and passed to the FPGA; FPGA is used to process the data playback of each DDR channel, the writing and reading of cached data, and detect the amount of cached playback data in the DDR channel in real time. When the amount of playback data is greater than the minimum playback threshold, the playback data is sent to the playback device through the arbitration module.

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