Chip data processing efficiency optimization method and system

Abstract

The invention provides a chip data processing efficiency optimization method and system, and the method comprises the steps: obtaining a plurality of chip operation parameters through recognizing the current operation state of a chip; performing data segment division on the to-be-processed data information to obtain a plurality of data segments, obtaining sub-processing tasks corresponding to the plurality of data segments, and constructing a plurality of data sets; performing data type extraction and data association processing on the plurality of data segments to obtain a data processing structure network diagram; performing target data screening and data processing on the data processing structure network diagram to obtain a target data sub-processing result; and performing sequence updating on the unprocessed data segments of the chip to obtain a data information processing result. The problem that in the prior art, the data processing efficiency is improved by reducing the data size of the data information, but the precision of the data processing result is poor is solved. According to the invention, the number of the data segments processed by the chip is increased, and the data processing accuracy of each data segment is ensured.

Description

Technical Field

[0001] The present invention relates to the technical field of Internet of Things chips, and in particular to a method and system for optimizing chip data processing efficiency. Background Art

[0002] With the development of integrated chips, the types and amounts of data processed by chips are gradually increasing, which places a higher demand on the processing efficiency of chips.

[0003] At present, the existing technology mainly optimizes chip data processing efficiency by reducing the amount of data information, thereby improving the chip's processing efficiency of multiple data information. However, the traditional method fails to fully consider the data that actually needs to be processed, and often affects the accuracy of the data information when reducing the amount of data information, which in turn leads to the problem of poor accuracy of data processing results. Summary of the invention

[0004] In order to solve the above problems, the present invention proposes a chip data processing efficiency optimization method and system, which reduces the amount of data actually required to be processed in each data segment without deleting the data in each data segment, thereby increasing the number of data segments processed by the chip and ensuring the data processing accuracy of each data segment.

[0005] To achieve the above objectives, an embodiment of the present invention provides a method for optimizing chip data processing efficiency, comprising:

[0006] Based on the data information to be processed, a number of chip operating parameters are obtained by identifying the current operating state of the chip;

[0007] Based on the data processing tasks corresponding to the data information to be processed, the data information to be processed is divided into data segments to obtain a plurality of data segments and obtain sub-processing tasks corresponding to the plurality of data segments;

[0008] Constructing a plurality of data sets based on the plurality of chip operating parameters and the sub-processing tasks corresponding to the plurality of data segments;

[0009] Based on the data sets, extracting data types and performing data association processing on the data segments to obtain a data processing structure network diagram;

[0010] Performing target data screening and data processing on the data processing structure network diagram to obtain target data sub-processing results;

[0011] Based on the target data sub-processing result, the unprocessed data segments of the chip are sequentially updated to obtain the data information processing result.

[0012] An embodiment of the present invention proposes a chip data processing efficiency optimization method. By identifying the current operating status of the chip, the data information to be processed is divided into data segments, and a number of data sets are constructed. After the data type extraction and data association processing are completed in each data segment, the target data is screened based on the data processing structure network, and each unprocessed data segment is updated. Therefore, without deleting the amount of data in each data segment, the amount of data actually required to be processed in each data segment is reduced, the number of data segments processed by the chip is increased, and the data processing accuracy of each data segment is ensured.

[0013] Furthermore, based on the data information to be processed, by identifying the current operating state of the chip, a number of chip operating parameters are obtained, including:

[0014] Obtain data information of the input chip port to obtain data information to be processed;

[0015] Based on the data information to be processed, obtaining chip operation data and identifying the current operation status of the chip;

[0016] Based on the current operating state of the chip, obtaining the operating type corresponding to the current operating data;

[0017] Based on the chip operation specifications corresponding to each operation type in the preset first chip database and the preset data conversion strategy, the current operation data of each operation type is converted to obtain a number of chip operation parameters.

[0018] A chip data processing efficiency optimization method proposed in an embodiment of the present invention determines the chip operating parameters by identifying the chip operating specifications corresponding to the chip operating type, thereby improving the accuracy of determining the chip operating parameters.

[0019] Further, based on the data processing task corresponding to the data information to be processed, the data information to be processed is divided into data segments to obtain a plurality of data segments and obtain sub-processing tasks corresponding to the plurality of data segments, including:

[0020] Based on the data information to be processed, obtain the data processing tasks and data processing task flow corresponding to the data information to be processed;

[0021] Based on the process nodes of the data processing task process, the data information to be processed is divided and processed to obtain a plurality of data segments;

[0022] Based on the data task contents corresponding to the data segments, sub-processing tasks corresponding to the data segments are obtained.

[0023] A chip data processing efficiency optimization method proposed in an embodiment of the present invention improves data splitting accuracy by splitting data content according to processing tasks.

[0024] Furthermore, based on the plurality of chip operating parameters and the sub-processing tasks corresponding to the plurality of data segments, a plurality of data sets are constructed, including:

[0025] Based on the preset chip specification corresponding strategy, the plurality of chip operating parameters are numerically converted to screen out the current data processing saturation range and the current saturation threshold range of the chip that meet the preset requirements, and obtain the current data processing threshold of the chip;

[0026] Based on a preset second chip database, query the data processing rates corresponding to the operating parameters of the plurality of chips to obtain a current data processing rate of the chip;

[0027] Based on the current data processing threshold of the chip and the current data processing rate of the chip, data division is performed on the sub-processing tasks corresponding to the plurality of data segments to construct a plurality of data sets.

[0028] A chip data processing efficiency optimization method proposed in an embodiment of the present invention determines the current data processing threshold of the chip and the current data processing rate of the chip by identifying the operating specifications and operating parameters of each chip, thereby improving the efficiency of identifying the current data processing threshold and the current data processing rate of the chip.

[0029] Further, based on the current data processing threshold of the chip and the current data processing rate of the chip, data division is performed on the sub-processing tasks corresponding to the plurality of data segments to construct a plurality of data sets, including:

[0030] Generate a data partitioning strategy for each data segment based on the data volume of each data segment and the current data processing threshold of the chip;

[0031] Based on the current data processing rate of the chip, data division is performed on the sub-processing tasks corresponding to the plurality of data segments through the data division strategy of each data segment to construct a plurality of data sets.

[0032] A chip data processing efficiency optimization method proposed in an embodiment of the present invention ensures that the chip can maintain the current highest operating rate when subsequently processing the data segments in each data set by dividing each data segment into data sets with a data processing rate greater than the current data processing rate and a data volume that satisfies a data volume range.

[0033] Further, based on the plurality of data sets, data type extraction and data association processing are performed on the plurality of data segments to obtain a data processing structure network diagram, including:

[0034] According to the plurality of data sets, extracting data types of the plurality of data segments to obtain data types of corresponding data segments in each data set;

[0035] Based on the data types of the data segments, the data segments are classified into the same type to obtain a plurality of initial data groups of the same data type;

[0036] Based on the several initial data groups of the same data type, obtaining several data groups of the same sub-processing tasks;

[0037] Data association processing is performed on the data groups of the plurality of identical sub-processing tasks to obtain a data processing structure network diagram.

[0038] A chip data processing efficiency optimization method proposed in an embodiment of the present invention improves the data processing correlation in each data group by dividing the data into multiple data groups with the same data type and the same sub-processing task; and constructs a data processing structure network diagram after feature vector quantization, thereby improving the accuracy and efficiency of the constructed data processing structure network diagram.

[0039] Furthermore, data association processing is performed on the data groups of the plurality of identical sub-processing tasks to obtain a data processing structure network diagram, including:

[0040] Based on the preset data feature recognition network, data feature recognition is performed on each data group, and the data feature recognition network corresponding to the data type of each data group is selected;

[0041] Based on the data feature recognition network corresponding to the data type of each data group, performing data vector conversion on each data segment in the data group to obtain a data vector corresponding to each data segment;

[0042] Based on the data vectors corresponding to the data segments, obtaining the same data content between the data segments and the data position information corresponding to each same data content;

[0043] Based on the identical data contents between the data segments and the data location information corresponding to each identical data content, a data processing structure network diagram is obtained by constructing data association nodes and a data tree diagram.

[0044] Further, the target data is screened and processed on the data processing structure network diagram to obtain the target data sub-processing results, including:

[0045] Based on the data processing structure network diagram, target data is screened for each data group to obtain a target data segment;

[0046] Based on the sub-processing tasks corresponding to the plurality of data segments, data processing is performed on the target data segment to obtain a data processing result of the target data segment;

[0047] Based on the data processing result of the target data segment, a sub-processing result corresponding to each data content of the target data segment is obtained.

[0048] Further, based on the target data sub-processing result, the unprocessed data segments of the chip are sequentially updated to obtain data information processing results, including:

[0049] Based on the data processing structure network diagram, the data content of each data segment is replaced by the sub-processing result corresponding to each data content of the target data segment to obtain the pre-stored result of the target data segment;

[0050] Based on the pre-stored result of the target data segment, the corresponding target data segment in each data group is deleted and the unprocessed data segments of the chip are sequentially updated until each data segment has a corresponding sub-processing task, thereby obtaining a data segment processing result;

[0051] Based on the data segment processing result, data concatenation processing is performed on the data information corresponding to the data segment processing result to obtain a data information processing result.

[0052] An embodiment of the present invention proposes a chip data processing efficiency optimization method. Through synchronous replacement, after each data segment is processed, the amount of data content in other data segments that requires the chip to process data gradually decreases, thereby improving the processing efficiency of the chip in processing all data segments.

[0053] The embodiment of the present invention also provides a chip data processing efficiency optimization system, including: a chip operation parameter acquisition module, a data segment processing task acquisition module, a data set construction module, a data processing structure network diagram acquisition module, a target data processing module and a chip data update module;

[0054] The chip operation parameter acquisition module is used to acquire a number of chip operation parameters by identifying the current operation state of the chip based on the data information to be processed;

[0055] The data segment sub-processing task acquisition module is used to divide the data information to be processed into data segments based on the data processing tasks corresponding to the data information to be processed, obtain a number of data segments and obtain sub-processing tasks corresponding to the data segments;

[0056] The data set construction module is used to construct a plurality of data sets based on the plurality of chip operating parameters and the sub-processing tasks corresponding to the plurality of data segments;

[0057] The data processing structure network diagram acquisition module is used to extract data types and perform data association processing on the data segments based on the data sets to obtain a data processing structure network diagram;

[0058] The target data processing module is used to perform target data screening and data processing on the data processing structure network diagram to obtain target data sub-processing results;

[0059] The chip data update module is used to perform sequence update on the unprocessed data segments of the chip based on the target data sub-processing result to obtain a data information processing result.

[0060] An embodiment of the present invention proposes a chip data processing efficiency optimization system, which identifies the current operating status of the chip through a chip operating parameter acquisition module, divides the data information to be processed into data segments through a data segment sub-processing task acquisition module, and then constructs several data sets through a data set construction module. After the data type extraction and data association processing are completed in each data segment through a data processing structure network acquisition module, the target data processing module will perform target data screening based on the data processing structure network, and finally the chip data update module will update each unprocessed data segment, thereby reducing the amount of data actually required to be processed in each data segment without deleting the amount of data in each data segment, thereby increasing the number of data segments processed by the chip and ensuring the data processing accuracy of each data segment. BRIEF DESCRIPTION OF THE DRAWINGS

[0061] Figure 1 A schematic flow chart of the steps of a chip data processing efficiency optimization method provided by an embodiment of the present invention;

[0062] Figure 2 A schematic diagram of the module structure of a chip data processing efficiency optimization system provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0063] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0064] A chip data processing efficiency optimization method proposed in an embodiment of the present invention can be applied to the application environment of Internet of Things chips and integrated circuit chip detection, and is implemented through the interaction between a terminal and a server. The terminal can be but is not limited to various personal computers, laptops, smart phones, and tablet computers, etc., which will not be described in detail below.

[0065] Example 1

[0066] See also Figure 1 , Figure 1 A schematic flow chart of the steps of a chip data processing efficiency optimization method provided by an embodiment of the present invention; Figure 1As shown, the embodiment of the present invention proposes a chip data processing efficiency optimization method, including steps 101 to 106, each step is specifically as follows:

[0067] Step 101, based on the data information to be processed, by identifying the current operating state of the chip, obtaining a number of chip operating parameters;

[0068] As an example of this embodiment, data information of the input chip port is obtained to obtain data information to be processed; based on the data information to be processed, chip operation data is obtained and the current operation status of the chip is identified; based on the current operation status of the chip, the operation type corresponding to the current operation data is obtained; based on the chip operation specifications corresponding to each operation type in the preset first chip database and the preset data conversion strategy, the current operation data of each operation type is converted to obtain a number of chip operation parameters.

[0069] A specific implementation method is to obtain data information input into the chip port to obtain data information to be processed, wherein each data information is data information of different data types and different data processing tasks, and the data types include audio data, text data, image data, video data and audio data, etc.; then, based on the chip operation data transmitted in response to the real-time transmission of the chip, the current operation state of the chip is identified; wherein the chip operation data corresponds to operation data of different operation types, and the operation type includes operation fluctuation range, operation data volume and data processing volume per unit time, etc.; then based on the current operation state of the chip, each operation parameter of the chip is identified; wherein each operation parameter is a specification parameter corresponding to the chip operation specification of the chip, and the chip operation specification is data throughput, data processing time per unit data volume and data operation fluctuation range, etc.

[0070] Another specific explanation is that based on the current operating state of the chip, each current operating data of the chip is identified, and the operating type corresponding to each current operating data is identified; specifically, in the chip database, the chip operating specification corresponding to each operating type is queried, and based on the chip operating specification corresponding to each operating type, the operating data of each operating type is converted into the operating parameters of each chip operating specification. The conversion process is a preset data conversion strategy for converting the operating data of the operating type into the operating parameters of the chip operating specification, which can be specifically: the range corresponding to each parameter value of the preset chip operating specification, and the range to which the chip operating range belongs are identified, thereby determining the operating parameters of the chip.

[0071] Step 102, based on the data processing tasks corresponding to the data information to be processed, the data information to be processed is divided into data segments to obtain a plurality of data segments and obtain sub-processing tasks corresponding to the plurality of data segments;

[0072] As an example of this embodiment, based on the data information to be processed, the data processing tasks and the data processing task flow corresponding to the data information to be processed are obtained; based on the flow nodes of the data processing task flow, the data information to be processed is divided and processed to obtain a number of data segments; based on the corresponding data task contents in the several data segments, the sub-processing tasks corresponding to the several data segments are obtained.

[0073] A specific implementation method is to divide each data information into multiple data segments based on the data processing tasks of each data information, and identify the sub-processing tasks corresponding to each data segment; wherein the sub-processing tasks are part of the data processing tasks, and the sub-processing tasks include but are not limited to data processing tasks such as data identification, data decoding, data aggregation, data analysis, data calculation and data classification.

[0074] Another specific explanation is that, for each piece of data information, the data processing flow corresponding to the data processing task is identified, and the data processing flow is divided and processed according to each flow node of the data processing flow to obtain each sub-processing flow of the data processing flow; wherein each flow node of each data processing flow is a turning point between different data processing methods of the data processing flow, and the data processing flow after the flow node is taken as the sub-processing flow corresponding to the flow node; in the historical database, the historical data information required for each sub-processing flow corresponding to the data type of the data information is queried, and based on the historical data information of each sub-processing flow, in the data information, the data content whose average similarity with each piece of historical data information of the sub-processing flow is greater than the similarity threshold is calculated as the target data content corresponding to the sub-data processing flow; each target data content is taken as each data segment of the data information, and the task content of the sub-processing flow corresponding to each target data content in the data processing task is taken as the sub-processing task corresponding to each target data processing content.

[0075] Step 103, constructing a plurality of data sets based on the plurality of chip operating parameters and the sub-processing tasks corresponding to the plurality of data segments;

[0076] As an example of this embodiment, based on the preset chip specification corresponding strategy, the numerical conversion is performed on the operating parameters of the several chips, and the current data processing saturation range and the current saturation threshold range of the chip that meet the preset requirements are screened out to obtain the current data processing threshold of the chip; based on the preset second chip database, the data processing rate corresponding to the operating parameters of the several chips is queried to obtain the current data processing rate of the chip; based on the current data processing threshold of the chip and the current data processing rate of the chip, data division is performed on the sub-processing tasks corresponding to the several data segments to construct several data sets.

[0077] A specific implementation method is to identify the current data processing threshold of the chip and the current data processing rate of the chip based on the various operating parameters of the chip, and divide each data segment into multiple data sets based on the sub-processing tasks corresponding to each data segment, the data volume corresponding to each data segment, the current data processing threshold of the chip and the current data processing rate of the chip; the current data processing threshold includes: the current data processing saturation of the chip and the current data processing saturation threshold of the chip, and the current data processing saturation threshold is affected by factors such as the temperature of the chip, the working life of the chip and the degree of aging and failure of the chip.

[0078] Another specific explanation is that based on the operating parameters of the operating specifications of each chip, through the chip specification corresponding strategy, the current data processing saturation and the current saturation threshold of the chip corresponding to the operating parameters of each chip operating specification of the chip are identified, and the current data processing saturation of the chip and the current saturation threshold of the chip are used as the current data processing threshold of the chip; in each chip operating specification, the target chip operating specification whose operating type is the data operating rate is screened, and based on the operating parameters of the target chip operating specification, the processing rate corresponding to the operating parameters is queried in the database to obtain the current data processing rate of the chip; wherein the specification corresponding strategy is a conversion strategy for converting the operating parameters of the chip operating specifications into actual values, and the conversion method of the conversion strategy is: based on the range corresponding to the operating parameters of each chip operating specification, the current data processing saturation range of the chip and the current saturation threshold range of the chip are identified, and the minimum value in the current data processing saturation range and the minimum value in the current saturation threshold range are used as the current data processing saturation of the chip and the current saturation threshold of the chip.

[0079] As another example of this embodiment, a data partitioning strategy for each data segment is generated based on the data amount of each data segment and the current data processing threshold of the chip; based on the current data processing rate of the chip, data partitioning is performed on the sub-processing tasks corresponding to the several data segments through the data partitioning strategy of each data segment to construct several data sets.

[0080] A specific feasible implementation plan is to generate a data partitioning strategy for each data segment based on the data volume corresponding to each data segment and in accordance with the current data processing saturation of the chip and the current saturation threshold of the chip; the data partitioning strategy corresponds to the data set to which each data segment belongs; the normal operating rate of each sub-processing task when the chip is running is collected, and based on the normal operating rate of each sub-processing task when the chip is running and the current data processing rate of the chip, it is determined whether there is a data partitioning strategy in which the sum of the data processing rates of the sub-processing tasks corresponding to each data segment in all data sets is greater than the current data processing rate; the sum of the data processing rates of the sub-processing tasks corresponding to each data segment in all data sets is greater than the current data processing rate. The data partitioning strategy is used as the target partitioning strategy of the chip, and based on the target partitioning strategy, each data segment is divided into multiple data sets; more specifically, based on the data amount corresponding to each data segment, each data partitioning strategy of each data segment is generated according to the current data processing saturation of the chip and the current saturation threshold of the chip; the data partitioning strategy corresponds to the data set to which each data segment belongs; wherein the data amount of all data segments in each data set is: any data amount in the data amount range that is lower than the current saturation threshold of the chip and greater than the current data processing saturation of the chip; the data partitioning strategy is used to match the data amount of each data segment so that the data amount in each obtained data set satisfies the above data amount range.

[0081] Step 104, based on the plurality of data sets, extracting data types and performing data association processing on the plurality of data segments to obtain a data processing structure network diagram;

[0082] As an example of this embodiment, based on the several data sets, data types are extracted for the several data segments to obtain data types of corresponding data segments in each data set; based on the data types of the data segments, the data segments are classified into the same category to obtain several initial data groups of the same data type; based on the several initial data groups of the same data type, several data groups of the same sub-processing tasks are obtained; data association processing is performed on the data groups of the same sub-processing tasks to obtain a data processing structure network diagram.

[0083] A specific feasible implementation plan is, for each data set, dividing each data segment in the data set into data groups according to the data type to which each data segment belongs and the sub-processing task corresponding to each data segment, and performing data association processing on each data group based on the data type of each data segment and the sub-processing task corresponding to each data segment, so as to obtain a data processing structure network diagram for each data group; wherein the data processing structure network diagram includes association information between each data segment in the data group, and the association information is used to characterize the same data content between the data segments and the position information in each data segment corresponding to the same data content; the data processing structure network diagram is used to characterize the correspondence between the same data content between the data segments; specifically, dividing each data segment in the data set into data groups according to the data type to which each data segment belongs and the sub-processing task corresponding to each data segment, including: for each data set, identifying the data of each data segment; type, and divide each data segment into multiple initial data groups of the same data type; based on dividing each data segment in each initial data group into multiple data groups with the same sub-processing task; for each data group, based on the data type corresponding to the data group, in each data feature recognition network, screen the data feature recognition network corresponding to the data type, and based on the data feature recognition network corresponding to the data group, convert each data segment in the data group into a data vector; based on the data vectors corresponding to each data segment, identify the same data vector value between each data segment and the vector position of the same data vector value in each data segment, and based on the data vector value between each data segment and the vector position of the same data vector value in each data segment, identify the same data content between each data segment and the data position information corresponding to each same data content; based on the same data content between each data segment and the data position information corresponding to each same data content, construct a data processing structure network diagram corresponding to the data group.

[0084] As another example of this embodiment, based on a preset data feature recognition network, data feature recognition is performed on each data group, and the data feature recognition network corresponding to the data type of each data group is screened; based on the data feature recognition network corresponding to the data type of each data group, data vector conversion is performed on each data segment in the data group to obtain the data vector corresponding to each data segment; based on the data vector corresponding to each data segment, the same data content between each data segment and the data location information corresponding to each same data content are obtained; based on the same data content between each data segment and the data location information corresponding to each same data content, a data processing structure network diagram is obtained by constructing data association nodes and a data tree diagram.

[0085] A specific possible implementation method is to preset a data feature recognition network corresponding to different data types; the data feature recognition network is used to convert the data content in each data segment into a data vector corresponding to the data segment or a data vector matrix composed of multiple data vectors; the data vector is a feature vector corresponding to the data segment; based on the data vector corresponding to each data segment, the same data vector value between each data segment and the vector position of the same data vector value in each data segment are identified, and based on the data vector value between each data segment and the vector position of the same data vector value in each data segment, the same data content between each data segment and the data position information corresponding to each same data content are identified; finally, the terminal constructs a data processing structure network diagram corresponding to the data group based on the same data content between each data segment and the data position information corresponding to each same data content; the method of constructing the data processing structure network diagram is: taking the same data content between each data segment as the connection point, constructing a data tree diagram corresponding to each data segment.

[0086] Step 105, performing target data screening and data processing on the data processing structure network diagram to obtain target data sub-processing results;

[0087] As an example of this embodiment, based on the data processing structure network diagram, target data is screened for each data group to obtain a target data segment; based on the sub-processing tasks corresponding to several data segments, data processing is performed on the target data segment to obtain a data processing result for the target data segment; based on the data processing result for the target data segment, a sub-processing result corresponding to each data content of the target data segment is obtained.

[0088] A specific implementation method is to randomly screen the target data segments of the data processing structure network diagram of the data group for each data group, and perform data processing on the target data segments based on the sub-processing tasks of the data group to obtain the data processing results of the target data segments, and identify the sub-processing results corresponding to each data content of the target data segments based on the data processing results of the target data segments.

[0089] Step 106: Based on the target data sub-processing result, the unprocessed data segments of the chip are sequentially updated to obtain a data information processing result.

[0090] As an example of this embodiment, based on the data processing structure network diagram, the data content of each data segment is replaced by the sub-processing result corresponding to each data content of the target data segment to obtain the pre-stored result of the target data segment; based on the pre-stored result of the target data segment, the corresponding target data segment in each data group is deleted and the unprocessed data segments of the chip are sequentially updated until each data segment has a corresponding sub-processing task to obtain a data segment processing result; based on the data segment processing result, the data information corresponding to the data segment processing result is subjected to data splicing processing to obtain a data information processing result.

[0091] A specific implementation method is to replace the data content in each data segment with the sub-processing result corresponding to each data content of the target data segment based on the data processing structure network, and store the target data segment in the data processing result database, delete the target data segment in the data group, and return to execute the target data segment of the data processing structure network diagram of the screening data group until all data segments complete the sub-processing task corresponding to each data segment to obtain the processing result corresponding to each data segment; the processing result of each data segment is processed according to the data information corresponding to each data segment to obtain the processing result of each data information; more specifically, after processing each target data segment, the deleted data segment is replaced with the sub-processing result corresponding to each data segment, and the target data segment is returned to execute the data processing structure network diagram of the screening data group, and the sub-processing task corresponding to each data segment is returned to execute the target data segment of the data processing structure network diagram of the screening data group until all data segments complete the sub-processing task corresponding to each data segment, and the processing result corresponding to each data segment is obtained; the processing result of each data segment is processed according to the data information corresponding to each data segment to obtain the processing result of each data information; more specifically, after processing each target data segment, the deleted data segment is returned to execute the data processing structure network diagram of the screening data group, and the target ... Except for the data content in other data segments that is identical to that of the data segment, and taking the sub-processing results of each identical data content as the sub-processing results of other data segments, then, when performing data processing on other data segments, it is only necessary to perform data processing on the data content in the data segment that does not have a sub-processing result; for example, the sub-processing task in the image data is to perform pixel refinement processing on each pixel point, then after the terminal processes each pixel point in the first image data and obtains the high-precision pixel point corresponding to each pixel point, when processing other second image data, the terminal only needs to process the pixel points in each second image data that do not have a corresponding high-precision pixel point, and so on and so forth.

[0092] The embodiment of the present invention proposes a chip data processing efficiency optimization method, which divides the data information to be processed into data segments by identifying the current operating state of the chip, constructs a number of data sets, and performs target data screening based on the data processing structure network after the data type extraction and data association processing are completed in each data segment, thereby updating each unprocessed data segment, thereby reducing the amount of data actually required to be processed in each data segment without deleting the amount of data in each data segment, thereby increasing the number of data segments processed by the chip and ensuring the data processing accuracy of each data segment; the present invention determines the chip operating parameters by identifying the chip operating specifications corresponding to the chip operating type, thereby improving the accuracy of determining the chip operating parameters; the present invention improves the data splitting accuracy by splitting the data content according to the processing tasks; the present invention determines the chip operating parameters by identifying the chip operating specifications and operating parameters of each chip The present invention improves the efficiency of identifying the current data processing threshold and the current data processing rate of the chip; the present invention divides each data segment into data combinations whose data processing rate is greater than the current data processing rate and whose data volume meets the data volume range, thereby ensuring that the chip can maintain the current highest operating rate when subsequently processing the data segments in each data set; the present invention improves the data processing correlation in each data group by dividing the data into multiple data groups with the same data type and the same sub-processing task; the present invention constructs a data processing structure network diagram after feature vector quantization, thereby improving the accuracy and efficiency of the constructed data processing structure network diagram; the present invention uses a synchronous replacement method, after each data segment is processed, the amount of data in the data content of other data segments that requires the chip to perform data processing gradually decreases, thereby improving the processing efficiency of the chip in processing all data segments.

[0093] Example 2

[0094] See also Figure 2 , Figure 2 A schematic diagram of the module structure of a chip data processing efficiency optimization system provided by an embodiment of the present invention. Figure 2 As shown, the embodiment of the present invention proposes a chip data processing efficiency optimization system, including: a chip operation parameter acquisition module 201, a data segment processing task acquisition module 202, a data set construction module 203, a data processing structure network diagram acquisition module 204, a target data processing module 205 and a chip data update module 206;

[0095] The chip operation parameter acquisition module 201 is used to acquire a number of chip operation parameters by identifying the current operation state of the chip based on the data information to be processed;

[0096] The data segment sub-processing task acquisition module 202 is used to divide the data information to be processed into data segments based on the data processing tasks corresponding to the data information to be processed, obtain a number of data segments and obtain sub-processing tasks corresponding to the data segments;

[0097] The data set construction module 203 is used to construct a plurality of data sets based on the plurality of chip operating parameters and the sub-processing tasks corresponding to the plurality of data segments;

[0098] The data processing structure network diagram acquisition module 204 is used to extract data types and perform data association processing on the data segments based on the data sets to obtain a data processing structure network diagram;

[0099] The target data processing module 205 is used to perform target data screening and data processing on the data processing structure network diagram to obtain target data sub-processing results;

[0100] The chip data updating module 206 is used to perform sequence update on the unprocessed data segments of the chip based on the target data sub-processing result to obtain a data information processing result.

[0101] An embodiment of the present invention proposes a chip data processing efficiency optimization system, which identifies the current operating status of the chip through a chip operating parameter acquisition module, divides the data information to be processed into data segments through a data segment sub-processing task acquisition module, and then constructs several data sets through a data set construction module. After the data type extraction and data association processing are completed in each data segment through a data processing structure network acquisition module, the target data processing module will perform target data screening based on the data processing structure network, and finally the chip data update module will update each unprocessed data segment, thereby reducing the amount of data actually required to be processed in each data segment without deleting the amount of data in each data segment, thereby increasing the number of data segments processed by the chip and ensuring the data processing accuracy of each data segment.

[0102] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the technical principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

[0103] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example" or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine different embodiments or examples described in this specification and the features of different embodiments or examples, unless they are contradictory.

[0104] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

Claims

1. A method for optimizing chip data processing efficiency, characterized in that: include: Based on the data information to be processed, a number of chip operating parameters are obtained by identifying the current operating state of the chip; Based on the data processing tasks corresponding to the data information to be processed, the data information to be processed is divided into data segments to obtain a plurality of data segments and obtain sub-processing tasks corresponding to the plurality of data segments; Constructing a plurality of data sets based on the plurality of chip operating parameters and the sub-processing tasks corresponding to the plurality of data segments; Based on the plurality of data sets, data type extraction and data association processing are performed on the plurality of data segments to obtain a data processing structure network diagram; Performing target data screening and data processing on the data processing structure network diagram to obtain target data sub-processing results; Based on the target data sub-processing result, the unprocessed data segments of the chip are sequentially updated to obtain the data information processing result.

2. A chip data processing efficiency optimization method as claimed in claim 1, characterized in that: The method of obtaining several chip operating parameters by identifying the current operating state of the chip based on the data information to be processed includes: Obtain data information of the input chip port to obtain data information to be processed; Based on the data information to be processed, obtaining chip operation data and identifying the current operation status of the chip; Based on the current operating state of the chip, obtaining the operating type corresponding to the current operating data; Based on the chip operation specifications corresponding to each operation type in the preset first chip database and the preset data conversion strategy, the current operation data of each operation type is converted to obtain a number of chip operation parameters.

3. A chip data processing efficiency optimization method as claimed in claim 1, characterized in that: Based on the data processing task corresponding to the data information to be processed, the data information to be processed is divided into data segments to obtain a plurality of data segments and obtain sub-processing tasks corresponding to the plurality of data segments, including: Based on the data information to be processed, obtain the data processing tasks and data processing task flow corresponding to the data information to be processed; Based on the process nodes of the data processing task process, the data information to be processed is divided and processed to obtain a plurality of data segments; Based on the data task contents corresponding to the data segments, sub-processing tasks corresponding to the data segments are obtained.

4. A chip data processing efficiency optimization method according to any one of claims 1 to 3, characterized in that: Based on the plurality of chip operating parameters and the sub-processing tasks corresponding to the plurality of data segments, a plurality of data sets are constructed, including: Based on the preset chip specification corresponding strategy, the plurality of chip operating parameters are numerically converted to screen out the current data processing saturation range and the current saturation threshold range of the chip that meet the preset requirements, and obtain the current data processing threshold of the chip; Based on a preset second chip database, query the data processing rates corresponding to the operating parameters of the plurality of chips to obtain a current data processing rate of the chip; Based on the current data processing threshold of the chip and the current data processing rate of the chip, data division is performed on the sub-processing tasks corresponding to the plurality of data segments to construct a plurality of data sets.

5. A chip data processing efficiency optimization method as claimed in claim 4, characterized in that: Based on the current data processing threshold of the chip and the current data processing rate of the chip, data is divided into sub-processing tasks corresponding to a plurality of data segments to construct a plurality of data sets, including: Generate a data partitioning strategy for each data segment based on the data volume of each data segment and the current data processing threshold of the chip; Based on the current data processing rate of the chip, data division is performed on the sub-processing tasks corresponding to the plurality of data segments through the data division strategy of each data segment to construct a plurality of data sets.

6. A chip data processing efficiency optimization method as claimed in claim 5, characterized in that: Based on the plurality of data sets, data type extraction and data association processing are performed on the plurality of data segments to obtain a data processing structure network diagram, including: According to the plurality of data sets, extracting data types of the plurality of data segments to obtain data types of corresponding data segments in each data set; Based on the data types of the data segments, the data segments are classified into the same type to obtain a plurality of initial data groups of the same data type; Based on the several initial data groups of the same data type, obtaining several data groups of the same sub-processing tasks; Data association processing is performed on the data groups of the plurality of identical sub-processing tasks to obtain a data processing structure network diagram.

7. A chip data processing efficiency optimization method as claimed in claim 1, characterized in that: Performing data association processing on the data groups of the plurality of identical sub-processing tasks to obtain a data processing structure network diagram, including: Based on the preset data feature recognition network, data feature recognition is performed on each data group, and the data feature recognition network corresponding to the data type of each data group is selected; Based on the data feature recognition network corresponding to the data type of each data group, performing data vector conversion on each data segment in the data group to obtain a data vector corresponding to each data segment; Based on the data vectors corresponding to the data segments, obtaining the same data content between the data segments and the data position information corresponding to each same data content; Based on the identical data contents between the data segments and the data location information corresponding to each identical data content, a data processing structure network diagram is obtained by constructing data association nodes and a data tree diagram.

8. A chip data processing efficiency optimization method as claimed in claim 1, characterized in that: The target data is screened and processed on the data processing structure network diagram to obtain target data sub-processing results, including: Based on the data processing structure network diagram, target data is screened for each data group to obtain a target data segment; Based on the sub-processing tasks corresponding to the plurality of data segments, data processing is performed on the target data segment to obtain a data processing result of the target data segment; Based on the data processing result of the target data segment, a sub-processing result corresponding to each data content of the target data segment is obtained.

9. A chip data processing efficiency optimization method as claimed in claim 1, characterized in that: Based on the target data sub-processing result, the unprocessed data segment of the chip is sequentially updated to obtain a data information processing result, including: Based on the data processing structure network diagram, the data content of each data segment is replaced by the sub-processing result corresponding to each data content of the target data segment to obtain the pre-stored result of the target data segment; Based on the pre-stored result of the target data segment, the corresponding target data segment in each data group is deleted and the unprocessed data segments of the chip are sequentially updated until each data segment has a corresponding sub-processing task, thereby obtaining a data segment processing result; Based on the data segment processing result, data concatenation processing is performed on the data information corresponding to the data segment processing result to obtain a data information processing result.

10. A chip data processing system, characterized in that: include: Chip operation parameter acquisition module, data segment processing task acquisition module, data set construction module, data processing structure network diagram acquisition module, target data processing module and chip data update module; The chip operation parameter acquisition module is used to acquire a number of chip operation parameters by identifying the current operation state of the chip based on the data information to be processed; The data segment sub-processing task acquisition module is used to divide the data information to be processed into data segments based on the data processing tasks corresponding to the data information to be processed, obtain a number of data segments and obtain sub-processing tasks corresponding to the data segments; The data set construction module is used to construct a plurality of data sets based on the plurality of chip operating parameters and the sub-processing tasks corresponding to the plurality of data segments; The data processing structure network diagram acquisition module is used to extract data types and perform data association processing on the data segments based on the data sets to obtain a data processing structure network diagram; The target data processing module is used to perform target data screening and data processing on the data processing structure network diagram to obtain target data sub-processing results; The chip data update module is used to perform sequence update on the unprocessed data segments of the chip based on the target data sub-processing result to obtain the data information processing result.

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