VCSEL chip test data processing method and device

Abstract

The present application relates to a method and device for processing test data of a VCSEL chip. The method includes: constructing an initial chip multi-task fusion model; obtaining a variety of different types of measured data that directly or indirectly characterize the high-speed performance of the VCSEL chip; importing a variety of different types of measured data into the initial chip multi-task fusion model to analyze the linear or nonlinear relationship between each measured data, and continuously iteratively updating the initial chip multi-task fusion model to obtain a trained chip multi-task fusion model; obtaining partial performance test data of the VCSEL chip to be tested, and inputting the partial performance test data into the trained chip multi-task fusion model. This method can efficiently and accurately output the target performance prediction data of the VCSEL chip to be tested based on the linear relationship between the analyzed partial performance test data, or output the performance level of the chip to be tested based on the nonlinear relationship between the analyzed partial performance test data.

Description

Technical Field

[0001] The present application relates to the field of data processing technology, and in particular to a VCSEL chip test data processing method, a chip performance prediction method, an apparatus, a computer device, a computer-readable storage medium, and a computer program product. Background Art

[0002] VCSEL chip, namely vertical cavity surface emitting laser chip, is a special type of semiconductor laser. In order to obtain the performance of VCSEL chip, the chip is usually tested to obtain test data of the chip at multiple levels.

[0003] If a comprehensive performance test is to be conducted on a VCSEL chip, the chip needs to be tested at every level, which makes the testing process complicated, time-consuming and costly. Summary of the invention

[0004] Based on this, it is necessary to provide a test data processing method, device, computer equipment, computer-readable storage medium and computer program product for a VCSEL chip that can efficiently and accurately obtain performance-related data of the chip in response to the above technical problems.

[0005] In a first aspect, the present application provides a method for processing test data of a VCSEL chip, comprising:

[0006] Construct an initial chip multi-task fusion model;

[0007] Obtaining various types of measured data that directly or indirectly characterize the high-speed performance of the reference VCSEL chip;

[0008] Importing the multiple different types of measured data into the initial chip multi-task fusion model to analyze the linear or nonlinear relationship between the measured data, and continuously iteratively updating the initial chip performance multi-task fusion model to obtain a trained chip multi-task fusion model;

[0009] Acquire partial performance test data of the VCSEL chip to be detected, and input the partial performance test data into the trained chip multi-task fusion model; the trained chip multi-task fusion model outputs target performance prediction data of the VCSEL chip to be detected according to the analyzed linear relationship between the partial performance test data, or outputs the performance level of the chip to be detected according to the analyzed nonlinear relationship between the partial performance test data.

[0010] In a second aspect, the present application also provides a test data processing device for a VCSEL chip, comprising:

[0011] A construction module, used to construct an initial chip multi-task fusion model;

[0012] An acquisition module, used to acquire various types of measured data that directly or indirectly characterize the high-speed performance of the reference chip;

[0013] A training module, used for importing the plurality of different types of measured data into the initial chip multi-task fusion model to analyze the linear or nonlinear relationship between the measured data, and continuously iteratively updating the initial chip performance multi-task fusion model to obtain a trained chip multi-task fusion model;

[0014] A prediction module is used to obtain partial performance test data of the VCSEL chip to be detected, and input the partial performance test data into the trained chip multi-task fusion model; the trained chip multi-task fusion model outputs the target performance prediction data of the VCSEL chip to be detected according to the analyzed linear relationship between the partial performance test data, or outputs the performance level of the VCSEL chip to be detected according to the analyzed nonlinear relationship between the partial performance test data.

[0015] In a third aspect, the present application further provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps described in the above method when executing the computer program.

[0016] In a fourth aspect, the present application further provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program implements the steps described in the above method when executed by a processor.

[0017] In a fifth aspect, the present application also provides a computer program product, including a computer program, which implements the steps described in the above method when executed by a processor.

[0018] The test data processing method, device, computer equipment, computer-readable storage medium and computer program product of the above-mentioned VCSEL chip, by constructing an initial chip multi-task fusion model, obtains various types of measured data of the VCSEL chip, and inputs these measured data into the initial chip multi-task fusion model to analyze the linear or nonlinear relationship between the measured data, and continuously iterates and updates the initial chip performance multi-task fusion model. In this way, by processing the test data of the chip, a trained chip multi-task fusion model can be obtained, and the trained chip multi-task fusion model obtained can analyze the linear relationship or nonlinear relationship of the performance test data input into the model to obtain the target performance prediction data of the chip or the performance level of the chip, thereby greatly reducing the time for testing the performance-related data of the chip, improving the efficiency of obtaining the performance-related data of the VCSEL chip, and then efficiently and accurately obtaining the performance-related data of the chip and comprehensively evaluating the chip performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the drawings required for use in the embodiments of the present application or related technical descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0020] Figure 1 1 is a flow chart of a method for processing test data of a VCSEL chip in one embodiment;

[0021] Figure 2 A schematic flow chart of a step of obtaining a correlation between DC data and high-speed data in one embodiment;

[0022] Figure 3 A schematic diagram of the structure of a chip multi-task fusion model in an embodiment;

[0023] Figure 4 A schematic flow chart of a step of obtaining the correlation between chip data and chip level in one embodiment;

[0024] Figure 5 It is a schematic diagram of the structure of a chip multi-task fusion model in another embodiment;

[0025] Figure 6 is a structural block diagram of a test data processing device for a VCSEL chip in one embodiment;

[0026] Figure 7 FIG. 4 is a diagram showing the internal structure of a computer device in one embodiment. DETAILED DESCRIPTION

[0027] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0028] In an exemplary embodiment, Figure 1 As shown, a method for processing test data of a VCSEL chip is provided. This embodiment uses the method applied to a server as an example for illustration. It can be understood that the method can also be applied to a terminal, and can also be applied to a system including a terminal and a server, and is implemented through the interaction between the terminal and the server. In this embodiment, the method includes the following steps S102 to S108, wherein:

[0029] Step S102, constructing an initial chip multi-task fusion model.

[0030] The initial chip multi-task fusion model is used to train a model that can handle various different types of tasks related to chip performance. The various different types of tasks may be, for example, tasks of predicting certain performance data of the chip or tasks of evaluating the performance level of the chip.

[0031] For example, Figure 3 As shown, the initial chip multi-task fusion model includes an input layer, two fully connected layers and an output layer connected in sequence. Between the two fully connected layers, a function is set to process the data in the model. That is, the data output by the first fully connected layer is input to the function, and the data output by the function is input to the second fully connected layer. The result output by the second fully connected layer is input to the output layer to obtain the target output based on the output layer. In this model, the function includes a first function and a second function. The first function is used to capture the linear relationship of the data input to the model. The second function is used to capture the nonlinear relationship of the data input to the model. Therefore, the constructed initial chip multi-task fusion model can match the corresponding function to the data input to the model, so as to obtain the corresponding target output. Optionally, the first function corresponds to the target performance data of the predicted chip. The second function corresponds to the performance level of the chip to be tested.

[0032] Step S104, obtaining various types of measured data that directly or indirectly characterize the high-speed performance of the VCSEL chip.

[0033] Among them, the VCSEL chip is a Vertical Cavity Surface Emitting Laser chip, which is a special type of semiconductor laser chip. The laser emission direction of the VCSEL chip is perpendicular to the surface of the chip. The measured data refers to the performance data obtained by testing the VCSEL chip. The measured data of a VCSEL chip can include high-speed data and DC data obtained by testing it, or it can include high-speed data and DC data obtained by testing it and the performance level obtained by analyzing it.

[0034] In this embodiment, the measured data directly representing the high-speed performance of the VCSEL chip is the high-speed data. The measured data indirectly representing the high-speed performance of the VCSEL chip is the DC data. The high-speed data includes the 3dB bandwidth (f 3dB ), relaxation oscillation frequency (f r ), relative intensity noise (RIN), and TDECQ value. The DC data includes the threshold current (I th )、series resistance(R s ), aperture diameter (OA), slope efficiency (SE), central wavelength (Wp), and spectral width (Spectral Width).

[0035] Exemplarily, after constructing an initial chip multi-task fusion model, the server can obtain various types of measured data that directly or indirectly characterize the high-speed performance of the VCSEL chip, so as to facilitate the subsequent use of these measured data to train each task in the model, thereby obtaining a trained chip multi-task fusion model.

[0036] Step S106, importing a plurality of different types of measured data into the initial chip multi-task fusion model to analyze the linear or nonlinear relationship between the measured data, and continuously iterating and updating the initial chip multi-task fusion model to obtain a trained chip multi-task fusion model.

[0037] Among them, the trained chip multi-task fusion model refers to the trained chip multi-task fusion model. Every time a set of measured data is input into the model, the model will adjust the parameters in the model based on this set of measured data so that the adjusted parameters are combined with part of the data in this set of measured data, and the output result can be within a preset range with the difference between the other part of the data in this set of measured data. Then, the above steps are performed for each set of measured data input to the model. When the parameters in the model are no longer adjusted, the chip multi-task fusion model training is completed. It can be understood that for each task branch model in the model, training is performed separately to obtain each trained task branch model.

[0038] Optionally, the chip multi-task fusion model includes a data prediction branch model and a level analysis branch model. The data prediction branch model is used to predict high-speed data based on DC data. The level analysis branch model is used to analyze the performance level of the chip based on the DC data and high-speed data of the chip.

[0039] Furthermore, when the chip multi-task fusion model is selected as the data prediction branch model, the model can refer to formula (1) to calculate the partial DC data (threshold current I th and aperture diameter OA) and high-speed data (f 3dB 、f r ) to learn, adjust and automatically iterate the relationship between them.

[0040] (1)

[0041] D represents the differential gain, I th is the threshold current, I b is the operating current, f r represents the relaxation oscillation frequency.

[0042] When the working current I b When a certain time, f 3dB It can be expressed by the following formula (2):

[0043] (2)

[0044] Wherein, OA represents the aperture diameter. In most cases (or within the scope of this patent), f r and f 3dB There is a proportional relationship, and the proportional coefficient is represented by a1. The size of the aperture diameter OA affects the size of the differential gain D in an approximately proportional manner. The simplified proportional coefficient is represented by a2. Generally, the smaller the aperture diameter OA, the larger the differential gain D.

[0045] Furthermore, for other DC data, such as series resistance (R s ), slope efficiency (SE), center wavelength (Wp), etc. have similar connections with high-speed performance parameters (such as fr, f3dB, TDECQ), which can be automatically adjusted by the model during the training process to establish corresponding connections within the model.

[0046] Optionally, since the input and output of the data prediction branch model and the level analysis branch model are different, after inputting a plurality of different types of measured data into the model, the input data may be processed first so that the type of data input to each branch model is matched. For the data prediction branch model, the input measured data may be DC data, and the output data may be high-speed data. For the level analysis branch model, the input measured data is DC data and high-speed data, and the output data is the level of the chip, such as the first level, the second level, and the like. Therefore, the processing of the input data may include: dividing the different types of measured data corresponding to each chip into a DC data class, a high-speed data class, and a chip level class according to preset major categories. Then, the measured data belonging to the DC data class and the high-speed data class are imported into the data prediction branch model to train the model, wherein the data of the DC data class is used as the model input data. The measured data of the high-speed data class is used as label data for comparing with the output data obtained by the model based on the linear relationship between the input data to adjust the model parameters. And the measured data belonging to the DC data class and the high-speed data class are imported into the level analysis branch model to train the model. The measured data of DC data and high-speed data are used as model input data. The chip level data is used as the label data of the model, which is used to adjust the parameters of the level analysis branch model by comparing with the output level obtained by the model based on the nonlinear relationship between the input data.

[0047] Step S108, obtaining partial performance test data of the VCSEL chip to be tested, and inputting the partial performance test data into the trained chip multi-task fusion model; the trained chip multi-task fusion model outputs the target performance prediction data of the VCSEL chip to be tested according to the analyzed linear relationship between the partial performance test data, or outputs the performance level of the chip to be tested according to the analyzed nonlinear relationship between the partial performance test data.

[0048] After obtaining the trained chip multi-task fusion model, the chip multi-task fusion model can be used to analyze the linear relationship between the data input to the model to obtain some performance data of the chip, or analyze the nonlinear relationship between the data input to the model to obtain the performance level of the chip.

[0049] Optionally, obtain some performance test data of the VCSEL chip to be tested. Some performance test data may be performance data obtained by testing the VCSEL chip. For example, some performance test data may be performance data obtained by a simple test of the VCSEL chip, such as some DC data. After some performance test data are input into the trained chip multi-task fusion model, the model analyzes the linear relationship between some performance test data and outputs target performance prediction data of the VCSEL chip to be tested. The target performance prediction data is not data obtained by testing the chip, but data predicted by the model. The target performance prediction data may be performance data obtained by a complex test of the VCSEL chip, such as data such as 3dB bandwidth, TDECQ value, etc. The type of target performance prediction data may be determined based on the measured data input during training. If the measured data input during training has only 3dB bandwidth, then the target performance prediction data only includes 3dB bandwidth. If the measured data input during training has 3dB bandwidth and TDECQ value, then the target performance prediction data may include 3dB bandwidth and TDECQ value.

[0050] Optionally, obtain some performance test data of the VCSEL chip to be tested. Some performance test data can be performance data obtained by performing simple tests and complex tests on the VCSEL chip, such as at least one DC data and at least one high-speed data. After these performance test data are input into the trained chip multi-task fusion model, if the model analyzes that the type of data input to the model includes high-speed data, the model determines whether to execute the grade analysis branch model based on the type of input data. If the model analyzes that the type of data input to the model belongs to DC data, the model determines whether to execute the data prediction branch model based on the type of input data. At this time, the grade analysis branch model obtains the grade corresponding to at least one DC data and at least one high-speed data by analyzing the nonlinear relationship between at least one DC data and at least one high-speed data.

[0051] In this embodiment, an initial chip multi-task fusion model is constructed to obtain various types of measured data of the VCSEL chip, and these measured data are input into the initial chip multi-task fusion model to analyze the linear or nonlinear relationship between the measured data, and the initial chip performance multi-task fusion model is continuously iterated and updated. In this way, a trained chip multi-task fusion model can be obtained by processing the chip test data, and the trained chip multi-task fusion model can analyze the linear relationship or nonlinear relationship of the performance test data input into the model to obtain the target performance prediction data of the chip or the performance level of the chip, thereby greatly reducing the time for testing the performance-related data of the chip and improving the efficiency of obtaining the performance-related data of the VCSEL chip, thereby efficiently and accurately obtaining the performance-related data of the chip and comprehensively evaluating the chip performance.

[0052] As mentioned above, the initial chip multi-task fusion model includes an input layer, two fully connected layers and an output layer connected in sequence. The two fully connected layers are connected by a function. The function includes a first function (such as a linear function) or a second function (such as an activation function). Among them, the linear function is used to perform arithmetic operations on the data input by the previous fully connected layer. The activation function is used to perform nonlinear operations on the data input by the previous fully connected layer. When the activation function is a ReLU function, the output of the activation function is equal to the input for positive input; for negative input, the output is zero.

[0053] Among them, the first fully connected layer is used to extract features from the measured data input to the initial chip multi-task fusion model, and the second fully connected layer is used to receive the features corresponding to the measured data after function processing and learn the decision boundary based on the features. In the first fully connected layer, each measured data is connected to each neuron of the layer and linearly transformed by the weight and bias of each neuron respectively. In this way, the features of the measured data input to the initial chip multi-task fusion model are extracted. The decision boundary refers to the boundary that distinguishes different categories in classification problems, or the function that predicts the target value in regression problems. The features input to the second fully connected layer are further combined and transformed to generate the final output. In the second fully connected layer, the network defines the decision boundary by learning weights and biases. This can be achieved by optimizing the loss function, which is used to measure the difference between the model prediction and the actual label.

[0054] In this embodiment, by connecting two fully connected layers through a function, the function includes a linear function or an activation function, so that the trained chip multi-task fusion model can capture the linear relationship between input data based on the linear function to obtain output data, or capture the nonlinear relationship between input data based on the activation function to obtain output data, thereby realizing the versatility of the model.

[0055] In some embodiments, when two fully connected layers are connected by a linear function, part of the test data is part of the DC data. The model is used to analyze the linear relationship between the measured data and output the target prediction data representing the high-speed performance of the chip to be tested based on the input part of the DC data.

[0056] When the model is used to predict target prediction data of a chip, the partial DC data is at least one DC data measured by the chip. The target prediction data is high-speed data. In this way, the relationship between DC data and high-speed data is captured by a linear function, so that the high-speed data can be obtained by using the model after the DC data is measured, which can reduce the complex test steps for testing high-speed data of the chip and shorten the time to obtain various performance data of the chip.

[0057] In some embodiments, when two fully connected layers are connected through an activation function, part of the test data is partial DC data and / or partial high-speed data. The model is used to analyze the nonlinear relationship between the measured data and output target level data representing the performance level of the chip to be tested based on the input partial DC data and / or partial high-speed data.

[0058] Among them, when the model is used to predict the target grade data of a chip, that is, when the chip is graded, part of the DC data and / or part of the high-speed data is at least one DC data and / or at least one high-speed data measured by executing the test steps on the chip. The target grade data refers to the performance grade of the chip, such as the first level and the second level mentioned above. In this way, the nonlinear relationship between the DC data and / or the high-speed data and the chip grade is captured by a nonlinear function, so that the model can be used to obtain the performance grade of the chip according to the input DC data and / or high-speed data, thereby improving the efficiency of analyzing the chip grade and facilitating the determination of the chip grade in large quantities.

[0059] In some embodiments, when training the model based on the data input to the initial chip multi-task fusion model, the correlation between different types of measured data can be obtained by adjusting the parameters of each network layer in the model. In this way, when applying the model, some types of test data are input to the model and combined with the parameters of each network layer to obtain other types of test data.

[0060] The training process of the model for predicting target performance data by analyzing the correlation between various measured data can be found in the following content.

[0061] like Figure 2 and Figure 3 As shown, in some embodiments, the step of importing a plurality of different types of measured data into the initial chip multi-task fusion model to analyze the correlation between the measured data includes steps S202 to S212. Among them:

[0062] Step S202 , classifying the multiple different types of measured data into measured DC data and measured high-speed data according to their types.

[0063] Step S204: input the measured DC data into the first fully connected layer to obtain multiple features corresponding to the measured DC data.

[0064] Step S206: input the multiple features into the linear function respectively to obtain multiple linear outputs corresponding to the multiple features.

[0065] Step S208, inputting the multiple linear outputs into the second fully connected layer to obtain a feature representation corresponding to the measured DC data.

[0066] Step S210, inputting the feature representation to the output layer to obtain target prediction data through the output layer.

[0067] Step S212, based on the difference between the target prediction data and the measured high-speed data, obtain the correlation between the measured DC data and the measured high-speed data.

[0068] The measured DC data refers to the DC data of the chip obtained by actually testing each chip, such as threshold current, series resistance, etc. The measured high-speed data refers to the high-speed data of the chip obtained by actually testing each chip, such as eye diagram value, 3D bandwidth, etc.

[0069] Exemplarily, in order to enable the trained chip multi-task fusion model to predict the high-speed data of the chip based on the DC data of the chip, after the various different types of measured data are imported into the initial chip multi-task fusion model, the various different types of measured data can be divided into measured DC data and measured high-speed data according to their types. Among them, the measured high-speed data is used as label data, which is used to adjust the parameters of the initial chip multi-task fusion model based on the difference between the target prediction data predicted by the initial chip multi-task fusion model based on the measured DC data, so as to obtain the correlation between the measured DC data and the measured high-speed data, and then obtain the trained chip multi-task fusion model. In the process of the initial chip multi-task fusion model obtaining the target prediction data based on the measured DC data, the measured DC data will first be input into the first fully connected layer through the input layer to obtain multiple features corresponding to the measured DC data. That is, the first fully connected layer performs feature extraction on the measured DC data. If there are multiple types of measured DC data input to the model, feature extraction is performed on multiple types of measured DC data. Figure 3As shown, the first fully connected layer includes multiple neurons. Each neuron extracts features from at least one measured DC data input to the model, and obtains features corresponding to each neuron in the first fully connected layer. These features are then input into linear functions, which perform digital operations on these features to obtain linear outputs corresponding to each feature. The linear output corresponding to each feature is then input into the corresponding second fully connected layer. The second fully connected layer also includes multiple neurons. Each neuron processes the obtained linear output, for example, by combining features, to obtain a feature representation corresponding to each linear output. In this way, multiple feature representations of the output of the second fully connected layer have been obtained. If there is only one measured high-speed data, there is only one corresponding output neuron in the output layer. The output neurons can process these feature representations to obtain target prediction data. If there are multiple measured high-speed data, there are multiple corresponding output neurons in the output layer (refer to Figure 3 ). At this time, each output neuron corresponds to a high-speed data that needs to be predicted. Each output neuron stores a processing strategy for the feature representation. In this way, each output neuron can obtain corresponding target prediction data based on all feature representations. For example, the first output neuron is used to predict the eye diagram value. The second output neuron is used to predict the 3D bandwidth. During the training process, the model may not know how to process the input measured DC data. Since the purpose of the model is to analyze the correlation between the measured DC data and the measured high-speed data, the parameters in the model can be adjusted based on the difference between the target prediction data and the measured high-speed data, so that after the measured DC data is processed by the parameters in the model, the target prediction data consistent with the measured high-speed data can be predicted, or the target prediction data with a difference within a preset range from the measured high-speed data can be predicted. The preset range is close to 0. In this way, through this embodiment, the correlation between the measured DC data and the measured high-speed data can be obtained based on the model analysis, so that the accurate high-speed data of the chip can be quickly obtained after the simple DC data test of the chip is performed, reducing the complex high-speed data test of the chip, and thus improving the efficiency of obtaining the performance data of the chip.

[0070] It is understandable that after the data is input into the model, each network layer in the model will use its own parameters to process the data. The network layer includes a first fully connected layer, a linear function, and a second fully connected layer. Therefore, in some embodiments, based on the difference between the target prediction data and the measured high-speed data, the correlation between the measured data is obtained, including: based on the difference between the target prediction data and the measured high-speed data, adjusting the weights and biases of the first fully connected layer, the linear function, and the second fully connected layer to obtain the correlation between the measured data. Among them, the weight is a parameter that is multiplied by the data input to the network layer. The bias is a parameter that is added or subtracted from the data input to the network layer.

[0071] In this embodiment, by adjusting the weights and bias of the first fully connected layer, the linear function, and the second fully connected layer, the difference between the target prediction data and the measured high-speed data can be reduced, so that when the target prediction data is basically consistent with the measured high-speed data, the correlation between the DC data and the high-speed data of the chip can be determined.

[0072] like Figure 4 and Figure 5 As shown, in some embodiments, in order to analyze the level of the chip, a plurality of different types of measured data are imported into the initial chip multi-task fusion model to analyze the correlation between the measured data, and the step also includes steps S402 to S412. Among them:

[0073] Step S402 , classifying the various types of measured data into measured chip data and measured levels according to their types.

[0074] The measured chip data includes measured DC data and / or measured high-speed data.

[0075] Step S404: input the measured chip data into the first fully connected layer to obtain multiple features corresponding to the measured chip data.

[0076] Step S406: Input the multiple features into the activation function respectively to obtain multiple nonlinear outputs corresponding to the multiple features.

[0077] Step S408, inputting the multiple nonlinear outputs into the second fully connected layer to obtain feature representation corresponding to the measured chip data.

[0078] Step S410, inputting the feature representation to the output layer to obtain the target level through the output layer.

[0079] Step S412, based on the difference between the target level and the measured level, obtain the correlation between the measured chip data and the measured level.

[0080] Since the relationship between the performance data of a chip and the grade data of the chip may be nonlinear, the grade analysis branch model processes data based on an activation function, which is different from the branch model for predicting target performance data. Optionally, the activation function may be a ReLU function or a tanh function.

[0081] Exemplarily, in order to enable the trained chip multi-task fusion model to analyze the performance level of the chip based on the chip's DC data and / or high-speed data, after the various different types of measured data are imported into the initial chip multi-task fusion model, the various different types of measured data can be divided into measured chip data and measured levels according to their types. Among them, the measured level is used as label data, which is used to adjust the parameters of the initial chip multi-task fusion model based on the difference between the target level obtained by the initial chip multi-task fusion model based on the analysis of the measured chip data, so as to obtain the correlation between the measured chip data and the measured level, and then obtain the trained chip multi-task fusion model. In the process of the initial chip multi-task fusion model obtaining the target prediction data based on the measured DC data, the measured chip data will first be input into the first fully connected layer through the input layer to obtain multiple features corresponding to the measured chip data. That is, the first fully connected layer performs feature extraction on the measured chip data. If there are multiple types of measured chip data input to the model, feature extraction is performed on multiple types of measured chip data. Figure 3 As shown, the first fully connected layer includes multiple neurons. Each neuron extracts features from at least one measured chip data input to the model, and obtains features corresponding to each neuron in the first fully connected layer. These features are then input to the activation function, which performs nonlinear processing on these features to obtain linear outputs corresponding to each feature. For example, features corresponding to features greater than zero are processed by the activation function and the feature itself is output. Features corresponding to features less than zero are processed by the activation function and the feature corresponding to zero is output. Then the nonlinear output corresponding to each feature is input to the corresponding second fully connected layer. The second fully connected layer also includes multiple neurons. Each neuron processes the obtained nonlinear output, such as performing feature combination, to obtain a feature representation corresponding to each nonlinear output. In this way, multiple feature representations of the output of the second fully connected layer have been obtained. Since the performance level of the chip should be one, there is only one corresponding output neuron in the output layer (refer to Figure 5). The output neurons can process these feature representations to obtain the target level. During the training process, the model may not know how to process the input measured chip data to analyze the level of the chip. Since the purpose of the model is to analyze the correlation between the measured chip data and the measured level, the parameters in the model can be adjusted based on the difference between the target level and the measured chip data, so that after the measured chip data is processed by the parameters in the model, the target level consistent with the measured level can be analyzed. In this way, through this embodiment, the correlation between the measured chip data and the measured level can be obtained based on the model analysis, thereby reducing the energy consumed by manpower to analyze the chip performance data and classify the chips, reducing the errors introduced by humans, and improving the efficiency and speed of classifying the chips. And the model analyzes the measured chip data and the measured levels of a large number of chips, and the correlation between the measured chip data and the measured levels can accurately analyze the chip level based on the chip performance data.

[0082] Optionally, based on the difference between the target level and the measured level, the correlation between the measured chip data and the measured level is obtained, including: based on the difference between the target level and the measured level, adjusting the weights and biases of the first fully connected layer and the second fully connected layer to obtain the correlation between the measured chip data and the measured level. Among them, the weight is a parameter multiplied by the data input to the network layer. The bias is a parameter added or subtracted from the data input to the network layer. In this embodiment, by adjusting the weights and biases of the first fully connected layer and the second fully connected layer, the target level and the measured level can be made consistent, thereby determining the correlation between the DC data and high-speed data of the chip.

[0083] In some embodiments, before importing various types of measured data into the initial chip multi-task fusion model, the measured data may be preprocessed to ensure the quality and usability of the measured data. The preprocessing steps include: data cleaning, data standardization, data enhancement, etc.

[0084] In some embodiments, determining the difference between the target level and the measured level or determining the difference between the target predicted data and the measured high-speed data can be determined based on a corresponding loss function. During the training process, a suitable optimizer and loss function should be selected to ensure the convergence and accuracy of the model. After the training is completed, that is, after the trained chip multi-task fusion model is obtained, the model can also be verified based on the measured data of some chips to evaluate the performance of the model.

[0085] In some embodiments, the trained chip multi-task fusion model can also evolve by adding data from newly designed chips (iterative, upgraded versions of the chips used in training) to better evaluate and predict the performance of the new design.

[0086] Through the above training of the model, the trained model can match the data input to the model. If the DC data of the chip is input to the model, the model can output high-speed data for predicting the chip. If the data input to the model includes high-speed data of the chip, the model can output the performance level obtained by analyzing the data of the chip. By training the model with the test data of the measured chip, the test data can be fully justified and analyzed, and the correlation between various performance data can be analyzed. The accuracy and efficiency of the obtained performance data can also be improved through the model.

[0087] It should be understood that, although the various steps in the flowcharts involved in the above-mentioned embodiments are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps does not have a strict order restriction, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above-mentioned embodiments can include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0088] Based on the same inventive concept, the embodiment of the present application also provides a VCSEL chip test data processing device for implementing the VCSEL chip test data processing method involved above. The implementation scheme for solving the problem provided by the device is similar to the implementation scheme recorded in the above method, so the specific limitations in the embodiments of the test data processing device for one or more VCSEL chips provided below can refer to the limitations of the VCSEL chip test data processing method above, and will not be repeated here.

[0089] In an exemplary embodiment, Figure 6 As shown, a training device for a chip performance prediction model is provided, comprising: a construction module 601, an acquisition module 602, a training module 603 and a prediction module 604, wherein:

[0090] The construction module 601 is used to construct an initial chip multi-task fusion model.

[0091] The acquisition module 602 is used to acquire various types of measured data that directly or indirectly characterize the high-speed performance of the VCSEL chip.

[0092] The training module 603 is used to import various types of measured data into the initial chip multi-task fusion model to analyze the linear or nonlinear relationship between the measured data, and continuously iterate and update the initial chip multi-task fusion model to obtain a trained chip multi-task fusion model.

[0093] The prediction module 604 is used to obtain partial performance test data of the VCSEL chip to be detected, and input the partial performance test data into the trained chip multi-task fusion model; the trained chip multi-task fusion model outputs the target performance prediction data of the VCSEL chip to be detected according to the analyzed linear relationship between the partial performance test data, or outputs the performance level of the VCSEL chip to be detected according to the analyzed nonlinear relationship between the partial performance test data.

[0094] In some embodiments, the initial chip multi-task fusion model includes an input layer, two fully connected layers and an output layer connected in sequence; the two fully connected layers are connected by a function; the first fully connected layer is used to extract features of the measured data input into the initial chip multi-task fusion model, and the second fully connected layer is used to receive the features corresponding to the measured data after function processing and perform decision boundary learning based on the features.

[0095] In some embodiments, the function comprises a linear function or an activation function.

[0096] In some embodiments, when two fully connected layers are connected by a linear function, part of the test data is partial DC data, and the model is used to analyze the linear relationship between the measured data, and output target prediction data representing the high-speed performance of the chip to be tested based on the input partial DC data; wherein the target prediction data is high-speed data.

[0097] In some embodiments, when two fully connected layers are connected through an activation function, part of the test data is partial DC data and / or partial high-speed data. The model is used to analyze the nonlinear relationship between the measured data and output target level data representing the performance level of the chip to be tested based on the input partial DC data and / or partial high-speed data.

[0098] In some embodiments, the measured data directly characterizing the high-speed performance of the VCSEL chip is high-speed data, and the measured data indirectly characterizing the high-speed performance of the VCSEL chip is DC data; the high-speed data includes at least one of 3dB bandwidth, relative intensity noise and TDECQ value; the DC data includes at least one of threshold current, series resistance, aperture diameter, slope efficiency, center wavelength and spectral width.

[0099] In some embodiments, the training module 603 is also used to: classify multiple different types of measured data into measured DC data and measured high-speed data according to their types; input the measured DC data into the first fully connected layer to obtain multiple features corresponding to the measured DC data; input the multiple features into the linear function respectively to obtain multiple linear outputs corresponding to the multiple features; input the multiple linear outputs into the second fully connected layer to obtain feature representations corresponding to the measured DC data; input the feature representations into the output layer to obtain target prediction data through the output layer; based on the difference between the target prediction data and the measured high-speed data, obtain the correlation between the measured DC data and the measured high-speed data.

[0100] In some embodiments, the training module 603 is also used to: adjust the weights and biases of the first fully connected layer, the linear function, and the second fully connected layer based on the difference between the target prediction data and the measured high-speed data to obtain the correlation between the measured data.

[0101] In some embodiments, the training module 603 is further used to: classify the multiple different types of measured data into measured chip data and measured levels according to the types, the measured chip data including measured DC data and / or measured high-speed data;

[0102] Inputting the measured chip data into the first fully connected layer to obtain multiple features corresponding to the measured chip data;

[0103] Input multiple features into the activation function respectively to obtain multiple nonlinear outputs corresponding to the multiple features;

[0104] Inputting the multiple nonlinear outputs into the second fully connected layer to obtain feature representations corresponding to the measured chip data;

[0105] Input the feature representation to the output layer to obtain the target level through the output layer;

[0106] Based on the difference between the target level and the measured level, the correlation between the measured chip data and the measured level is obtained.

[0107] In some embodiments, the training module 603 is also used to: adjust the weights and biases of the first fully connected layer and the second fully connected layer based on the difference between the target level and the measured level to obtain the correlation between the measured chip data and the measured level.

[0108] Each module in the test data processing device of the VCSEL chip can be implemented in whole or in part by software, hardware and a combination thereof. Each module can be embedded in or independent of a processor in a computer device in the form of hardware, or can be stored in a memory in a computer device in the form of software, so that the processor can call and execute operations corresponding to each module.

[0109] In an exemplary embodiment, a computer device is provided. The computer device may be a server, and its internal structure diagram may be as shown in FIG. Figure 7 As shown. The computer device includes a processor, a memory, an input / output interface (Input / Output, referred to as I / O) and a communication interface. Among them, the processor, the memory and the input / output interface are connected through a system bus, and the communication interface is connected to the system bus through the input / output interface. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store data for training and applying a chip performance prediction model. The input / output interface of the computer device is used to exchange information between the processor and an external device. The communication interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, a training method for a chip performance prediction model and a chip performance prediction method are implemented.

[0110] Those skilled in the art will understand that Figure 7 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0111] In an exemplary embodiment, a computer device is provided, including a memory and a processor, wherein a computer program is stored in the memory, and the processor implements the steps in any of the above-mentioned embodiments when executing the computer program.

[0112] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps in any of the above-mentioned embodiments are implemented.

[0113] In one embodiment, a computer program product is provided, including a computer program, which implements the steps in any of the above-mentioned method embodiments when executed by a processor.

[0114] A person of ordinary skill in the art can understand that all or part of the processes in the above-mentioned embodiment method can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to the memory, database or other medium used in the embodiments provided in the present application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The database involved in each embodiment provided in this application may include at least one of a relational database and a non-relational database. Non-relational databases may include distributed databases based on blockchains, etc., but are not limited to this. The processor involved in each embodiment provided in this application may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, an artificial intelligence (AI) processor, etc., but are not limited to this.

[0115] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0116] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A method for processing test data of a VCSEL chip, characterized in that: The method comprises: Constructing an initial chip multi-task fusion model; the initial chip multi-task fusion model includes an input layer, two fully connected layers and an output layer connected in sequence; wherein the two fully connected layers are connected by a function; the function includes a linear function or an activation function, the linear function is used to capture the linear relationship of the data input into the model, and the activation function is used to capture the nonlinear relationship of the data input into the model; Obtain various types of measured data that directly or indirectly characterize the high-speed performance of VCSEL chips; Importing the multiple different types of measured data into the initial chip multi-task fusion model to analyze the linear or nonlinear relationship between each of the measured data, and continuously iterating and updating the initial chip multi-task fusion model to obtain a trained chip multi-task fusion model; wherein the first fully connected layer is used to extract features of the measured data input to the initial chip multi-task fusion model, and the second fully connected layer is used to receive the features corresponding to the measured data after function processing and perform decision boundary learning based on the features; Acquire partial performance test data of the VCSEL chip to be detected, and input the partial performance test data into the trained chip multi-task fusion model; the trained chip multi-task fusion model outputs target performance prediction data of the VCSEL chip to be detected according to the analyzed linear relationship between the partial performance test data, or outputs the performance level of the VCSEL chip to be detected according to the analyzed nonlinear relationship between the partial performance test data; Among them, the chip multi-task fusion model includes a data prediction branch model and a level analysis branch model. The data prediction branch model is used to predict high-speed data based on DC data, and the level analysis branch model is used to analyze the performance level of the VCSEL chip to be detected based on the DC data and high-speed data of the VCSEL chip to be detected.

2. The test data processing method of the VCSEL chip according to claim 1, characterized in that: The measured data directly representing the high-speed performance of the VCSEL chip is high-speed data, and the measured data indirectly representing the high-speed performance of the VCSEL chip is DC data.

3. The test data processing method of the VCSEL chip according to claim 1, characterized in that: The high-speed data includes at least one of a 3 dB bandwidth, a relaxation oscillation frequency, a relative intensity noise, and a TDECQ value.

4. The test data processing method of the VCSEL chip according to claim 3, characterized in that: When two fully connected layers are connected by the linear function, the partial performance test data is partial DC data, and the model is used to analyze the linear relationship between the measured data, and output the target prediction data representing the high-speed performance of the VCSEL chip to be tested according to the input partial DC data; wherein the target prediction data is high-speed data.

5. The test data processing method of the VCSEL chip according to claim 3, characterized in that: When two fully connected layers are connected through the activation function, the partial performance test data is partial DC data and / or partial high-speed data, and the model is used to analyze the nonlinear relationship between the measured data, and output target level data representing the performance level of the VCSEL chip to be tested based on the input partial DC data and / or the partial high-speed data.

6. The test data processing method of the VCSEL chip according to claim 1, characterized in that: The DC data includes at least one of a threshold current, a series resistance, a through hole diameter, a slope efficiency, a central wavelength, and a spectrum width.

7. The test data processing method of the VCSEL chip according to claim 4, characterized in that: The step of importing the plurality of different types of measured data into the initial chip multi-task fusion model to analyze the correlation between the measured data includes: Classifying the multiple different types of measured data into measured DC data and measured high-speed data according to the type; Inputting the measured DC data into the first fully connected layer to obtain a plurality of features corresponding to the measured DC data; Inputting the plurality of features into the linear function respectively to obtain a plurality of linear outputs corresponding to the plurality of features; Inputting the plurality of linear outputs into the second fully connected layer to obtain a feature representation corresponding to the measured DC data; Inputting the feature representation into the output layer to obtain target prediction data through the output layer; Based on the difference between the target prediction data and the measured high-speed data, the correlation between the measured DC data and the measured high-speed data is obtained.

8. The test data processing method of the VCSEL chip according to claim 7, characterized in that: The obtaining the correlation between the measured data based on the difference between the target prediction data and the measured high-speed data includes: Based on the difference between the target prediction data and the measured high-speed data, the weights and biases of the first fully connected layer, the linear function, and the second fully connected layer are adjusted to obtain the correlation between the measured data.

9. The test data processing method of the VCSEL chip according to claim 5, characterized in that: The step of importing the plurality of different types of measured data into the initial chip multi-task fusion model to analyze the correlation between the measured data includes: Classifying the multiple different types of measured data into measured chip data and measured levels according to the types, wherein the measured chip data includes measured DC data and / or measured high-speed data; Inputting the measured chip data into the first fully connected layer to obtain a plurality of features corresponding to the measured chip data; Inputting the multiple features into the activation function respectively to obtain multiple nonlinear outputs corresponding to the multiple features; Inputting the plurality of nonlinear outputs into the second fully connected layer to obtain a feature representation corresponding to the measured chip data; Inputting the feature representation into the output layer to obtain a target level through the output layer; Based on the difference between the target level and the measured level, the correlation between the measured chip data and the measured level is obtained.

10. The test data processing method of the VCSEL chip according to claim 9, characterized in that: The obtaining, based on the difference between the target level and the measured level, the correlation between the measured chip data and the measured level comprises: Based on the difference between the target level and the measured level, the weights and biases of the first fully connected layer and the second fully connected layer are adjusted to obtain the correlation between the measured chip data and the measured level.

11. A test data processing device for a VCSEL chip, characterized in that: The test data processing device comprises: A construction module is used to construct an initial chip multi-task fusion model; the initial chip multi-task fusion model includes an input layer, two fully connected layers and an output layer connected in sequence; wherein the two fully connected layers are connected by a function; the function includes a linear function or an activation function, the linear function is used to capture the linear relationship of the data input into the model, and the activation function is used to capture the nonlinear relationship of the data input into the model; An acquisition module is used to acquire various types of measured data that directly or indirectly characterize the high-speed performance of the VCSEL chip; A training module, used for importing the multiple different types of measured data into the initial chip multi-task fusion model to analyze the linear or nonlinear relationship between each of the measured data, and continuously iteratively updating the initial chip multi-task fusion model to obtain a trained chip multi-task fusion model; wherein the first fully connected layer is used for extracting features of the measured data input into the initial chip multi-task fusion model, and the second fully connected layer is used for receiving the features corresponding to the measured data after function processing and performing decision boundary learning based on the features; A prediction module is used to obtain partial performance test data of a VCSEL chip to be detected, and input the partial performance test data into the trained chip multi-task fusion model; the trained chip multi-task fusion model outputs target performance prediction data of the VCSEL chip to be detected according to the linear relationship between the analyzed partial performance test data, or outputs the performance level of the VCSEL chip to be detected according to the nonlinear relationship between the analyzed partial performance test data; wherein the chip multi-task fusion model includes a data prediction branch model and a grade analysis branch model, the data prediction branch model is used to predict high-speed data based on DC data, and the grade analysis branch model is used to analyze the performance level of the VCSEL chip to be detected based on the DC data and high-speed data of the VCSEL chip to be detected.

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