Shaping filter and coefficient generation method, device, medium and program product thereof

Abstract

The present invention relates to the technical field of high-speed data transmission, and provides a coefficient generation method, device, shaping filter, storage medium and computer program product of a shaping filter, the method comprising: obtaining setting parameters input externally; performing even symmetric conversion and preprocessing on the setting parameters to obtain preprocessing parameters; combining with the Cordic algorithm, calculating the preprocessing parameters to obtain the first part of the calculated value, the second part of the calculated value and the third part of the calculated value respectively, and then calculating the final calculated value as the calculated value of half of the coefficient of the shaping filter; performing a folding operation on the calculated value of half of the coefficient of the shaping filter to obtain the calculated value of the coefficient of the shaping filter and output it. This scheme can adopt FPGA design, generate the shaping coefficient of the root raised cosine filter in real time based on the Cordic algorithm, and does not occupy the ROM storage resources of the FPGA, thereby improving the flexibility and performance of the shaping coefficient design of the root raised cosine filter.

Description

Technical Field

[0001] The present invention relates to the technical field of high-speed digital data transmission (DDT, radio high-speed data transmission), and in particular to a method, device, shaping filter, storage medium and computer program product for generating coefficients of a shaping filter, and in particular to a method, device, shaping filter, storage medium and computer program product for generating shaping filter coefficients in real time and arbitrarily settable based on a Cordic algorithm in high-speed data transmission. Background Art

[0002] Shaping filters are used in communication systems. In practical applications, shaping filters mainly have two functions: first, filtering the baseband signal; second, compressing the bandwidth of the transmission signal.

[0003] Digital baseband signals are square wave signals with abundant high-frequency components, which cannot be transmitted without distortion in the channel. The purpose of adding shaping filters is to filter out the high-frequency signals in the square wave so that the signal can be transmitted without errors in the channel. On the other hand, assuming that the baseband signal symbol rate (i.e., the number of symbols transmitted per second) is R, the bandwidth required for channel transmission in the MPSK (Multiple Phase Shift Keying) system is 2*R. However, if a shaping filter is added, the required transmission bandwidth is (1+δ)*R, where δ is the shaping coefficient of the shaping filter, and its value range is ∈「0, 1] (i.e., greater than 0 and less than or equal to 1). The bandwidth is compressed within 2*R, saving the channel width. It is an effective signal processing method in bandwidth-limited communication systems.

[0004] Based on the above characteristics, shaping filters are widely used in the field of high-speed data transmission. Shaping filters can be divided into two types, namely root raised cosine filters and raised cosine filters. The root raised cosine filter is mainly used in the field of high-speed data transmission, and the shaping coefficient design of the root raised cosine filter is a key link. However, due to the characteristics that FPGA chips are not good at calculating trigonometric functions, FPGA ROM has been used to store the calculated coefficients for a long time. However, due to the limited ROM resources, only limited coefficients can be stored, which has a great impact on the design flexibility and performance of the root raised cosine filter.

[0005] Therefore, there is an urgent need to develop a coefficient generation method, device, shaping filter, storage medium and computer program product for a shaping filter, and in particular, to develop a shaping filter coefficient generation method, device, shaping filter, storage medium and computer program product based on a Cordic algorithm in high-speed data transmission, which can generate shaping coefficients of a root raised cosine filter in real time based on the Cordic algorithm in high-speed data transmission and can be set arbitrarily. The invention can adopt FPGA design, generate shaping coefficients of a root raised cosine filter based on the Cordic algorithm in real time, and does not occupy the ROM storage resources of the FPGA, thereby greatly improving the flexibility and performance of the shaping coefficient design of the root raised cosine filter.

[0006] The above contents are only used to assist in understanding the technical solution of the present invention and do not constitute an admission that the above contents are prior art. Summary of the invention

[0007] The purpose of the present invention is to provide a coefficient generation method, device, shaping filter, storage medium and computer program product for a shaping filter, and more particularly to a method, device, shaping filter, storage medium and computer program product for generating shaping filter coefficients in real time and arbitrarily settable based on a Cordic algorithm in high-speed data transmission. The method can adopt FPGA design, generate shaping coefficients of a root raised cosine filter in real time based on the Cordic algorithm, and do not occupy the ROM storage resources of the FPGA, thereby greatly improving the flexibility and performance of the shaping coefficient design of the root raised cosine filter.

[0008] To solve the above technical problems, as one aspect of the present invention, a coefficient generation method for a shaping filter is provided, comprising the following steps: obtaining setting parameters of external input; the setting parameters include: coefficients of the shaping filter, order of the shaping filter, clock, sampling frequency, and data rate; performing even-symmetric conversion and preprocessing on the setting parameters to obtain preprocessing parameters; calculating the preprocessing parameters in combination with the Cordic algorithm to obtain a first part of the calculated value, a second part of the calculated value, and a third part of the calculated value, respectively; calculating a final calculated value based on the first part of the calculated value, the second part of the calculated value, and the third part of the calculated value as the calculated value of half of the coefficients of the shaping filter; performing a folding operation on the calculated value of half of the coefficients of the shaping filter to obtain and output the calculated value of the coefficients of the shaping filter.

[0009] According to an example embodiment of the present invention, the preprocessing parameters are calculated in combination with the Cordic algorithm to obtain the first part of the calculated values, the second part of the calculated values ​​and the third part of the calculated values, respectively, including: performing the first part of the calculation based on the Cordic algorithm according to the preprocessing parameters to obtain the first part of the calculated values; performing the second part of the calculation based on the Cordic algorithm according to the preprocessing parameters to obtain the second part of the calculated values; performing the third part of the calculation according to the preprocessing parameters to obtain the third part of the calculated values.

[0010] According to an exemplary embodiment of the present invention, performing a first part of calculation based on the Cordic algorithm according to the preprocessing parameters to obtain a first part of calculated values ​​includes: performing calculation using the following formula to obtain the first part of calculated values:

[0011] ;

[0012] Among them, Hd1 represents the first part of the calculated value, k1 represents the preset first calculation coefficient, R represents the coefficient of the shaping filter, f represents the data rate, fs represents the sampling frequency, and L represents the value of half the order of the shaping filter.

[0013] According to an exemplary embodiment of the present invention, performing the second part of calculation based on the Cordic algorithm according to the preprocessing parameters to obtain the second part of the calculated value includes: performing calculation using the following formula to obtain the second part of the calculated value:

[0014] ;

[0015] Among them, Hd2 represents the calculated value of the second part, k2 represents the preset second calculation coefficient, R represents the coefficient of the shaping filter, f represents the data rate, fs represents the sampling frequency, and L represents the value of half the order of the shaping filter.

[0016] According to an exemplary embodiment of the present invention, performing a third part of calculation according to the preprocessing parameters to obtain a third part of calculated values ​​includes: performing calculation using the following formula to obtain the third part of calculated values:

[0017] ;

[0018] Among them, Hd3 represents the calculated value of the third part, k3 represents the preset third calculation coefficient, R represents the coefficient of the shaping filter, f represents the data rate, fs represents the sampling frequency, and L represents the value of half the order of the shaping filter.

[0019] According to an exemplary embodiment of the present invention, calculating a final calculated value according to the first part of the calculated values, the second part of the calculated values, and the third part of the calculated values ​​includes: calculating using the following formula to calculate the final calculated value:

[0020] Hd(L)=(Hd1(L)+Hd2(L)) / Hd3(L);

[0021] Among them, Hd represents the final calculated value, Hd1 represents the first part of the calculated value, Hd2 represents the second part of the calculated value, Hd3 represents the third part of the calculated value, and L represents the filter order.

[0022] As a second aspect of the present invention, the present invention provides a coefficient generating device for a shaping filter, comprising: an acquisition unit, configured to acquire setting parameters of external input; the setting parameters include: the coefficient of the shaping filter, the order of the shaping filter, the clock, the sampling frequency, and the data rate; a control unit, configured to obtain preprocessing parameters after performing even-symmetric conversion and preprocessing on the setting parameters; the control unit is also configured to calculate the preprocessing parameters in combination with the Cordic algorithm to obtain a first part of the calculated value, a second part of the calculated value, and a third part of the calculated value, respectively; the control unit is also configured to calculate a final calculated value based on the first part of the calculated value, the second part of the calculated value, and the third part of the calculated value as the calculated value of half of the coefficient of the shaping filter; the control unit is also configured to perform a folding operation on the calculated value of half of the coefficient of the shaping filter to obtain and output the calculated value of the coefficient of the shaping filter.

[0023] According to an example embodiment of the present invention, the control unit, in combination with the Cordic algorithm, calculates the preprocessing parameters to obtain a first part of the calculated values, a second part of the calculated values ​​and a third part of the calculated values, respectively, including: performing a first part of the calculation based on the Cordic algorithm according to the preprocessing parameters to obtain a first part of the calculated values; performing a second part of the calculation based on the Cordic algorithm according to the preprocessing parameters to obtain a second part of the calculated values; performing a third part of the calculation based on the preprocessing parameters to obtain a third part of the calculated values.

[0024] According to an exemplary embodiment of the present invention, the control unit performs a first part of calculation based on the Cordic algorithm according to the preprocessing parameters to obtain a first part of the calculated value, including: using the following formula to calculate to obtain the first part of the calculated value:

[0025] ;

[0026] Among them, Hd1 represents the first part of the calculated value, k1 represents the preset first calculation coefficient, R represents the coefficient of the shaping filter, f represents the data rate, fs represents the sampling frequency, and L represents the value of half the order of the shaping filter.

[0027] According to an exemplary embodiment of the present invention, the control unit performs the second part calculation based on the Cordic algorithm according to the preprocessing parameters to obtain the second part calculation value, including: using the following formula to calculate to obtain the second part calculation value:

[0028] ;

[0029] Among them, Hd2 represents the calculated value of the second part, k2 represents the preset second calculation coefficient, R represents the coefficient of the shaping filter, f represents the data rate, fs represents the sampling frequency, and L represents the value of half the order of the shaping filter.

[0030] According to an exemplary embodiment of the present invention, the control unit performs the third part calculation according to the preprocessing parameter to obtain the third part calculation value, including: using the following formula to calculate to obtain the third part calculation value:

[0031] ;

[0032] Among them, Hd3 represents the calculated value of the third part, k3 represents the preset third calculation coefficient, R represents the coefficient of the shaping filter, f represents the data rate, fs represents the sampling frequency, and L represents the value of half the order of the shaping filter.

[0033] According to an exemplary embodiment of the present invention, the control unit calculates the final calculated value according to the first part of the calculated value, the second part of the calculated value and the third part of the calculated value, including: using the following formula to calculate and obtain the final calculated value:

[0034] ;

[0035] Among them, Hd represents the final calculated value, Hd1 represents the first part of the calculated value, Hd2 represents the second part of the calculated value, Hd3 represents the third part of the calculated value, and L represents the filter order.

[0036] As a third aspect of the present invention, the present invention provides a shaping filter, comprising: a coefficient generating device of the shaping filter described above.

[0037] As a fourth aspect of the present invention, the present invention provides a storage medium, which includes a stored program, wherein when the program is running, the device where the storage medium is located is controlled to execute the coefficient generation method of the shaping filter described above.

[0038] As a fifth aspect of the present invention, the present invention provides a computer program, which, when executed by a processor, implements the steps of the coefficient generation method of the above-mentioned shaping filter.

[0039] The beneficial effects of the present invention are:

[0040] The method of the present invention sets a calculation formula by combining a Cordic algorithm; after preprocessing the setting parameters of external input (such as the coefficient of the shaping filter, the order of the shaping filter, the clock, the sampling frequency, the data rate, etc.), FPGA design is adopted, and the calculation formula is used to calculate the first part calculation value Hd1, the second part calculation value Hd2 and the third part calculation value Hd3, and then the shaping coefficient of the root raised cosine filter is calculated to generate the shaping coefficient of the root raised cosine filter in real time without occupying the ROM storage resources of the FPGA, thereby greatly improving the flexibility and performance of the shaping coefficient design of the root raised cosine filter. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 A schematic flow chart of an embodiment of a method for generating coefficients of a shaping filter according to the present invention;

[0042] Figure 2 Rotate the vector graph for the angle;

[0043] Figure 3 The schematic diagram of the modelsim simulation of the Cordic algorithm outputting sine and cosine waves, where (a) is a screenshot of the two parameters and displayed values ​​of dout_cos and dout_sin of the Cordic algorithm, and (b) is a schematic diagram of the curve of the modelsim simulation of sine and cosine waves;

[0044] Figure 4 A table showing FPGA resource usage;

[0045] Figure 5 It is the ROM table;

[0046] Figure 6 Schematic diagram of the principle of a shaping filter coefficient generating device in an embodiment of the present invention;

[0047] Figure 7 for Figure 6 Schematic diagram of the implementation principle of the Cordic algorithm;

[0048] Figure 8It is a structural schematic diagram of an embodiment of a coefficient generating device of a shaping filter of the present invention.

[0049] Among them, 1—parameter preprocessing module, 2—M1 function calculation module, 3—M2 function calculation module, 4—G1 function normalization mapping module, 5—G2 function normalization mapping module, 6—Cordiccos(x) calculation module, 7—Cordicsin(x) calculation module, 8—Hd1 partial function calculation module, 9—Hd2 partial function calculation module, 10—Hd3 partial function calculation module, 11—Hd calculation module, 12—data output processing module, 13—quadrant mapping module, 14—rotation vector initialization assignment module, 15—vector rotation module, 16—quadrant selection output module, 17—multiple vector table modules stored in ROM table; 102—acquisition unit; 104—control unit. DETAILED DESCRIPTION

[0050] The following is a detailed description of embodiments of the present invention, but the present invention can be implemented in many different ways as defined and covered by the claims.

[0051] Considering that the Cordic (Coordinate Rotation Digital Computer) algorithm is a coordinate rotation digital calculation method, it was proposed by Jack E. Volder et al. in 1959. It is an algorithm for generating sine waves in digital signal processing. After a series of algorithms such as coordinate rotation and vector comparison, it finally outputs the algorithm of trigonometric functions.

[0052] Figure 2 is the angle rotation vector diagram. The vector rotation method can be as follows Figure 2 Clearly stated, is the initial angle vector, is the final position. and The initial value of the angle between is Z 0 , and then perform the first rotation to get the angle Z 1 And Z 1 >0, then rotate counterclockwise; the position after the second rotation is the same as The angle is Z 2 <0, then rotate clockwise; the position after the third rotation is the same as The angle is Z 3 >0, then rotate counterclockwise. The position after the fourth rotation is the same as The angle is Z 4 <0, rotate clockwise to reach the final position , we can see that after enough iterations, the vector and Basically coincident, realizing vector Angle rotation.

[0053] After several iterations the vector The coordinates of can finally be expressed as:

[0054] .

[0055] Among them, k≈1.647 can be ignored in hardware implementation, x n That is, the output function of cosine (cosθ), y n That is, the output function of sine (sinθ). i ,y i are the projection values ​​of the vector on the x-axis and y-axis after the i-th rotation, i.e., the coordinate values. k≈1.647 can be ignored in hardware implementation. n That is, after rotating n times, the final output vector is projected on the x-axis, that is, the output function of cosine (cosθ), y n That is, after rotating n times, the final output vector is the projection value on the y-axis, the output function of sine (sinθ). Figure 3 The output of the Cordic algorithm is a sine wave modelsim (i.e., HDL language simulation software) simulation, where (a) is a screenshot of the two parameters and displayed values ​​of the Cordic algorithm dout_cos and dout_sin, and (b) is a schematic diagram of the modelsim simulation curve of the sine wave and cosine wave. The two signals output by the Cordic algorithm are as follows Figure 3 As shown. Figure 3 In the figure (a), the two parameters dout_cos and dout_sin and the displayed values ​​are just the amplitude values ​​of the sine function and cosine function of the marked point in the current figure, that is, the trigonometric function value at a certain moment. That is, the y value in y=cos(x). The x value entered here is not captured, but x is a continuous value, taking the value [0,2Π], so y will continuously output a sine wave.

[0056] FPGA (Field-Programmable Gate Array) is a digital circuit design completed in a hardware description language such as Verilog (Verilog HDL is a hardware description language) or VHDL (VHDL is a high-level language used for circuit design). It can quickly design and build digital circuits, and repeatedly burn them into FPGA chips to realize various digital circuit functions.

[0057] In terms of shaping coefficient design of shaping filters (such as root raised cosine filters), due to the complexity of shaping filter (such as root raised cosine filter) coefficient implementation, the following two methods are generally used in FPGA-based system design in the field of high-speed data transmission for a long time:

[0058] The first method is software generation and sending to the chip for processing: this method can achieve real-time performance and any coefficient in the range of [0, 1] can be set, but it must rely on the computer system, which increases the system cost and complexity.

[0059] The second method is to store the filter coefficients in the FPGA's read-only memory (ROM): the filter coefficients can be generated in advance using tools such as MATLAB (MATLAB is a commercial mathematical software produced by MathWorks, USA, used in data analysis, wireless communications, deep learning, image processing and computer vision, signal processing, quantitative finance and risk management, robotics, control systems, etc.), and then stored in the FPGA's ROM and output when used. However, the ROM hardware storage space is limited, and this method can only store a limited set of filter coefficients, and cannot be set arbitrarily within the range of [0, 1].

[0060] Therefore, the scheme of the present invention proposes a coefficient generation method for a shaping filter, and in particular, relates to a method for generating shaping filter coefficients in real time and arbitrarily setting them based on the Cordic algorithm in high-speed data transmission, and is mainly designed for root raised cosine filters. The root raised cosine filter coefficient generation method and implementation device designed by the scheme of the present invention adopt FPGA design, can generate filter coefficients in real time, and do not occupy the storage resources of FPGA; can realize arbitrary coefficient orders, shaping coefficients are in the range of [0, 1], and can be arbitrarily set while retaining 2 decimal places, that is, the shaping filter coefficient range is arbitrarily set within [0.01, 1.00]. Moreover, it does not rely on the computer system to calculate the filter coefficients, and only requires the host computer to send a limited number of parameters.

[0061] As a first embodiment of the present invention, a coefficient generation method of a shaping filter is provided, such as Figure 1 The flowchart of an embodiment of the method of the present invention is shown in FIG. The coefficient generation method of the shaping filter may include: steps S110 to S150.

[0062] At step S110, the setting parameters of the external input are obtained; the setting parameters include: the coefficient of the shaping filter, the order of the shaping filter, the clock, the sampling frequency, and the data rate. Among them, the coefficient of the shaping filter is such as the filter coefficient R, the order of the shaping filter is such as the filter order L1, the clock, the sampling frequency is such as the sampling rate fs, and the data rate is such as the data rate f. Among them, the clock is the working clock of the FPGA, the driving clock of the chip, and all signals are driven to work under this clock, which can be any frequency.

[0063] In step S120, even-symmetry conversion and preprocessing are performed on the setting parameters to obtain preprocessing parameters.

[0064] At step S130, the preprocessing parameters are calculated in combination with the Cordic algorithm to obtain the first part of the calculated values, the second part of the calculated values ​​and the third part of the calculated values, respectively. The first part of the calculated values ​​is such as the value of Hd1, the second part of the calculated values ​​is such as the value of Hd2, and the third part of the calculated values ​​is such as the value of Hd3.

[0065] In some implementations, the Cordic algorithm is combined in step S130 to calculate the preprocessing parameters, and the calculation process of obtaining the first part of the calculated value, the second part of the calculated value, and the third part of the calculated value respectively includes the following three calculation parts:

[0066] The first calculation part: according to the preprocessing parameters, the first calculation part is performed based on the Cordic algorithm to obtain the first calculation value (such as the value of Hd1).

[0067] In some embodiments, in the first calculation part, performing the first calculation based on the Cordic algorithm according to the preprocessing parameters to obtain the first calculation value includes: performing the calculation using the following formula to obtain the first calculation value:

[0068] ;

[0069] Among them, Hd1 represents the calculated value of the first part, k1 represents the preset first calculation coefficient (preferably k1 is 4), R represents the coefficient of the shaping filter, f represents the data rate (that is, the transmission rate of the data in the setting parameters), fs represents the sampling frequency, and L represents the value of half the order of the shaping filter.

[0070] The second calculation part: according to the preprocessing parameters, the second calculation part is performed based on the Cordic algorithm to obtain the second calculation value (such as the value of Hd2);

[0071] In some embodiments, in the second calculation part, performing the second calculation based on the Cordic algorithm according to the preprocessing parameters to obtain the second calculation value includes: performing the calculation using the following formula to obtain the second calculation value:

[0072] ;

[0073] Among them, Hd2 represents the calculated value of the second part, k2 represents the preset second calculation coefficient (preferably k2 is 4), R represents the coefficient of the shaping filter, f represents the data rate (that is, the transmission rate of the data in the setting parameters), fs represents the sampling frequency, and L represents the value of half the order of the shaping filter.

[0074] The third calculation part: according to the preprocessing parameters, the third calculation part is performed to obtain the third calculation value (such as the value of Hd3).

[0075] In some embodiments, in the third calculation part, performing the third calculation according to the preprocessing parameters to obtain the third calculation value includes: performing the calculation using the following formula to obtain the third calculation value:

[0076] ;

[0077] Among them, Hd3 represents the calculated value of the third part, k3 represents the preset third calculation coefficient (preferably k3 is 4), R represents the coefficient of the shaping filter, f represents the data rate (that is, the transmission rate of the data in the setting parameters), fs represents the sampling frequency, and L represents the value of half the order of the shaping filter.

[0078] At step S140, a final calculated value is calculated based on the first part of the calculated value, the second part of the calculated value and the third part of the calculated value, as the calculated value of half the coefficient of the shaping filter.

[0079] In some implementations, calculating the final calculated value according to the first part of the calculated value, the second part of the calculated value, and the third part of the calculated value in step S140 includes: using the following formula to calculate and obtain the final calculated value:

[0080] Hd(L)=(Hd1(L)+Hd2(L)) / Hd3(L);

[0081] Among them, Hd represents the final calculated value, Hd1 represents the first part of the calculated value, Hd2 represents the second part of the calculated value, Hd3 represents the third part of the calculated value, and L represents the filter order.

[0082] In step S150, a folding operation is performed on the calculated values ​​of half of the coefficients of the shaping filter to obtain the calculated values ​​of the coefficients of the shaping filter and output them.

[0083] The scheme of the present invention provides a scheme for generating and arbitrarily setting shaping filter coefficients based on the Cordic algorithm in high-speed data transmission in real time. The scheme adopts FPGA design and can generate required filter coefficients of arbitrary orders online in real time based on the Cordic algorithm, without relying on the computer environment and without storing the coefficients in advance. The algorithm is mainly implemented by the FPGA chip, and only a limited number of parameters need to be sent from a host computer. The ROM storage resources of the FPGA are not occupied, and only a multiplier, a divider, a shifter and the Cordic algorithm are needed to implement the algorithm.

[0084] Figure 6 FIG. 1 is a schematic diagram showing the principle of a shaping filter coefficient generating device in an embodiment of the present invention. Figure 6 The shaping filter coefficient generating device shown includes: a parameter preprocessing module 1, an M1 function calculation module 2, an M2 function calculation module 3, a G1 function normalization mapping module 4, a G2 function normalization mapping module 5, a Cordiccos(x) calculation module 6, a Cordicsin(x) calculation module 7, an Hd1 partial function calculation module 8, an Hd2 partial function calculation module 9, an Hd3 partial function calculation module 10, an Hd partial function calculation module 11, and a data output processing module 12. Among them, the parameter preprocessing module 1 is used to complete the reception, even-symmetry conversion and processing of external input parameters. The processed parameters are sent to the M1 function calculation module 2, the M2 function calculation module 3 and the Hd3 partial function calculation 10 respectively; the values ​​calculated by the M1 function calculation module 2 and the M2 function calculation module 3 are sent to the G1 function normalization module 4 and the G1 function normalization module 5 respectively, and finally sent to the Cordiccos(x) calculation module 6 and the Cordicsin(x) calculation module 7 respectively to complete the trigonometric function calculation under the Cordic algorithm, and the obtained results are sent to the Hd1 partial function calculation module 8 and the Hd2 partial function calculation module 9 respectively, and finally the obtained Hd1, Hd2, and Hd3 values ​​are sent to the Hd calculation module 11 to complete the final Hd calculation, and finally the obtained results are output after even-symmetry processing. In the scheme of the present invention, a method for generating and arbitrarily setting shaping filter coefficients based on the Cordic algorithm in high-speed data transmission in real time does not rely on a computer to calculate the filter coefficients. The algorithm is mainly implemented by an FPGA chip, and only a limited number of parameters need to be sent from a host computer. The ROM storage resources of the FPGA are not occupied, and only multipliers, dividers, shifters and the Cordic algorithm are required to implement it.

[0085] The scheme of the present invention provides a method and device for real-time generation and arbitrary setting of shaping filter coefficients based on Cordic algorithm in high-speed data transmission, and the device is composed of parameter preprocessing module 1, M1 function calculation module 2, M2 function calculation module 3, G1 function normalization mapping module 4, G2 function normalization mapping module 5, Cordiccos(x) calculation module 6, Cordicsin(x) calculation module 7, Hd1 part function calculation module 8, Hd2 part function calculation module 9, Hd3 part function calculation module 10, Hd part function calculation module 11, data output processing module 12, etc. The root raised cosine filter coefficient generation scheme provided by the scheme of the present invention adopts FPGA design, can generate filter coefficients in real time, does not occupy the ROM storage resources of FPGA, can realize arbitrary order of coefficients, and the shaping coefficients are within the range of [0, 1] and can be arbitrarily set while retaining 2 decimal places; and does not rely on the computer system to calculate the filter coefficients, and only requires the upper computer to send limited parameters.

[0086] Specifically, in the solution of the present invention, it is implemented by a shaping filter coefficient generating device, which can be specifically performed according to the following steps:

[0087] Step 1: Simplify the formula.

[0088] Impulse Response of Root Raised Cosine Filter h ( t ) is shown in formula (1):

[0089] (1).

[0090] Formula (1) is the time domain expression of the impulse response, where T is the symbol period of the data and is related to the data rate, T=1 / f, and f is the frequency of the data to be filtered. When the above time domain impulse response is sampled at fs, the time domain signal becomes a digital signal, and t / T becomes f / fs*L, where L is the number of discrete points sampled. The filter coefficients can be generated by formula (1), but it can also be seen that the filter generation polynomial is relatively complex. Since FPGA is good at processing logical operations such as "and", "or", and "not", but is not good at processing arithmetic operations such as "multiplication", "division", and trigonometric functions, the "multiplication" and "division" operations should be minimized. It is difficult for FPGA to directly implement the above formula. In actual projects, the only way is to use the method of storing the calculated filter coefficients in FPGA ROM in advance. However, this method will greatly consume the storage resources of FPGA and is only applicable to the method of fixed filter order and limited filter coefficients. In project projects that require filter coefficients to be arbitrarily set from 0.01 to 1.00, this cannot be achieved. The traditional solution can only use peripheral devices to calculate and then transmit the calculation results to FPGA. However, this solution is relatively complicated and cannot be applied to projects without a computer motherboard or requiring miniaturized equipment.

[0091] It can be seen that the generation of the above arbitrary shaping filter coefficients by FPGA will be conducive to the purpose of miniaturization of equipment and reduction of FPGA storage resources. However, in order to realize the online arbitrary setting of the above filter coefficients by FPGA, it is necessary to adapt formula (1). After the transformation, the formula is divided into three parts, as shown below:

[0092] (2);

[0093] (3);

[0094] (4).

[0095] Then the impulse response formula (1) of the root raised cosine filter is transformed into the following expression in the digital domain:

[0096] Hd(L)=(Hd1(L)+Hd2(L)) / Hd3(L) (5).

[0097] Where R is the shaping filter coefficient, f is the code rate, fs is the filter sampling rate, and L is the filter order, which is an integer in the range ∈[-L,L]. Cordiccos(x) represents the trigonometric function cos(x) implemented by the Cordic algorithm, and Cordicsin(x) represents the trigonometric function sin(x) implemented by the Cordic algorithm. Hd=h(t) is the digital expression of the impulse response; Hd1, Hd2, and Hd3 are the three parts of the decomposition, and L is the filter order.

[0098] The difficulty and feature of the scheme of the present invention lies in the algorithm implementation of Cordiccos(x). It is known that the value range of x in the trigonometric function cos(x) is ∈ (0, 2π), and the value range of cos(x) is ∈ (-1, 1). In the Cordiccos(x) module implemented by FPGA in the present invention, x is quantized to 16 bits, and the input range is 0~2 16 , the output range is -26980~26980, so it is necessary to map the input and output from mathematical theory to FPGA engineering implementation, and the implementation method is realized through normalization operation. In order to facilitate understanding and operation, formulas (2)~(4) are further simplified to obtain:

[0099] Assumptions:

[0100] (6);

[0101] (7).

[0102] Further transformation yields:

[0103] (8);

[0104] (9).

[0105] in:

[0106] (10);

[0107] (11).

[0108] Since the theoretical formula G1 needs to be normalized before it can be implemented using FPGA, formulas (8) and (9) are further normalized to obtain:

[0109] (12);

[0110] (13).

[0111] Then formulas (2) to (4) are transformed into the following expressions:

[0112] (14);

[0113] (15).

[0114] Therefore, the key part of Hd1 and Hd2 becomes the solution of Cordiccos(Y1) and Cordicsin(Y2).

[0115] Step 2: Input parameter preprocessing.

[0116] The input parameters include the filter parameter R and the filter length L1. Because two decimal places are required, R is the parameter amplified 100 times, and the value range is ∈[1,100]. Because the filter is evenly symmetrical, only half of the filter length needs to be calculated, so the filter length after transformation is L=L1 / 2. For example: Figure 6 The parameter preprocessing module 1 shown is implemented.

[0117] That is to say, L=L1 / 2, L is the length of the folded filter, and L1 is the input filter length parameter, which is also the actual length. Because the filter is even symmetrical, it is sufficient to calculate half of the length, and then fold it even symmetrically. For example: the calculated filter coefficients are as follows: 8 9 4 5 6 6 5 4 9 8. It can be seen that the coefficients are symmetrical, and the length L1=10, but only the coefficient length of L=L1 / 2=5 (L value∈1 2 3 4 5) is calculated, and the other half is filled in at the end.

[0118] Step 3: Calculation of M1 function.

[0119] From formula (10), we can see that In step 1, the filter coefficient R is a parameter that is amplified 100 times after retaining 2 decimal places, so M1 is further transformed:

[0120] (16).

[0121] The formulas are all integer operations, which can be completed by calling the addition, multiplication, and division devices. For example: Figure 6 The M1 function shown is implemented by calculation module 2.

[0122] Step 4: Calculation of M2 function.

[0123] From formula (11), we can see that As in the calculation of M1, R is a parameter that is magnified 100 times after retaining 2 decimal places, so M2 is further transformed:

[0124] (17).

[0125] The formulas are all integer operations, which can be completed by calling the addition, multiplication, and division devices. For example: Figure 6 The M2 function shown is implemented by calculation module 3.

[0126] Step 5: Normalization calculation of G1.

[0127] From formula (12), we can know that the normalization formula of G1 is: In FPGA implementation, M1 can be shifted left and amplified by 15 times. Figure 6 The G1 function normalized mapping module 4 shown is implemented.

[0128] Step 6: Normalization calculation of G2.

[0129] From formula (13), we can know that the normalized formula of G2 is: In FPGA implementation, M2 can be shifted left and amplified by 15 times. For example: Figure 6 The G2 function normalization mapping module 5 shown is implemented.

[0130] Step 7: Calculation of Cordiccos(x) and Cordicsin(x). For example: Figure 6 The Cordiccos(x) calculation module 6 and the Cordicsin(x) calculation module 7 shown are implemented.

[0131] Figure 7 for Figure 6 Schematic diagram of the implementation principle of the Cordic algorithm. Figure 7 It includes: quadrant mapping module 13, rotation vector initialization assignment module 14, vector rotation module 15, quadrant selection output module 16, and multiple vector table modules stored in ROM table 17. Among them, Cordiccos(x) calculation module 6 and Cordicsin(x) calculation module 7 are based on FPGA Cordic algorithm to realize calculation. The specific calculation process is as follows: the normalized calculation values ​​of G1 and G2 are input into the quadrant mapping module 13 of FPGA Cordic. For the convenience of calculation, all values ​​with a value range of (-65535~65535) in the 16-bit range are removed from the sign bit and mapped to the (0, π / 2) quadrant, with a value range of ∈ (0, 16283). The highest 2 sign bits are retained for use when output; the compressed value enters the rotation vector initialization assignment module 14, complete parameter initialization; after initialization, enter the vector rotation module 15, the rotation step is stored in the ROM table in advance, and the target angle value is compared after each rotation until the target angle value is reached. The final vector accumulation value, i.e., cos(x) and sin(x), is output; finally, the signal enters the quadrant selection output module 16. Because of the operation of the first step of quadrant mapping, the final vector accumulation value is restricted to the first quadrant. According to the symbol value stored in the first step of operation, the signal is restored to the real quadrant, and the final output is the Cordicsin(x) and Cordicscos(x) values ​​under FPGA. Figure 7 As shown, the Cordic module completes the calculation of trigonometric functions in four steps:

[0132] Step 1, quadrant mapping: Input the calculated values ​​of Y1 and Y2 into the Cordic calculation module of FPGA. The values ​​of Y1 and Y2 have been normalized and have been limited to the 16-bit range ∈ (-65535~65535). In this module, we use the vector rotation method to calculate the trigonometric function. We know that trigonometric functions can be divided into four quadrants: (0, π / 2), (π / 2, π), (π, 3π / 2), and (3π / 2, 2π). For the convenience of calculation, remove the sign bit of all values ​​and map them to the (0, π / 2) quadrant. The value range ∈ (0, 16283) is retained, and the highest 2 sign bits are retained for use when output. For example: Figure 7 The quadrant mapping module 13 is shown implemented.

[0133] Step 2: Initialize the rotation vector: Because the output is the sine and cosine functions, the angle is initialized, the cosine is assigned the maximum value 16383, and the sine is assigned the minimum value 0. For example: Figure 7 The rotation vector initialization assignment module 14 shown is implemented.

[0134] Step 3, vector rotation: After initialization, rotate from the initial value to the target value Y1, Y2. The rotation step is in the ROM table stored in advance. After each rotation, it is compared with the target angle value Y1 or Y2 until the target angle value Y1 or Y2 is reached. The final vector accumulation value is cos(x) and sin(x) output. For example: Figure 7 The vector rotation module 15 shown is implemented.

[0135] Step 4: Quadrant selection output: Because of the quadrant mapping operation in the first step, the final vector accumulation value is limited to the first quadrant. According to the symbol value stored in the first step, the signal can be restored to the real quadrant. Finally, the cos(x) and sin(x) values ​​are output. For example: Figure 7 The quadrant selection output module 16 is shown implemented.

[0136] Step 8: Calculation of Hd1, Hd2, and Hd3.

[0137] According to formulas (14), (15), and (4), the values ​​of Hd1, Hd2, and Hd3 are calculated respectively. It can be seen from the formulas that only simple addition, multiplication, and division operations are required. For example: Figure 6 The Hd1 partial function calculation module 8, Hd2 partial function calculation module 9, and Hd3 partial function calculation module 10 shown are implemented.

[0138] Step 9: Calculation of Hd.

[0139] According to formula (5), the final Hd value can be obtained by solving the three parts Hd1, Hd2, and Hd3. Figure 6 The Hd calculation module 11 shown is implemented.

[0140] Step 10: Data output processing.

[0141] According to the symmetry of the filter, the filter order is cut in half at the input, and a folding operation is performed at the output to fill in the remaining half of the coefficients to get the final result. Figure 6 The data output processing module 12 shown is implemented.

[0142] In the scheme of the present invention, the implementation process of the scheme of generating shaping filter coefficients in real time and arbitrarily settable based on the Cordic algorithm in high-speed data transmission includes: simplifying the impulse response formula of the root raised cosine filter in the relevant scheme, and adopting a simple digital simplified formula that is easy to implement in FPGA; decomposing the digital formula into four parts, Hd1, Hd2, Hd3, and Hd, and calculating them respectively; before the implementation of Hd1 and Hd2, external parameters are required to participate, and the external parameters are first processed, and then Hd1 and Hd2 are input to participate in the calculation; when calculating the Hd1 part, the intermediate result G1 is obtained after complex calculations such as addition, subtraction, multiplication, division, and shifting are performed according to the digital formula (2), and G1 is normalized and input into the Cordic algorithm. The dic calculation module performs trigonometric calculations to obtain the cos(x) function output; when calculating the Hd2 part, the intermediate result G2 is obtained after complex calculations such as addition, subtraction, multiplication, division, and shift are performed according to the digital formula (3). After G2 is normalized, it is input to the Cordic calculation module for trigonometric calculations to obtain the sin(x) function output; when calculating the Hd3 part, the output result is obtained after complex calculations such as addition, subtraction, multiplication, division, and shift are performed according to the digital formula (4); the results obtained by the Hd1, Hd2, and Hd3 modules are calculated according to formula (5) to obtain Hd; finally, the output result is subjected to scaling processing, even symmetry processing, and other operations, and finally output to obtain the root raised cosine filter coefficient output.

[0143] In the scheme of the present invention, the impulse response formula of the root raised cosine filter is modified, and a series of digital formulas that are beneficial to the digital processing of FPGA are invented; the normalization processing in the Cordic algorithm is utilized; the algorithm design in the Cordic algorithm implementation is simple, occupies less FPGA resources, and only requires a small amount of DSP, LUTRAM resources and LUT resources.

[0144] Figure 4 This is a table showing the FPGA resource usage. Figure 4In the example shown, LUT (Look Up Table): lookup table, usually called basic logic unit; LUTRAM (Look-Up Table Random Access Memory): lookup table random access memory, usually called distributed RAM; FF (Flip-Flop): trigger; DSP (Digital Signal Processing): digital signal processing unit; IO (Input / Output): module input and output pins. The final filter coefficients of this module are output in parallel; BUFG (Buffered Clock Gate): buffer. The root raised cosine filter coefficient generation scheme designed by the scheme of the present invention can generate filter coefficients in real time, and does not occupy the ROM storage resources of the FPGA, and only occupies a small amount of LUTRAM resources, such as Figure 4 As shown in the figure, any order of coefficients can be realized, and the shaping coefficients are within the range of [0, 1] and can be set arbitrarily while retaining 2 decimal places; and the filter coefficients are calculated independently of the computer system, and only limited parameters need to be sent from the host computer. Among them, LUTRAM, the full name of which is Look-Up Table Random Access Memory, is an important storage unit in FPGA (field programmable gate array).

[0145] The solution of the present invention also provides a processing solution implemented by G1, G2 and Cordic algorithm: The normalization processing of G1 and G2 adopts the formula: x=(M*2 16 ) / (2*π),2 16 is the input bit width of the Cordic module, that is, the maximum number of quantization bits that the Cordic module can process. The normalization of G1 and G2 uses the formula: G=(M*2 16 ) / (2*π),2 16 is the input bit width of the Cordic module, that is, the maximum number of quantization bits that the Cordic module can process, G is G1 or G2, and M is M1 or M2.

[0146] G is G1 or G2, and M is M1 or M2. In the calculation of G1 and G2, the order L originally takes a value range ∈ [-L, L]. Due to the even symmetry of the shaping filter coefficients, in order to save resources and simplify the design, only the values ​​in the range [0, L] are calculated, and even symmetry is padded in the final output. In the calculation of G1, because FPGA is not easy to process decimals, the numerical shaping coefficients in formula (6) are enlarged by 100 times, and then reduced by 100 times after the results are obtained.

[0147] When the Cordic module is calculating, the input data is firstly divided into quadrants and divided into 4 phase data according to the sign bit; then the vector to be rotated is initialized and assigned a value and input into the vector rotation module 15; the data after the quadrant division is used as the final vector, and in the vector rotation module 15, the initialization vector is calculated according to the ROM table (i.e. Figure 5 The angle value in the table shown in the figure is rotated, and the final vector is compared after each rotation. If there is an error with the final vector, the rotation will continue until the rotation is in place; the value processed by the phase rotation module is input into the quadrant selection output module 16, and different trigonometric function values ​​are output according to the sign bit of the data. For example: the ROM table can be composed of Figure 7 The ROM table shown stores a variety of vector table modules 17. In the vector rotation module 15, the initialization vector is rotated according to the angle value in the ROM table, and is compared with the final vector after each rotation.

[0148] The solution of the present invention has at least the following advantages:

[0149] 1. It does not rely on computers to calculate filter coefficients. The main FPGA chip is used to implement the algorithm, and only a limited number of parameters need to be sent from the host computer;

[0150] 2. It does not occupy the ROM storage resources of FPGA and only requires multipliers, dividers, shifters and Cordic algorithm to implement;

[0151] 3. The impulse response formula of the root raised cosine filter was modified, and a digital formula that is conducive to FPGA digital processing was invented;

[0152] 4. Normalization processing in the implementation of the Cordic algorithm is the key to converting theoretical formulas into FPGA engineering implementation;

[0153] 5. The algorithm design in the Cordic algorithm implementation is simple, occupies less FPGA resources, and only requires a small amount of MUT resources and LUT resources.

[0154] The technical solution of this embodiment is adopted, and the calculation formula is set by combining the Cordic algorithm; after preprocessing the setting parameters of the external input (such as the coefficient of the shaping filter, the order of the shaping filter, the clock, the sampling frequency, the data rate, etc.), FPGA design is adopted, and the calculation formula is used to calculate the first part calculation value Hd1, the second part calculation value Hd2 and the third part calculation value Hd3, and then the shaping coefficient of the root raised cosine filter is calculated to generate the shaping coefficient of the root raised cosine filter in real time without occupying the ROM storage resources of the FPGA, which greatly improves the flexibility and performance of the shaping coefficient design of the root raised cosine filter.

[0155] According to a second embodiment of the present invention, a coefficient generating device for a shaping filter corresponding to the coefficient generating method for the shaping filter is also provided. Figure 7 The schematic diagram of the structure of an embodiment of the device of the present invention is shown. The coefficient generation device of the shaping filter may include: an acquisition unit 102 and a control unit 104.

[0156] The acquisition unit 102 is configured to acquire external input setting parameters; the setting parameters include: the coefficient of the shaping filter, the order of the shaping filter, the clock, the sampling frequency, and the data rate. The coefficient of the shaping filter is such as the filter coefficient R, the order of the shaping filter is such as the filter order L1, the clock, the sampling frequency is such as the sampling rate fs, and the data rate is such as the data rate f. The specific functions and processing of the acquisition unit 102 refer to step S110.

[0157] The control unit 104 is configured to perform even-symmetry conversion and preprocessing on the setting parameters to obtain preprocessing parameters. The specific functions and processing of the control unit 104 refer to step S120.

[0158] The control unit 104 is further configured to calculate the preprocessing parameters in combination with the Cordic algorithm to obtain the first part of the calculated values, the second part of the calculated values ​​and the third part of the calculated values, respectively. The first part of the calculated values ​​is such as the value of Hd1, the second part of the calculated values ​​is such as the value of Hd2, and the third part of the calculated values ​​is such as the value of Hd3. The specific functions and processing of the control unit 104 are also referred to step S130.

[0159] In some implementations, the control unit 104 calculates the preprocessing parameters in combination with the Cordic algorithm to obtain the first part of the calculated values, the second part of the calculated values, and the third part of the calculated values, respectively, including:

[0160] The control unit 104 is further specifically configured to perform a first part of calculation based on the Cordic algorithm according to the preprocessing parameters to obtain a first part of calculated values ​​(such as the value of Hd1).

[0161] In some implementations, the control unit 104 performs the first part of the calculation based on the Cordic algorithm according to the preprocessing parameters to obtain the first part of the calculated value, including: the control unit 104 is further configured to use the following formula to perform the calculation to obtain the first part of the calculated value:

[0162] ;

[0163] Among them, Hd1 represents the calculated value of the first part, k1 represents the preset first calculation coefficient (preferably k1 is 4), R represents the coefficient of the shaping filter, f represents the data rate (that is, the transmission rate of the data in the setting parameters), fs represents the sampling frequency, and L represents the value of half the order of the shaping filter.

[0164] The control unit 104 is further specifically configured to perform a second part of calculation based on the Cordic algorithm according to the preprocessing parameters to obtain a second part of calculated values ​​(such as the value of Hd2).

[0165] In some implementations, the control unit 104 performs the second part of the calculation based on the Cordic algorithm according to the preprocessing parameters to obtain the second part of the calculated value, including: the control unit 104 is further configured to use the following formula to perform the calculation to obtain the second part of the calculated value:

[0166] ;

[0167] Among them, Hd2 represents the calculated value of the second part, k2 represents the preset second calculation coefficient (preferably k2 is 4), R represents the coefficient of the shaping filter, f represents the data rate (that is, the transmission rate of the data in the setting parameters), fs represents the sampling frequency, and L represents the value of half the order of the shaping filter.

[0168] The control unit 104 is further specifically configured to perform a third part of calculation according to the preprocessing parameters to obtain a third part of calculated values ​​(such as the value of Hd3).

[0169] In some implementations, the control unit 104 performs the third part calculation according to the preprocessing parameter to obtain the third part calculation value, including: the control unit 104 is further configured to use the following formula to perform the calculation to obtain the third part calculation value:

[0170] ;

[0171] Among them, Hd3 represents the calculated value of the third part, k3 represents the preset third calculation coefficient (preferably k3 is 4), R represents the coefficient of the shaping filter, f represents the data rate (that is, the transmission rate of the data in the setting parameters), fs represents the sampling frequency, and L represents the value of half the order of the shaping filter.

[0172] The control unit 104 is further configured to calculate a final calculated value according to the first part calculated value, the second part calculated value and the third part calculated value as the calculated value of half the coefficient of the shaping filter. The specific function and processing of the control unit 104 are also shown in step S140.

[0173] In some implementations, the control unit 104 calculates the final calculated value according to the first part of the calculated value, the second part of the calculated value, and the third part of the calculated value, including: the control unit 104 is further configured to use the following formula to calculate and obtain the final calculated value:

[0174] Hd(L)=(Hd1(L)+Hd2(L)) / Hd3(L);

[0175] Among them, Hd represents the final calculated value, Hd1 represents the first part of the calculated value, Hd2 represents the second part of the calculated value, Hd3 represents the third part of the calculated value, and L represents the filter order.

[0176] The control unit 104 is further configured to perform a folding operation on the calculated values ​​of half of the coefficients of the shaping filter to obtain and output the calculated values ​​of the coefficients of the shaping filter. The specific functions and processing of the control unit 104 are also shown in step S150.

[0177] The scheme of the present invention provides a scheme for generating and arbitrarily setting shaping filter coefficients based on the Cordic algorithm in high-speed data transmission in real time. The scheme adopts FPGA design and can generate required filter coefficients of arbitrary orders online in real time based on the Cordic algorithm, without relying on the computer environment and without storing the coefficients in advance. The algorithm is mainly implemented by the FPGA chip, and only a limited number of parameters need to be sent from a host computer. The ROM storage resources of the FPGA are not occupied, and only a multiplier, a divider, a shifter and the Cordic algorithm are needed to implement the algorithm.

[0178] Figure 6 FIG. 1 is a schematic diagram showing the principle of a shaping filter coefficient generating device in an embodiment of the present invention. Figure 6The shaping filter coefficient generating device shown includes: a parameter preprocessing module 1, an M1 function calculation module 2, an M2 function calculation module 3, a G1 function normalization mapping module 4, a G2 function normalization mapping module 5, a Cordiccos(x) calculation module 6, a Cordicsin(x) calculation module 7, an Hd1 partial function calculation module 8, an Hd2 partial function calculation module 9, an Hd3 partial function calculation module 10, an Hd partial function calculation module 11, and a data output processing module 12. Among them, the parameter preprocessing module 1 is used to complete the reception, even symmetry conversion and processing of external input parameters. The processed parameters are sent to the M1 function calculation module 2, the M2 function calculation module 3 and the Hd3 partial function calculation 10 respectively; the values ​​calculated by the M1 function calculation module 2 and the M2 function calculation module 3 are sent to the G1 function normalization module 4 and the G1 function normalization module 5 respectively, and finally sent to the Cordiccos(x) calculation module 6 and the Cordicsin(x) calculation module 7 respectively to complete the trigonometric function calculation under the Cordic algorithm, and the obtained results are sent to the Hd1 partial function calculation module 8 and the Hd2 partial function calculation module 9 respectively, and finally the obtained Hd1, Hd2, and Hd3 values ​​are sent to the Hd calculation module 11 to complete the final Hd calculation, and finally the obtained results are even symmetric processed and output. Among them, the parameter preprocessing module 1 specifically calculates L=L1 / 2 after receiving the filter length L1, and generates a vector value of length L under the control of the FPGA clock, that is, [1 2 3...L], which is sequentially input into the following modules for use. L only takes half the value of L1, which reduces the calculation amount of the subsequent modules by half, which will reduce resources and improve the operation rate. In the scheme of the present invention, the method of generating and arbitrarily setting the shaping filter coefficients based on the Cordic algorithm in high-speed data transmission does not rely on the computer to calculate the filter coefficients. The main FPGA chip implements the algorithm, and only a limited number of parameters need to be sent from the host computer; it does not occupy the ROM storage resources of the FPGA, and only requires a multiplier, a divider, a shifter and a Cordic algorithm to implement it.

[0179] The scheme of the present invention provides a method and device for real-time generation and arbitrary setting of shaping filter coefficients based on Cordic algorithm in high-speed data transmission, and the device is composed of parameter preprocessing module 1, M1 function calculation module 2, M2 function calculation module 3, G1 function normalization mapping module 4, G2 function normalization mapping module 5, Cordiccos(x) calculation module 6, Cordicsin(x) calculation module 7, Hd1 part function calculation module 8, Hd2 part function calculation module 9, Hd3 part function calculation module 10, Hd part function calculation module 11, data output processing module 12, etc. The root raised cosine filter coefficient generation scheme provided by the scheme of the present invention adopts FPGA design, can generate filter coefficients in real time, does not occupy the ROM storage resources of FPGA, can realize arbitrary order of coefficients, and the shaping coefficients are within the range of [0, 1] and can be arbitrarily set while retaining 2 decimal places; and does not rely on the computer system to calculate the filter coefficients, and only requires the upper computer to send limited parameters.

[0180] Since the processing and functions implemented by the device of this embodiment basically correspond to the embodiments, principles and examples of the aforementioned method, for the details not fully described in this embodiment, please refer to the relevant descriptions in the aforementioned embodiments, and no further elaboration will be made here.

[0181] According to a third embodiment of the present invention, there is provided a shaping filter corresponding to a coefficient generating device of a shaping filter, comprising: the above-mentioned coefficient generating device of the shaping filter.

[0182] Since the processing and functions implemented by the shaping filter of this embodiment basically correspond to the embodiments, principles and examples of the aforementioned device, for the details not fully described in this embodiment, please refer to the relevant descriptions in the aforementioned embodiments, and no further elaboration will be given here.

[0183] According to a fourth embodiment of the present invention, a storage medium corresponding to a coefficient generation method of a shaping filter is provided, wherein the storage medium includes a stored program, wherein when the program is running, the device where the storage medium is located is controlled to execute the coefficient generation method of the shaping filter described above.

[0184] Since the processing and functions implemented by the storage medium of this embodiment basically correspond to the embodiments, principles and examples of the aforementioned method, for the details not fully described in this embodiment, please refer to the relevant descriptions in the aforementioned embodiments, and no further elaboration will be made here.

[0185] According to a fifth embodiment of the present invention, a computer program product corresponding to a coefficient generation method of a shaping filter is provided, comprising a computer program, which implements the steps of the coefficient generation method of the shaping filter described above when executed by a processor.

[0186] Since the processing and functions implemented by the computer program product of this embodiment basically correspond to the embodiments, principles and examples of the aforementioned method, for the details not fully described in this embodiment, please refer to the relevant descriptions in the aforementioned embodiments and will not be repeated here.

[0187] In summary, it is easy for those skilled in the art to understand that, under the premise of no conflict, the above-mentioned advantageous methods can be freely combined and superimposed.

[0188] The above are only preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A method for generating coefficients of a shaping filter, characterized in that: include: Get the setting parameters of external input; The setting parameters include: coefficients of the shaping filter, the order of the shaping filter, clock, sampling frequency, and data rate; After performing even symmetry conversion and preprocessing on the setting parameters, preprocessing parameters are obtained; The preprocessing parameters are calculated in combination with the Cordic algorithm to obtain the first part of the calculated values, the second part of the calculated values ​​and the third part of the calculated values ​​respectively; According to the first part of the calculated values, the second part of the calculated values ​​and the third part of the calculated values, a final calculated value is calculated as the calculated value of half the coefficient of the shaping filter; wherein, according to the first part of the calculated values, the second part of the calculated values ​​and the third part of the calculated values, the final calculated value is calculated, including: using the following formula to calculate and obtain the final calculated value: Hd(L)=(Hd1(L)+Hd2(L)) / Hd3(L); Wherein, Hd represents the final calculated value, Hd1 represents the first part calculated value, Hd2 represents the second part calculated value, Hd3 represents the third part calculated value, and L represents the filter order; A folding operation is performed on the calculated values ​​of half of the coefficients of the shaping filter to obtain and output the calculated values ​​of the coefficients of the shaping filter.

2. The coefficient generation method of the shaping filter according to claim 1, characterized in that: In combination with the Cordic algorithm, the preprocessing parameters are calculated to obtain the first part of the calculated values, the second part of the calculated values ​​and the third part of the calculated values, respectively, including: According to the preprocessing parameters, a first part of the calculation is performed based on the Cordic algorithm to obtain a first part of the calculated value; According to the preprocessing parameters, the second part of the calculation is performed based on the Cordic algorithm to obtain the second part of the calculated value; The third part of calculation is performed according to the preprocessing parameters to obtain the third part of calculated values.

3. The coefficient generation method of the shaping filter according to claim 2, characterized in that: According to the preprocessing parameters, performing the first part of calculation based on the Cordic algorithm to obtain the first part of calculation values ​​includes: using the following formula to calculate to obtain the first part of calculation values: ； Among them, Hd1 represents the first part of the calculated value, k1 represents the preset first calculation coefficient, R represents the coefficient of the shaping filter, f represents the data rate, fs represents the sampling frequency, and L represents the value of half the order of the shaping filter.

4. The coefficient generation method of the shaping filter according to claim 2, characterized in that: According to the preprocessing parameters, performing the second part of calculation based on the Cordic algorithm to obtain the second part of calculation value includes: using the following formula to calculate to obtain the second part of calculation value: ； Among them, Hd2 represents the calculated value of the second part, k2 represents the preset second calculation coefficient, R represents the coefficient of the shaping filter, f represents the data rate, fs represents the sampling frequency, and L represents the value of half the order of the shaping filter.

5. The coefficient generation method of the shaping filter according to claim 2, characterized in that: Performing a third part of calculation according to the preprocessing parameters to obtain a third part of calculated values ​​includes: performing calculation using the following formula to obtain the third part of calculated values: ； Among them, Hd3 represents the calculated value of the third part, k3 represents the preset third calculation coefficient, R represents the coefficient of the shaping filter, f represents the data rate, fs represents the sampling frequency, and L represents the value of half the order of the shaping filter.

6. A coefficient generating device for a shaping filter, characterized in that: include: An acquisition unit configured to acquire externally input setting parameters; The setting parameters include: coefficients of the shaping filter, the order of the shaping filter, clock, sampling frequency, and data rate; A control unit is configured to perform even-symmetry conversion and preprocessing on the setting parameters to obtain preprocessing parameters; The control unit is further configured to calculate the preprocessing parameters in combination with the Cordic algorithm to obtain a first part of calculated values, a second part of calculated values, and a third part of calculated values ​​respectively; The control unit is further configured to calculate a final calculated value according to the first part of the calculated value, the second part of the calculated value, and the third part of the calculated value, as the calculated value of half the coefficient of the shaping filter; wherein the control unit calculates the final calculated value according to the first part of the calculated value, the second part of the calculated value, and the third part of the calculated value, including: using the following formula to calculate and obtain the final calculated value: Hd(L)=(Hd1(L)+Hd2(L)) / Hd3(L); Wherein, Hd represents the final calculated value, Hd1 represents the first part calculated value, Hd2 represents the second part calculated value, Hd3 represents the third part calculated value, and L represents the filter order; The control unit is further configured to perform a folding operation on the calculated values ​​of half of the coefficients of the shaping filter to obtain and output the calculated values ​​of the coefficients of the shaping filter.

7. A shaping filter, characterized in that: include: The coefficient generating device of the shaping filter as claimed in claim 6.

8. A storage medium, characterized in that: The storage medium includes a stored program, wherein when the program is executed, the device where the storage medium is located is controlled to execute the coefficient generation method of the shaping filter according to any one of claims 1 to 5.

9. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method for generating coefficients of a shaping filter according to any one of claims 1 to 5 are realized.

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