Method and system for realizing automatic generation of parameterized device based on interface

Abstract

The invention discloses a parameterized device automatic generation method and system based on an interface, a device is decomposed into a plurality of mutually associated components, a preset area is constructed by means of area creation, area reference and area transformation, and after a layer is bound to the preset area, the component of the device is obtained; construction parameters can be flexibly set when the area is constructed, and finally, all the components are spliced into a complete device. According to the method, parameterization of device design is realized, underlying codes do not need to be deeply mastered, the development time of the process suite is shortened, the development cost is reduced, and the device design efficiency is improved. Besides, parameters of a complete device or all components of the device are stored, templates are formed, so that parameter multiplexing is achieved, the device design efficiency is improved, the stored templates are converted into formats compatible with different platforms, parameterized devices can be automatically generated on the different platforms according to the exported parameters, and the device design efficiency is improved. And the device design efficiency and flexibility are improved.

Description

Technical Field

[0001] The present invention relates to the field of electronic design automation, and in particular to a method and system for automatically generating parameterized devices based on an interface. Background Art

[0002] In the development of integrated circuit process kits, the design of process kits usually requires professional R&D personnel to develop and edit them through code, and then import the code into the design tool for display to judge the accuracy of the development content. If there are errors that need to be modified, they will go back to the code development to patch them and verify and modify them repeatedly. This method is cumbersome and has high requirements for the code development capabilities of R&D personnel. In addition, for different process technologies, the same type of device process kits often need to be redeveloped and cannot be reused, resulting in a lot of time waste. Summary of the invention

[0003] The purpose of the present invention is to provide a method and system for automatically generating parameterized devices based on an interface, thereby shortening the development time of a process kit, reducing development costs, and improving efficiency.

[0004] The present invention provides a method for automatically generating a parameterized device based on an interface, the method comprising the steps of:

[0005] Create preset areas by using area creation, area reference and area transformation;

[0006] Binding layer attributes to the preset area to generate device components;

[0007] A plurality of the device components are spliced ​​together to form a complete device.

[0008] Furthermore, the region creation includes: creating a region according to input coordinate parameters and size parameters, wherein the coordinate parameters are used to determine a preset starting position, and the size parameters are used to determine the width and height of the region; and referencing the region after the region is created.

[0009] Furthermore, the area transformation includes performing at least one transformation operation of area filling, array referencing, array penetration, area edge expansion, area point expansion, area circularization, area maximization, area projection, area translation, area connection, area size expansion, area bounding box enclosing, area arraying, area union, area difference and area intersection on the area to form a preset area.

[0010] Furthermore, the layer attributes are bound to the preset area, and the generated device components include:

[0011] Binding layer information to the target area, wherein the layer information includes a layer type and a description tag;

[0012] A first graphic is placed in the target area.

[0013] Furthermore, the layer attributes are bound to the preset area, and the generated device components also include:

[0014] If the first graphic in the target area needs to be connected to the second graphic in other areas to be determined, the area to be determined is set according to the design rule, and after binding the layer information to the area to be determined, the second graphic is placed in the area to be determined;

[0015] A connection area is generated according to the design rule, and after the layer information is bound to the connection area, a third graphic for realizing physical connection is placed in the connection area, and the first graphic is connected to the third graphic through the second graphic.

[0016] Furthermore, based on the size and position of the target area, the size and position of the to-be-determined area and the connection area are automatically calculated according to the design rules.

[0017] Further, the first graphic, the second graphic and the third graphic are placed in front of the preset area, and the position parameters of the graphics are set; and CDF parameters corresponding to the first graphic, the second graphic and the third graphic are set.

[0018] Furthermore, after the CDF parameter is selected as the dynamic parameter, the first graph, the second graph or the third graph is copied respectively according to the dynamic parameter to generate a plurality of graphs having the same CDF parameter.

[0019] The present invention also provides a system for automatically generating parameterized devices based on an interface, the system comprising:

[0020] The target area creation module creates a preset area by means of area creation, area reference and area transformation;

[0021] A device component generation module, which places graphics in the preset area after binding layer attributes to the area, and connects the graphics to generate device components;

[0022] The complete device generation module is used to splice a plurality of the device components to form a complete device.

[0023] Compared with the prior art, the present invention has at least the following technical effects:

[0024] The device automatic generation method disclosed in the present invention decomposes a complex device into interrelated components. A preset region is constructed by using region creation, region reference and region transformation, and the device components are obtained after binding the preset region with a layer; when constructing the region, the construction parameters can be flexibly set, and finally, the various components are spliced ​​into a complete device. This method realizes the parameterization of device design without the need to deeply master the underlying code, effectively shortens the process kit development time, reduces development costs, and significantly improves device design efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 A simplified flow chart of a method for automatically generating a parameterized device based on an interface in an embodiment of the present invention;

[0026] Figure 2 A schematic diagram of the operations in the region transformation process and the components of the generating device in one embodiment of the present invention;

[0027] Figure 3 A schematic diagram of the regional position relationship of the gate portion of a MOS transistor device in an embodiment of the present invention;

[0028] Figure 4 It is a schematic diagram of the structure of a MOS tube device constructed in one embodiment of the present invention. DETAILED DESCRIPTION

[0029] The following is a description of a method and system for automatically generating parameterized devices based on an interface in conjunction with a schematic diagram of the present invention, wherein a preferred embodiment of the present invention is shown, and it should be understood that those skilled in the art can modify the present invention described herein while still achieving the beneficial effects of the present invention. Therefore, the following description should be understood as being widely known to those skilled in the art, and not as a limitation of the present invention.

[0030] The present invention is described in more detail in the following paragraphs by way of example with reference to the accompanying drawings. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the accompanying drawings are in very simplified form and in non-precise proportions, and are only used to facilitate and clearly assist in illustrating the purpose of the embodiments of the present invention.

[0031] Please refer to Figure 1 This embodiment provides a method for automatically generating parameterized devices based on an interface, the method comprising the steps of:

[0032] S1. Create a preset area by using area creation, area reference and area transformation;

[0033] S2. Binding layer attributes to the preset area to generate device components;

[0034] S3. Splicing a plurality of the device components to form a complete device.

[0035] The device automatic generation method disclosed in this embodiment decomposes complex devices into interrelated components. Use region creation, region reference and region transformation to construct preset regions, bind layers to preset regions to obtain device components; when constructing regions, construction parameters can be flexibly set, and finally, the components are spliced ​​into a complete device. This method realizes the parameterization of device design without the need to deeply master the underlying code, effectively shortens the process kit development time, reduces development costs, and significantly improves device design efficiency.

[0036] In this embodiment, the device includes various components in an integrated circuit, such as transistors, capacitors, and resistors.

[0037] In this embodiment, before step S1, it is necessary to first import the process design rule manual (DRM). A complete DRM file should include design rules, dependencies between various device components and layer information, and be stored in the system in an informationized manner.

[0038] Specifically, in step S1, the device is decomposed according to the device structure, so that any device is divided into multiple device components.

[0039] In a specific embodiment, for example, a custom MOS tube (transistor) device needs to be regionally decomposed. First, the device is analyzed according to the logical structure and can be decomposed into a middle body (i.e., the core area of ​​the semiconductor material, which may be the base area, the substrate, or the entire semiconductor body for different semiconductor devices), a first ring part, and a second ring part.

[0040] Furthermore, creating an area includes creating an area according to input coordinate parameters and size parameters, wherein the coordinate parameters are used to determine a preset starting position, and the size parameters are used to determine the width and height of the area; specifically, the area is a plane area, which can be an irregular plane area; or a regular plane area, such as a circular and rectangular regular plane area, preferably a rectangular area. The shape of the area can be based on the outlines of different component units of the device, or different shapes can be customized. In addition, after the area is created, the area is referenced.

[0041] Furthermore, in this embodiment, the area transformation includes: at least one transformation operation of array reference, area filling, area edge expansion, area point expansion, area circularization, area maximization, area projection, area translation, area connection, area size expansion, area bounding box enclosing, area arraying, union between areas, difference between areas and intersection between areas to form a preset area.

[0042] Please refer to Figure 2 ,Specifically, the region intersection operation is used to perform intersection operations on ,multiple regions to obtain overlapping regions.

[0043] The region union operation is used to merge multiple regions into a complete region.

[0044] The region difference operation is used to subtract one region from another to obtain the difference.

[0045] Array reference operations are used to select a portion of a specified range of rows and columns from a regularly arranged array area, or to merge and reorganize certain rows and columns, for example: converting one array into another, such as selecting 3x3 with odd subscripts in a 5x5 array, or merging certain columns in the horizontal direction into a 1x5 array.

[0046] The array penetration operation is used to cover another area within any specified row and column range of the array area.

[0047] The region edge extension operation is used to extend the four sides of the region outward by a preset distance to generate a new rectangular region.

[0048] The region point expansion operation is used to select a reference point at a specified row and column position in a regular array, and expand in a specified direction based on the point to form a new rectangular region.

[0049] The region ringization operation is used to simultaneously shrink the region inward and expand it outward by a preset distance to generate a ring-shaped region.

[0050] The region maximization operation is used to ensure that the width and height of the region are not less than the preset minimum size requirements. For example: based on the input rectangle, the inner distance is expanded inward and the outer distance is expanded outward to generate a rectangular ring.

[0051] The region projection operation is used to project a region onto a target region along a specified direction and optionally establish a connection between the projected region and the target region.

[0052] The region translation operation is used to translate the region by the specified horizontal and vertical displacement amounts.

[0053] The region connection operation is used to establish a connection region between a region and another region, and can be selectively extended to the interior of the target region to connect with the interior of another region.

[0054] The region size expansion operation is used to expand the boundaries of the region outward by a preset distance at the same time.

[0055] The region arraying operation is used to copy and arrange the region according to the specified number of rows, columns and spacing.

[0056] The area filling operation is used to fill the area with specified filler size, minimum spacing, and alignment.

[0057] The region bounding box enclosing operation is used to generate at least one graphic in the smallest rectangular region that can completely enclose the region.

[0058] Specifically, in the above transformation operation, the parameters in the operation can be automatically set according to the actual situation or defined according to the design rules. For example, the preset area is obtained according to the design rules or the length, width and height of the custom area, or the spacing between the custom areas, thereby ensuring that the line width and size of the preset area after the transformation meet the process requirements.

[0059] In the specific operation process, the above transformation operations can be used in combination to simultaneously realize the preliminary positional relationship between the regions in the device components and the definition of the preliminary size of the regions in the device components. For example, a region is first scaled, and the scaling factor is set, and then the scaled region is placed in a certain region. In addition, the above transformation operations can also be used alone to independently realize the positional relationship between the regions in the device components or the definition of the preliminary size of the regions in the device components.

[0060] For further information, please continue to refer to Figure 2 In step S2, layer attributes are bound to the preset area, and generating device components means binding layer information to the target area (i.e. Figure 2 and placing a first graphic matching the layer information in the target area (i.e. Figure 2 ). For example, to design a MOS tube gate structure, first bind layer information in the target area, such as binding the relevant information of the polysilicon (Poly) layer, and then place the corresponding graphics in the area, such as placing a graphic representing the MOS tube gate structure in the area.

[0061] Furthermore, if the first graphic in the target area needs to be connected to the second graphic in the other area to be determined, the area to be determined is set according to the design rule, the layer information is bound to the area to be determined, the second graphic is placed in the area to be determined, and a connection area is generated according to the design rule, and the layer information is bound to the connection area (i.e. Figure 2 Then, a third graphic (i.e., Figure 2 An example of placement compliance rule is shown), connecting the first graphic with the third graphic through the second graphic.

[0062] In this embodiment, the CDF parameter is selected as a dynamic parameter, and the plurality of graphs are set according to the dynamic parameter. Specifically, the dynamic parameter is a CDF parameter (Component Description File, component design file). Specifically, the CDF parameter includes parameters such as electrical characteristics, physical characteristics and environmental parameters of the device.

[0063] In a specific embodiment, the CDF parameters of the MOS tube gate include but are not limited to physical characteristic parameters such as gate material type (polysilicon / metal, etc.), gate oxide layer thickness, gate length (L), gate width (W), gate area (A), gate channel length, gate junction depth, channel doping concentration, substrate doping concentration, junction capacitance interface state density and surface roughness, as well as electrical characteristic parameters such as gate-source voltage (VGS), drain-source voltage (VDS), gate threshold voltage (Vth), transconductance (gm), output admittance (gd), drain current (ID), breakdown voltage (VBR), gate capacitance (Cg), input capacitance (Ciss), output capacitance (Coss), reverse transfer capacitance (Crss), gate charge (Qg), on-resistance (RDS(on)), subthreshold swing (SS), maximum transconductance point and saturation current (IDsat).

[0064] In a specific embodiment, if there are multiple graphics with the same CDF parameters in a region, multiple graphics with the same CDF parameters are automatically generated in the specified position in the region. If multiple graphics need to be connected with graphics in other regions, the connection area and the area to be determined (i.e. Figure 2 Create a sandwich array as shown).

[0065] In this embodiment, by changing the dynamic parameters, designers are allowed to automatically generate corresponding device graphics by adjusting parameter values ​​without repeated creation, and can automatically adapt parameters according to different process nodes and process corners, thereby improving design efficiency in scenarios such as standard cell library development, IP reuse, and process evaluation, and ensuring consistency of cross-process design.

[0066] In a specific embodiment, for example, to design a gate structure of a MOS tube, firstly, layer information is bound in a target area, such as binding relevant information of a polysilicon (Poly) layer, and then a corresponding graphic is placed in the area, such as placing a graphic representing the gate structure of the MOS tube in the area; if the graphic needs to be connected to other areas, the connection area is determined according to the design rules and the upper layer information is bound to the connection area, for example: binding relevant information of the metal layer, and placing metal wire wiring in the area, and then determining the position of the polysilicon contact hole according to the design rules, thereby determining the connection area, and then placing a third graphic above the connection area as a polysilicon contact hole, and finally physically connecting the gate of the MOS tube and the metal wire wiring through an intermediate connection structure (such as a polysilicon contact hole).

[0067] Please refer to Figure 3 , which is a schematic diagram of the connection relationship between the graphics corresponding to the gate part of the MOS device, reflects the electrical connection relationship between the gate 1 and the metal layer 2.

[0068] In a specific embodiment, please refer to Figure 2 , which is a schematic diagram of the connection relationship between the regions corresponding to the gate part of the MOS device, reflects the electrical connection relationship between the gate 1 and the metal layer 2.

[0069] Furthermore, the graphic is placed before the preset area, and the position parameters of the graphic are set (CreateInstance); and the CDF parameters corresponding to the graphic are set (Component Description Format).

[0070] Furthermore, in this embodiment, the size and position of the target area can be used as a reference to automatically calculate the size and position of the area to be determined and the connection area according to the design rule.

[0071] For example, see Figure 4, is the layer corresponding to the MOS tube device obtained after the S3 step. The gate 1 forms a capacitive coupling with the active area 4 to control the switching state of the transistor: the contact hole 3 forms an electrical connection with the source and drain located in the active area 4; the metal layer 2 contacts the active area 4 by filling the contact hole 3; the source and drain protection layer 5, as a part of the active area 4, together with the active area 4 constitutes the source and drain of the transistor. Among them, the design of the guard ring (Guard Ring) must meet the specific layer spacing rules between the wrapped target: the guard ring includes the source and drain protection layer 5 (SDP layer), and the spacing between the source and drain protection layer 5 and the active area 4 (AA layer) and the gate 1 (GT layer) must meet the minimum spacing requirement of 0.238um (this value is based on the SDPxAA_S and SDPxGT_S rules). Based on these spacing constraints, the specific size of the Guard Ring can be calculated: its width is equal to the width of the wrapped target plus the minimum spacing of 0.238um on both sides (i.e., target width + 2×0.238um), and the height is calculated in the same way; and the position of the Guard Ring can be calculated by the corresponding offset based on the position coordinates of the wrapped target and the required spacing value.

[0072] Furthermore, in step S3, the positional relationship of each of the device components includes: surrounding, one unit template completely surrounds another unit template; being surrounded, that is, one device component is completely surrounded by another device component; left-sticking / right-sticking, the edges of the two device components fit together; connected, the two device components are connected through a specific connecting line.

[0073] After completing step S3, a complete device can be derived and characteristic parameters of the complete device can be obtained.

[0074] Specifically, the characteristic parameters of the complete device include, but are not limited to, structural parameters such as length, width, and height of the device and each layer, and connection relationships between the layers of the device.

[0075] Furthermore, in this embodiment, a template may be exported after any step of S1-S3.

[0076] Specifically, the method systematically saves the basic structure information, parameterization definition, operation sequence, layer binding relationship, connection rules, CDF parameter configuration and other information of the device by exporting the template after any step, and classifies and manages them by device type, process node, functional module and design rule version; the template supports inheritance extension, combination nesting and cross-process migration, and integrates functions such as DRC rule checking, parameter verification, layer integrity and connection relationship verification, which can be applied to scenarios such as standard cell library development, customized device design, rapid prototyping and process transplantation evaluation, so as to achieve standardization and reuse of device design.

[0077] In addition, in this embodiment, after saving the templates of the various components of the device or the template of the complete device, the user can translate and export them, that is, translate the template into a compatible format of the target platform and then export it to the target platform, so that parameterized devices can be automatically generated on each platform based on the exported template.

[0078] In a specific embodiment, if SKILL language is used for device design, the template can be converted into SKILL; if Python language is used for device design, the template can be converted into Python.

[0079] By converting device design information into a template (intermediate representation) in a common format and then converting it into a format compatible with different platforms, parameterized devices can be automatically generated on different platforms, improving the efficiency and flexibility of device design.

[0080] To summarize, by using integrated circuits to implement automatic device generation of parameterized devices based on interfaces and methods, this embodiment provides users with the ability to quickly generate device templated process kits through simple interface operations without writing code, supports the reuse of different process technologies, and can convert design results into codes in multiple programming languages, thereby lowering the development threshold, shortening development time, reducing development costs, and improving design efficiency.

[0081] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A method for automatically generating parameterized devices based on an interface, characterized in that: Create preset areas by using area creation, area reference and area transformation; Binding layer attributes to the preset area to generate device components; A plurality of the device components are spliced ​​together to form a complete device.

2. The method for automatically generating parameterized devices based on an interface as claimed in claim 1, characterized in that: The region creation includes: creating a region according to input coordinate parameters and size parameters, wherein the coordinate parameters are used to determine a preset starting position, and the size parameters are used to determine the width and height of the region; Reference the zone after it has been created.

3. The method for automatically generating parameterized devices based on an interface as claimed in claim 2, characterized in that: The area transformation includes performing at least one transformation operation of area filling, array reference, array penetration, area edge expansion, area point expansion, area circularization, area maximization, area projection, area translation, area connection, area size expansion, area bounding box enclosing, area arraying, area union, area difference and area intersection on the area to form a preset area.

4. The method for automatically generating parameterized devices based on an interface as claimed in claim 1, characterized in that: Binding layer attributes to the preset area, generating device components including: Binding layer information to the target area, wherein the layer information includes a layer type and a description tag; A first graphic is placed in the target area.

5. The method for automatically generating parameterized devices based on an interface as claimed in claim 4, characterized in that: Binding layer attributes to the preset area, generating device components also includes: If the first graphic in the target area needs to be connected to the second graphic in other areas to be determined, the area to be determined is set according to the design rule, and after binding the layer information to the area to be determined, the second graphic is placed in the area to be determined; A connection area is generated according to the design rule, and after the layer information is bound to the connection area, a third graphic for realizing physical connection is placed in the connection area, and the first graphic is connected to the third graphic through the second graphic.

6. The method for automatically generating parameterized devices based on an interface as claimed in claim 5, characterized in that: The size and position of the target area are used as a reference, and the size and position of the area to be determined and the connection area are automatically calculated according to the design rules.

7. The method for automatically generating parameterized devices based on an interface as claimed in claim 5, characterized in that: Placing the first graphic, the second graphic and the third graphic in front of the preset area, and setting position parameters of the graphics; And, setting CDF parameters corresponding to the first graph, the second graph and the third graph.

8. The method for automatically generating parameterized devices based on an interface as claimed in claim 7, characterized in that: After the CDF parameter is selected as the dynamic parameter, the first graph, the second graph or the third graph is copied respectively according to the dynamic parameter to generate a plurality of graphs with the same CDF parameter.

9. A system for automatically generating parameterized devices based on an interface, characterized in that: The system comprises: The target area creation module creates a preset area by means of area creation, area reference and area transformation; A device component generation module, which places graphics in the preset area after binding layer attributes to the area, and connects the graphics to generate device components; The complete device generation module is used to splice a plurality of the device components to form a complete device.

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