Novel level conversion driving circuit and driving method

Abstract

The embodiment of the invention relates to a novel level conversion driving circuit and driving method, the circuit comprises a mainboard, a display panel and a target level conversion module, and the target level conversion module comprises at least one level converter; the mainboard is connected with one end of the level translator in the target level conversion module; the other end of the level converter in the target level conversion module is connected with the display panel; different types of level translators are selected according to the odd-even number time sequence requirement of the display panel or the 2line mode, and the purpose that the display panel flexibly drives and displays according to the special time sequence requirement is achieved. Therefore, time sequence support of various requirements of the display screen end can be realized, and the technical effects of flexible display and improvement of the driving refresh rate of the display screen are achieved.

Description

Technical Field

[0001] The embodiments of the present application relate to the technical field of level conversion control in a display driving process, and more particularly to a novel level conversion driving circuit and driving method. Background Art

[0002] In TV display panel driving, the level shifter IC is a very important component. In the full-function (with TCON IC) TCON board, the Level shifter IC and TCON IC cooperate to complete the GOA (Gate onarray, the scanning circuit is made on the glass, which is different from the early Gate COF architecture) driving timing for the display screen, including the start scanning signal STV, the row scanning clock signal CK, the GOA driving circuit direction control input signal LC1 / LC2, and the partial screen reset signal STV0 or Reset and other signals. In the TCON-less board, the system-level chip SOC (TCON function is integrated into the SOC) cooperates with the Level shifter IC to generate the GOA driving signal required by the display screen. In addition to receiving control signals or input signals from the SOC or TCON IC, the Level shifter IC requires normal power supply from the PMIC, such as VGH / VGL / DVDD3V3, etc., in order to ensure normal operation. Under normal power supply, the Level shifter IC is controlled by the input of the SOC or TCON IC, and combined with its own internal logic, it generates the driving timing required for a specific screen.

[0003] The functions of early level shifter ICs were relatively simple, mostly with one-input and one-output logic, and their logic was completely determined by the TCON IC or SOC. However, for GOA timing with more complex rules, a two-input and multiple-output level shifter IC may not be able to meet the needs.

[0004] In recent years, display panels have been developing in the direction of high refresh rate local control. HSR (through external drive, the refresh rate is improved, while sacrificing a certain resolution) panels are emerging in an endless stream. At the same time, in order to achieve cost reduction of the panel, a dual gate design is carried out on the basis of HSR to save half of the COF drive. The main problem encountered by panels with the above characteristics is the picture quality problem, and the most important factor affecting the picture quality is the charging time. In order to improve the charging time, various special GOA timings are required. These special GOA timings are difficult to drive using the currently widely used binary input and multiple output Level shifter ICs. Summary of the invention

[0005] In view of this, in order to solve the technical problem that the above-mentioned display panel cannot meet the timing requirements of odd-even timing or specific HSR mode, the embodiment of the present application provides a novel level conversion driving circuit and driving method.

[0006] In a first aspect, an embodiment of the present application provides a novel level conversion driving circuit, comprising:

[0007] A main board, a display panel and a target level conversion module, wherein the target level conversion module includes at least one level converter;

[0008] The mainboard is connected to one end of the level converter in the target level conversion module;

[0009] The other end of the level converter in the target level conversion module is connected to the display panel;

[0010] The mainboard is used to input a driving signal and a timing signal to the target level conversion module;

[0011] The target level conversion module is used to generate a driving signal after receiving the control signal and the timing signal input by the mainboard;

[0012] The display panel is used to drive the liquid crystal screen to display after receiving the driving signal input by the target level conversion module.

[0013] In a possible implementation manner, the target level conversion module includes at least one one-input and one-output level converter;

[0014] The one-input-one-output level converter comprises n signal input terminals and n signal output terminals, and one input terminal of the one-input-one-output level converter corresponds to one output terminal, and n is a positive integer greater than or equal to 1;

[0015] Each input end of the one-input-one-output level converter is connected to the n output ends of the mainboard, and each output end of the one-input-one-output level converter is connected to the n input ends of the display panel;

[0016] The one-input-one-output level converter is used to generate a first driving signal after receiving the first control signal and the first timing signal input by the mainboard;

[0017] The one-input-one-output level converter is also used to input a first driving signal to the display panel.

[0018] In a possible implementation manner, the target level conversion module includes at least one multi-input multi-output level converter, the number of input ports of each of the multi-input multi-output level converters is not completely the same, and the number of output ports of each of the multi-input multi-output level converters is not completely the same;

[0019] The multiple input terminals of each of the multi-input multi-output level converters are respectively connected to the multiple output terminals of the mainboard, and the multiple output terminals of each of the multi-input multi-output level converters are respectively connected to the multiple input terminals of the display panel;

[0020] The MIMO level converter is used to generate a second driving signal after receiving the second timing signal and the second control signal input by the mainboard;

[0021] The MIMO level converter is further configured to input the second driving signal to the display panel.

[0022] In a possible implementation manner, the target level conversion module includes at least one one-input one-output level converter and at least one multi-input multi-output level converter, and the one-input one-output level converter is of a different type from the multi-input multi-output level converter;

[0023] The multiple input terminals of the one-input-one-output level converter are connected to the multiple output terminals of the mainboard correspondingly, and the multiple output terminals of the one-input-one-output level converter are connected to the multiple input terminals of the display panel correspondingly;

[0024] The multiple input ends of each of the multi-input multi-output level converters are respectively connected to the multiple output ends of the mainboard, and the multiple output ends of each of the multi-input multi-output level converters are respectively connected to the multiple input ends of the display panel, and there is no cross connection between the input ends and the output ends of any two level converters.

[0025] In a possible implementation manner, the one-input-one-output level converter is a six-input-six-output level converter;

[0026] The six input signal terminals of the 6-input and 6-output level converter are respectively connected to the six output terminals of the mainboard, and the six output terminals of the 6-input and 6-output level converter are respectively connected to the six input terminals of the display panel;

[0027] Alternatively, the one-input-one-output level converter is an 8-input-8-output level converter;

[0028] The eight input signal terminals of the 8-input and 8-output level converter are respectively connected to the eight output terminals of the mainboard, and the eight output terminals of the 8-input and 8-output level converter are respectively connected to the eight input terminals of the display panel;

[0029] Alternatively, the one-input-one-output level converter is a 10-input-10-output level converter;

[0030] The 10 input signal terminals of the 10-input 10-output level converter are respectively connected to the 10 output terminals of the mainboard, and the 10 output terminals of the 10-input 10-output level converter are respectively connected to the 10 input terminals of the display panel;

[0031] Alternatively, the one-input-one-output level converter is a 12-input-12-output level converter;

[0032] The 12 input signal terminals of the 12-input 12-output level converter are respectively connected to the 12 output terminals of the mainboard, and the 12 output terminals of the 12-input 12-output level converter are respectively connected to the 12 input terminals of the display panel;

[0033] Alternatively, the one-input-one-output level converter is a 16-input-16-output level converter;

[0034] The 16 input signal terminals of the 16-input 16-output level converter are respectively connected to the 16 output terminals of the mainboard, and the 16 output terminals of the 16-input 16-output level converter are respectively connected to the 16 input terminals of the display panel.

[0035] In a possible implementation manner, the multi-input multi-output level converter is a 2-input 12-output level converter;

[0036] The two input terminals of the 2-input 12-output level converter are respectively connected to the two output terminals of the mainboard, and the 12 output terminals of the 2-input 12-output level converter are respectively connected to the 12 input terminals of the display panel;

[0037] Alternatively, the multi-input multi-output level converter is a 2-input 10-output level converter;

[0038] The two input terminals of the 2-input 10-output level converter are respectively connected to the two output terminals of the mainboard, and the ten output terminals of the 2-input 10-output level converter are respectively connected to the ten input terminals of the display panel;

[0039] Alternatively, the multi-input multi-output level converter is a 2-input 8-output level converter;

[0040] The two input terminals of the 2-input 8-output level converter are respectively connected to the two output terminals of the mainboard, and the eight output terminals of the 2-input 8-output level converter are respectively connected to the eight input terminals of the display panel;

[0041] Alternatively, the multi-input multi-output level converter is a 2-input 6-output level converter;

[0042] The two input terminals of the 2-input 6-output level converter are respectively connected to the two output terminals of the mainboard, and the six output terminals of the 2-input 6-output level converter are respectively connected to the six input terminals of the display panel.

[0043] In a second aspect, an embodiment of the present application provides a novel level conversion driving method, which is applied to any universal level conversion driving circuit as described in the first aspect, including:

[0044] Acquire a target timing requirement of a display panel, and determine a target mode of the display panel corresponding to the target timing requirement, wherein the target mode represents display parity or multilinearity of the display panel;

[0045] Determine a target model corresponding to the level conversion module according to the target mode, wherein the target model represents an application product type of the level converter in the level conversion module;

[0046] A level conversion driving circuit is constructed based on the target model so that the display panel drives the picture display.

[0047] In a possible implementation manner, determining the target mode of the display panel corresponding to the target timing requirement includes:

[0048] When the target timing requirement includes a driving requirement of an odd number of timings, determining that the target category of the display panel is an odd mode;

[0049] or,

[0050] When the target timing requirement includes a driving requirement of an even number of timings, determining that the target category of the display panel is an even mode;

[0051] or,

[0052] When the target timing requirement includes a driving requirement of a threshold output timing signal, determining that the target category of the display panel is a super-resolution mode, and the threshold output timing signal represents that the number of output signals is a preset maximum output number;

[0053] or,

[0054] When the target timing requirement includes an odd number of timings and a driving requirement of a threshold output timing signal, determining that the target mode of the display panel is an odd number super-resolution mode;

[0055] or,

[0056] When the target timing requirement includes an even number of timings and a driving requirement of a threshold output timing signal, the target mode of the display panel is determined to be an even super-resolution mode.

[0057] In a possible implementation manner, determining a target model corresponding to the level conversion module according to the target mode includes:

[0058] When the target mode is an odd-numbered mode, determining that the target model of the level conversion module is one one-input one-output level converter, or one one-input one-output level converter and at least one multi-input multi-output level converter;

[0059] When the target mode is an even mode, determining that the target model of the level conversion module is one one-input one-output level converter and / or at least one multiple-input multiple-output level converter;

[0060] When the target mode is the super-resolution mode, determining that the target model of the level conversion module is at least one multi-input multi-output level converter, or one one-input one-output level converter and at least one multi-input multi-output level converter;

[0061] When the target mode is an odd super-resolution mode, determining the target model of the level conversion module to be one one-input one-output level converter and at least one multi-input multi-output level converter;

[0062] When the target mode is the even super-resolution mode, the target model of the level conversion module is determined to be at least one MIMO level converter, or one 1I1O level converter and at least one MIMO level converter.

[0063] In a possible implementation manner, the step of constructing a level conversion driving circuit based on the target model includes:

[0064] When the target model is one one-input one-output level converter and at least one multiple-input multiple-output level converter, an odd number of input terminals and an odd number of output terminals are configured for the one-input one-output level converter;

[0065] Connecting the output end of each of the multi-input multi-output level converters to the input end of the display panel according to a preset rule to construct a level conversion drive circuit;

[0066] or,

[0067] When the target model is at least one multi-input multi-output level converter, the output end of each multi-input multi-output level converter is connected to the input end of the display panel according to a preset rule to construct a level conversion driving circuit;

[0068] or,

[0069] When the target model is a one-input-one-output level converter, the output end of each of the one-input-one-output level converters is connected to the input end of the display panel according to a preset rule to construct a level conversion driving circuit.

[0070] The novel level conversion driving circuit provided by the embodiment of the present application is provided with a mainboard, a display panel and a target level conversion module, wherein the target level conversion module contains at least one level converter; the mainboard is connected to one end of the level converter in the target level conversion module; the other end of the level converter in the target level conversion module is connected to the display panel; the mainboard is used to input a driving signal and a timing signal to the target level conversion module; the target level conversion module is used to generate a driving signal after receiving the control signal and the timing signal input by the mainboard; the display panel is used to drive the liquid crystal screen to display after receiving the driving signal input by the target level conversion module. Different types of level converters are selected according to the display panel's requirements for odd and even timing or super-resolution mode, so as to achieve the purpose of flexible driving and displaying of the display panel for special timing requirements. By this scheme, the timing support of various requirements of the display screen can be realized, and the technical effect of flexible display and improving the driving refresh rate of the display screen can be achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0071] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0072] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0073] One or more embodiments are exemplarily described by pictures in the corresponding drawings, and these exemplified descriptions do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings represent similar elements, and unless otherwise stated, the figures in the drawings do not constitute proportional limitations.

[0074] Figure 1a A timing diagram of a level conversion driving display circuit provided in the prior art;

[0075] Figure 1b A schematic diagram of the structure of a level conversion drive display circuit provided in the prior art;

[0076] Figure 1c A timing diagram of another level conversion driving display circuit provided in the prior art;

[0077] Figure 1d It is a structural schematic diagram of another level conversion driving display circuit provided in the prior art;

[0078] Figure 2 A schematic diagram of the structure of a novel level conversion drive circuit provided in Example 1 of the present application;

[0079] Figure 3 A schematic diagram of the structure of a novel level conversion drive circuit provided in Example 2 of the present application;

[0080] Figure 4 A schematic diagram of the structure of another novel level conversion drive circuit provided in the second embodiment of the present application;

[0081] Figure 5a A timing diagram of a novel level conversion driving circuit provided in Example 3 of the present application;

[0082] Figure 5b A schematic diagram of the structure of a novel level conversion drive circuit provided in Example 3 of the present application;

[0083] Figure 5c A schematic diagram of the structure of another novel level conversion drive circuit provided in Embodiment 3 of the present application;

[0084] Figure 6a A timing diagram of a novel level conversion driving circuit provided in the fourth embodiment of the present application;

[0085] Figure 6b A schematic diagram of the structure of a novel level conversion drive circuit provided in Embodiment 4 of the present application;

[0086] Figure 6c A schematic diagram of the structure of another novel level conversion drive circuit provided in the fourth embodiment of the present application;

[0087] Figure 7 A schematic diagram of the structure of a novel level conversion drive circuit provided in Example 5 of the present application;

[0088] Figure 8 A timing diagram of another novel level conversion driving circuit provided in Embodiment 5 of the present application;

[0089] Figure 9a A timing diagram of a novel level conversion driving circuit provided in Example 6 of the present application;

[0090] Figure 9b A schematic diagram of the structure of a novel level conversion drive circuit provided in Example 6 of the present application;

[0091] Fig.9c A schematic diagram of the structure of another novel level conversion drive circuit provided in Example 6 of the present application;

[0092] Figure 9dA structural schematic diagram of another novel level conversion drive circuit provided in Embodiment 6 of the present application;

[0093] Fig.9e A schematic diagram of the structure of another novel level conversion drive circuit provided in Example 6 of the present application;

[0094] Fig.10 A schematic flow chart of a novel level conversion driving method provided in Example 6 of the present application;

[0095] Fig.11 A flow chart of another novel level conversion driving method provided in Example 7 of the present application. DETAILED DESCRIPTION

[0096] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0097] The terms "including" and "having" in the embodiments of the present application are used to express an open-ended inclusive meaning, and mean that in addition to the listed elements / components / etc., there may be additional elements / components / etc.; the terms "first" and "second" etc. are used only as labels and are not intended to limit the quantity of their objects. In addition, the different elements and regions in the drawings are only schematically shown, so the present application is not limited to the sizes or distances shown in the drawings.

[0098] Level Shift is a level converter. Usually when two devices need to communicate, but the voltage specifications are different and cannot be directly connected, level conversion is required.

[0099] The HSR mode of the display is the abbreviation of Hardware Super Resolution, which is hardware super-resolution technology. This technology realizes differential display through timing adjustment. In each frame of the image, only the pixels of odd or even rows are rendered, while the other row is displayed by fusing the information of two adjacent rows. Although this method can achieve a higher refresh rate. Compared with DLG technology, HSR technology has made obvious progress in display. It does not display only one row of data, but displays by fusing the information of two adjacent rows, thereby improving the clarity and smoothness of the picture to a certain extent.

[0100] like Figure 1aThis is a timing diagram of a level conversion drive display circuit provided in the prior art. Figure 1 shows the logic of the level shifter with 1 input and 1 output, which is only responsible for pulling up the input waveform, and the other logic is determined by the TCON IC or SOC. The output waveform of the level shifter IC with this logic can theoretically be moved arbitrarily, and the output of the TCON IC or the system-level chip SOC is flexible, and the timing of the final display can also be flexibly controlled. Figure 1b The present invention is a schematic diagram of the structure of a level conversion driving display circuit provided in the prior art. Figure 1b yes Figure 1a The hardware connection diagram between the TCON IC or SOC corresponding to the timing and the level shifter IC and the display panel panel. Figure 1b The connection relationship can realize 6-input and 6-output level conversion control.

[0101] The current level shifter IC generally adopts 2-input and multiple-output or 4-input and multiple-output, such as Figure 1c This is a timing diagram of another level conversion driving display circuit provided in the prior art. Figure 1d The present invention is a schematic diagram of the structure of another level conversion driving display circuit provided in the prior art. Figure 1d for Figure 1c Schematic diagram of the hardware connection of the corresponding timing. Figure 1cThis is the simplest 2-input 6-output level shifter IC input and output logic. When CPV1 rises, CLK high level is output, and when CPV2 rises, CLK falling edge is output. There may also be other logics, such as outputting CLK rising edge when CPV1 falls, and outputting CLK falling edge when CPV2 falls. Or the output timing of CLK is controlled by the rising and falling edges of a CPV. However, no matter which method is used, the 2-input and multiple-output control logic has certain rules, such as the output CLK is output after staggering a specific number of rows in sequence, and the SOC or TCON IC can output the timing required by the screen by controlling the cycle of CPV1 / CPV2 or the output timing of the first waveform. While performing logic processing, the level shifter IC also pulls the square wave with a low level of 0V and a high level of 3.3V to a square wave with a low level of VGL and a high level of VGH. Only when the square wave with a high level of VGH and a low level of VGL can the TFT switch of the display panel be turned on and off. The 2-input and 2-output level shifter IC also has a 2-line mode reserved, which can be enabled by setting the register. This 2-line mode is the simplest, i.e., CLK1 = CLK2, CLK3 = CLK4, CLK5 = CLK6, etc. In actual applications, it may not necessarily meet the needs.

[0102] With the development of TV panels, especially with the rapid development of gaming TVs, HSR panels emerge in an endless stream to meet people's needs for entertainment such as watching movies and playing games. At the same time, in order to achieve cost reduction, dual gate technology is gradually used in HSR panels. The use of this technology can reduce COF by half and achieve significant cost reduction. While saving COF, dual gate panels double the number of gates, so that the charging time is halved, which poses a great challenge to the picture quality. In order to improve the picture quality, it is proposed to improve the GOA timing and obtain the GOA timing of the HSR panel based on the dual gate architecture. Multi-line mode has become an important countermeasure to improve the display effect of the HSR panel with dual gate architecture, but in terms of implementation, the 2-input and 12-output level shifter IC cannot display the timing logic of the 2-line mode.

[0103] In response to the above problems, this solution proposes a new level conversion driving circuit. By analyzing the different timing requirements of the display panel, a universal one-input-one-output level converter or a multi-input-multi-output level converter is selected as the level conversion module of the display driver, thereby realizing specific timing requirements and using universal timing control logic to meet flexible and diverse timing.

[0104] To facilitate understanding of the embodiments of the present application, further explanation will be given below with reference to specific embodiments in conjunction with the accompanying drawings. The embodiments do not constitute a limitation on the embodiments of the present application.

[0105] Embodiment 1

[0106] Figure 2 This is a schematic diagram of a novel level conversion drive circuit provided in Example 1 of the present application. Figure 2 According to the diagram provided, the structure of the novel level conversion driving circuit includes:

[0107] The main board 10 , the display panel 20 and the target level conversion module 30 , wherein the target level conversion module 30 includes at least one level converter 301 .

[0108] The mainboard 10 is connected to one end of the level converter 301 in the target level conversion module 30 .

[0109] The other end of the level converter 301 in the target level conversion module 30 is connected to the display panel 20 .

[0110] The main board 10 is used to input a driving signal and a timing signal to the target level conversion module 30 .

[0111] The target level conversion module 30 is used to generate a driving signal after receiving a control signal and a timing signal input from the mainboard 10 .

[0112] The display panel 20 is used to drive the liquid crystal screen to display after receiving the driving signal input by the target level conversion module 30.

[0113] according to Figure 2 The diagram provided shows that different types of level converters are selected according to the different timing requirements of the display panel. For complex timing requirements, such as a display panel in the HSR mode of the 2line mode, a level converter with 12 clock signals CK is required. A universal level converter is used to meet the panel requirements of complex timing, and at the same time, the function of the level converter is simplified. The level converter is only responsible for the level pull-up function. At the same time, multiple universal level converters are used to achieve the situation where the number of clock signals CK exceeds the maximum output number of the current level converter, and then a highly universal level converter is used to achieve the purpose of driving the display panel to display after the level is pulled up.

[0114] The novel level conversion driving circuit provided by the embodiment of the present application is provided with a mainboard, a display panel and a target level conversion module, wherein the target level conversion module includes at least one level converter; the mainboard is connected to one end of the level converter in the target level conversion module; the other end of the level converter in the target level conversion module is connected to the display panel; the mainboard is used to input a driving signal and a timing signal to the target level conversion module; the target level conversion module is used to generate a driving signal after receiving a control signal and a timing signal input by the mainboard; the display panel is used to drive the liquid crystal screen to display after receiving a driving signal input by the target level conversion module. Different types of level converters are selected according to the display panel's requirements for odd and even timing or the HSR mode, so as to achieve the purpose of flexible driving and displaying of the display panel for special timing requirements. By this scheme, the timing support of various requirements of the display screen can be realized, and the technical effect of flexible display and improving the driving refresh rate of the display screen can be achieved.

[0115] Embodiment 2

[0116] Figure 3 A schematic diagram of the structure of a novel level conversion drive circuit provided in Example 2 of the present application. Figure 3 This is introduced based on the previous embodiment. Figure 3 According to the diagram provided, the structure of the novel level conversion driving circuit includes:

[0117] The main board 10 , the display panel 20 and the target level conversion module 30 , wherein the target level conversion module 30 includes at least one level converter 301 .

[0118] according to Figure 3 According to the provided diagram, the target level conversion module 30 in the novel level conversion driving circuit includes at least one one-input and one-output level converter 3011 .

[0119] The one-input-one-output level converter 3011 includes n signal input terminals and n signal output terminals, and one input terminal in the one-input-one-output level converter 3011 corresponds to one output terminal, and n is a positive integer greater than or equal to 1.

[0120] Each input terminal of the one-input-one-output level converter 3011 is connected to the n output terminals of the mainboard 10 , and each output terminal of the one-input-one-output level converter 3011 is connected to the n input terminals of the display panel 20 .

[0121] The one-input-one-output level converter 3011 is used to generate a first driving signal after receiving a first control signal and a first timing signal input from the mainboard 10 .

[0122] The one-input-one-output level converter 3011 is also used to input the first driving signal to the display panel 20 .

[0123] according to Figure 3 The provided diagram selects different types of level converters according to the different timing requirements of the display panel. For complex timing requirements, such as a display panel in the HSR mode of the even state 2line mode, a level converter with 12 clock signals CK is required. A one-input-one-output level converter 3011 is used to meet the panel requirements of complex timing, and at the same time, the function of the level converter is simplified. The one-input-one-output level converter 3011 is only responsible for the level pull-up function. At the same time, multiple one-input-one-output level converters 3011 are used to achieve the situation where the number of clock signals CK exceeds the maximum output number of the current level converter, and then a highly versatile level converter is used to achieve the purpose of driving the display panel to display after the level is pulled up, thereby improving the flexible adjustment of the level converter.

[0124] according to Figure 3 According to the provided diagram, the one-input-one-output level converter 3011 in the novel level conversion driving circuit is a six-input-six-output level converter.

[0125] The six input signal terminals of the 6-input 6-output level converter are respectively connected to the six output terminals of the mainboard 10 , and the six output terminals of the 6-input 6-output level converter are respectively connected to the six input terminals of the display panel 20 .

[0126] Alternatively, the one-input-one-output level converter 3011 is an 8-input-8-output level converter.

[0127] The eight input signal terminals of the 8-input and 8-output level converter are respectively connected to the eight output terminals of the mainboard 10 , and the eight output terminals of the 8-input and 8-output level converter are respectively connected to the eight input terminals of the display panel 20 .

[0128] Alternatively, the one-input-one-output level converter 3011 is a 10-input-10-output level converter.

[0129] The 10 input signal terminals of the 10-input 10-output level converter are respectively connected to the 10 output terminals of the mainboard 10 , and the 10 output terminals of the 10-input 10-output level converter are respectively connected to the 10 input terminals of the display panel 20 .

[0130] Alternatively, the one-input-one-output level converter 3011 is a 12-input-12-output level converter.

[0131] The 12 input signal terminals of the 12-input 12-output level converter are respectively connected to the 12 output terminals of the mainboard 10 , and the 12 output terminals of the 12-input 12-output level converter are respectively connected to the 12 input terminals of the display panel 20 .

[0132] Alternatively, the one-input-one-output level converter 3011 is a 16-input-16-output level converter.

[0133] The 16 input signal terminals of the 16-input 16-output level converter are respectively connected to the 16 output terminals of the mainboard 10 , and the 16 output terminals of the 16-input 16-output level converter are respectively connected to the 16 input terminals of the display panel 20 .

[0134] according to Figure 3 The diagram provided shows that when the display panel has special timing requirements, a combination of multiple one-input and one-output level converters 3011 is used to meet the requirements of the clock signal CK, or any one or more of 6in6out Level shifter IC, 8in8outLevel shifter IC, 10in10out Level shifter IC, 12in12out Level shifter IC, and 16in16out Level shifter IC are selected to form a level conversion module. By arbitrarily combining multiple one-input and one-output level converters 3011, the special timing requirements of the display panel are achieved, thereby achieving the versatility and flexibility of the level converter.

[0135] Further, Figure 4 A schematic diagram of the structure of another novel level conversion drive circuit provided in Example 2 of the present application. Figure 4 The invention is introduced on the basis of the first embodiment. Figure 4 According to the diagram provided, the structure of the novel level conversion driving circuit includes:

[0136] The main board 10 , the display panel 20 and the target level conversion module 30 , wherein the target level conversion module 30 includes at least one level converter 301 .

[0137] according to Figure 4 According to the provided diagram, the target level conversion module 30 in the novel level conversion driving circuit includes at least one multi-input multi-output level converter 3012, the number of input ports of each multi-input multi-output level converter 3012 is not exactly the same, and the number of output ports of each multi-input multi-output level converter 3012 is not exactly the same.

[0138] The multiple input terminals of each MIMO level converter 3012 are respectively connected to the multiple output terminals of the mainboard 10 , and the multiple output terminals of each MIMO level converter 3012 are respectively connected to the multiple input terminals of the display panel 20 .

[0139] The MIMO level converter 3012 is used to generate a second driving signal after receiving the second timing signal and the second control signal input from the mainboard 10.

[0140] The MIMO level converter 3012 is also used to input a second driving signal to the display panel 20 .

[0141] according to Figure 4 The provided diagram selects different types of level converters according to the different timing requirements of the display panel. For complex timing requirements, such as a display panel in the HSR mode of the even state 2line mode, a level converter with 12 clock signals CK is required. At this time, a multi-input multi-output level converter 3012 is selected to meet the panel requirements of complex timing, and at the same time, the function of the level converter is simplified. The multi-input multi-output level converter 3012 is only responsible for the level pull-up function. At the same time, multiple multi-input multi-output level converters 3012 are used to achieve the situation where the number of clock signals CK exceeds the maximum output number of the current level converter, and then a highly versatile level converter is used to achieve the purpose of driving the display panel to display after the level is pulled up, thereby improving the flexible adjustment of the level converter.

[0142] according to Figure 4 According to the provided diagram, the multi-input multi-output level converter 3012 in the novel level conversion driving circuit is a 2-input 12-output level converter.

[0143] The two input terminals of the 2-input 12-output level converter are respectively connected to the two output terminals of the mainboard 10 , and the 12 output terminals of the 2-input 12-output level converter are respectively connected to the 12 input terminals of the display panel 20 .

[0144] Alternatively, the MIMO level converter 3012 is a 2-input 10-output level converter.

[0145] The two input terminals of the 2-input 10-output level converter are respectively connected to the two output terminals of the mainboard 10 , and the ten output terminals of the 2-input 10-output level converter are respectively connected to the ten input terminals of the display panel 20 .

[0146] Alternatively, the MIMO level converter 3012 is a 2-input 8-output level converter.

[0147] The two input terminals of the 2-input 8-output level converter are connected to the two output terminals of the mainboard 10 respectively, and the eight output terminals of the 2-input 8-output level converter are connected to the eight input terminals of the display panel 20 respectively.

[0148] Alternatively, the MIMO level converter 3012 is a 2-input 6-output level converter.

[0149] The two input terminals of the 2-input 6-output level converter are connected to the two output terminals of the mainboard 10 respectively, and the six output terminals of the 2-input 6-output level converter are connected to the six input terminals of the display panel 20 respectively.

[0150] according to Figure 4The diagram provided shows that when the display panel has special timing requirements, multiple multi-input and multi-output level converters are used, and the parity of the multi-input and multi-output level converters is used to achieve the requirements of multiple clock signal CKs or super-resolution HSR mode. By selecting the same or different types of multi-input and multi-output level converters among 2in12out Level shifter IC, 2in10out Level shifter IC, 2in8outLevel shifter IC, and 2in6out Level shifter IC, the logic control for the 2line mode / 3line mode of the HSR mode under the condition of multiple clock signals CK is realized, so as to achieve the flexibility and universality of the universal level converter and provide a stable signal for the subsequent driving display panel.

[0151] Embodiment 3

[0152] To further demonstrate the versatility of using a one-input and one-output level converter, Figure 5a This is a timing diagram of a novel level conversion driving circuit provided in Example 3 of the present application. Figure 5a The diagram provided uses multiple one-input and one-output level converters to achieve special timing drive display requirements.

[0153] like Figure 5a The display panel panel shown shows the even CK timing requirements for the 2-line mode. During the GOA drive scan, two lines are regularly turned on (i.e., CK1=CK2, CK3=CK4, CK5=CK6, CK7=CK8, CK9=CK10, CK11=CK12, etc.) to achieve even output. The switch from the ordinary one-line mode to the 2-line mode is achieved by adjusting the internal register of the level shifter IC. There are very few levelshifter ICs with 2 inputs and 12 outputs and 2-line mode. Consider using two level shifter ICs to meet the drive requirements, such as Figure 5b This is a schematic diagram of the structure of a new level conversion drive circuit provided in Example 3 of the present application. Figure 5c This is a schematic diagram of the structure of another novel level conversion drive circuit provided in the third embodiment of the present application. Figure 5bWhen two level shifter ICs with one input and one output are used for driving, the clock signal CK output is at least 6CK output, and can also be 8CK output or 10CK output, etc. If it is 8CK or 10CK output channels, then according to the requirements of the display, each level shifter IC can NC 2 or 4 CK output channels and NC 2 or 4 CK inputs.

[0154] Figure 5c When two 2-input and multiple-output level shifter ICs are used for driving, the CK output is at least 6CK output, and can also be 8CK output or 10CK output. If it is 8CK or 10CK output channels, then each level shifter IC can NC 2 or 4 CK output channels according to the needs of the display. It is also possible to use a single level shifter IC with 2-input and 12-output or 12-input and 12-output for driving.

[0155] Embodiment 4

[0156] Further, in order to illustrate the logic analysis process of multiple MIMO level converters in odd mode, Figure 6a This is a timing diagram of a new level conversion drive circuit provided in Example 4 of the present application. Figure 6a It is a 12CK 2line mode mode that meets the timing requirements of the display panel corresponding to the odd clock signal, that is, the clock signal CK satisfies CK1=CK3, CK2=CK4, CK5=CK7, CK6=CK8, CK9=CK11, CK10=CK12, etc. In this mode, if two 2-input and multiple-output level shifter ICs are used, they need to open the odd-numbered 2line mode when switching to HSR mode, and special processing is required on the hardware connection, such as one of the 2-input and multiple-output level shifter ICs outputs an odd CK (that is, the CK output channels CK1 / CK3 / CK5 / CK7 / CK9 / CK11 of the levelshifter IC are connected to the corresponding odd clock signal CK input of the display panel), and the output channel of the other 2-input and multiple-output level shifter IC is connected to the even clock signal CK, that is, the channels corresponding to the clock signal CK output channels of the 2-input and multiple-output level shifter IC are connected to the channels corresponding to the even clock signal CK of the display panel. The specific hardware connection is as follows Figure 6b and Figure 6c As shown, especially Figure 6c shown. Figure 6b A schematic diagram of the structure of a novel level conversion drive circuit provided in Example 4 of the present application. Figure 6c This is a schematic diagram of another novel level conversion driving circuit provided in the fourth embodiment of the present application. In addition, the motherboard SOC or TCON IC needs to perform corresponding level converter logic control to adjust to the specific timing required by the display screen.

[0157] Embodiment 5

[0158] Figure 7 This is a schematic diagram of the structure of a new level conversion drive circuit provided in Example 5 of the present application. Figure 7 This is introduced based on the previous embodiment. Figure 7 According to the diagram provided, the structure of the novel level conversion driving circuit includes:

[0159] The main board 10 , the display panel 20 and the target level conversion module 30 , wherein the target level conversion module 30 includes at least one level converter 301 .

[0160] according to Figure 7 According to the provided diagram, the target level conversion module 30 in the novel level conversion driving circuit includes at least one one-input one-output level converter 3011 and at least one multi-input multi-output level converter 3012, and the one-input one-output level converter 3011 and the multi-input multi-output level converter 3012 are of different types.

[0161] Multiple input terminals of the one-input-one-output level converter 3011 are correspondingly connected to multiple output terminals of the mainboard 10 , and multiple output terminals of the one-input-one-output level converter 3011 are correspondingly connected to multiple input terminals of the display panel 20 .

[0162] The multiple input terminals of each multi-input multi-output level converter 3012 are respectively connected to the multiple output terminals of the mainboard 10, and the multiple output terminals of each multi-input multi-output level converter 3012 are respectively connected to the multiple input terminals of the display panel 20. There is no cross connection between the input terminals and output terminals of any two level converters 301.

[0163] according to Figure 7The diagram provided shows that when the display panel has special timing requirements, multiple one-input-one-output and multiple multi-input-multi-output level converters are used, and the parity timing setting of the one-input-one-output level converter and the multi-input-multi-output level converter is used to achieve the requirements of multiple clock signal CK or HSR mode. By selecting the same or different multi-input-multi-output level converters among 2in12out Level shifter IC, 2in10out Level shifter IC, 2in8out Level shifter IC, and 2in6out Level shifter IC, and one or more one-input-one-output level converters among 6in6out Level shifter IC and 8in8outLevel shifter IC, the logic control for the super-resolution HSR mode 2line mode / 3line mode under the condition of multiple clock signal CK is realized, so as to achieve the flexibility and universality of the universal level converter, and provide a stable signal for the subsequent driving display panel.

[0164] In one possible example scenario, Figure 8 This is a timing diagram of another novel level conversion driving circuit provided in Example 5 of the present application. Figure 8 The timing diagram of the 12CK input channel corresponding to the 12CK output channel under the 12CK timing requirement in the 3line mode is shown. The timing requirements of the 3line mode can be achieved by selecting two 6-input 6-output level converters or multiple multi-input multi-output level converters, further improving the flexible application of the new level converter.

[0165] Embodiment 6

[0166] Figure 9a This is a timing diagram of a novel level conversion driving circuit provided in Example 6 of the present application. Figure 9a According to the timing requirements of the display panel, the motherboard SOC or TCON IC has 15 clock signal inputs. At the same time, the display panel requires an odd CK timing, which requires the use of a one-in-one-out level shifter. At the same time, corresponding to 12 timing input signals, a 12in12out Level shifter IC or 16in16out Level shifter IC can be used to achieve the 12 clock signal input requirements. Through the above analysis, we can get Figure 9b and Fig.9c Meet the needs. Among them, Figure 9b This is a structural schematic diagram of a new level conversion drive circuit provided in Example 6 of the present application. Fig.9cThis is a schematic diagram of the structure of another novel level conversion drive circuit provided in Example 6 of the present application. Figure 9b According to the diagram provided, using two 8in8out level shifter ICs, with one pin at the input and output of one level shifter IC disconnected, the 15CK odd-number timing requirement can be achieved. Fig.9c The diagram provided shows that the 15ck odd-number timing requirement can also be met by using a 16in16out Levelshifter IC. By using multiple one-input and one-output Levelshifter ICs, a universal Level shifter IC can be used to pull up the level. The internal timing logic control is achieved through the motherboard SOC or TCON IC, thereby improving the flexibility of the display panel drive.

[0167] Furthermore, based on the use of a one-input and one-output level converter to achieve timing control under odd conditions, in order to further reduce the number of pin outputs of the motherboard SOC or TCON IC, you can also use Figure 9d and Fig.9e The diagram provided. Figure 9d This is a structural schematic diagram of another novel level conversion drive circuit provided in Example 6 of the present application. Fig.9e A schematic diagram of a novel level conversion drive circuit provided in the sixth embodiment of the present application. When considering the driving timing requirements of an odd-number CK display panel, it is necessary to consider a one-input-one-output (multi-input-multi-output) level shifter IC, or a one-input-one-output (multi-input-multi-output) level shifter IC combined with a 2-input-multi-output or 4-input-multi-output level shifter IC to meet the driving requirements. From the perspective of cost saving and integration space, Figure 9d Select one 4in4out Level shifter IC and one 2in12out Level shifter IC, and disconnect one pin at the input and output of the 4in4out Level shifter IC to achieve an odd number of three control terminals and three clock signal output terminals. Then use a 2in12out Level shifter IC to reduce the input pins, which greatly saves basic space and production costs, and also improves the flexibility of the level converter in the display panel driver. Similarly, refer to Fig.9eThe diagram provided selects one 4in4out Level shifter IC and any two of two 2in6out Level shifter ICs or two 2in8out Level shifter ICs or two 2in10out Level shifter ICs, and uses the 4in4out Level shifter IC to achieve the purpose of inputting an odd number of three control signals and outputting an odd number of three clock signals, and uses two 2-input and multiple-output Levelshifter ICs to achieve the purpose of having fewer input signals and each Level shifter IC outputting six clock signals CK, thereby achieving special timing requirements and driving the display panel to display.

[0168] Embodiment 7

[0169] Fig.10 A schematic flow chart of a novel level conversion driving method provided in Example 6 of the present application. Applicable to a novel level conversion driving circuit. Fig.10 According to the provided diagram, the steps of the novel level conversion driving method specifically include:

[0170] S1001. Obtain a target timing requirement of a display panel, and determine a target mode of the display panel corresponding to the target timing requirement.

[0171] This application analyzes the different timing requirements of the display panel, and then selects a universal level converter to achieve level conversion on the basis of meeting the timing requirements. According to different needs, a one-input-one-output or multi-input-multi-output level converter is used, and the TCON IC or the motherboard SOC performs timing logic control, and the level converter only performs voltage pull-up drive control, thereby improving the flexible application of the level converter.

[0172] The target mode mentioned here represents the display parity or multi-linearity of the display panel, which can be understood as a special type of demand determined by factors such as the number of control signals in the target timing, the mapping relationship between the clock signal and the control signal, and the driving mode of the panel is determined according to different analysis categories, such as 2line mode, super-resolution HSR mode, odd clock signal mode, even clock signal mode, etc.

[0173] Furthermore, it is first necessary to obtain the timing requirements of the display panel, analyze the characteristics of the timing requirements, and determine whether the mode corresponding to the timing requirements is a multi-clock signal mode or a parity output signal mode, or a multi-line mode timing mode, etc. According to the different categories of the timing obtained by analysis, the different rated driving modes of the display panel are determined. For example, when the target category is the 2line mode category, the driving mode of the display panel is determined to be the super-resolution HSR mode, which provides a reference for the next step of selecting the model of the level converter.

[0174] S1002. Determine a target model corresponding to the level conversion module according to the target mode.

[0175] The target model mentioned here can be understood as representing the application product type of the level converter in the level conversion module, as well as different types of level converters corresponding to different numbers of input and output terminals of the selected level converter.

[0176] Furthermore, different types of level converters are selected according to different target modes. In odd mode, a one-input one-output level converter is selected, and in 2line mode or even mode, a multi-input multi-output level converter is selected.

[0177] S1003 , constructing a level conversion driving circuit based on the target model, so that the display panel drives the picture display.

[0178] Furthermore, after determining the model of the level converter, one or more level converters are used to connect the mainboard and the display panel to build a level conversion drive circuit. Through timing control, the mainboard SOC or TCON IC outputs a clock signal of the control signal, and the level converter is used to pull up the level, so that the square wave with a low level of 0V and a high level of 3.3V is pulled up to a square wave with a low level of VGL and a high level of VGH. Only when the high level is VGH and the low level is VGL, can the TFT switch of the display panel be turned on and off, so that the display panel drives the picture to display.

[0179] The embodiment of the present application provides a novel level conversion driving method, which obtains the selected model and number of level converters by analyzing the timing requirements of the display panel, and then utilizes the level-pulling function of the level converter to flexibly realize the driving display of the display screen.

[0180] Embodiment 8

[0181] Fig.11 A flow chart of another novel level conversion driving method provided in Example 7 of the present application. Fig.11 This is introduced based on the previous embodiment. Fig.11 According to the provided diagram, the steps of the novel level conversion driving method specifically include:

[0182] S1101 , obtaining a target timing requirement of a display panel.

[0183] S1102 : When the target timing requirement includes a driving requirement of an odd number of timings, determine that the target category of the display panel is an odd mode.

[0184] S1103 : When the target timing requirement includes a driving requirement of an even number of timings, determine that the target category of the display panel is an even mode.

[0185] S1104 : When the target timing requirement includes a driving requirement of a threshold output timing signal, determine that the target category of the display panel is a super-resolution mode.

[0186] S1105 . When the target timing requirement includes an odd number of timings and a driving requirement of a threshold output timing signal, determine that the target mode of the display panel is an odd number super-resolution mode.

[0187] S1106 : When the target timing requirement includes an even number of timings and a driving requirement of a threshold output timing signal, determine that the target mode of the display panel is an even super-resolution mode.

[0188] The threshold output timing signal mentioned here represents that the number of output signals is a preset maximum output number, which can be set to 12 output timing signals, 14 output timing signals, 16 output timing signals and other timing signals with more output numbers. The threshold output timing signal represents the maximum number of output signals of the current level converter.

[0189] Furthermore, when obtaining the target timing requirement of the display panel, after analyzing the target timing requirement, it is determined whether the timing requirement is an odd number of timings or an even number of timings, or when the driving requirement exceeds the limited number of output clock signals, the corresponding mode of the display panel is determined according to the limited factors, providing a reference basis for selecting a suitable level converter in the next step.

[0190] S1107 . When the target mode is an odd-numbered mode, determine that the target model of the level conversion module is one one-input one-output level converter, or one one-input one-output level converter and at least one multiple-input multiple-output level converter.

[0191] S1108 . When the target mode is an even mode, determine that the target model of the level conversion module is one one-input one-output level converter and / or at least one multiple-input multiple-output level converter.

[0192] S1109: When the target mode is the super-resolution mode, determine that the target model of the level conversion module is at least one multi-input multi-output level converter, or one one-input one-output level converter and at least one multi-input multi-output level converter.

[0193] S1110 , when the target mode is the odd super-resolution mode, determining the target model of the level conversion module to be one one-input one-output level converter and at least one multi-input multi-output level converter.

[0194] S1111. When the target mode is the even super-resolution mode, determine that the target model of the level conversion module is at least one multi-input multi-output level converter, or one one-input one-output level converter and at least one multi-input multi-output level converter.

[0195] Furthermore, after selecting the mode of the display panel, the model of the level converter is selected accordingly. When the target mode is an odd mode or an odd super-resolution HSR mode, in order to achieve the purpose of an odd number of clock signals, one one-input and one-output level converter and at least one multi-input and multi-output level converter can be selected. Based on the premise of realizing the odd mode, in order to solve the cost, one or more one-input and one-output level converters can also be selected to achieve the requirements of odd timing outputs. When the target mode is an even mode or an even super-resolution HSR mode, in order to achieve drive display in an even environment, under the premise of saving production costs, the target model of the level conversion module selects at least one multi-input and multi-output level converter, or for versatility, a one-input and one-output level converter and at least one multi-input and multi-output level converter are selected to achieve the special timing requirements of the display panel.

[0196] S1112. When the target model is one one-input one-output level converter and at least one multiple-input multiple-output level converter, configure an odd number of input terminals and an odd number of output terminals for the one-input one-output level converter.

[0197] S1113 , connecting the output end of each multi-input multi-output level converter to the input end of the display panel according to a preset rule to construct a level conversion driving circuit.

[0198] S1114: When the target model is at least one MIMO level converter, the output end of each MIMO level converter is connected to the input end of the display panel according to a preset rule to construct a level conversion driving circuit.

[0199] S1115 , when the target model is a one-input-one-output level converter, the output end of each one-input-one-output level converter is connected to the input end of the display panel according to a preset rule to construct a level conversion driving circuit.

[0200] Furthermore, the mainboard and the display panel are connected by using the selected matching mode of the level converter to realize the corresponding odd clock signal output or even clock signal output, or multi-clock signal output, so that the display panel drives the picture display.

[0201] The specific implementation methods described above further illustrate the purpose, technical solutions and beneficial effects of the present application in detail. It should be understood that the above description is only the specific implementation method of the present application and is not intended to limit the scope of protection of the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application should be included in the scope of protection of the present application.

Claims

1. A novel level conversion driving circuit, characterized in that: include: A main board, a display panel and a target level conversion module, wherein the target level conversion module includes at least one level converter; The mainboard is connected to one end of the level converter in the target level conversion module; The other end of the level converter in the target level conversion module is connected to the display panel; The mainboard is used to input a driving signal and a timing signal to the target level conversion module; The target level conversion module is used to generate a driving signal after receiving the control signal and the timing signal input by the mainboard; The display panel is used to drive the liquid crystal screen to display after receiving the driving signal input by the target level conversion module.

2. The circuit according to claim 1, characterized in that The target level conversion module includes at least one one-input and one-output level converter; The one-input-one-output level converter comprises n signal input terminals and n signal output terminals, and one input terminal of the one-input-one-output level converter corresponds to one output terminal, and n is a positive integer greater than or equal to 1; Each input end of the one-input-one-output level converter is connected to the n output ends of the mainboard, and each output end of the one-input-one-output level converter is connected to the n input ends of the display panel; The one-input-one-output level converter is used to generate a first driving signal after receiving the first control signal and the first timing signal input by the mainboard; The one-input-one-output level converter is also used to input a first driving signal to the display panel.

3. The circuit according to claim 1, characterized in that The target level conversion module includes at least one multi-input multi-output level converter, the number of input ports of each of the multi-input multi-output level converters is not completely the same, and the number of output ports of each of the multi-input multi-output level converters is not completely the same; The multiple input terminals of each of the multi-input multi-output level converters are respectively connected to the multiple output terminals of the mainboard, and the multiple output terminals of each of the multi-input multi-output level converters are respectively connected to the multiple input terminals of the display panel; The MIMO level converter is used to generate a second driving signal after receiving the second timing signal and the second control signal input by the mainboard; The MIMO level converter is further configured to input the second driving signal to the display panel.

4. The circuit according to claim 1, characterized in that The target level conversion module includes at least one one-input one-output level converter and at least one multiple-input multiple-output level converter, and the one-input one-output level converter is of a different type from the multiple-input multiple-output level converter; The multiple input terminals of the one-input-one-output level converter are connected to the multiple output terminals of the mainboard correspondingly, and the multiple output terminals of the one-input-one-output level converter are connected to the multiple input terminals of the display panel correspondingly; The multiple input ends of each of the multi-input multi-output level converters are respectively connected to the multiple output ends of the mainboard, and the multiple output ends of each of the multi-input multi-output level converters are respectively connected to the multiple input ends of the display panel, and there is no cross connection between the input ends and the output ends of any two level converters.

5. The circuit according to claim 2, characterized in that The one-input-one-output level converter is a six-input-six-output level converter; The six input signal terminals of the 6-input and 6-output level converter are respectively connected to the six output terminals of the mainboard, and the six output terminals of the 6-input and 6-output level converter are respectively connected to the six input terminals of the display panel; Alternatively, the one-input-one-output level converter is an 8-input-8-output level converter; The eight input signal terminals of the 8-input and 8-output level converter are respectively connected to the eight output terminals of the mainboard, and the eight output terminals of the 8-input and 8-output level converter are respectively connected to the eight input terminals of the display panel; Alternatively, the one-input-one-output level converter is a 10-input-10-output level converter; The 10 input signal terminals of the 10-input 10-output level converter are respectively connected to the 10 output terminals of the mainboard, and the 10 output terminals of the 10-input 10-output level converter are respectively connected to the 10 input terminals of the display panel; Alternatively, the one-input-one-output level converter is a 12-input-12-output level converter; The 12 input signal terminals of the 12-input 12-output level converter are respectively connected to the 12 output terminals of the mainboard, and the 12 output terminals of the 12-input 12-output level converter are respectively connected to the 12 input terminals of the display panel; Alternatively, the one-input-one-output level converter is a 16-input-16-output level converter; The 16 input signal terminals of the 16-input 16-output level converter are respectively connected to the 16 output terminals of the mainboard, and the 16 output terminals of the 16-input 16-output level converter are respectively connected to the 16 input terminals of the display panel.

6. The circuit according to claim 3, characterized in that The multi-input multi-output level converter is a 2-input 12-output level converter; The two input terminals of the 2-input 12-output level converter are respectively connected to the two output terminals of the mainboard, and the 12 output terminals of the 2-input 12-output level converter are respectively connected to the 12 input terminals of the display panel; Alternatively, the multi-input multi-output level converter is a 2-input 10-output level converter; The two input terminals of the 2-input 10-output level converter are respectively connected to the two output terminals of the mainboard, and the ten output terminals of the 2-input 10-output level converter are respectively connected to the ten input terminals of the display panel; Alternatively, the multi-input multi-output level converter is a 2-input 8-output level converter; The two input terminals of the 2-input 8-output level converter are respectively connected to the two output terminals of the mainboard, and the eight output terminals of the 2-input 8-output level converter are respectively connected to the eight input terminals of the display panel; Alternatively, the multi-input multi-output level converter is a 2-input 6-output level converter; The two input terminals of the 2-input 6-output level converter are respectively connected to the two output terminals of the mainboard, and the six output terminals of the 2-input 6-output level converter are respectively connected to the six input terminals of the display panel.

7. A novel level conversion driving method, applied to the novel level conversion driving circuit as claimed in any one of claims 1 to 6, characterized in that: include: Acquire a target timing requirement of a display panel, and determine a target mode of the display panel corresponding to the target timing requirement, wherein the target mode represents display parity or multilinearity of the display panel; Determine a target model corresponding to the level conversion module according to the target mode, wherein the target model represents an application product type of the level converter in the level conversion module; A level conversion driving circuit is constructed based on the target model so that the display panel drives the picture display.

8. The method according to claim 7, characterized in that The determining a target mode of the display panel corresponding to the target timing requirement includes: When the target timing requirement includes a driving requirement of an odd number of timings, determining that the target category of the display panel is an odd mode; or, When the target timing requirement includes a driving requirement of an even number of timings, determining that the target category of the display panel is an even mode; or, When the target timing requirement includes a driving requirement of a threshold output timing signal, determining that the target category of the display panel is a super-resolution mode, and the threshold output timing signal represents that the number of output signals is a preset maximum output number; or, When the target timing requirement includes an odd number of timings and a driving requirement of a threshold output timing signal, determining that the target mode of the display panel is an odd number super-resolution mode; or, When the target timing requirement includes an even number of timings and a driving requirement of a threshold output timing signal, the target mode of the display panel is determined to be an even super-resolution mode.

9. The method according to claim 8, characterized in that The step of determining a target model corresponding to the level conversion module according to the target mode includes: When the target mode is an odd-numbered mode, determining that the target model of the level conversion module is one one-input one-output level converter, or one one-input one-output level converter and at least one multi-input multi-output level converter; When the target mode is an even mode, determining that the target model of the level conversion module is one one-input one-output level converter and / or at least one multiple-input multiple-output level converter; When the target mode is the super-resolution mode, determining that the target model of the level conversion module is at least one multi-input multi-output level converter, or one one-input one-output level converter and at least one multi-input multi-output level converter; When the target mode is an odd super-resolution mode, determining the target model of the level conversion module to be one one-input one-output level converter and at least one multi-input multi-output level converter; When the target mode is the even super-resolution mode, the target model of the level conversion module is determined to be at least one MIMO level converter, or one IO level converter and at least one MIMO level converter.

10. The method according to claim 9, characterized in that The step of constructing a level conversion driving circuit based on the target model includes: When the target model is one one-input one-output level converter and at least one multiple-input multiple-output level converter, an odd number of input terminals and an odd number of output terminals are configured for the one-input one-output level converter; Connecting the output end of each of the multi-input multi-output level converters to the input end of the display panel according to a preset rule to construct a level conversion drive circuit; or, When the target model is at least one multi-input multi-output level converter, the output end of each multi-input multi-output level converter is connected to the input end of the display panel according to a preset rule to construct a level conversion driving circuit; or, When the target model is a one-input-one-output level converter, the output end of each of the one-input-one-output level converters is connected to the input end of the display panel according to a preset rule to construct a level conversion driving circuit.

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