Memory circuit, interface circuit therefor, and method of operating memory circuit

Abstract

The memory circuit includes a memory array and a peripheral circuit. The peripheral circuit includes an internal clock generation circuit and a first access signal generation circuit. The internal clock generation circuit is configured to generate a series of internal clock pulses during an internal clock period corresponding to a pulse width of the control signal pulse in response to the control signal pulse. The first access signal generation circuit is configured to generate a first access signal in response to a first edge of the control signal pulse. The peripheral circuit is configured to control an access operation in the memory array based on at least one of the series of internal clock pulses and a first access signal. The embodiment of the invention also discloses an interface circuit of the memory circuit and a method for operating the memory circuit.

Description

Technical Field

[0001] Embodiments of the present application relate to a memory circuit, an interface circuit thereof, and a method of operating the memory circuit. Background Art

[0002] Integrated circuits (ICs) are widely used in various digital devices and / or applications in different fields. Memory or memory circuits are components of IC devices that are configured to store data and / or applications to be processed and / or executed by the IC devices. As ICs and their memories become more complex and / or decrease in size, the reliability of read operations and / or write (or program) operations performed in the memory needs to be considered. Summary of the invention

[0003] According to one aspect of an embodiment of the present application, a memory circuit is provided, comprising: a memory array; and a peripheral circuit, the peripheral circuit comprising: an internal clock generation circuit, configured to respond to a control signal pulse to generate a series of internal clock pulses in an internal clock period corresponding to the pulse width of the control signal pulse, and a first access signal generation circuit, configured to respond to a first edge of the control signal pulse to generate a first access signal, and wherein the peripheral circuit is configured to control access operations in the memory array based on at least one internal clock pulse in the series of internal clock pulses and the first access signal.

[0004] According to another aspect of an embodiment of the present application, an interface circuit for a memory circuit is provided, the interface circuit comprising: a first counting circuit, the first counting circuit comprising: an input terminal coupled to a control signal input, a clock input terminal coupled to a clock signal input, and an output terminal; a first latch circuit, the first latch circuit comprising: an input terminal coupled to the output terminal of the first counting circuit, a clock input terminal coupled to the clock signal input, and an output terminal; a second counting circuit, the second counting circuit comprising: a clock input terminal coupled to the clock signal input, and an output terminal; a first comparison circuit, the first comparison circuit comprising: a first input terminal coupled to the output terminal of the first latch circuit, a second input terminal coupled to the output terminal of the second counting circuit, and an output terminal; and a second latch circuit, the second latch circuit comprising: a clock input terminal coupled to the output terminal of the first comparison circuit, and an output terminal.

[0005] According to another aspect of an embodiment of the present application, a method for operating a memory circuit is provided, the method comprising: generating, in response to a single pulse of a control signal: a series of internal clock pulses, a first access signal, and a second access signal; and performing at least one of a read operation or a programming operation in the memory circuit based on the first access signal, the second access signal, and at least one internal clock pulse in the series of internal clock pulses. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the present disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are only used for illustrative purposes. In fact, the size of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 is a schematic block diagram of a memory circuit according to some embodiments.

[0008] Figure 2A is a schematic circuit diagram of a memory cell according to some embodiments.

[0009] Figure 2B is a schematic block diagram of a memory circuit according to some embodiments.

[0010] Figure 3A is a schematic block diagram of an interface circuit of a memory circuit according to some embodiments.

[0011] Figure 3B It is a schematic timing diagram of various signals in the interface circuit.

[0012] Figure 3C is a schematic block diagram of an interface circuit of a memory circuit according to some embodiments.

[0013] Figure 4A-Figure 4K is a schematic circuit diagram of various circuits according to some embodiments.

[0014] Figure 5A-Figure 5B is a schematic timing diagram of various operations of an interface circuit and / or a peripheral circuit of a memory circuit according to some embodiments.

[0015] Figure 6A-6B is a schematic circuit diagram of various circuits according to some embodiments.

[0016] Figure 7A-7B are flow diagrams of various methods according to some embodiments. DETAILED DESCRIPTION

[0017] The following disclosure provides many different embodiments or examples for realizing the different features of the present disclosure. The specific embodiments or examples of components, materials, values, steps, and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. Other components, materials, values, steps, arrangements, etc. can be considered. For example, in the following description, forming a first component above or on a second component can include an embodiment in which the first component and the second component are directly contacted to form, and can also include an embodiment in which an additional component can be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present disclosure can repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed. Source / drain can refer to source or drain individually or collectively, depending on the context.

[0018] Additionally, for ease of description, spacing relation terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another element or component as shown in the figures. The spacing relation terms are intended to encompass different orientations of the device in use or in the process of operation in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spacing relation descriptors used herein may likewise be interpreted accordingly.

[0019] An access operation in a memory circuit, such as a read operation or a program operation, is a relatively complex process involving multiple signals that meet one or more requirements of a predetermined timing sequence and / or predetermined waveform to ensure that the access operation is performed correctly and / or reliably. In various cases, generating multiple signals individually or independently to meet the requirements is a difficult task and / or requires complex circuits.

[0020] In some embodiments, multiple signals for access operations in a memory circuit are generated from a common control signal. In at least one embodiment, such multiple signals are generated from a single pulse of a control signal. In one or more embodiments, examples of signals generated from a pulse of a control signal (or a control signal pulse) include, but are not limited to, a series of internal clock pulses, one or more access signals, and the like. In some embodiments, access operations in a memory circuit are performed based on the generated internal clock pulses and the generated one or more access signals. As a result, in one or more embodiments, it can be ensured that various signals generated from a common control signal meet one or more requirements for timing and / or waveforms, thereby avoiding or at least reducing the risk of failure in the memory circuit being accessed.

[0021] In at least one embodiment in which one or more signals for accessing a memory circuit are external signals provided from a circuit or device external to the memory circuit, the number of input / output (I / O) pins (also referred to as I / O pin count) required to receive such external signals is advantageously reduced because multiple signals for internal access to the memory circuit can be generated based on a common control signal provided externally. Some embodiments also provide an over-time protection scheme to prevent erroneous programming or erroneous reading. In at least one embodiment, the time threshold of such an over-time protection scheme and / or the cell count of the memory cell to be accessed is advantageously adjustable. In at least one embodiment, improvements in one or more aspects of power performance area (PPA), reliability, etc. can be achieved.

[0022] Figure 1 1 is a schematic block diagram of a memory circuit 100 according to some embodiments. In at least one embodiment, the memory circuit 100 is a separate IC device. In some embodiments, the memory circuit 100 is included as part of a larger IC device that includes circuits for other functions in addition to the memory circuit 100.

[0023] Memory circuit 100 includes memory partitions 101, 102, 103. Each of memory partitions 101, 102, 103 includes one or more memory banks, one or more word line (WL) driver circuits, and one or more memory bank decoder circuits. For example, memory partition 101 includes memory banks 110, 111, and WL driver circuits 116 and memory bank decoder circuits 117 between memory banks 110, 110. Memory partition 102 includes memory banks 120, 121, and WL driver circuits 126 and memory bank decoder circuits 127 located between memory banks 120 and 121. Memory partition 103 includes memory banks 130, 131, and WL driver circuits 136 and memory bank decoder circuits 137 located between memory banks 130, 132. In some embodiments, the memory bank decoder circuits are configured as part of the corresponding WL driver circuits. For example, the memory bank decoder circuit 117 is configured as part of the WL driver circuit 116. In one or more embodiments, each of the WL driver circuits 116 , 126 , 136 includes a program word line (WLP) driver circuit and a read word line (WL) driver circuit, as described herein.

[0024] Each memory bank includes a memory array and a bit line (BL) selection circuit. For example, each of the memory banks 110, 111, 120, 121, 130, 131 includes one of the memory arrays 112, 113, 122, 123, 132, 133 and one of the BL selection circuits 114, 115, 124, 125, 134, 135, respectively. As described herein, each of the memory arrays 112, 113, 122, 123, 132, 133 includes a plurality of memory cells ( Figure 1 Not shown), and through a plurality of word lines along the row ( Figure 1 Not shown) and a plurality of bit lines along the column ( Figure 1 (not shown) are coupled to corresponding WL driver circuits and corresponding BL selection circuits. In at least one embodiment, the plurality of word lines include programming word lines and reading word lines, as described herein. Figure 2A-2B Example configurations and / or arrangements of memory cells, bit lines, and word lines are described.

[0025] In some embodiments, the memory circuit 100 includes a non-volatile (NVM) memory, and the memory cells in the memory circuit 100 are correspondingly NVM memory cells. Examples of non-volatile memory include, but are not limited to, one-time programmable (OTP) memory, such as an electric fuse (eFuse), an antifuse, a flash memory, a resistive random access memory (RAM), a ferroelectric RAM, a magnetoresistive RAM, a phase change memory (PCM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), etc.

[0026] The memory circuit 100 also includes BL driver circuits 142, 143, read / program circuits 144, 145, global bit lines 146, 147, and a control circuit 150. The BL driver circuit 142 and the read / program circuit 144 can be selectively coupled to one of the memory arrays 112, 122, 132 via the global bit line 146 and the corresponding BL selection circuits 114, 124, 134. The BL driver circuit 143 and the read / program circuit 145 can be selectively coupled to one of the memory arrays 113, 123, 133 via the global bit line 147 and the corresponding BL selection circuits 115, 125, 135. Figure 1 In the embodiment of the present invention, the number of memory partitions, global bit lines, BL driver circuits, and read / program circuits in memory circuit 100, the number of memory banks and WL driver circuits in each memory partition, and the number of memory arrays and BL selection circuits in each memory bank are examples. Other configurations are within the scope of various embodiments.

[0027] Each of the WL driver circuits 116, 126, 136 is configured to receive one or more address signals and apply a word line voltage on one or more word lines according to the address signals. In some embodiments, where the WL driver circuits 116, 126, 136 include a WLP driver circuit and a WLR driver circuit, the WLP driver circuit is configured to apply a program word line voltage on one or more program word lines according to the address signals, and the WLR driver circuit is configured to apply a read word line voltage on one or more read word lines according to the address signals.

[0028] Each memory bank decoder circuit 117, 127, 137 is configured to generate an enable signal corresponding to a memory cell identified by one or more address signals and output the enable signal to a corresponding memory bank of a corresponding memory partition 101, 102, 103. For example, the memory bank decoder circuit 117 is configured to output enable signals to the memory banks 110, 111, etc. of the memory partition 101.

[0029] Each of the BL selection circuits 114, 115, 124, 125, 134, 135 is configured to selectively couple one or more bit lines to corresponding BL driver circuits 142, 143 and / or corresponding read / program circuits 144, 145 via corresponding global bit lines 146, 147 to selectively access one or more bit lines in the corresponding memory array 112, 113, 122, 123, 132, 133.

[0030] Each of the BL driver circuits 142, 143 is configured to generate a bit line voltage and apply the bit line voltage on the corresponding global bit lines 146, 147 according to an access operation of one or more memory cells in the memory circuit 100. The bit line voltage is applied to one or more memory cells to be accessed through the corresponding BL selection circuit and bit line.

[0031] Each of the read / program circuits 144, 145 is configured to perform read and / or program operations of one or more memory cells in the memory circuit 100. In some embodiments, each of the read / program circuits 144, 145 includes a read circuit configured to perform a read operation and a program circuit configured to perform a program operation on one or more memory cells in the memory circuit 100. In some embodiments, the read circuit includes a sense amplifier configured to determine an absolute and / or relative voltage and / or current level of one or more signals received from a selected memory cell via a corresponding global bit line 146, 147.

[0032] The control circuit 150 is configured to control some or all programming and reading operations on the memory cells in the memory circuit 100, for example, by generating and / or outputting one or more control signals and / or enable signals. In some embodiments, the control circuit 150 includes one or more circuits, including but not limited to global address decoder circuits, pre-decoder circuits, pre-charge circuits, address latches, pulse generators, timing circuits, clock generators and / or drivers, input / output (I / O) circuits for exchanging data, addresses, clocks and / or controls with external devices, etc. Examples of I / O signals sent and / or received by the I / O circuits include clock signals, addresses of memory cells to be accessed, input data to be written or programmed to the accessed memory cells, output data read from the accessed memory cells, chip enable (CEB) signals, write enable (WEB) signals, etc. The CEB signal is a signal that enables or disables the memory circuit 100 or one or more memory partitions 101, 102, 103 thereof. The signal WEB is a signal that enables or disables writing to one or more memory cells. Other I / O signals are within the scope of various embodiments. The described memory circuit configurations are examples and other memory circuit configurations are within the scope of the various embodiments.

[0033] In some embodiments, the circuits in the memory circuit other than the memory array are collectively referred to as peripheral circuits. Figure 1 In the example configuration in FIG. 1 , WL driver circuits 116, 126, 136, bank decoder circuits 117, 127, 137, BL driver circuits 142, 143, read / program circuits 144, 145, and control circuits 150 are collectively referred to as peripheral circuits 160. In some embodiments, peripheral circuits 160 also include BL selection circuits 114, 115, 124, 125, 134, 135. Peripheral circuits are sometimes referred to as memory controllers.

[0034] Peripheral circuit 160 includes interface circuit 170 having a plurality of I / O pins 173. Some I / O pins 173 are configured to receive input signals 175 for controlling access operations of one or more memory cells in memory circuit 100. One or more other I / O pins 173 are configured to transmit output signals 177. In some embodiments, as described herein, at least one, some, or all of input signals 175 and / or output signals 177 are I / O signals. Figure 1In the example configuration in FIG. 1 , input signal 175 includes clock signal CLK, power supply voltage VDDIO, and control signal SCLKEN. In at least one embodiment, interface circuit 170 is configured to generate an internal clock pulse series and one or more access signals for controlling access operations of one or more memory cells in memory circuit 100 based on pulses of control signal SCLKEN. In at least one embodiment, output signal 177 includes data read from one or more memory cells of memory circuit 100. In some embodiments, output signal 177 is omitted or output by an I / O circuit other than interface circuit 170. Figure 1 The arrangement of the interface circuit 170 in the control circuit 150 in FIG. 1 is an example. In at least one embodiment, the interface circuit 170 is included in the peripheral circuit 160 but is outside the control circuit 150.

[0035] In some embodiments, at least one, some, or all of input signals 175 are generated and / or provided by an IC device that includes memory circuit 100 or is permanently coupled to memory circuit 100. An example of an IC device that is permanently coupled to a memory circuit is an IC structure or package in which the memory circuit is configured as a memory chip or die disposed on or adjacent to the IC device. I / O pins of the memory die, such as I / O pin 173, are coupled to corresponding I / O pins of the IC device via conductive traces and / or vias on or through a substrate that is disposed between or on which the memory die and the IC device are supported.

[0036] In some embodiments, at least one, some, or all of the input signals 175 are generated and / or provided by an external circuit or external device that is detachably or removably coupled to the memory circuit 100. For example, after the memory circuit 100 is manufactured, before the memory circuit 100 is shipped to a customer or continues to further manufacturing processes, the memory circuit 100 is subjected to a test sometimes referred to as a wafer acceptance test (WAT). For such a test, the terminals of the external test equipment are contacted with the corresponding terminals of the memory circuit 100. The test equipment sends test signals, data, or patterns through the test equipment and the corresponding terminals of the memory circuit 100, and receives the test results to verify whether the memory circuit 100 is manufactured and / or operates as designed. When the test is completed, the terminals of the external test equipment are removed or disconnected from the terminals of the memory circuit 100.

[0037] In at least one embodiment, the configuration of the interface circuit 170 that generates various signals internally based on the control signal SCLKEN ensures the reliability of the access operation and / or reduces the number of I / O pins 173 required to receive the input signal 175 for controlling the access operation. In some embodiments, this effect is more pronounced in test situations where the number of pins or terminals of the test equipment is limited, and / or when the timing and / or waveform of the test signal provided by the test equipment is less than ideal and / or is subject to undesirable changes.

[0038] Figure 2A 1 is a schematic circuit diagram of a memory cell MC according to some embodiments. In at least one embodiment, the memory cell MC corresponds to a memory cell in the memory circuit 100. Figure 2A In the example configuration of , the memory cell MC is an anti-fuse. Other memory configurations are within the scope of various embodiments.

[0039] The memory cell MC is coupled to a read word line WLR0, a programming word line WLP0, and a bit line BL0. The memory cell MC includes transistors T1, T2. The transistor T1 (sometimes referred to as an access transistor) includes a gate terminal 210 coupled to the read word line WLR0, a first terminal 211 coupled to the bit line BL0, and a second terminal 212. The transistor T2 (sometimes referred to as an anti-fuse transistor) includes a gate terminal 220 coupled to the programming word line WLP0, a floating first terminal 221, and a second terminal 222 coupled to the second terminal 212 of the transistor T1. In other words, the transistors T1, T2 are coupled to each other in series.

[0040] The read word line WLR0 is an example of one of the first word line and the second word line coupled to the memory cell MC, and the program word line WLP0 is an example of the other of the first word line or the second word line. Figure 2A The number of word lines and / or bit lines coupled to the memory cells is an example. Other configurations are within the scope of various embodiments. For example, in various memory configurations, each memory cell is coupled to one word line and one bit line, or each memory cell is coupled to one word line and a pair of bit lines, or each memory cell is connected to a pair of word lines and a pair of bit lines, etc.

[0041] Examples of transistor T1 and / or transistor T2 include, but are not limited to, metal oxide semiconductor field effect transistors (MOSFETs), complementary metal oxide semiconductor (CMOS) transistors, P-channel metal oxide semiconductors (PMOS), N-channel metal oxide semiconductors (NMOS), bipolar junction transistors, high voltage transistors, high frequency transistors, P-channel and / or N-channel field effect transistors (PFET / NFET), FinFETs (fin field effect transistors), planar MOS transistors with protruding sources / drains, nanosheet FETs, nanowire FETs, etc. The first terminal 211 is the source / drain of transistor T1, and the second terminal 212 is the other source / drain of transistor T1. The first terminal 221 is the source / drain of transistor T2, and the second terminal 222 is the other source / drain of transistor T2. In reference to Figure 2A and Figure 2B In the described example configuration, transistor T1 and transistor T2 are NMOS transistors, the first terminal 211 is the source of transistor T1, the second terminal 212 is the drain of transistor T1, the first terminal 221 is the drain of transistor T2, and the second terminal 222 is the source of transistor T2. Other configurations including PMOS transistors instead of NMOS transistors are within the scope of various embodiments. In some embodiments, the second terminal 212 of transistor T1 and the second terminal 222 of transistor T2 are the same, that is, transistor T1 and transistor T2 share a common source / drain. In at least one embodiment, transistor T1 and transistor T2 are configured identically. For example, transistor T1 and transistor T2 have the same size and are manufactured by the same process.

[0042] The transistor T2 includes a gate dielectric, and when a predetermined breakdown voltage sufficient to break down the gate dielectric is applied to the gate dielectric, the gate dielectric is configured to break down. When the gate dielectric of the transistor T2 breaks down, the broken down gate dielectric is configured as a resistor and corresponds to the first data stored in the memory cell MC, such as a logic "0". When the gate dielectric is not broken down, the memory cell MC stores different second data, such as a logic "1". Example materials of the gate dielectric include, but are not limited to, silicon dioxide, high-k dielectrics, etc. Examples of high-k dielectrics include, but are not limited to, zirconium dioxide, hafnium dioxide, zirconium silicate, hafnium silicate, etc.

[0043] In some embodiments, access operations of the memory cells MC, such as read operations and program operations, are controlled by a controller (not shown). In at least one embodiment, the controller corresponds to the peripheral circuit 160. The controller is coupled to the memory cells MC via the read word line WLR0, the program word line WLP0, and the bit line BL0. Example access operations according to some embodiments are described herein.

[0044] In a programming operation for programming the memory cell MC to store a logic "0", the controller applies a ground voltage (e.g., 0V) to the bit line BL0, applies a first access voltage (e.g., 1.2V) to the bit line WLR0, and applies a programming voltage (e.g., 5V) to the programming word line WLP0. Since the first access voltage is applied to the gate terminal 210 of the transistor T1 through the read word line WLR0, the transistor T1 is turned on. The ground voltage on the bit line BL0 is applied to the second terminal 222 of the transistor T2 through the turned-on transistor T1. The programming voltage applied to the gate terminal 220 of the transistor T2 and the ground voltage on the second terminal 222 of the transistor T2 generate a voltage stress equal to the programming voltage across the gate dielectric of the transistor T2. Since the programming voltage is higher than the predetermined breakdown voltage of the gate dielectric, the gate dielectric of the transistor T2 is broken down, corresponding to the logic "0" stored in the memory cell MC.

[0045] In a programming operation for programming the memory cell MC to store a logic "1", the controller applies a first access voltage (e.g., 1.2V) to the bit line BL0 and the read word line WLR0, and applies a programming voltage (e.g., 5V) to the bit line WLP0. The transistor T1 is turned on, and the first access voltage is applied to the second terminal 222 of the transistor T2 through the turned-on transistor T1. The voltage stress across the gate dielectric of the transistor T2 is the voltage difference between the programming voltage and the first access voltage (e.g., 5V minus 1.2V). The voltage stress is not higher than the predetermined breakdown voltage of the gate dielectric, and the gate dielectric of the transistor T2 is not broken down, corresponding to the logic "1" stored in the memory cell MC.

[0046] In a read operation of the memory cell MC, the controller applies a ground voltage, a second access voltage (e.g., 0.75V) to the read word line WLR0, and applies a read voltage (e.g., 1.45V) to the programming word line WLP0. Transistor T1 is turned on, the read voltage is not enough to change the programming state (or data) of transistor T2, and the read current flows to the controller through the bit line BL0. When the gate dielectric of transistor T2 is broken down, the read current is high, and when the gate dielectric of transistor T2 is not broken down, the read current is low. The sense amplifier in the controller detects the read current and outputs the data stored in the memory cell MC and the data read from the memory cell MC. The specific voltage values ​​described herein, such as 1.2V, 5V, 0.75V, 1.45V, are examples. Other voltage values ​​are within the scope of various embodiments.

[0047] Figure 2B is a schematic block diagram of a memory circuit 200 according to some embodiments. In some embodiments, the memory circuit 200 corresponds to the memory circuit 100.

[0048] The memory circuit 200 includes N segments represented as segment 1, segment 2 to segment N, where N is a natural number. In some embodiments, segment 1, segment 2 to segment N are configured similarly. Segment 1 is described here, and detailed descriptions of segment 2 to segment N are omitted. Segment 1 includes one or more memory arrays and corresponding one or more BL selection circuits. For example, Figure 2B Memory array 230 and corresponding BL selection circuit 240 are shown in FIG. In some embodiments, memory array 230 corresponds to one or more of memory arrays 112, 113, 122, 123, 132, 133, and BL selection circuit 240 corresponds to one or more of BL selection circuits 114, 115, 124, 125, 134, 135.

[0049] exist Figure 2B In the example configuration, the memory array 230 includes reference Figure 2A A plurality of memory cells MC are described. The memory cells MC are arranged into a plurality of rows (unnumbered) and a plurality of columns (unnumbered). The memory cells MC in each row are coupled to a corresponding pair of word lines, and the memory cells MC in each column are coupled to a corresponding bit line. For example, the memory array 230 includes K pairs of word lines and M columns, where K and M are natural numbers. A pair of word lines WLR[1], WLP[1] are coupled to the memory cells MC in the first row 231, another pair of word lines (not shown) are coupled to the memory cells MC in the second row (not shown), and a pair of word lines WLR[K], WLP[K] are coupled to the memory cells MC in the Kth row. The bit line BL[1] is coupled to the memory cells MC in the first column, another bit line (not shown) is coupled to the memory cells MC in the second column, and the bit line BL[M] is coupled to the memory cells MC in the Mth column. In some embodiments, each of the bit lines BL[1] to BL[M] corresponds to bit line BL0, each of the word lines WLP[1] to WLP[K] corresponds to programming word line WLP0, and each of the word lines WLR[1] to WLR[K] corresponds to read word line WLR0.

[0050] Segment 1 further includes a global bit line GBL and a read / program circuit 250 coupled to the BL selection circuit 240 through the global bit line GBL. In some embodiments, the global bit line GBL corresponds to one or more of the global bit lines 146, 147, and the read / program circuit 250 corresponds to one or more of the read / program circuits 144, 145. In some embodiments, segment 1 further includes a BL driver circuit corresponding to one or more of the BL driver circuits 142, 143. The read / program circuit 250 is configured to output read data Q read from one or more memory cells MC of the memory array 230. <1> The corresponding read / program circuits of Segment 2 to Segment N are configured to output the read data Q <2> , to read data Q from one or more memory cells of the corresponding memory array in Segment 2 to Segment N <n>. Read data Q <1> , Q <2> To Q <n>They are collectively referred to as read data Q<1:N>.

[0051] As reference Figure 2A As described, in the access operation of the memory array 230, various voltages are applied to the word lines in the memory array 230, for example, by the controller described herein. For example, in the access operation of one or more memory cells MC in the row 231, the word lines WLR[1] and WLP[1] are accessed by applying the first or second access voltage to the word line WLR[1] and applying the programming voltage or the reading voltage to the word line WLP[1]. In some embodiments, the voltage levels (or voltage values) of the first access voltage, the second access voltage, the programming voltage, and the reading voltage are controlled by the corresponding WL driver circuits coupled to the word lines WLR[1] and WLP[1], and the timing and duration (or rising edge and falling edge) of the voltages are controlled by the access signals WLR and WLP. In some embodiments, the timing and duration (or rising edge and falling edge) of the first access voltage or the second access voltage on the word line WLR[1] corresponds to the timing and holding time (or falling edge and rising edge) of the access signal WLR. For example, the access signal WLR is applied to a gate or input or control terminal of a WLR driver circuit (e.g., a transistor or an inverter), and causes the WLR driver circuit to output a corresponding first access voltage or a second access voltage to the word line WLR[1]. In some embodiments, the timing and duration (or rising edge and falling edge) of the programming voltage or the reading voltage on the word line WLP[1] correspond to the timing and holding time (or falling edge and rising edge) of the access signal WLP. For example, the access signal WLP is applied to a gate or input or control terminal of a WLP driver circuit (e.g., a transistor or an inverter), and causes the WLP driver circuit to output a corresponding programming voltage or a reading voltage to the word line WLP[1]. The access signal WLR is an example of a first access signal and a second access signal, and the access signal WLP is an example of the other of the first access signal and the second access signal.

[0052] Furthermore, during an access operation of the memory array 230, the BL selection circuit 240 is configured to respond to the BL selection signal SBL <1> To SBL <m>The read / program circuit 250 sequentially accesses the bit lines BL[1] to BL[M] one at a time by coupling each of the bit lines BL[1] to BL[M] to the global bit line GBL. As a result, the read / program circuit 250 sequentially couples to or sequentially accesses the bit lines BL[1] to BL[M] one at a time to perform a read operation or a program operation of the memory cells MC coupled to the word lines WLR[1], WLP[1] and the accessed bit lines. The memory cells MC in other rows of the memory array 230 are accessed in a similar manner.

[0053] In some embodiments, the BL selection signals SBL<1:M> correspond to a series of internal clock pulses. Figure 4A An example circuit configured to generate BL select signals SBL<1:M> based on an internal clock signal SCLK having a series of internal clock pulses is described. In some embodiments, at least one of the internal clock signal SCLK and the access signals WLR, WLP is generated by an interface circuit (e.g., one or more interface circuits described herein) based on pulses of a control signal (e.g., control signal SCLKEN).

[0054] Figure 3A is a schematic block diagram of an interface circuit 300 of a memory circuit according to some embodiments. Figure 3B is a schematic timing diagram of a control signal SCLKEN input to the interface circuit 300 and an internal clock signal SCLK output from the interface circuit 300 according to some embodiments. In at least one embodiment, the interface circuit 300 corresponds to the interface circuit 170, and / or is part of a peripheral circuit of a memory circuit (e.g., the peripheral circuit 160 of the memory circuit 100, or the peripheral circuit of the memory circuit 200).

[0055] The interface circuit 300 includes an internal clock generation circuit 302 and access signal generation circuits 304, 306. One of the access signal generation circuits 304, 306 is an example of a first access signal generation circuit, and the other is an example of a second access signal generation circuit. In some embodiments, one of the access signal generation circuits 304, 306 is omitted.

[0056] The internal clock generation circuit 302 includes a pulse width detection circuit 310 , a storage circuit 320 , a pulse width counting circuit 330 , a comparison circuit 340 , another output circuit 350 , and a unit counting circuit 360 .

[0057] The pulse width detection circuit 310 includes an input terminal 311 coupled to a control signal input terminal to receive a control signal SCLKEN, a clock input terminal 312 coupled to a clock signal input terminal to receive a clock signal CLK, and an output terminal 315. For simplicity, input terminals, nodes, or output terminals are sometimes referred to herein by the same reference number of the signal at the input terminal, node, or output terminal. For example, a control signal input terminal for receiving a control signal SCLKEN is sometimes referred to herein as a control signal input SCLKEN, a clock signal input terminal for receiving a clock signal CLK is sometimes referred to herein as a clock signal input CLK, and the like. The control signal input SCLKEN and the clock signal input CLK correspond to input terminals of the internal clock generation circuit 302. Referring to Figure 4B An example configuration of the pulse width detection circuit 310 is described.

[0058] The storage circuit 320 includes an input terminal 321 coupled to the output terminal 315 of the pulse width detection circuit 310, a clock input terminal 322 coupled to the clock signal input CLK, and an output terminal 325. Figure 3A In the example configuration of , storage circuit 320 includes a latch circuit (sometimes referred to as a latch). Other storage circuit configurations configured to store data are within the scope of various embodiments.

[0059] The pulse width counting circuit 330 includes an input terminal 331 coupled to the control signal input SCLKEN, a clock input terminal 332 coupled to the clock signal input CLK, a reset input terminal 334, and an output terminal 335. Figure 4C An example configuration of the pulse width counting circuit 330 is described.

[0060] Comparison circuit 340 includes a first input 341 coupled to output 325 of storage circuit 320, a second input 342 coupled to output 335 of pulse width counting circuit 330, and an output 345 coupled to reset input 334 of pulse width counting circuit 330. In an example configuration, comparison circuit 340 includes an operational amplifier and / or a logic gate. Other comparison circuit configurations are within the scope of various embodiments.

[0061] The output circuit 350 includes a clock input 352 coupled to the output 345 of the comparison circuit 340, an enable input 354, and an output 355 corresponding to the output of the internal clock generation circuit 302. Figure 3A In the example configuration of , output circuit 350 includes a latch circuit. Other output circuit configurations are within the scope of various embodiments.

[0062] The unit counting circuit 360 includes an input terminal 361 coupled to the output terminal 345 of the comparison circuit 340, a clock input terminal 362 coupled to the clock signal input CLK, and an output terminal 365 coupled to the enable input terminal 354 of the output circuit 350. Figure 4D An example configuration of the unit counting circuit 360 is described.

[0063] The pulse width detection circuit 310 is configured to detect the pulse width of the control signal pulse of the control signal SCLKEN received at the input terminal 311 and output the detected pulse width through the signal S1 at the output terminal 315. Figure 3B As shown, the control signal SCLKEN includes a control signal pulse 316 having a rising edge 318, a falling edge 319, and a pulse width PW between the rising edge 318 and the falling edge 319. In at least one embodiment, in response to the rising edge 318, the pulse width detection circuit 310 is configured to start counting the number of clock pulses of the clock signal CLK (referred to herein as clock pulses CLK), and in response to the falling edge 319, the pulse width detection circuit 310 is configured to stop counting. The number of clock pulses CLK counted by the pulse width detection circuit 310 between the rising edge 318 and the falling edge 319 corresponds to the detected pulse width PW of the control signal pulse 316. The count of the clock pulses CLK or the detected pulse width PW is output at the output terminal 315 of the pulse width detection circuit 310 via the signal S1.

[0064] The storage circuit 320 is configured to store the detected pulse width PW of the received control signal pulse 316 via the signal S1 at the input terminal 321, and output the detected pulse width PW via the signal RECCLK at the output terminal 325. In at least one embodiment, the storage circuit 320 is configured to store and output the count number of the clock pulse CLK output by the pulse width detection circuit 310 as the detected pulse width PW of the control signal pulse 316.

[0065] The pulse width counting circuit 330 is configured to count the number of clock pulses CLK in response to the edge of the control signal pulse 316. In some embodiments, the pulse width counting circuit 330 is configured to count the number of clock pulses CLK in response to the falling edge 319 of the control signal pulse 316. In at least one embodiment, the pulse width counting circuit 330 is configured to count the number of clock pulses CLK after the falling edge 319, i.e., after the end of the control signal pulse 316. The number of clock pulses CLK counted by the pulse width counting circuit 330 is output at the output 335 of the pulse width counting circuit 320 via the signal PWCLK.

[0066] The comparison circuit 340 is configured to compare the number of clock pulses CLK counted by the pulse width counting circuit 330 as a signal PWCLK received at the second input terminal 342 with the detected pulse width PW of the control signal pulse 316 as a signal RECCLK received at the first input terminal 341. In response to the number of clock pulses CLK represented by the signal PWCLK being equal to the detected pulse width PW represented by the signal RECCLK, the comparison circuit 340 is configured to output a pulse of the signal PRESCLK at the output 345. The pulse of the signal PRESCLK (sometimes referred to herein as a PRESCLK pulse) is applied to the reset input terminal 334 to reset the count number of the pulse width counting circuit 330, for example to zero. The pulse width counting circuit 330 is configured to count the number of clock pulses CLK upward from zero again to the detected pulse width PW represented by the signal RECCLK, at which time the comparison circuit 340 is configured to output the next PRESCLK pulse. The next PRESCLK pulse resets the pulse width counting circuit 330 again, and the process is repeated. As a result, a PRESCLK pulse is generated in a period corresponding to the detected pulse width PW stored in the storage circuit 320 .

[0067] Output circuit 350 is configured to output a corresponding pulse of internal clock signal SCLK at at least one conductor 355 in response to each pulse in signal PRESCLK arriving at clock input 352. For example, Figure 3B As shown, the internal clock signal SCLK includes a series of internal clock pulses 356, 357, etc. The internal clock pulses of the internal clock signal SCLK are sometimes referred to as internal clock pulses SCLK. The internal clock pulses SCLK have an internal clock period T between consecutive internal clock pulses SCLK. BL The internal clock period T is generated at, for example, between the rising edge 358 of the internal clock pulse 356 and the rising edge 359 of the internal clock pulse 357. Because each internal clock pulse SCLK corresponds to one PRESCLK pulse, the internal clock period T BL The internal clock generation circuit 302 is configured to respond to the control signal pulse 316 and detect the pulse width PW of the control signal pulse 316 during the internal clock period T corresponding to the pulse width PW of the control signal pulse 316. BL The internal clock pulse series SCLK is generated at.

[0068] The cell counting circuit 360 is configured to count the number of pulses in the signal PRESCLK arriving at the input terminal 361, which number of pulses corresponds to the number of internal clock pulses SCLK output at the output terminal 355. In response to the counted number of internal clock pulses SCLK being equal to a predetermined value (or predetermined cell count) set or input in the cell counting circuit 360, the cell counting circuit 360 is configured to output a signal S2 at the output terminal 365. The signal S2 is applied to the enable input terminal 354 of the output circuit 350 to stop the output circuit 350 from outputting further internal clock pulses SCLK regardless of the arrival of further PRESCLK pulses at the clock input 352. As a result, the number of internal clock pulses SCLK output by the internal clock generating circuit 302 is controlled by the predetermined cell count of the cell counting circuit 360. In some embodiments, the predetermined cell count in the cell counting circuit 360 is M, and M is the number of bit lines in the memory array to be accessed in an access operation, as shown in reference to FIG. Figure 2B For example, Figure 3B As shown, the internal clock signal SCLK includes M pulses. In some embodiments, the predetermined unit count in the unit counting circuit 360 is greater than M, resulting in some internal clock pulses SCLK not being used for access operations. The interface circuit 300 or another circuit of the peripheral circuit of the memory circuit is configured to generate a BL selection signal based on the internal clock pulse SCLK output by the internal clock generating circuit 302, as shown in FIG. Figure 2B described.

[0069] As described herein, the configuration of the output circuit 350 as a latch circuit is an example. Any output circuit 350 configured to disable or stop outputting further internal clock pulses SCLK in response to the signal S2 is within the scope of various embodiments. The signal S1, the signal RECCLK, the signal PWCLK, the signal PRESCLK, the signal S2, and the signals S3-S9 described below are examples of intermediate signals in the internal clock generation circuit 302. The configuration of the internal clock generation circuit 302 described is an example. Other configurations are within the scope of various embodiments.

[0070] The access signal generating circuit 304 includes a rising edge detection circuit 370 and a delay circuit 380. The rising edge detection circuit 370 includes an input terminal 371 coupled to the control signal input SCLKEN, a clock input terminal 372 coupled to the clock signal input CLK, a reset input terminal 374 configured to receive a reset signal reset1, and an output terminal 375. The delay circuit 380 includes an input terminal 381 coupled to an output terminal 375 of the rising edge detection circuit 370, and an output terminal 385. The control signal input SCLKEN and the clock signal input CLK correspond to the inputs of the access signal generating circuit 304, and the output terminal 385 of the delay circuit 380 corresponds to the access signal generating circuit 304. In some embodiments, the delay circuit 380 is omitted, and the output terminal 375 of the rising edge detection circuit 370 corresponds to the output of the access signal generating circuit 304. Referring to Figure 4E An example configuration of rising edge detection circuit 370 is described. An example configuration of delay circuit 380 includes one or more inverters. Other configurations of rising edge detection circuit 370 and / or delay circuit 380 are within the scope of various embodiments.

[0071] The rising edge detection circuit 370 is configured to detect the rising edge 318 of the control signal pulse 316, and in response to the detected rising edge 318, generate a rising edge of the signal S3 at the output terminal 375. The rising edge detection circuit 370 is configured to maintain the output 375 at a high level, such as a logic "1", until the reset signal reset1 is applied to the reset input terminal 374. In response to the reset signal reset1 applied at the reset input terminal 374, the rising edge detection circuit 370 is configured to generate a falling edge of the signal S3. Figure 4G An example circuit configured to generate a reset signal reset1 is described.

[0072] The delay circuit 380 is configured to output a delayed version of the signal S3 as the access signal WLR. In some embodiments, the delay circuit 380 is omitted, and the signal S3 is output as the access signal WLR. The duration of the access signal WLR is determined by the rising edge 318 of the control signal pulse 316 and the reset signal reset1, and is configured to be sufficient for an access operation in the memory circuit.

[0073] The access signal generating circuit 306 includes a falling edge detection circuit 390 and a delay circuit 386. The falling edge detection circuit 390 includes an input terminal 391 coupled to the control signal input SCLKEN, a clock input terminal 392 coupled to the clock signal input CLK, a reset input terminal 394 configured to receive a reset signal reset2, and an output terminal 395. The delay circuit 386 includes an input terminal 387 coupled to an output terminal 395 of the falling edge detection circuit 390, and an output terminal 389. The control signal input SCLKEN and the clock signal input CLK correspond to the inputs of the access signal generating circuit 306, and the output terminal 389 of the delay circuit 386 corresponds to the output of the access signal generating circuit 306. In some embodiments, the delay circuit 386 is omitted, and the output terminal 395 of the falling edge detection circuit 390 corresponds to the output of the access signal generating circuit 306. Referring to FIG. Figure 4F An example configuration of falling edge detection circuit 390 is described. An example configuration of delay circuit 386 includes one or more inverters. Other configurations of falling edge detection circuit 390 and / or delay circuit 386 are within the scope of various embodiments.

[0074] The falling edge detection circuit 390 is configured to detect a falling edge 319 of the control signal pulse 316, and in response to the detected falling edge 319, generate a rising edge of the signal S4 at the output terminal 395. The falling edge detection circuit 390 is configured to maintain the output terminal 395 at a high level, such as a logic "1", until the reset signal reset2 is applied to the reset input 394. In response to the reset signal reset2 applied at the reset input 394, the falling edge detection circuit 390 is configured to generate a falling edge of the signal S4. In at least one embodiment, the reset signal reset2 is received at the reset input terminal 394 before the reset signal reset1 is received at the reset input terminal 374. Referring to Figure 4H An example circuit configured to generate a reset signal reset2 is described.

[0075] The delay circuit 386 is configured to output a delayed version of the signal S4 as the access signal WLP. In some embodiments, the delay circuit 386 is omitted and the signal S4 is output as the access signal WLP. The duration of the access signal WLP is determined by the falling edge 319 of the control signal pulse 316 and the reset signal reset2, and is configured to be sufficient for access operations in the memory circuit. In some embodiments, the duration of the access signal WLP is within the duration of the access signal WLR. The configurations of the access signal generation circuits 304, 306 described are examples. Other configurations are within the scope of various embodiments.

[0076] In some embodiments, the peripheral circuit of the memory circuit is configured to control the access operation in the memory array based on at least one of the internal clock pulses SCLK and at least one of the access signals WLR, WLP. Figure 2B and / or Figure 4A As described above, the internal clock pulse SCLK is used to generate a BL selection signal to select a bit line coupled to a memory cell to be accessed, and the access signals WLR and WLP are used to control various voltages applied to corresponding word lines coupled to the memory cell to be accessed.

[0077] Compared to other methods in which various signals similar to signals SCLK, WLR, and WLP are input separately into a memory circuit for access operations, according to some embodiments, it is sufficient to input a common signal (such as a control signal SCLKEN) into an interface circuit, which is configured to internally generate signals SCLK, WLR, and / or WLP for controlling access operations based on the control signal SCLKEN. In some embodiments, the signals SCLK, WLR, and WLP are generated based on a single pulse of the control signal SCLKEN. As a result, in one or more embodiments, the number of I / O pins required to receive control signals is reduced, while one or more requirements for the correct signal sequence and / or waveform are met to ensure that access operations are performed correctly and / or reliably. In at least one embodiment, the reduction in the number of required I / O pins makes it possible to minimize the area occupied by the interface circuit and / or memory circuit. In some embodiments, the single pulse control avoids or at least reduces the risk of the control signal being erroneously input into the memory circuit, which in turn avoids or at least reduces the risk of the memory circuit malfunctioning. According to various embodiments, other effects and / or advantages can be achieved.

[0078] Figure 3C is a schematic block diagram of an interface circuit 301 of a memory circuit according to some embodiments. In at least one embodiment, the interface circuit 301 corresponds to the interface circuit 170 and / or is part of a peripheral circuit of a memory circuit (e.g., the peripheral circuit 160 of the memory circuit 100 or the peripheral circuit of the memory circuit 200). Figure 3A , Figure 3C Corresponding elements in the drawings are denoted by the same reference numerals.

[0079] Interface circuit 301 is the same as interface circuit 300, including internal clock generation circuit 303 and access signal generation circuits 304 and 306. For simplicity, Figure 3C The access signal generating circuits 304 and 306 are not shown.

[0080] Compared with the internal clock generation circuit 302 in the interface circuit 300, the internal clock generation circuit 303 further includes an overtime protection circuit 305, which is configured to prevent misprogramming or misreading in overtime when the control signal pulse of the control signal SCLKEN is too long, for example, when the pulse width of the control signal pulse 316 is not shorter than a predetermined time threshold. Figure 3C In the example configuration, the protection circuit 305 includes a rising edge detection circuit 307 and an OR gate 309 .

[0081] The rising edge detection circuit 307 includes an input terminal 327, a clock input terminal 328, and an output terminal 329. The input terminal 327 is coupled to the output terminal 345 of the comparison circuit 340 to receive the signal PRESCLK. The clock input terminal 328 is coupled to the clock signal input CLK. At the output terminal 329, the rising edge detection circuit 307 outputs a signal S8. The OR gate 309 includes a first input terminal coupled to the output terminal 329 of the rising edge detection circuit 307 to receive the signal S8, a second input terminal configured to receive the overtime detection signal OVP, and an output terminal coupled to the reset input terminal 334 of the pulse width counting circuit 330. Figure 4K An example configuration of the rising edge detection circuit 307 is described. Figure 4B An example circuit configured to generate the recovery detection signal OVP is described. The configuration of the recovery protection circuit 305 described is an example. Other recovery protection circuit configurations are within the scope of various embodiments.

[0082] The rising edge detection circuit 307 is configured to detect the rising edge of the signal PRESCLK at the input terminal 327, and in response to the detected rising edge of the signal PRESCLK, output a signal S8 having a high level (e.g., logic "1") to the corresponding input terminal of the OR gate 309 through the output terminal 329. Then, the OR gate 309 outputs a signal S9 of logic "1" to the reset input terminal 334 of the pulse width counting circuit 330 to reset the count number of the pulse width counting circuit 330, e.g., to zero. This operation is similar to the operation described with respect to the interface circuit 300, and is performed when the overclocking detection signal OVP is at logic "0", i.e., the overclocking condition is not detected.

[0083] When a timeout condition is detected, the timeout detection signal OVP is at logic "1", the output terminal of the OR gate 309 and the signal S9 of the reset input terminal 334 are maintained at logic "1", the pulse width counting circuit 330 is maintained in the reset state, and the signal PWCLK is maintained at logic "0". In response to the signal PWCLK being maintained at logic "0", the comparison circuit 340 maintains the signal PRESCLK at "0" state, that is, does not output the PRESCLK pulse. As a result, the output circuit 350 maintains the internal clock signal SCLK at logic "0", that is, does not output the internal clock pulse SCLK. As shown in reference Figure 2B and / or Figure 4A As described above, the internal clock pulse SCLK is used to generate a BL selection signal to select a bit line coupled to a memory cell MC to be accessed. In at least one embodiment, when the internal clock pulse SCLK is not output, the BL selection signal is not generated, and a read operation and / or a program operation of the memory cell MC in the memory array 230 is not performed to prevent misprogramming or misreading due to a detected time-varying situation. According to various embodiments, other effects and / or advantages may be achieved.

[0084] Figure 4A is a schematic circuit diagram of a BL selection signal generation circuit 400A according to some embodiments. In some embodiments, the BL selection signal generation circuit 400A is part of an interface circuit (e.g., interface circuit 170 and / or interface circuit 300) described herein. In at least one embodiment, the BL selection signal generation circuit 400A is part of a peripheral circuit external to the interface circuit. The BL selection signal generation circuit 400A is configured based on the Figure 3B The internal clock pulse SCLK is used to generate Figure 2B BL selection signal SBL<1:M> is described in Figure 4A In the example configuration of , the BL selection signal generation circuit 400A includes a shift register. Other circuit configurations are within the scope of various embodiments.

[0085] The BL selection signal generating circuit 400A includes a plurality of flip-flops FF0, FF1, FF2 to FFM coupled in series. Figure 4A In the example configuration in FIG. 1 , flip-flops FF0, FF1, FF2 to FFM include D flip-flops. Other flip-flop configurations are within the scope of various embodiments. The data input terminal D of flip-flop FF0 is grounded, and the data input terminal D of each of the flip-flops FF1, FF2 to FFM is coupled to the data output terminal Q of the previous flip-flop. For example, the data input terminal D of flip-flop FF1 is coupled to the data output terminal Q of flip-flop FF0, the data input terminal D of flip-flop FF2 is coupled to the data output terminal Q of flip-flop FF1, and so on. The inverted data output terminals (Q inverted) of flip-flops FF0, FF1, FF2 to FFM are connected to the ground. ) is not used. The clock input terminals of the flip-flops FF0, FF1, FF2 to FFM are connected to the output terminal 355 of the internal clock generation circuit 302 to receive the internal clock signal SCLK. The set input Set of the flip-flop FF0 and the reset input Reset of the flip-flops FF1, FF2 to FFM are coupled to receive the signal RST. In some embodiments, the signal RST is provided through an I / O pin, such as one of the I / O pins 173. In at least one embodiment, the signal RST is generated by a peripheral circuit of the memory circuit. The data output terminal Q of the flip-flops FF1, FF2 to FFM corresponds to the BL selection signal SBL <1> To SBL <m>.

[0086] At the beginning of the access operation, the signal RST is applied to the set input terminal of the flip-flop FF0 and the reset input terminals of the flip-flops FF1, FF2 to FFM, and the data output terminal Q in the flip-flop FF0 has a first logic state, for example, logic "1", and the data output terminal Q in the flip-flops FF1, FF2 to FF has a second logic state, that is, logic "0". In response to each pulse of the internal clock signal SCLK, the logic state at the data output Q of each flip-flop is shifted to the data input terminal Q of the subsequent flip-flop. For example, in response to the first internal clock pulse SCLK, the logic "1" at the data output terminal Q of the flip-flop FF0 is shifted to the data output terminal Q of the flip-flop FF1, resulting in the BL selection signal SBL <1> is logical "1", which in turn corresponds to Figure 2B The data output terminal Q of the flip-flop FF0 becomes logic "0", which corresponds to the data input D of the flip-flop FF0 being grounded. In response to the second internal clock pulse SCLK, the logic "1" at the data output terminal Q of the flip-flop FF1 is shifted to the data output terminal Q of the flip-flop FF2, resulting in the BL selection signal SBL <2> is logic "1", which in turn corresponds to the selection of the bit line BL[2] (not shown) in the memory circuit 200. As a result, in response to the M internal clock pulses SCLK, the BL selection signal generating circuit 400A is configured to sequentially generate M BL selection signals SBL<1:M>, which in turn corresponds to the sequential selection of the M bit lines in the memory circuit 200.

[0087] Figure 4B is a schematic circuit diagram of a pulse width detection circuit 400B according to some embodiments. In some embodiments, the pulse width detection circuit 400B corresponds to the pulse width detection circuit 310 and includes an input terminal and an output terminal corresponding to the input terminal 311, the clock input terminal 312, and the output terminal 315 of the pulse width detection circuit 310. The pulse width detection circuit 400B includes a ripple counter 410, a multiplexer MUX1, a comparison circuit COMP1, and a switch SW1. The multiplexer MUX1, the comparison circuit COMP1, and the switch SW1 constitute a recovery time detection circuit 405. In some embodiments, the recovery time detection circuit 405 is configured to cooperate with the recovery time protection circuit 305 to provide recovery time protection as described herein. For example, when the recovery time protection circuit 305 is not included in the interface circuit, the recovery time detection circuit 405 is omitted in one or more embodiments. Other recovery time detection circuit configurations are within the scope of various embodiments.

[0088] The ripple counter 410 includes an input terminal corresponding to the input terminal 311, a clock input terminal corresponding to the clock input terminal 312, and an output terminal 415. In one or more embodiments where the time detection circuit 405 is omitted, the output terminal 415 corresponds to the output terminal 315. Fig. 4I An example configuration of ripple counter 410 is described. Ripple counter 410 is an example of a counting circuit of pulse width detection circuit 400B. Other counting circuit configurations are within the scope of various embodiments.

[0089] The multiplexer MUX1 includes a plurality of input terminals (unnumbered) configured to receive a plurality of different time values ​​Time_1, Time_2 to Time_n, where n is a natural number. In some embodiments, the time values ​​Time_1, Time_2 to Time_n are arranged in ascending order, that is, Time_1 is less than Time_2, and Time_n is the largest time value. The multiplexer MUX1 also includes a selection input terminal (unnumbered) and an output terminal (unnumbered) configured to receive a selection signal SEL_1. In some embodiments, one or more or all of the time values ​​Time_1, Time_2 to Time_n and the selection signal SEL_1 are set or generated in an interface circuit or a peripheral circuit of the memory circuit. In at least one embodiment, one or more or all of the time values ​​Time_1, Time_2 to Time_n and the selection signal SEL_1 are input to the memory circuit through one or more I / O pins (e.g., one or more I / O pins 173). In the example configuration, the time values ​​Time_1, Time_2 to Time_n are included in an interface circuit or a peripheral circuit, and the selection signal SEL_1 is input to the memory circuit through an I / O pin.

[0090] The comparison circuit COMP1 includes a first input terminal 416 coupled to the output terminal 415 of the ripple counter 410, a second input terminal 417 coupled to the output terminal of the multiplexer MUX1, and an output terminal configured to output the healing time detection signal OVP. In at least one embodiment, the output terminal of the comparison circuit COMP1 is coupled to the corresponding input terminal of the OR gate 309 to provide the healing time detection signal OVP to the healing time protection circuit 305. Figure 4B In the example configuration of , the comparison circuit COMP1 includes an operational amplifier. Other comparison circuit configurations are within the scope of various embodiments.

[0091] The switch SW1 is coupled between the output terminal 415 of the ripple counter 410 and the output terminal 315 of the pulse width detection circuit 400B. The control terminal 419 of the switch SW1 is coupled to the output terminal of the comparison circuit COMP1. Figure 4B In the example configuration of , switch SW1 is a normally closed switch. A normally open switch is within the scope of one or more embodiments. Normally closed switch SW1 generally connects output 415 of ripple counter 410 to output 315 of pulse width detection circuit 400B. An example configuration of switch SW1 includes a transistor, such as a PMOS transistor. Other switch configurations are within the scope of various embodiments.

[0092] In an access operation according to some embodiments, in response to a rising edge 318 of a control signal pulse 316 of a control signal SCLKEN arriving at an input terminal 311, the ripple counter 410 is configured to start counting the number of clock pulses CLK at the clock input terminal 312. In response to a falling edge 319 of the control signal pulse 316, the ripple counter 410 is configured to stop counting and hold or latch the counted number of clock pulses CLK. During the counting operation of the ripple counter 410, the counted number of clock pulses CLK is output as a signal S5 at an output terminal 415 and increases.

[0093] In response to the selection signal SEL_1, the multiplexer MUX1 is configured to output a time threshold T_Thres at its output terminal. The time threshold T_Thres corresponds to one of the time values ​​Time_1, Time_2 to Time_n, or a combination of multiple of the time values ​​Time_1 to Time_n. Therefore, the time threshold T_Thres can be adjusted by selecting the desired selection signal SEL_1. For example, in response to the selection signal SEL_1 having a first value, a shorter time value (e.g., Time_1) is output as the time threshold T_Thres, and in response to the selection signal SEL_1 having a second value different from the first value, a longer time value (e.g., Time_2) is output as the time threshold T_Thres, and so on. The comparison circuit COMP1 is configured to compare the count number increased in the signal S5 output by the ripple counter 410 to the first input terminal 416 with the time threshold T_Thres output by the multiplexer MUX1 to the second input terminal 417.

[0094] When the pulse width of the control signal pulse 316 is shorter than the time threshold T_Thres, the ripple counter 410 is configured to stop counting before the count number in the signal S5 is equal to or greater than the time threshold T_Thres. In this case, the comparison circuit COMP1 is configured to keep the switch SW1 in a closed state, for example, by outputting a logic "0" of the overtime detection signal OVP to the control terminal 419. When the ripple counter 410 stops counting, the final count number in the signal S5 is output as the signal S1 to the output terminal 315 through the closed switch SW1, and then output to the storage circuit 320. The final count number is stored in the storage circuit 320 as the pulse width PW of the detected control signal pulse 316. Figure 3A , Figure 3B As shown, an internal clock pulse series SCLK is generated based on the stored detected pulse width PW.

[0095] When the pulse width of the control signal pulse 316 is not shorter than the time threshold T_Thres, that is, in the case of a recovery time, the number of counts in the signal S5 is equal to or greater than the time threshold T_Thres. In this case, the comparison circuit COMP1 is configured to switch the switch SW1 to an off state, for example, by outputting a logic "1" of the recovery time detection signal OVP to the control terminal 419. The disconnected switch SW1 disconnects the number of counts in the signal S5 at the output terminal 415 and the output terminal 415 of the storage circuit 320. The recovery time detection signal OVP at logic "1" is also provided to the corresponding input terminal of the OR gate 309, as shown in FIG. Figure 3C As shown, the OR gate 309 keeps the signal PRESCLK, the signal PWCLK and the internal clock signal SCLK at logic “0”. The internal clock pulse SCLK is not output, and overtime protection is implemented to prevent malfunction caused by the control signal pulse 316 being too long.

[0096] In at least one embodiment, the described configuration of the time values ​​Time_1, Time_2 to Time_n and the selection signal SEL_1 with multiple time values ​​Time_1, Time_2 to Time_n and the output time threshold T_Thres of the selection signal SEL_1 improves the adjustability or customizability of the pulse width detection circuit 400B and / or the interface circuit or peripheral circuit including the pulse width detection circuit 400B. In some embodiments, when the programming voltage and / or the read voltage is low, the time threshold T_Thres is adjusted to be longer, and when the programming voltage or the read voltage is high, the time threshold T_Thres is adjusted to be shorter. In some embodiments, by providing the selection signal SEL_1 from the external circuit and / or the external device, the time threshold T_Thres can be adjusted to obtain the best time protection. In at least one embodiment, one or more advantages described herein can be achieved by the interface circuit including the pulse width detection circuit 400B.

[0097] Figure 4C is a schematic circuit diagram of a pulse width counting circuit 400C according to some embodiments. In some embodiments, the pulse width counting circuit 400C corresponds to the pulse width counting circuit 330 and includes input terminals and output terminals corresponding to the input terminal 331, the clock input terminal 332, the reset input terminal 334, and the output terminal 335 of the pulse width counting circuit 330. The pulse width counting circuit 400C includes a falling edge detection circuit 430 and a ripple counter 440.

[0098] The falling edge detection circuit 430 includes an input terminal corresponding to the input 331, a clock input corresponding to the clock input 332, and an output terminal 435. Figure 4J An example configuration of the falling edge detection circuit 430 is described.

[0099] The ripple counter 440 includes an input terminal 441 coupled to the output terminal 435 of the falling edge detection circuit 430, a clock input terminal 442 coupled to the clock signal input CLK, a reset input terminal corresponding to the reset input terminal 334, and an output terminal corresponding to the output terminal 335. Fig. 4I An example configuration of ripple counter 440 is described. Ripple counter 440 is an example of a counting circuit of pulse width counting circuit 400C. Other counting circuit configurations are within the scope of various embodiments.

[0100] The falling edge detection circuit 430 is configured to detect the falling edge 319 of the control signal pulse 316 and generate a signal S6 at an output 435, the signal S6 having at least one pulse corresponding to the detected falling edge 319. For example, in response to a high level or logic "1" of the signal S6, the ripple counter 440 is enabled. The enabled ripple counter 440 is configured to count the number of clock pulses CLK at the clock input terminal 442 and output the counted number of clock pulses LK as a signal PWCLK at the output terminal 335. As described herein, when the counted number of clock pulses CLK represented by the signal PWCLK is equal to the detected pulse width PW stored in the storage circuit 320 and represented by the signal RECCLK, the comparison circuit (such as the comparison circuit 340) is configured to output a PRESCLK pulse. Figure 3A The PRESCLK pulse shown (or Figure 3C The signal S9 shown in FIG. 1 is applied to the reset input terminal 334 and resets the count number of the pulse width counting circuit 400C to zero. When the recovery protection is not invoked (e.g., the pulse width PW of the control signal pulse 316 is equal to or lower than the pre-timing threshold) or the recovery protection is not provided (e.g., the recovery protection circuit 305 and / or the recovery detection circuit 405 are omitted), the pulse width counting circuit 400C is then configured to count again to the detected pulse width PW stored in the storage circuit 320 and repeat the process. When the recovery protection is invoked, the pulse width counting circuit 400C remains in the reset state and the signal PWCLK remains at a low level. In at least one embodiment, one or more advantages described herein can be achieved by an interface circuit including the pulse width counting circuit 400C.

[0101] Figure 4D is a schematic circuit diagram of a unit counting circuit 400D according to some embodiments. In some embodiments, the unit counting circuit 400D corresponds to the unit counting circuit 360 and includes an input terminal and an output terminal corresponding to the input terminal 361, the clock input terminal 362, and the output terminal 365 of the unit counting circuit 36. The unit counting circuit 400D includes a ripple counter 460, a multiplexer MUX2, a comparison circuit COMP2, and a switch SW2.

[0102] The ripple counter 460 includes an input terminal corresponding to the input 361, a clock input corresponding to the clock input 362, and an output terminal 465. Fig. 4I An example configuration of ripple counter 460 is described. Ripple counter 460 is an example of a counting circuit of unit counting circuit 400D. Other counting circuit configurations are within the scope of various embodiments.

[0103] The multiplexer MUX2 includes a plurality of input terminals (unnumbered) configured to receive a plurality of different unit count values ​​Count_1, Count_2 to Count_m, where m is a natural number. In some embodiments, the unit count values ​​Count_1, Count_2 to Count_m are arranged in ascending order, that is, Count_1 is less than Count_2, and Count_m is the largest unit count value. The multiplexer MUX2 also includes a selection input terminal (unnumbered) and an output terminal (unnumbered) configured to receive a selection signal SEL_2. In some embodiments, one or more or all of the unit count values ​​Count_1, Count_2 to Count_m and the selection signal SEL_2 are set or generated in the interface circuit or peripheral circuit of the memory circuit. In at least one embodiment, one or more or all of the unit count values ​​Count_1, Count_2 to Count_m and the selection signal SEL_2 are input to the memory circuit through one or more I / O pins (e.g., one or more I / O pins 173). In the example configuration, the cell count values ​​Count_1, Count_2 to Count_m are included in an interface circuit or a peripheral circuit, and the selection signal SEL_2 is input to the memory circuit through an I / O pin.

[0104] The comparison circuit COMP2 includes a first input terminal 466 coupled to the output terminal 465 of the ripple counter 460, a second input terminal 467 coupled to the output terminal of the multiplexer MUX2, and an output terminal (not numbered). Figure 4D In the example configuration of , the comparison circuit COMP2 includes an operational amplifier. Other comparison circuit configurations are within the scope of various embodiments.

[0105] The switch SW2 is coupled between the output terminal 465 of the ripple counter 460 and the output terminal 365 of the unit counting circuit 400D. The control terminal 469 of the switch SW2 is coupled to the output terminal of the comparison circuit COMP2. Figure 4D In the example configuration of , switch SW2 is a normally open switch. A normally closed switch is within the scope of one or more embodiments. Normally open switch SW2 normally disconnects output 465 of ripple counter 460 from output 365 of cell counting circuit 400D. An example configuration of switch SW2 includes a transistor, such as an NMOS transistor. Other switch configurations are within the scope of various embodiments.

[0106] In an access operation according to some embodiments, in response to a rising edge of a first pulse in a signal PRESCLK arriving at an input terminal 361, the ripple counter 460 is configured to start counting clock pulses CLK at a clock input terminal 362. In response to a falling edge of the PRESCLK pulse, the unit counting circuit 400D is configured to stop counting but to hold or latch the counted number of clock pulses CLK.

[0107] In response to the rising edge of the next pulse in the signal PRESCLK arriving at the input terminal 361 , the ripple counter 460 is configured to continue counting or incrementing from the counted number of latched clock pulses CLK.

[0108] In at least one embodiment, the pulse width of each pulse in the signal PRESCLK corresponds to the clock period of the clock signal CLK. For each pulse in the signal PRESCLK, the ripple counter 460 counts one clock pulse CLK and increases the count number of the clock pulse CLK by 1. In other words, the ripple counter 460 is configured to count the number of pulses in the signal PRESCLK, which corresponds to the number of internal clock pulses SCLK output at the output terminal 355. During the counting operation of the ripple counter 460, the count number is output as the signal S7 at the output terminal 465 and increases.

[0109] In response to the selection signal SEL_2, the multiplexer MUX2 is configured to output a threshold C_Thres at its output terminal. The threshold C_Thres corresponds to one of the cell count values ​​Count_1, Count_2 to Count_m, or a combination of multiple cell count values. Therefore, the threshold C_Thres can be adjusted by selecting the desired selection signal SEL_2. For example, in response to the selection signal SEL_2 having a first value, a smaller cell count value (e.g., Count_1) is output as the threshold C_Thres, and in response to the selection signal SEL_2 having a second value different from the first value, a larger cell count value (e.g., Count_2) is output as the threshold C_Thres, and so on. The comparison circuit COMP2 is configured to compare the increased count number in the signal S7 output by the ripple counter 460 to the first input terminal 466 with the threshold C_Thres output by the multiplexer MUX2 to the second input terminal 467. In some embodiments, the threshold C_Thres corresponds to the number of memory cells or the number of bit lines accessible in an access operation.

[0110] When the count in the signal S7 output by the ripple counter 460 is less than the threshold value C_Thres, the comparison circuit COMP2 is configured to keep the switch SW2 in the off state, for example by outputting a logic "0" to the control terminal 469. The output terminal 465 remains disconnected from the output terminal 365, and the signal S2 at the output terminal 365 remains at an inactive level or inactive logic state.

[0111] When the count number in the signal S7 output by the ripple counter 460 increases to the threshold value C_Thres, the comparison circuit COMP2 is configured to switch the switch SW2 to a closed state, for example by outputting a logic "1" to the control terminal 469. The closed switch SW2 connects the output terminal 465 to the output terminal 365, so that the signal S2 has an active level or an active logic state, which is applied to the enable input terminal 354 of the output circuit 350 to stop the output circuit 350 from outputting further internal clock pulses SCLK. As a result, the number of internal clock pulses SCLK generated by the interface circuit is controlled by the threshold value C_Thres and / or the selection signal SEL_2 to correspond to the number of memory cells or the number of bit lines that can be accessed in an access operation.

[0112] In at least one embodiment, the described configuration of multiple cell count values ​​Count_1, Count_2 to Count_m and a selection signal SEL_2 outputting a threshold C_Thres of multiple cell count values ​​Count_1, Count_2 to Count_m and a selection signal SEL_2 improves the adjustability or customizability of the cell counting circuit 400D and / or an interface circuit or peripheral circuit including the cell counting circuit 400D. In some embodiments, the threshold C_Thres is adjusted by an appropriate selection signal SEL_2 to correspond to the density of memory cells in the memory circuit to be accessed. As a result, in one or more embodiments, generation of unnecessary internal clock pulses SCLK, for example, more internal clock signals SCLK than the number of access bit lines, can be avoided, thereby reducing power consumption and / or increasing programming or reading speed. In one or more embodiments, PPA optimization can be achieved in combination with the reduced number of I / O pins and the improvement of area. In at least one embodiment, one or more advantages described herein can be achieved by an interface circuit including the cell counting circuit 400D.

[0113] Figure 4E 4 is a schematic circuit diagram of a rising edge detection circuit 400E according to some embodiments. In some embodiments, the rising edge detection circuit 400E corresponds to the rising edge detection circuit 370 .

[0114] The rising edge detection circuit 400E includes D flip-flops DFF1, DFF2 and an AND gate AND1. Each of the flip-flops DFF1, DFF2 includes a data input terminal ( Figure 4E Marked as "D"), clock input terminal ( Figure 4E The middle mark is "clk"), reset input terminal ( Figure 4E The middle mark is "rst"), output terminal ( Figure 4E The inverting output terminal ( Figure 4E The flip-flop DFF1 has a data input terminal coupled to receive the control signal SCLKEN, a clock input terminal coupled to receive the clock signal CLK, a reset input terminal coupled to receive the reset signal reset1, and an output terminal coupled to the data input terminal of the flip-flop DFF2 and the first input terminal of the gate AND1. The flip-flop DFF2 has a clock input terminal coupled to receive the clock signal CLK, a reset input terminal coupled to receive the reset signal reset1, and an inverting output terminal coupled to the second input terminal of the gate AND1. The described configuration is an example. Other rising edge detection circuit configurations are within the scope of various embodiments.

[0115] The rising edge detection circuit 400E is configured to detect the rising edge of the control signal SCLKEN arriving at the data input terminal of the flip-flop DFF1, and output the signal S3 at the output terminal of the gate AND1. As a result, in response to the rising edge of the control signal SCLKEN, the access signal WLR corresponding to the signal S3 is raised to logic "1". The access signal WLR remains at logic "1" until the reset signal reset1 arrives at the reset input terminals of the flip-flops DFF1 and DFF2. The reset signal reset1 resets the rising edge detection circuit 400E and the signal S3, and as a result, the access signal WLR is reset to logic "0". In at least one embodiment, one or more advantages described herein can be achieved by an interface circuit including the rising edge detection circuit 400E.

[0116] Figure 4F 4 is a schematic circuit diagram of a falling edge detection circuit 400F according to some embodiments. In some embodiments, the falling edge detection circuit 400F corresponds to the falling edge detection circuit 390 .

[0117] The falling edge detection circuit 400F includes D flip-flops DFF3, DFF4, DFF5, an inverter INV2, and an AND gate AND2. Each of the flip-flops DFF3-DFF5 includes a data input terminal, a clock input terminal, a reset input terminal, an output terminal, and an inverting output terminal, as described with respect to the flip-flops DFF1 and DFF2. The flip-flop DFF3 has a data input terminal coupled to receive a control signal SCLKEN, a clock input terminal coupled to receive a clock signal CLK, a reset input terminal coupled to receive a reset signal reset2, and an output terminal coupled to the data input terminal of the flip-flop DFF4 and the input terminal of the inverter INV2. The output terminal of the inverter INV2 is coupled to the first input terminal of the gate AND2. The flip-flop DFF4 has a clock input terminal coupled to receive a clock signal CLK, a reset input terminal coupled to receive a reset signal reset2, and an inverting output terminal coupled to the second input terminal of the gate AND2. The flip-flop DFF5 has a data input terminal coupled to receive a reference voltage (e.g., a power supply voltage VDDIO), a clock input terminal coupled to the output terminal of the gate AND2, and a reset input terminal coupled to receive a reset signal reset2. The described configuration is an example. Other falling edge detection circuit configurations are within the scope of various embodiments.

[0118] The falling edge detection circuit 400F is configured to detect the falling edge of the control signal SCLKEN arriving at the data input terminal of the flip-flop DFF3, and output the signal S4 at the output terminal of the flip-flop DFF5. As a result, in response to the falling edge of the control signal SCLKEN, the access signal WLP corresponding to the signal S4 is raised to logic "1". The access signal WLP remains at logic "1" until the reset signal reset2 arrives at the reset input terminal of the flip-flops DFF3-DFF5. The reset signal reset2 resets the falling edge detection circuit 400F and the signal S4, and as a result, the access signal WLP is reset to logic "0". In at least one embodiment, one or more advantages described herein can be achieved by an interface circuit including the falling edge detection circuit 400F.

[0119] Figure 4G is a schematic circuit diagram of a circuit 400G configured to generate a reset signal reset1 according to some embodiments.

[0120] Circuit 400G includes latch circuits 470 and 480 coupled in series. Latch circuit 470 includes an input terminal 471 coupled to receive an internal clock signal SCLK, a clock input terminal 472 coupled to receive a signal PRESCLK, and an output terminal 475. Latch circuit 480 includes an input terminal 481 coupled to an output terminal 475 of latch circuit 470, a clock input terminal 482 coupled to receive a signal PRESCLK, and an output terminal 485, and circuit 400G is configured to generate a reset signal reset1 at the output terminal 485. In at least one embodiment, latch circuits 470 and 480 are replaced by flip-flops. The described circuit for generating a reset signal reset1 is an example. Other configurations are within the scope of various embodiments.

[0121] Figure 4H is a schematic circuit diagram of a circuit 400H configured to generate a reset signal reset2 according to some embodiments.

[0122] Circuit 400H includes a latch circuit 490. Latch circuit 490 includes an input terminal 491 coupled to receive an internal clock signal SCLK, a clock input terminal 492 coupled to receive a signal PRESCLK, and an output terminal 495 of circuit 400H configured to generate a reset signal reset2. In at least one embodiment, latch circuit 490 is replaced by a flip-flop. The circuit described for generating reset signal reset2 is an example. Other configurations are within the scope of various embodiments.

[0123] In the example operation of the circuit 400H, when both the internal clock pulse SCLK and the PRESCLK pulse are input to the latch circuit 490, the reset signal reset2 has a first level or a first logic state. When the output of the internal clock pulse SCLK stops, for example, as the signal S2 described herein, the PRESCLK pulse is applied to the clock input terminal 492, but no internal clock pulse SCLK is applied to the input terminal 491. After the output of the internal clock pulse SCLK stops, on the second PRESCLK pulse, the reset signal reset2 is switched to a second level or logic state different from the first level or logic state. The switching level or logic state of the reset signal reset2 causes the falling edge detection circuit 390 or the falling edge detection circuit 400F to reset, thereby causing a falling edge of the access signal WLP, as described herein.

[0124] In the example operation, the circuit 400G is configured to operate similarly to the circuit 400H. However, the presence of the additional latch circuit 480 causes the reset signal reset1 to switch to a different level or logic state on the third PRESCLK pulse after the output of the internal clock pulse SCLK stops. The switching level or logic state of the reset signal reset1 causes the rising edge detection circuit 370 or the rising edge detection circuit 400E to reset, thereby causing the falling edge of the access signal WLR to follow the falling edge of the access signal WLP, as described herein. In at least one embodiment, one or more advantages described herein can be achieved by an interface circuit including the circuit 400G and / or the circuit 400H.

[0125] Fig. 4I 4 is a schematic circuit diagram of a ripple counter 400I according to some embodiments. In some embodiments, the ripple counter 400I corresponds to at least one of the ripple counter 410 , the ripple counter 440 , or the ripple counter 460 .

[0126] The ripple counter 400I includes a plurality of JK flip-flops JK0, JK1, and JK2 coupled in series. Other flip-flop configurations and / or numbers of flip-flops are within the scope of various embodiments. For k flip-flops in the ripple counter 400I, the ripple counter 400I is configured to count from zero to 2. k -1. The J and K inputs of all flip-flops JK0, JK1, and JK2 are coupled to receive the JK input signal. The clock input of the flip-flop JK0 is coupled to receive the clock signal CLK. The clock input of each flip-flop JK1, JK2 is connected to the inverted data output (Q inverted) of the previous flip-flop. For example, the clock input of the flip-flop JK1 is connected to the inverted data output (Q inverted) of the flip-flop JK0, the clock input of the flip-flop JK2 is connected to the inverted data input (Q inverted) of the flip-flop JK1, and so on. The data output Q of the flip-flops JK0, JK1, and JK2 corresponds to the bits Q0, Q1, and Q2 of the number counted by the ripple counter 400I. Each flip-flop JK0, JK1, and JK2 also includes a reset input.

[0127] In the example operation of each flip-flop JK0, JK1, and JK2, when the JK input signal is at a high level, the level or logic state of the data output terminal Q and the inverted data output terminal (Q inverted) is switched according to the signal at the clock input. When the JK input signal is at a low level, the level or logic state of the data output terminal Q and the inverted data output terminal (Q inverted) remains unchanged.

[0128] When the ripple counter 400I is configured as the ripple counter 410, the JK input signal is the control signal SCLKEN, the reset input terminal is not used, and the bits Q0, Q1, Q2 correspond to the bits of the count number in the signal S5. When the ripple counter 400I is configured as the ripple counter 440, the JK input signal is the signal S6, the reset input terminal is coupled to receive the signal PRESCLK, and the bits Q0, Q1, Q2 correspond to the bits of the count number in the signal PWCLK. When the ripple counter 400I is configured as the ripple counter 460, the JK input signal is the signal PRESCLK, the reset input terminal is not used, and the bits Q0, Q1, Q2 correspond to the bits of the count number in the signal S7. In at least one embodiment, one or more advantages described herein can be achieved by an interface circuit including the ripple counter 400I.

[0129] Figure 4J 4 is a schematic circuit diagram of a falling edge detection circuit 400J according to some embodiments. In some embodiments, the falling edge detection circuit 400J corresponds to the falling edge detection circuit 430 .

[0130] Falling edge detection circuit 400J includes a D flip-flop DFF6, an inverter INV6, and an AND gate AND6. In some embodiments, the configuration of flip-flop DFF6 is similar to flip-flops DFF1-DFF5. Flip-flop DFF6 includes an input terminal coupled to receive a control signal SCLKEN, a clock input terminal coupled to receive a clock signal CLK, and an output terminal.

[0131] Inverter INV6 includes an input terminal coupled to the input terminal of the flip-flop DFF6 and receiving an input terminal of the control signal SCLKEN, and an output terminal. Gate AND6 includes a first input terminal coupled to the output terminal of the inverter INV6, a second input terminal coupled to the output terminal of the flip-flop DFF6, and an output terminal configured as an output signal S6 of a falling edge detection circuit 400J. In some embodiments, signal S6 includes a pulse having a rising edge corresponding to the falling edge 319 of the control signal pulse 316, and a duration corresponding to a time period during which the output terminals of the inverter INV6 and the flip-flop DFF6 have a high level (e.g., logic "1"). Other falling edge detection circuit configurations are also within the scope of various embodiments. In at least one embodiment, one or more advantages described herein can be achieved by an interface circuit including a falling edge detection circuit 400J.

[0132] Figure 4K 4 is a schematic circuit diagram of a rising edge detection circuit 400K according to some embodiments. In some embodiments, the rising edge detection circuit 400K corresponds to the rising edge detection circuit 307 .

[0133] The rising edge detection circuit 400K includes a D flip-flop DFF8, an inverter INV8, and an AND gate AND8. In some embodiments, the configuration of the flip-flop DFF8 is similar to the flip-flops DFF1-DFF5. The flip-flop DFF8 includes an input terminal coupled to receive a control signal SCLKEN, a clock input coupled to receive a clock signal CLK, and an output terminal.

[0134] Inverter INV8 includes an input and an output coupled to the output of flip-flop DFF8. Gate AND8 includes a first input coupled to receive a control signal SCLKEN, a second input coupled to the output of inverter INV8, and an output of rising edge detection circuit 400K configured to output signal S8. In some embodiments, signal S8 includes a pulse having a rising edge corresponding to the rising edge of signal PRESCLK, and a duration corresponding to a time period in which both the output of inverter INV8 and signal PRESCLK have a high level (e.g., logic "1"). Other rising edge detection circuit configurations are also within the scope of various embodiments. In at least one embodiment, one or more advantages described herein can be achieved by an interface circuit including a rising edge detection circuit 400K.

[0135] The described rising edge detection circuit and falling edge detection circuit are examples of edge detection circuits. In at least one embodiment, one or more of the rising edges can be modified to falling edges, vice versa, and / or one or more of the rising edge detection circuits can be modified to falling edge detection circuits, vice versa.

[0136] Figure 5A-Figure 5B is a schematic timing diagram of various operations of the interface circuit and / or peripheral circuit of the memory circuit according to some embodiments. Figure 5A-Figure 5B One or more operations described are performed in the memory circuit 100, the peripheral circuit 160, the interface circuit 170, the memory circuit 200, the interface circuit 300, the interface circuit 301, and the related Figure 4A-Figure 4K The various circuits described in one or more of the embodiments may be located at or performed by the various circuits described in the embodiment. Figure 5A-Figure 5B Corresponding signals and / or features in are represented by the same reference numerals. Figure 5A An example case where the healing protection is not invoked is shown. Figure 5B An example case where the healing protection is invoked is shown.

[0137] Figure 5A A schematic timing diagram of various signals in an access operation of one or more memory cells in a row of a memory array in a memory circuit according to some embodiments is included. Figure 5A In the example configuration in FIG. 1 , the clock signal CLK, the power supply voltage VDDIO and the control signal SCLKEN are input to the interface circuit of the memory circuit through the corresponding I / O pins, as shown in FIG. Figure 1 The remaining signals, namely, the signal RECCLK, the signal PWCLK, the signal PRESCLK, the internal clock signal SCLK, the access signal WLR, the access signal SLP, the BL selection signal SBL <1> To SBL <m>, generated by an interface circuit or a peripheral circuit of the memory circuit based on a clock signal CLK and a control signal SCLKEN for performing an access operation.

[0138] The clock signal CLK includes a plurality of clock pulses CLK, with a clock period T between consecutive clock pulses CLK. CLK .exist Figure 5A Some clock pulses CLK are specified, such as clock pulses 521-525.

[0139] The power supply voltage VDDIO provides the execution of Figure 5A Describes the power required for one or more operations.

[0140] The control signal SCLKEN includes a control signal pulse 516 having a rising edge 518, a falling edge 519, and a pulse width PW between the rising edge 518 and the falling edge 519. In at least one embodiment, the control signal pulse 516, the rising edge 518, and the falling edge 519 correspond to the control signal pulse 316, the rising edge 318, and the falling edge 319. Figure 5A In the example configuration in FIG. 1 , the control signal SCLKEN is an analog signal, which means that the rising edge 518 and / or the falling edge 519 are not necessarily synchronized or aligned with the rising edge and / or the falling edge of the clock pulse CLK. Other arrangements in which at least one of the rising edge 518 or the falling edge 519 is synchronized or aligned with the rising edge or the falling edge of the clock pulse CLK are within the scope of various embodiments.

[0141] The signal RECCLK indicates the operation at the pulse width detection circuit 310 and / or the pulse width detection circuit 400B. For example, in response to the rising edge 518 of the control signal pulse 516, the ripple counter 410 is enabled and starts counting the clock pulse CLK. The clock pulse 521 having a rising edge at the time t1 immediately after the rising edge 518 is the first clock pulse counted. The ripple counter 410 continues to count the clock pulse CLK until the counting operation of the ripple counter 410 is disabled by the falling edge 519. The clock pulses 521, 522, 523 whose rising edges fall within the pulse width PW of the control signal pulse 516 are counted. The clock pulse 524 having a rising edge at the time t2 immediately after the falling edge 519 and the subsequent clock pulses CLK are not counted. The count of the ripple counter 410 is stored by the storage circuit 320 and output as the signal RECCLK. When the clock pulses 521, 522, 523 are counted, the counted numbers are reflected in the signal RECCLK as "1", "2", "3" respectively. Figure 5A When the counting operation of the ripple counter 410 is disabled by the falling edge 519, the last counted number (ie, "3") is retained by the storage circuit 320 until the access operation is completed.

[0142] The number "3" stored in the storage circuit 320 indicates that the pulse width PW of the control signal pulse 516 corresponds to 3 clock periods T. CLK (ie 3T CLK ). In some embodiments, the stored number "3" does not mean that the pulse width PW is equal to 3 clock cycles T CLK ; On the contrary, this means 3 clock cycles T CLK is an estimate of the pulse width PW. Figure 5A In the 3-clock period T CLK The corresponding pulse width PW is an example. Other values ​​of pulse width PW are within the scope of various embodiments.

[0143] Signal PWCLK represents the operation of pulse width counting circuit 330 and / or pulse width counting circuit 400C. For example, falling edge 519 is detected by falling edge detection circuit 430. Falling edge detection circuit 430 outputs signal S6 when falling edge 519 is detected. Signal S6 enables ripple counter 440 to start counting clock pulses CLK. Clock pulse 525 having a rising edge at time t3 is the first clock pulse counted by ripple counter 440. Time t3 is approximately 2T after falling edge 519. CLK About 2T CLK This example time delay of is caused at least in part by the operation of falling edge detection circuit 430. Figure 5A As shown, the ripple counter 440 continues to count "1", "2", and "3".

[0144] Signal PRESCLK indicates the operation at the comparison circuit 340. For example, the comparison circuit 340 compares the count of the ripple counter 440 with the count stored in the storage circuit 320. When the count of the ripple counter 440 reaches the stored number, i.e., "3", the comparison circuit 340 raises the signal PRESCLK to a high level at time t(1) to start the PRESCLK pulse 541. The high level of the PRESCLK pulse 541 resets the ripple counter 440, as shown by the signal PWCLK, and the ripple counter 440 restarts counting from "1" at time t(1). The restarted count "1" is less than the count "3" stored in the storage circuit 320, so the comparison circuit 340 lowers the signal PRESCLK to a low level, thereby ending the PRESCLK pulse 541. The pulse width of the PRESCLK pulse 541 is equal to T CLK .

[0145] Repeat the above process. For example, the ripple counter 440 counts "1", "2", "3", then resets, and counts "1", "2", "3" again. CLK (e.g., at times t(1), t(2), ... t(M), t(M+1), t4, t5, t6) PRESCLK pulses, such as PRESCLK pulses 541, 542, 543, 544, 545, 546, are generated. Each PRESCLK pulse has a T CLK The pulse width of the PRESCLK pulse is equal to 3T CLK Time period T BL generate.

[0146] The internal clock signal SCLK indicates the operation of the output circuit 350, the unit counting circuit 360 and / or the unit counting circuit 400D. For example, when the comparison circuit 340 starts to output the PRESCLK pulse, the output circuit 350 generates a corresponding internal clock pulse SCLK for each PRESCLK pulse. Each internal clock pulse SCLK has the same pulse width T as the corresponding PRESCLK pulse. CLK , and the internal clock pulse SCL K is in the same period T of the PRESCLK pulse BL The internal clock pulse SCLK period T BL It is called the internal clock period T BL .exist Figure 5A , the internal clock pulses SCLK are represented as 551, 552, 553, ... 55M at corresponding times t(1), t(2), t(3) ... t(M).

[0147] The ripple counter 460 counts the number of generated internal clock pulses SCLK, and the comparison circuit COMP2 compares the count number of the ripple counter 460 with the threshold value C_Thres output by the multiplexer MUX2. In one example, the threshold value C_Thres is equal to M, where M is the number of bit lines to be accessed. When M internal clock pulses SCLK have been generated, the count number of the ripple counter 460 is equal to the threshold value C_Thres, and the comparison circuit COMP2 closes the switch SW2 to send a signal S2 to stop the output circuit 350 from outputting further internal clock pulses SCLK. Figure 5A As shown, the last internal clock pulse SCLK is pulse 55M, and no other internal clock pulses SCLK are generated regardless of whether there are other PRESCLK pulses (such as pulses 544, 545, 546).

[0148] BL selection signal SBL <1> 、SBL <2> 、SBL <m>Indicates the operation at the BL selection signal generating circuit 400A. For example, for each internal clock pulse SCLK, the BL selection signal generating circuit 400A generates a corresponding BL selection signal. Figure 5A In the example of FIG. 1 , the rising edge of the internal clock pulse 551 causes the BL selection signal SBL to be <1> The rising edge of the corresponding pulse 581 in the internal clock signal 552 causes the falling edge of the pulse 581. The rising edge of the internal clock pulse 552 also causes the BL selection signal SBL to <2> The rising edge of the corresponding pulse 582 in the internal clock pulse 553 causes the falling edge of the pulse 582. The process is repeated, and the corresponding BL selection signal SBL <1> 、SBL <2> , ... SBL<M> pulses 581, 582, ... 58M correspond to internal clock pulses 551, 552, ... 55M. In some embodiments, the BL selection signal SBL <1> 、SBL <2> , . . . SBL<M> is applied to the BL selection circuit 240 for sequentially selecting or accessing the M bit lines BL[1] to BL[M] in an access operation.

[0149] Due to the shift operation in the BL selection signal generating circuit 400A, there is a T between the rising edge of each internal clock pulse SCLK (eg, pulse 552) and the rising edge of the corresponding pulse in the corresponding BL selection signal (eg, pulse 582). CLK In at least one embodiment, T CLK This time delay prevents continuous BL selection signals (such as SBL <1> 、SBL <2> ) in a continuous pulse (e.g., 581, 582) overlap with each other to prevent potential malfunctions due to such pulse overlap.

[0150] The access signal WLR indicates the operation at the access signal generation circuit 304, the rising edge detection circuit 400E and / or the circuit 400G. For example, in response to the rising edge 518 of the control signal pulse 516, the rising edge detection circuit 370 raises the access signal WLR to a high level, resulting in a rising edge 568 of the access signal WLL. In some embodiments, there is a time delay between the rising edge 518 of the control signal pulse 516 and the rising edge 568 of the access signal WLR, and is at least partially caused by the delay circuit 380. The high level of the access signal WLR is maintained until the reset signal reset1 is applied to the rising edge detection circuit 370, resulting in a falling edge 569 of the access signal WLL. When the output of the internal clock pulse SCLK stops, the circuit 400G generates the reset signal reset1. In the example operation, when both the PRESCLK pulse and the internal clock pulse SCLK are output (for example, in Figure 5A t(1), t(2) to t(M) in FIG. 1 ), the reset signal reset1 output by the circuit 400G is at a high level, i.e., logic "1", corresponding to the access signal WLR at a high level. When the output of the internal clock pulse SCLK stops and the PRESCLK pulse is still output (for example, at Figure 5A At t(M+1), t4, t5, t6 in FIG. 1 , the circuit 400G switches the reset signal reset1 to a low level, i.e., logic "0", which resets the rising edge detection circuit 370 and the signal S3, and switches the access signal WLR to logic "0). Figure 5A In the example of FIG. 4 , the reset signal reset1 of logic “0” triggers a falling edge 569 of the access signal WLR at time t5, and the falling edge 569 corresponds to the rising edge of the PRESCLK pulse 545.

[0151] The access signal WLP indicates the operation at the access signal generation circuit 306, the falling edge detection circuit 400F and / or the circuit 400H. For example, in response to the falling edge 519 of the control signal pulse 516, the falling edge detection circuit 390 raises the access signal WLP to a high level, resulting in a rising edge 578 of the access signal WLP. In some embodiments, the time delay between the falling edge 519 of the control signal pulse 516 and the rising edge 578 of the access signal WLP is at least partially caused by the delay circuit 386. The high level of the access signal WLP is maintained until the reset signal reset2 is applied to the falling edge detection circuit 390, resulting in a falling edge 579 of the access signal WLP. When the output of the internal clock pulse SCLK stops, the circuit 400H generates the reset signal reset2 in a manner similar to that described herein with respect to the reset signal reset1 and the circuit 400G. Figure 5A In the example of FIG. 5 , the reset signal reset2 triggers a falling edge 579 of the access signal WLP at time t4, and the falling edge 579 corresponds to the rising edge of the PRESCLK pulse 544. The falling edge 579 of the access signal WLP is at the last BL selection signal SBL. <m>The falling edge 569 of the access signal WLR is generated one TBL after the last pulse (i.e., pulse 58M) of the access signal WLP. BL The duration of the access signal WLP between the corresponding rising edge 578 and the falling edge 579 is completely within the duration of the access signal WLR between the corresponding rising edge 568 and the falling edge 569. All internal clock pulses SCLK and corresponding pulses 581, 582, ... 58M are generated within the duration of the access signal WLP and the access signal WLR.

[0152] exist Figure 5A In the example of FIG. 5 , the pulse width of the control signal pulse 516 is shorter than the time threshold T_Thres output by the multiplexer MUX1 , and the recovery protection is not invoked.

[0153] exist Figure 5B In the example of FIG. 5 , the control signal pulse 596 of the control signal SCLKEN is longer than the time threshold T_Thres output by the multiplexer MUX1, and the recovery time protection is called. In at least one embodiment, the recovery time protection circuit 305 and the recovery time detection circuit 405 are configured to provide the recovery time protection, as shown in FIG. Figure 3C , Figure 4B described.

[0154] exist Figure 5B In the example configuration of FIG. 5 , the control signal SCLKEN includes a control signal pulse 596 having a pulse width PW greater than a predetermined timing threshold T_Thres. Figure 4B When the ripple counter 410 is triggered by the rising edge (not numbered) of the control signal pulse 596, the ripple counter 410 counts upward from "1", "2", "3" ..., the count number of the ripple counter 410 is still lower than the time threshold T_Thres, and the switch SW1 remains closed to allow the signal S1 to be output to the storage circuit 320, and the storage circuit 320 stores and outputs the signal S1 as shown in FIG. Figure 5B The count numbers of the signal RECCLK shown are "1", "2", "3", "4", "5", "6", "7", "8", "9", "10", and "11". When the count number of the ripple counter 410 reaches or exceeds the recovery time threshold T_Thres (for example, "11" in this example), the comparison circuit COMP1 outputs a recovery time detection signal OVP of logic "1", which switches the switch SW1 to the off state and stops outputting further counts to the storage circuit 320. In addition, as described with respect to Figure 3C As described above, the logic "1" reset detection signal OVP is provided to the OR gate 309, and the pulse width counting circuit 330 is kept in the reset state. As a result, the signal PWCLK is kept at logic "0", the PRESCLK pulse is not output, the internal clock pulse SCLK is not output, the access signals WLR and WLP are kept at logic "0", and the BL selection signal SBL is kept at logic "0". <1> 、SBL <2> ,......SBL<M> is not generated, such as Figure 5B In at least one embodiment, by performing Figure 5A-Figure 5B An interface circuit that implements one or more of the operations described in one or more of the embodiments can achieve one or more of the advantages described herein.

[0155] Fig. 6A 6 is a schematic circuit diagram of a memory circuit 600A according to some embodiments. In some embodiments, the memory circuit 600A corresponds to at least one of the memory circuit 100 or the memory circuit 200 . Figure 1 , Figure 2B , Fig. 6A Corresponding elements in are denoted by the same reference numerals.

[0156] exist Fig. 6A , a memory cell MC having a corresponding read word line WLR[k], a programming word line WLP[k], and a bit line BL[i] in segment 1 of the memory circuit 600A is shown, where k is a natural number between 1 and k, and i is a natural number between 1 and M. For simplicity, other memory cells, word lines, and bit lines are omitted. The memory circuit 600A includes a BL selection circuit 640 and a read / programming circuit 650. In some embodiments, the BL selection circuit 640 corresponds to the BL selection circuit 240, and / or 650 corresponds to the read / programming circuit 250.

[0157] The BL selection circuit 640 includes a NOR gate 641, an AND gate 642, a PMOS transistor P61, and an NMOS transistor N61. The NOR gate 641 includes first and second input terminals coupled to receive the signal ENb and the signal SCLKb, respectively, and an output terminal coupled to the first input terminal of the AND gate 642. The AND gate 642 includes a second input terminal and an output terminal, and the second input terminal is coupled to receive the BL selection signal SBL corresponding to the bit line BL[i]. The output terminal is coupled to the gates of transistors P61 and N61. Transistor P61 includes a first source / drain coupled to the read word line WLR[k] and a second source / drain coupled to the bit line BL[i]. Transistor N61 includes a first and a second source / drain coupled to the bit line BL[i] and the global bit line GBL, respectively.

[0158] The read / program circuit 650 includes PMOS transistors P62-P63, NMOS transistors N62-N64, and an inverter 652. Transistors P62 and N62 are coupled in series between a node or I / O pin 655 having a power supply voltage VDDIO and a node or input / output pin 657 having a ground voltage VSS. Transistors P63 and N63 are coupled in series between a node 655 of VDDIO and a node 657 of VSS. The gates of transistors P62 and P63 are connected together and connected to a common source / drain of transistors P62 and N62. The common source / drain of transistors P63 and N63 is coupled to an input terminal of the inverter 652. The gate of transistor N63 is coupled to a global bit line GBL. The gates of transistors N62 and N64 are coupled together and coupled to a gate of an NMOS transistor N65 outside of segment 1 of the memory circuit 600A. Transistor N64 is coupled between global bit line GBL and node 657 of VSS. Transistor N65 is coupled to a resistor between node or I / O pin 659 and node 657 of VSS. Node 659 is configured to receive reference current Iref. Inverter 652 includes an output terminal for outputting read data Q<1>, as shown in FIG. Figure 2B In Fig. 6A In the example configuration in FIG. 1 , the read / program circuit 650 includes a sense amplifier configured to output read data Q by detecting a read current on a global bit line GBL and comparing the read current with a reference current Iref. <1> .

[0159] Signal ENb is an inverted version of enable signal EN. In at least one embodiment, enable signal EN is a chip enable (CEB) signal, a write enable (WEB) signal, etc. Signal SCLKb is an inverted version of internal clock signal SCLK. When all enable signals EN, internal clock signal SCLK and BL selection signal SBL When the AND gate 642 is at a high level or has a logic "1", the output terminal of the AND gate 642 is at a high level or has a logic "1". As a result, the transistor P61 is turned off and the transistor N61 is turned on to couple the bit line BL[i] to the global bit line GBL. The bit line BL[i] is selected or accessed for access operation. When the enable signal EN, the internal clock signal SCLK and the BL selection signal SBL When any one of is at a low level or has a logic "0", the output terminal of AND gate 642 is at a low level or has a logic "0". As a result, transistor P61 is turned on and transistor N61 is turned off. Bit line BL[i] is disconnected from global bit line GBL and will not be selected or accessed for access operation.

[0160] Figure 6B is a schematic circuit diagram of an interface circuit 600B according to some embodiments. In some embodiments, the interface circuit 600B corresponds to at least one of the interface circuit 170 or the interface circuit 300. In at least one embodiment, except Figure 6B In addition to the circuits discussed in Figure 3A , Figure 4A-4J One or more circuits described in.

[0161] The interface circuit 600B includes an XOR (exclusive OR) gate 671, an N-input AND gate 672, an AND gate 673, and D flip-flops 674, 675, 676. The XOR gate 671 includes first and second input and output terminals coupled to receive the read data Q<1:N> and the signal CHK, respectively. The AND gate 672 includes input and output terminals coupled to the output terminal of the XOR gate 671. The AND gate 673 includes a first input terminal, a second input and output terminal coupled to receive the internal clock signal SCLK. The flip-flop 674 includes a data input terminal D connected to ground, a clock input terminal coupled to receive the signal SCLKb, a set input terminal coupled to receive the signal RST, and an inverting output terminal (Q inverted) coupled to the first input terminal of the AND gate 673. The flip-flop 675 includes a data input terminal D coupled to the output terminal of the AND gate 672, a clock input terminal coupled to the output terminal of the AND gate 673, a set input terminal coupled to receive the signal RST, an output terminal Q coupled to the node or I / O pin 685, and an inverting output terminal (Qinvert). The flip-flop 676 includes a data input terminal D connected to ground, a clock input terminal coupled to the inverting output terminal of the flip-flop 675, a set input terminal coupled to receive the signal RST, and an output terminal Q coupled to the node or I / O pin 686.

[0162] In a read operation according to some embodiments, the signal CHK includes detection data to verify whether the data previously programmed into the memory circuit is correctly programmed. In at least one embodiment, the detection data is input into the memory circuit through one or more I / O pins. In some embodiments, the detection data is stored in the memory circuit or generated by the memory circuit.

[0163] At the beginning of the read operation, the signal RST is applied to the set input terminals of the flip-flops 674, 675, and 676, and the output terminals Q of the flip-flops 674, 676, and 676 have a first logic state, such as logic "1". The read operation is performed based on the internal clock signal SCLK, the access signal WLR, and the access signal WLP. Figure 5A The AND gate 673 and the flip-flop 674 are configured to provide a clock signal similar to the internal clock signal SCLK to the clock input terminal of the flip-flop 675 .

[0164] When the read data Q<1:N> is output in the read operation, the XOR gate 671 compares the detection data in the signal CHK with the output read data Q<1:N>. Fig. 6A In response to the first internal clock pulse SCLK, the read data Q is read from the segment 1 along the corresponding accessed bit line BL[1] (i.e., i=1). <1> Similarly, the data Q is read from segment 2. <2> bits, ... The XOR gate 671 compares the N-bit read data Q<1:N> (e.g., N-bit word) obtained in response to the first internal clock pulse SCLK with the corresponding bits in the detection data of the signal CHK, and inputs the N comparison results (i.e., N bits) into and is combined by the AND gate 672.

[0165] When the N-bit word of the read data Q<1:N> is identical to the corresponding word in the detection data, AND gate 672 outputs a logic "1" to the data input terminal D of the flip-flop 675. The output terminal Q of the flip-flop 675 remains at a logic "1", which is output at a node 685 in the form of a signal Q_ALL to indicate to an external circuit or device that there is no error in the current N-bit word. The inverting output terminal (Q invert) of the flip-flop 675 remains at a logic "0", which is applied to the clock input terminal of the flip-flop 676. In response to the logic "0" at the clock input, the flip-flop 676 maintains the output terminal Q at a logic "1". The logic "1" at the output terminal Q of the flip-flop 676 is output at a node 686 in the form of a signal PGM_OK to indicate to an external circuit or device that no error has been found so far.

[0166] When at least one bit in the N-bit word of the read data Q<1:N> is different from the corresponding bit in the detection data, the AND gate 672 outputs a logic "0" to the data input terminal D of the flip-flop 675. The output terminal Q of the flip-flop 675 is switched to a logic "0", which is output in the signal Q_ALL at the node 685 to indicate to the external circuit or device that the current N-bit word has an error. The inverting output terminal (Q inverted) of the flip-flop 675 is switched to a logic "1", which is applied to the clock input terminal of the flip-flop 676. In response to the logic "1" at the clock input terminal, the flip-flop 676 switches the output Q to a logic "0", corresponding to the data input terminal D being grounded. The logic "0" at the output terminal Q of the flip-flop 676 is output in the signal PGM_OK at the node 686 to indicate to the external circuit or device that an error exists. Regardless of the verification result of the subsequent internal clock pulse SCLK, the logic "0" of the signal PGM_OK will not change.

[0167] In response to the subsequent internal clock pulse SCLK, the process is repeated. Specifically, another N-bit word is read from each of the segments 1 to N and compared with the corresponding N-bit word in the detection data. The comparison result will be output at the node 685, that is, the logic "1" of the node 685 indicates that there is no error in the current N-bit word, and the logic "0" indicates that the current N-bit word has an error.

[0168] At the end of the read operation, the signal PGM_OK at node 686 indicates whether any errors were found, and the information Q_ALL at node 685 indicates the specific location or specific N-bit word with errors. In some embodiments, when errors are found, the memory circuit will be reprogrammed, repaired, or rejected.

[0169] Fig. 7A is a flow chart of a method 700A according to some embodiments. In some embodiments, the method 700A comprises a memory circuit 100, a peripheral circuit 160, an interface circuit 170, a memory circuit 200, an interface circuit 300, an interface circuit 301, Figure 4A-Figure 4K One or more of the various circuits described in one or more of the memory circuits 600A and the interface circuit 600B are implemented.

[0170] At operation 705, in response to a single pulse of the control signal, a series of internal clock pulses, a first access signal, and a second access signal are generated. Figure 5A As described above, in response to a single control signal pulse 516 of the control signal SCLKEN, an internal clock pulse series SCLK is generated, the first access signal is one of the access signal WLR and the access signal WLP, and the second access signal is the other of the access signal WLR or the access signal WLP. In at least one embodiment, the internal clock pulse SCLK is pulsed with an internal clock period T corresponding to the pulse width PW of the control signal pulse 516. BL In at least one embodiment, the access signal WLR is generated in response to a rising edge 518 of the control signal pulse 516 , and / or the access signal WLP is generated in response to a falling edge 519 of the control pulse 516 .

[0171] At operation 715, at least one of a read operation or a program operation is performed in the memory circuit based on the first access signal, the second access signal, and at least one internal clock pulse in the series of internal clock pulses. Figure 2A , Figure 2B , Figure 5A As discussed, in one or more embodiments, a programming operation is performed. The access signal WLR is applied directly to the corresponding read word lines WLR[1]-WLR[K] ( Figure 2B ), or applied to a WLR driver circuit coupled to a corresponding read word line to apply a first access voltage to an access transistor (eg, Figure 2A The access signal WLP is directly applied to the corresponding programming word lines WLP[1]~WLP[K] ( Figure 2B ), or applied to a WLP driver circuit coupled to a corresponding programming word line to provide a voltage to an anti-fuse transistor (eg, Figure 2A A programming voltage is applied to the gate of the transistor T2 in the anti-fuse transistor. In response to the BL selection signal SBL<1:M> generated based on the internal clock pulse SCLK, multiple bit lines BL[1] to BL[M] are sequentially selected or accessed. When the selected bit line is grounded, the corresponding memory cell is programmed (e.g., stores logic "0") by the voltage stress caused by the programming voltage on the gate dielectric of the anti-fuse transistor. When a sufficient voltage higher than the ground voltage (e.g., the first access voltage) is applied to the selected bit line, the corresponding memory cell will not be programmed logic (e.g., stores logic "1"). The read operation is performed similarly, although different voltage sets are applied to the word line and the bit line. In at least one embodiment, one or more advantages described herein can be achieved by method 700A.

[0172] Figure 7B is a flowchart of a method 700B according to some embodiments. In some embodiments, the method 700B comprises a memory circuit 100, a peripheral circuit 160, an interface circuit 170, a memory circuit 200, an interface circuit 300, an interface circuit 301, Figure 4A-Figure 4K One or more of the various circuits described in one or more of the memory circuits 600A and the interface circuit 600B are implemented.

[0173] At operation 725, the pulse width of the control signal pulse is determined. Figure 4B , Figure 5A As shown, in response to the rising edge 518 of the control signal pulse 516, the ripple counter 410 is enabled and starts counting the clock pulse CLK. The ripple counter 410 continues to count the clock pulse CLK until the counting operation of the ripple counter 410 is disabled by the falling edge 519 of the control signal pulse 516. The number of counts of the clock pulse CLK between the rising edge 518 and the falling edge 519 of the control signal pulse 516 is determined as the pulse width of the control signal pulse 516.

[0174] At operation 735, it is determined whether the pulse width of the control signal pulse is less than a time threshold. Figure 4B , Figure 5A As described above, the comparison circuit COMP1 compares the count number of the ripple counter 410 (which is determined as the pulse width of the control signal pulse 516) with the time threshold T_Thres output by the multiplexer MUX1. In response to the count number of the ripple counter 410 (i.e., the pulse width of the control signal pulse 516) being less than the time threshold T_Thres (i.e., "yes" from operation 735), the process proceeds to operation 745. Otherwise (i.e., "no" in operation 735), the process proceeds to operation 765.

[0175] At operation 745, for example, as described with respect to Figure 5A and Fig. 7A As described in operation 705 in the embodiment, a series of internal clock pulses are generated with an internal clock period corresponding to a pulse width of a control signal pulse.

[0176] At operation 755, at least one of a read operation or a program operation is performed in the memory circuit based on at least one internal clock pulse in the series of internal clock pulses, for example, as described with respect to Figure 5A and Fig. 7A As described in operation 715 in.

[0177] At operation 765, the generation of the internal clock pulse SCLK is prevented. Figure 4B , Figure 5B As described above, when the comparison circuit COMP1 determines that the pulse width of the control signal pulse 316 is not shorter than the time threshold T_Thres, the comparison circuit COMP1 switches the switch SW1 to the off state to disconnect the output terminal 415 and the count number of the ripple counter 410 stored in the storage circuit 320, thereby invoking the overtime protection, which in turn prevents the generation of the internal clock pulse SCLK, such as Figure 5B In at least one embodiment, by preventing the use of control signal pulses longer than a time threshold to control access operations, power consumption and / or potential failures are reduced. In at least one embodiment, one or more other advantages described herein can be achieved by method 700B.

[0178] The various low levels, high levels, logic "0", logic "1" described herein are examples. Within the scope of various embodiments, one or more of the circuits or signals described are modified to include a low level instead of the high level, or vice versa, and / or to include a logic "0" instead of the described logic "1", or vice versa.

[0179] The method includes example operations, but does not necessarily need to be performed in the order shown. According to the spirit and scope of the embodiments of the present disclosure, operations can be appropriately added, replaced, changed in order, and / or eliminated. Embodiments combining different features and / or different embodiments are within the scope of the present disclosure, and will be apparent to those of ordinary skill in the art after reading the present disclosure.

[0180] In some embodiments, a memory circuit includes a memory array and a peripheral circuit. The peripheral circuit includes an internal clock generation circuit and a first access signal generation circuit. The internal clock generation circuit is configured to generate an internal clock pulse series in an internal clock period corresponding to a pulse width of the control signal pulse in response to a control signal pulse. The first access signal generation circuit is configured to generate a first access signal in response to a first edge of the control signal pulse. The peripheral circuit is configured to control an access operation in the memory array based on at least one internal clock pulse in the internal clock pulse series and the first access signal.

[0181] In some embodiments, a memory array includes: a plurality of memory cells arranged in a plurality of rows and a plurality of columns, a plurality of first word lines, each first word line coupled to memory cells in a corresponding one of the plurality of rows of the memory array, and a plurality of bit lines, each bit line coupled to memory cells in a corresponding one of the plurality of columns of the memory array, and the peripheral circuit is configured to: access a first word line of the plurality of first word lines in response to a first access signal, and access a corresponding one of the plurality of columns in response to each internal clock pulse in a series of internal clock pulses.

[0182] In some embodiments, the memory array further includes: a plurality of second word lines, each second word line coupled to memory cells in a corresponding row of the plurality of rows of the memory array, the peripheral circuit further includes: a second access signal generating circuit configured to generate a second access signal in response to a second edge of the control signal pulse, and the peripheral circuit is configured to: access a second word line of the plurality of first word lines in response to the second access signal, wherein the accessed first word line and the accessed second word line are coupled to memory cells in the same row of the plurality of rows of the memory array.

[0183] In some embodiments, the first edge is a rising edge of the control signal pulse, the second edge is a falling edge of the control signal pulse, and a duration of the second access signal is within a duration of the first access signal.

[0184] In some embodiments, the internal clock generation circuit includes: a pulse width detection circuit, configured to detect the pulse width of a control signal pulse, and a storage circuit, coupled to the output end of the pulse width detection circuit and configured to store the detected pulse width of the control signal pulse, and the internal clock generation circuit is configured to generate a series of internal clock pulses in an internal clock period corresponding to the stored pulse width of the detected control signal pulse.

[0185] In some embodiments, the internal clock generation circuit is configured to disconnect the storage circuit from the output terminal of the pulse width detection circuit in response to a detected pulse width of the control signal pulse being greater than an adjustable time threshold.

[0186] In some embodiments, the pulse width detection circuit includes a first counting circuit, which is configured to count a first number of clock pulses of a clock signal during a pulse width of a control signal pulse, and a storage circuit is configured to store the first number output by the first counting circuit as the stored detected pulse width of the control signal pulse.

[0187] In some embodiments, the internal clock generation circuit also includes: a second counting circuit, configured to count a second number of clock pulses of the clock signal after the control signal pulse ends, and a comparison circuit, configured to output an intermediate signal in response to the second number output by the second counting circuit being equal to the first number stored in the storage circuit to: cause the internal clock pulse to be output in the internal clock pulse series, and reset the second counting circuit.

[0188] In some embodiments, the internal clock generation circuit further includes: a cell counting circuit configured to count a third number of internal clock pulses output in the series of internal clock pulses, and to output another intermediate signal to stop outputting the series of internal clock pulses in response to the third number being equal to an adjustable threshold value corresponding to the number of memory cells of the memory array accessible in an access operation.

[0189] In some embodiments, an interface circuit for a memory circuit includes a first counting circuit, a first latch circuit, a second counting circuit, a first comparison circuit, and a second latch circuit. The first counting circuit includes an input terminal coupled to a control signal input, a clock input terminal coupled to a clock signal input, and an output terminal. The first latch circuit includes an input terminal coupled to an output terminal of the first counting circuit, a clock input terminal coupled to a clock signal input, and an output terminal. The second counting circuit includes a clock input terminal coupled to a clock signal input and an output terminal. The first comparison circuit includes a first input terminal coupled to an output terminal of the first latch circuit, a second input terminal coupled to an output terminal of the second counting circuit, and an output terminal. The second latch circuit includes a clock input terminal and an output terminal coupled to an output terminal of the first comparison circuit.

[0190] In some embodiments, an output terminal of the first comparison circuit is coupled to a reset input terminal of the second counting circuit.

[0191] In some embodiments, the interface circuit further includes: a third counting circuit, the third counting circuit including: an input terminal coupled to the output terminal of the first comparison circuit, a clock input terminal coupled to the clock signal input, and an output terminal coupled to the enable input terminal of the second latch circuit.

[0192] In some embodiments, the interface circuit also includes: a multiplexer, the multiplexer includes: a plurality of input terminals, and an output terminal; a second comparison circuit, the second comparison circuit includes: a first input terminal coupled to the output terminal of the third counting circuit, a second input terminal coupled to the output terminal of the multiplexer, and an output terminal; and a switch coupled between the output terminal of the third counting circuit and the enable input terminal of the second latch circuit, the switch including a control terminal coupled to the output terminal of the second comparison circuit.

[0193] In some embodiments, the switch comprises a normally open switch.

[0194] In some embodiments, at least one of the first counting circuit, the second counting circuit, or the third counting circuit includes a ripple counter.

[0195] In some embodiments, the interface circuit also includes: a multiplexer, the multiplexer includes: a plurality of input terminals, and an output terminal; a second comparison circuit, the second comparison circuit includes: a first input terminal coupled to the output terminal of the first counting circuit, a second input terminal coupled to the output terminal of the multiplexer, and an output terminal; and a switch coupled between the output terminal of the first counting circuit and the input terminal of the first latch circuit, the switch including a control terminal coupled to the output terminal of the second comparison circuit.

[0196] In some embodiments, the switch comprises a normally closed switch.

[0197] In some embodiments, the interface circuit further includes: an edge detection circuit, the edge detection circuit including: an input terminal coupled to a control signal input, a clock input terminal coupled to a clock signal input, and an output terminal coupled to an input terminal of a second counting circuit.

[0198] In some embodiments, the interface circuit also includes: a rising edge detection circuit, the rising edge detection circuit includes: an input terminal coupled to a control signal input, a clock input terminal coupled to a clock signal input, and a reset input terminal, configured to receive a first reset signal; and a falling edge detection circuit, the falling edge detection circuit includes: an input terminal coupled to a control signal input, a clock input terminal coupled to a clock signal input, and a reset input terminal, configured to receive a second reset signal before the first reset signal is received at the reset input terminal of the rising edge detection circuit.

[0199] In some embodiments, a method of operating a memory circuit includes generating a series of internal clock pulses, a first access signal, and a second access signal in response to a single pulse of a control signal. The method also includes performing at least one of a read operation or a program operation in the memory circuit based on the first access signal, the second access signal, and at least one internal clock pulse in the series of internal clock pulses.

[0200] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for achieving the same purpose of the embodiments introduced herein and / or achieving the same advantages thereof. Those skilled in the art will also appreciate that such equivalent structures do not deviate from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and changes in the present disclosure without departing from the spirit and scope of the present disclosure. < / m> < / m> < / m> < / m> < / m> < / n> < / n>

Claims

1. A memory circuit, comprising: Memory array; as well as A peripheral circuit, the peripheral circuit comprising: an internal clock generating circuit configured to generate a series of internal clock pulses in an internal clock period corresponding to a pulse width of the control signal pulse in response to the control signal pulse, and A first access signal generating circuit is configured to generate a first access signal in response to a first edge of the control signal pulse, and The peripheral circuit is configured to control an access operation in the memory array based on at least one internal clock pulse in the internal clock pulse series and the first access signal.

2. The memory circuit according to claim 1, wherein: The memory array comprises: A plurality of memory cells, arranged in a plurality of rows and a plurality of columns, a plurality of first word lines, each first word line coupled to the memory cells in a corresponding one of the plurality of rows of the memory array, and a plurality of bit lines, each bit line coupled to the memory cells in a corresponding one of the plurality of columns of the memory array, and The peripheral circuit is configured to access a first word line of the plurality of first word lines in response to the first access signal, and In response to each internal clock pulse in the series of internal clock pulses, a corresponding one of the plurality of columns is accessed.

3. The memory circuit according to claim 2, wherein: The memory array further comprises: a plurality of second word lines, each second word line coupled to the memory cells in a corresponding one of the plurality of rows of the memory array, The peripheral circuit also includes: a second access signal generating circuit configured to generate a second access signal in response to a second edge of the control signal pulse, and The peripheral circuit is configured as In response to the second access signal, a second word line of the plurality of second word lines is accessed, wherein the accessed first word line and the accessed second word line are coupled to the memory cells in the same row of the plurality of rows of the memory array.

4. The memory circuit according to claim 3, wherein: The first edge is a rising edge of the control signal pulse, The second edge is a falling edge of the control signal pulse, and The duration of the second access signal is within the duration of the first access signal.

5. The memory circuit according to claim 1, wherein: The internal clock generation circuit comprises: a pulse width detection circuit configured to detect the pulse width of the control signal pulse, and a storage circuit coupled to the output terminal of the pulse width detection circuit and configured to store the detected pulse width of the control signal pulse, and The internal clock generation circuit is configured to generate the series of internal clock pulses at the internal clock period corresponding to the stored detected pulse width of the control signal pulse.

6. An interface circuit for a memory circuit, the interface circuit comprising: A first counting circuit, wherein the first counting circuit comprises: Input terminal, coupled to the control signal input, A clock input terminal coupled to a clock signal input, and Output terminal; A first latch circuit, wherein the first latch circuit comprises: an input terminal coupled to the output terminal of the first counting circuit, A clock input terminal coupled to the clock signal input, and Output terminal; A second counting circuit, wherein the second counting circuit comprises: A clock input terminal coupled to the clock signal input, and Output terminal; A first comparison circuit, wherein the first comparison circuit comprises: a first input terminal coupled to the output terminal of the first latch circuit, a second input terminal coupled to the output terminal of the second counting circuit, and output terminal; and A second latch circuit, wherein the second latch circuit comprises: a clock input terminal coupled to the output terminal of the first comparison circuit, and Output end.

7. The interface circuit according to claim 6, further comprising: A third counting circuit, the third counting circuit comprising: an input terminal coupled to the output terminal of the first comparison circuit, A clock input terminal coupled to the clock signal input, and The output terminal is coupled to the enable input terminal of the second latch circuit.

8. The interface circuit according to claim 7, further comprising: A multiplexer, the multiplexer comprising: Multiple inputs, and Output terminal; A second comparison circuit, wherein the second comparison circuit comprises: a first input terminal coupled to the output terminal of the third counting circuit, a second input terminal coupled to the output terminal of the multiplexer, and output terminal; and A switch is coupled between the output terminal of the third counting circuit and the enable input terminal of the second latch circuit, the switch comprising a control terminal coupled to the output terminal of the second comparison circuit.

9. The interface circuit according to claim 6, further comprising: A multiplexer, the multiplexer comprising: Multiple inputs, and Output terminal; A second comparison circuit, wherein the second comparison circuit comprises: a first input terminal coupled to the output terminal of the first counting circuit, a second input terminal coupled to the output terminal of the multiplexer, and output terminal; and A switch is coupled between the output terminal of the first counting circuit and the input terminal of the first latch circuit, the switch comprising a control terminal coupled to the output terminal of the second comparison circuit.

10. A method of operating a memory circuit, the method comprising: In response to a single pulse of the control signal, generates: Internal clock pulse series, The first access signal, and a second access signal; as well as At least one of a read operation or a program operation is performed in the memory circuit based on the first access signal, the second access signal, and at least one internal clock pulse in the series of internal clock pulses.

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