Address comparison circuit and memory system

Abstract

The embodiment of the invention provides an address comparison circuit and a storage system. The circuit comprises a delay circuit, a reset circuit and a detection circuit. The delay circuit receives an activation command and outputs an enable signal. The reset circuit is configured to receive a control command and adjust the level of the feedback node to a first level. The detection circuit is configured to compare the first address with the second address, and select whether to conduct a transmission path between the feedback node and the ground end or not during an enabling signal effective period based on a comparison result of the first address and the second address; if the first address is not consistent with the second address, the transmission path is conducted, so that the level of the feedback node is adjusted to be a second level, and the level value of the second level is smaller than the level value of the first level; and if the first address is consistent with the second address, the transmission path is cut off, so that the level of the feedback node is kept at the first level. According to the embodiment of the invention, the circuit area is reduced, the transmission delay caused by address comparison is reduced, and the accuracy of a comparison result is improved.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and in particular to an address comparison circuit and a storage system. Background Art

[0002] Memory systems are typically provided as internal semiconductor integrated circuits in computers or other electronic systems. There are many different types of memory systems, including, for example, random access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), resistive random access memory (RRAM), double data rate memory (DDR), low power double data rate memory (LPDDR), phase change memory (PCM), and flash memory.

[0003] The storage system includes an address comparison circuit, which can be used to compare whether a row address obtained by decoding based on row address information is consistent with an address stored in a register.

[0004] However, the current storage system has a problem that the address comparison circuit is complex, resulting in a large address comparison transmission delay and the accuracy needs to be improved. Summary of the invention

[0005] The embodiments of the present disclosure provide an address comparison circuit and a storage system, which are at least beneficial to reducing the complexity of the address comparison circuit, reducing the transmission delay caused by address comparison, and improving the accuracy of address comparison judgment.

[0006] According to some embodiments of the present disclosure, the embodiments of the present disclosure provide an address comparison circuit on one hand, including: a delay circuit, configured to receive the activation command and perform a delay operation to generate and output an enable signal; a reset circuit, having a feedback node, configured to receive a control command, and in response to the effective control command, adjust the level of the feedback node to a first level before receiving a valid enable signal; a detection circuit, connected between the feedback node and a ground terminal, configured to receive a first address and a second address during the validity period of the enable signal, and compare the first address with the second address, and select whether to conduct a transmission path between the feedback node and the ground terminal based on the comparison result of the first address with the second address; wherein, when the enable signal is valid, the first address and the second address have been received by the detection circuit, if the first address is inconsistent with the second address, the transmission path is conducted, so that the level of the feedback node is adjusted to a second level, and the level value of the second level is less than the level value of the first level; if the first address is consistent with the second address, the transmission path is cut off, so that the level of the feedback node remains at the first level.

[0007] In some embodiments, the first address includes N-bit first data, and the second address includes N-bit second data; the delay circuit is configured so that when the enable signal is valid, all the first data and the second data have been received by the detection circuit.

[0008] In some embodiments, the delay circuit includes: an even number of cascaded first sub-inverters, the input end of the first sub-inverter in the first position receives the activation command, and the output end of the first sub-inverter in the last position outputs the enable signal.

[0009] In some embodiments, the delay circuit includes: an even number of cascaded second sub-inverters, the input end of the second sub-inverter in the first position receives the activation command; a first sub-PMOS tube, the source of the first sub-PMOS tube is connected to the working power supply, and the gate is connected to the output end of the second sub-inverter in the last position; a second sub-NMOS tube, the gate of the second sub-NMOS tube is connected to the output end of the second sub-inverter in the last position, and the source is connected to the ground end; a plurality of third sub-NMOS tubes connected in series between the first sub-PMOS tube and the second sub-NMOS tube, wherein the gate of each of the third sub-NMOS tubes is connected to the working power supply, the drain of one of the third sub-NMOS tubes is connected to the drain of the first sub-PMOS tube, and the source of another of the third sub-NMOS tubes is connected to the drain of the second sub-NMOS tube; a third sub-inverter, the input end is connected to the drain of the first sub-PMOS tube, and the output end outputs the enable signal.

[0010] In some embodiments, the address comparison circuit also includes: a latch circuit, connected to the feedback node, configured to receive the enable signal, and if the first address is consistent with the second address during the validity period of the enable signal, latch the signal of the feedback node and output a detection signal via an output node, the detection signal and the signal of the feedback node are in an inverse relationship with each other.

[0011] In some embodiments, the latch circuit includes: a latch NAND gate, one input of which is connected to the feedback node and the other input of which receives the enable signal; a latch PMOS tube, a gate of which is connected to the output of the latch NAND gate, a source of which is connected to a working power supply, and a drain of which is connected to the feedback node.

[0012] In some embodiments, the first address includes N-bit first data, and the second address includes N-bit second data; the detection circuit includes: N detection modules, each of which is connected between the feedback node and the ground terminal to form a sub-transmission path connecting the feedback node and the ground terminal, and each of the detection modules is configured to receive a first data and a corresponding second data, and compare the first data with the second data. If the first data is different from the second data, the sub-transmission path is turned on, and if the first data is the same as the second data, the sub-transmission path is turned off.

[0013] In some embodiments, the detection module includes: a first comparison circuit, connected between the feedback node and the ground terminal, configured to receive the first data and the second inverse data, if the first data is the same as the second inverse data, the sub-transmission path is turned on, if the first data is different from the second inverse data, the sub-transmission path is turned off; and / or, a second comparison circuit, connected between the feedback node and the ground terminal, configured to receive the first inverse data and the second data, if the first inverse data is the same as the second data, the sub-transmission path is turned on, if the first inverse data is different from the second data, the sub-transmission path is turned off; wherein, the first inverse data is the inverse of the first data, and the second inverse data is the inverse of the second data.

[0014] In some embodiments, the first comparison circuit includes: a first NMOS tube, whose drain is connected to the feedback node, and whose gate receives the first data; a second NMOS tube, whose drain is connected to the source of the first NMOS tube, whose gate receives the second inverted data, and whose source is connected to the ground; the second comparison circuit includes: a third NMOS tube, whose drain is connected to the feedback node, whose gate receives the first inverted data; and a fourth NMOS tube, whose drain is connected to the source of the third NMOS tube, whose gate receives the second data, and whose source is connected to the ground.

[0015] In some embodiments, each of the detection modules has a ground terminal; the detection circuit also includes: a first switch module, connected between the ground terminal and the ground terminal of each detection module, and configured to be turned on in response to the valid enable signal to enable conduction between the ground terminal and the ground terminal, and if the activation command is invalid, the first switch module is turned off to disconnect the ground terminal and the ground terminal.

[0016] In some embodiments, the first switch module includes: a fifth NMOS transistor, a drain of the fifth NMOS transistor is connected to the ground terminal, a gate receives the enable signal, and a source is connected to the ground terminal.

[0017] In some embodiments, the reset circuit includes: a control module, configured to receive the control command and output a control signal; a pull-up module, connected between the working power supply and the feedback node, configured such that, during the period when the control command is valid, the pull-up module is turned on in response to the control signal to connect the working power supply to the feedback node, and during the period when the control command is invalid, the pull-up module is turned off in response to the control signal.

[0018] In some embodiments, the control module is further configured to receive an inverted signal of an enable signal, the control signal is generated based on the control command and the enable signal, and when both the enable signal and the control command are valid, the pull-up module is cut off in response to the control signal.

[0019] In some embodiments, the pull-up module includes: a first PMOS tube, a gate of which receives the control signal, a source of which is connected to the working power supply, and a drain of which is connected to the feedback node.

[0020] According to some embodiments of the present disclosure, the embodiments of the present disclosure further provide a storage system, including the address comparison circuit provided by any of the above embodiments.

[0021] The technical solution provided by the embodiments of the present disclosure has at least the following advantages:

[0022] The address comparison circuit includes a delay circuit, a reset circuit and a detection circuit. The delay circuit is used to perform a delay operation on the activation command to generate an enable signal, and the reset circuit is used to reset the level of the feedback node to the first level in response to a valid control command; the detection circuit is used to detect whether the first address and the second address are consistent, and in response to a valid enable signal, if the first address and the second address are inconsistent, the transmission path between the feedback node and the ground end is turned on, so that the level of the feedback node is pulled down from the first level to the second level, and if the first address and the second address are consistent, the transmission path between the feedback node and the ground end is cut off, and the level of the feedback node is maintained at the first level. Therefore, by monitoring the level of the feedback node in the address comparison stage, it can be known whether the first address is consistent with the second address. The circuit structure of the above-mentioned address comparison circuit is simple, which can not only reduce the area occupied by the circuit, but also reduce the transmission delay of the address comparison circuit and improve the address comparison efficiency. Furthermore, since the enable signal has a certain delay compared to the activation command, when the enable signal is valid, the detection circuit has already received most of the data in the first address and the second address and may even have received all of the data, thereby avoiding the problem of glitches in the feedback node signal caused by the different time at which the data arrives at the detection circuit, thereby improving the signal quality of the feedback node and facilitating improving the accuracy of address comparison. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings, which do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are represented as similar elements, and the figures in the drawings do not constitute a scale limitation unless otherwise stated. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0024] Figure 1 A functional block diagram of an address comparison circuit provided in an embodiment of the present disclosure;

[0025] Figure 2 A schematic diagram of a circuit diagram structure of a delay circuit;

[0026] Figure 3 is another circuit structure schematic diagram of a delay circuit;

[0027] Figure 4 is another block diagram of an address comparison circuit;

[0028] Figure 5 A schematic diagram of a circuit structure of a latch circuit;

[0029] Figure 6 A functional block diagram of a detection circuit;

[0030] Figure 7 A functional block diagram of a detection module;

[0031] Figure 8 A schematic diagram of a circuit structure of a first comparison circuit and a second comparison circuit;

[0032] Fig. 9 Another functional block diagram of the detection module;

[0033] Fig.10 A schematic diagram of a circuit structure of a latch;

[0034] Fig.11 A schematic diagram of a circuit structure of a detection module;

[0035] Fig.12 is a schematic diagram of a circuit structure of a first switch module;

[0036] Fig.13 is another functional block diagram of an address comparison circuit;

[0037] Fig.14 for Fig.13The corresponding timing diagram of each signal in the address comparison circuit and the schematic diagram of the level change of the feedback node netr;

[0038] Fig.15 is another functional block diagram of an address comparison circuit;

[0039] Fig.16 A circuit structure diagram of a reset module;

[0040] Fig.17 A schematic diagram of a specific circuit structure of an address comparison circuit;

[0041] Fig.18 FIG. 4 is another specific circuit structure diagram of the address comparison circuit. DETAILED DESCRIPTION

[0042] As can be seen from the background art, the address comparison circuit structure in the current storage system is complex and the transmission delay is large.

[0043] The following will describe the various embodiments of the present disclosure in detail with reference to the accompanying drawings. However, it will be appreciated by those skilled in the art that in the various embodiments of the present disclosure, many technical details are provided in order to enable the reader to better understand the present disclosure. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the present disclosure can be implemented.

[0044] Figure 1 This is a functional block diagram of an address comparison circuit provided by an embodiment of the present disclosure. Figure 1In the embodiment of the present disclosure, the address comparison circuit includes: a delay circuit 100, configured to receive an activation command ACT and perform a delay operation to generate and output an enable signal RFUET_EN. A reset circuit 101, having a feedback node netr, is configured to receive a control command MasterMaster, and in response to a valid control command Master, adjust the level of the feedback node netr to a first level before receiving a valid enable signal RFUET_EN; a detection circuit 102, connected between the feedback node netr and the ground terminal GND, is configured to receive a first address RA[N-1:0] and a second address FA[N-1:0], and compare the first address RA[N-1:0] and the second address FA[N-1:0], and during the validity period of the enable signal RFUET_EN, based on the first address RA[N-1:0] and the second address FA[ N-1:0], selects whether to turn on the transmission path between the feedback node netr and the ground terminal GND; wherein, when the enable signal RFUET_EN is valid, the first address RA[N-1:0] and the second address FA[N-1:0] have been received by the detection circuit 102, and if the first address RA[N-1:0] is inconsistent with the second address FA[N-1:0], the transmission path is turned on to adjust the level of the feedback node netr to the second level, and the level value of the second level is less than the level value of the first level; if the first address RA[N-1:0] is consistent with the second address FA[N-1:0], the transmission path is cut off to keep the level of the feedback node netr at the first level.

[0045] It is understandable that the following problem may occur during the comparison of the address comparison circuit: part of the data in the first address RA[N-1:0] and part of the data in the second address FA[N-1:0] arrive at the detection circuit 102 for comparison first, and obtain the first comparison result; the rest of the data in the first address RA[N-1:0] and the rest of the data in the second address FA[N-1:0] arrive at the detection circuit 102 for comparison later, and obtain the second comparison result. If the first comparison result and the second comparison result affect the level of the feedback node netr successively, it will cause glitches on the signal of the feedback node netr. In addition, even if all data in the first address RA[N-1:0] and all data in the second address FA[N-1:0] arrive at the detection circuit 102 for comparison at the same time, the detection circuit 102 may have different comparison capabilities for different data in the first address RA[N-1:0] and different data in the second address FA[N-1:0]. For example, the detection circuit 102 includes multiple detection modules, and the tr / tf of each detection module is different. Then, the time when the comparison results of different data affect the feedback node netr is also not uniform, which may also cause glitches in the signal of the feedback node netr, affecting the judgment of the accuracy of the comparison result.

[0046] Since the delay circuit 100 is provided in the address comparison circuit, the delay circuit 100 can delay the activation command ACT to generate and output the enable signal RFUET_EN, that is, the enable signal RFUET_EN has a delay compared to the activation command ACT. In this way, when the enable signal RFUET_EN is valid, it can be ensured that the first address RA[N-1:0] and the second address FA[N-1:0] have been transmitted to the detection circuit 102, avoiding the glitch problem caused by the different time when the data in the first address RA[N-1:0] and the data in the second address FA[N-1:0] arrive at the detection circuit 102. Therefore, even if the total data of the first address RA[N-1:0] and the second address FA[N-1:0] arrive at the detection circuit 102 at different times or the tr / tf (rising edge time / falling edge time) of the detection circuit 102 itself is different, there will be no glitch problem in the signal of the feedback node netr, thereby avoiding the problem of misjudgment of the detection result.

[0047] The address comparison circuit provided by the embodiment of the present disclosure will be described in detail below in conjunction with the accompanying drawings. Unless otherwise specified, the inverted triangle symbol in the accompanying drawings represents the ground terminal GND.

[0048] The address comparison circuit can be applied to a storage system, and the storage system can be a DRAM (Dynamic Random Access Memory) or an SRAM (Static Random Access Memory). In some embodiments, the address comparison circuit can be applied to an SDRAM (Synchronous Dynamic Random Access Memory), and the SDRAM can be a DDR (Double Data Rate) SDRAM, such as a DDR4 storage system, a DDR5 storage system, a DDR6 storage system, an LPDDR4 storage system, an LPDDR5 storage system, or an LPDDR6 storage system.

[0049] In some embodiments, the first address RA[N-1:0] may be a row address obtained by decoding based on the row address information, i.e., a Row address, and the second address FA[N-1:0] may be an address provided by a register. It is understood that, in some embodiments, the first address RA[N-1:0] may also be an address provided by a register, and the second address FA[N-1:0] may be a row address obtained by decoding based on the row address information.

[0050] The memory system may have a first address bus and a second address bus, the first address bus is used to transmit the first address RA[N-1:0], and the second address bus is used to transmit the second address FA[N-1:0].

[0051] The first address can be N-bit first data, and the first data is address data; the second address can be N-bit second data, and the second data is address data; the corresponding first address is recorded as the first address RA[N-1:0], and the second address is recorded as the second address FA[N-1:0], and N can be any positive integer greater than or equal to 2. For example, N can be 14, the first address is recorded as RA[13:0], and the second address is recorded as FA[13:0]. N can also be any natural number such as 3, 4, 5, etc. The first data and the second data are both binary numbers.

[0052] In addition, each bit of first data in the first address RA[N-1:0] corresponds to each bit of second data in the second address FA[N-1:0], and the address comparison circuit is used to compare whether each first data is identical to a corresponding second data. If each first data in the N first data is identical to the corresponding second data, the first address RA[N-1:0] is identical to the second address FA[N-1:0]; if at least one first data in the N first data is different from a corresponding second data, the first address RA[N-1:0] is inconsistent with the second address FA[N-1:0].

[0053] Taking N as 14 as an example, if each of the 14 first data in the first address RA[N-1:0] is the same as the corresponding second data, the 14-bit first address RA[N-1:0] is consistent with the 14-bit second address FA[N-1:0]; otherwise, the 14-bit first address RA[N-1:0] is inconsistent with the 14-bit second address FA[N-1:0].

[0054] Taking the first address RA[N-1:0] as the row address as an example, the storage system may also have a first inverted address RAB[N-1:0] corresponding to the first address RA[N-1:0] as an inverted code, and the first inverted address RAB[N-1:0] includes N-bit first inverted code data, wherein each first inverted code data is the inverted code of a corresponding first data, in other words, the first data of the mth bit is the inverted code of the first inverted code data of the mth bit. If the first data of the mth bit is 0, the first inverted code data of the mth bit is 1, and if the first data of the mth bit is 1, the first inverted code data of the mth bit is 0, 0≤m≤N-1.

[0055] Correspondingly, the storage system may further include a third address bus, and the third address bus is used to transmit the first inverted address RAB[N-1:0].

[0056] In some embodiments, the delay circuit 100 can be used to ensure that when the enable signal RFUET_EN is valid, all the first data and all the second data have been received by the detection circuit 102. Therefore, a design principle of the delay circuit 100 can be: considering the maximum possible time deviation of the first data and the second data arriving at the detection circuit 102, for example, considering the PVT (Pressure / Volume / Temperature) deviation in the transmission path of the first data and the second data arriving at the detection circuit 102, to design the delay amount of the delay circuit 100 to perform the delay operation, so as to ensure that when the enable signal RFUET_EN is valid, all the first data and all the second data have been received by the detection circuit 102.

[0057] Figure 2 A schematic diagram of a circuit diagram structure of a delay circuit.

[0058] refer to Figure 2 The delay circuit 100 may include an even number of cascaded first inverters 1001 , an input end of the first sub-inverter 1001 at the first position receives an activation command ACT, and an output end of the first sub-inverter 1001 at the last position outputs an enable signal RFUET_EN.

[0059] It can be understood that the number of the first sub-inverters 1001 can be determined according to the required delay amount and the delay amount of each first sub-inverter itself.

[0060] Figure 3 Another circuit structure diagram of a delay circuit.

[0061] refer to Figure 3 The delay circuit 100 may include: an even number of cascaded second sub-inverters 1002, the input end of the second sub-inverter 1002 at the first position receives the activation command ACT; a first sub-PMOS tube 1003, the source of the first sub-PMOS tube 1003 is connected to the working power supply VDD, and the gate is connected to the output end of the second sub-inverter 1002 at the last position; a second sub-NMOS tube 1004, the gate of the second sub-NMOS tube 1004 is connected to the output end of the second sub-inverter 1002 at the last position, and the source is connected to the ground terminal GND; a series of A plurality of third sub-NMOS tubes 1005 are connected between the first sub-PMOS tube and the second sub-NMOS tube, wherein the gate of each third sub-NMOS tube 1005 is connected to the working power supply VDD, the drain of a third sub-NMOS tube 1005 is connected to the drain of the first sub-PMOS tube, and the source of another third sub-NMOS tube 1005 is connected to the drain of the second sub-NMOS tube 1004; a third sub-inverter 1006, the input end of which is connected to the drain of the first sub-PMOS tube 1003, and the output end of which outputs an enable signal RFUET_EN.

[0062] The delay circuit 100 may further include a fourth sub-inverter 1007 connected to an output terminal of the third sub-inverter 1006 , and an output terminal of the fourth sub-inverter 1007 outputs an inverted signal RFUETB_EN of the enable signal.

[0063] It should be noted that Figure 2 and Figure 3 These are merely schematic diagrams of two different circuit structures of the delay circuit. The embodiments of the present disclosure do not limit the specific circuit structure of the delay circuit 100 , and any circuit that can implement the above-mentioned delay operation can be used as the delay circuit in the embodiments of the present disclosure.

[0064] If the first address RA[N-1:0] is the same as the second address FA[N-1:0], and the enable signal RFUET_EN is valid, the level of the feedback node netr is the second level, which may be 0 or a level greater than 0. It can be understood that even if the sub-transmission path between the feedback node netr and the ground terminal GND is conductive, this sub-transmission path also has an equivalent resistance, and considering the current introduced by the equivalent resistance, the second level of the feedback node netr is greater than 0.

[0065] If the first address RA[N-1:0] and the second address FA[N-1:0] are different and the enable signal RFUET_EN is valid, the level of the feedback node netr is maintained at the first level.

[0066] The first level may be a logic "1", ie, a high level, and the second level may be a logic "0", ie, a low level.

[0067] Figure 4 Another block diagram of the address comparison circuit.

[0068] refer to Figure 4 The address comparison circuit may further include a latch circuit 103, connected to the feedback node netr, configured to receive an enable signal RFUET_EN, and if the first address RA[N-1:0] is consistent with the second address FA[N-1:0] during the validity period of the enable signal RFUET_EN, latch the signal of the feedback node netr and output a detection signal via the output node OUT, the detection signal and the signal of the feedback node netr are in an inverse relationship with each other.

[0069] During the comparison, if the first address RA[N-1:0] is consistent with the second address FA[N-1:0], the level of the feedback node netr is maintained at the first level, and the latch circuit 103 is used to latch the level of the feedback node netr to prevent the level of the feedback node netr from being disturbed and fluctuating, so as to further improve the accuracy of the comparison result. In addition, the latch circuit 103 is controlled by the enable signal RFUET_EN, so it can be further ensured that the latch circuit 103 starts to work after all the first data and the second data are compared, which is conducive to further reducing burrs and further improving the accuracy of the comparison result.

[0070] Figure 5 A schematic diagram of a circuit structure of a latch circuit.

[0071] refer to Figure 5 The latch circuit 103 may include a latch NAND gate 1031 and a latch PMOS tube 1302. One input end of the latch NAND gate 1031 is connected to the feedback node netr, and the other input end receives the enable signal RFUET_EN. The gate of the latch PMOS tube 1032 is connected to the output end of the latch NAND gate 1031, the source is connected to the working power supply VDD, and the drain is connected to the feedback node netr.

[0072] If the first address is consistent with the second address, the level of the feedback node netr is the first level, that is, the feedback node netr is 1, and the enable signal RFUET_EN is valid, that is, the enable signal RFUET_EN is 1. At this time, the output end of the latched NAND gate 1031 is 0, and the latched PMOS tube 1302 is turned on, so that the feedback node netr is connected to the working power supply VDD via the latched PMOS tube 1302. In this way, the level of the feedback node netr can be further maintained at the first level, so that the feedback node netr remains at 1, and the level of the feedback node netr is prevented from being disturbed. Further, the detection signal output by the output node OUT remains at "0".

[0073] Figure 6 is a functional block diagram of the detection circuit 102, refer to Figure 6 The detection circuit 102 may include: N detection modules 112, each detection module 112 is connected between the feedback node netr and the ground terminal GND to form a sub-transmission path connecting the feedback node netr and the ground terminal GND; each detection module 112 is configured to receive a first data and a corresponding second data, and compare the first data with the second data. If the first data is different from the second data, the sub-transmission path is turned on, and if the first data is the same as the second data, the sub-transmission path is turned off.

[0074] Continue to refer Figure 6, each detection module 112 has a ground terminal gnd; the detection circuit 102 also includes: a first switch module 122, connected between the ground terminal gnd and the ground terminal GND of each detection module 112, and configured to be turned on in response to a valid enable signal RFUET_EN to conduct between the ground terminal gnd and the ground terminal GND; if the enable signal RFUET_EN is invalid, the first switch module 122 is turned off to disconnect the ground terminal gnd from the ground terminal GND.

[0075] The first switch module 122 is set so that the address comparison circuit is also controlled by the enable signal RFUET_EN. Only when the enable signal RFUET_EN is valid, it is necessary to compare the first address RA[N-1:0] with the second address FA[N-1:0], and the ground terminal gnd of the detection module 112 is connected to the ground terminal GND via the first switch module 122. When the enable signal RFUET_EN is invalid, it is not necessary to compare the first address RA[N-1:0] with the second address FA[N-1:0], and the ground terminal gnd of the detection module 112 is disconnected from the ground terminal. In this way, the current generated by the detection module 112 during the invalid period of the enable signal RFUET_EN can be reduced, thereby reducing the power consumption of the address comparison circuit.

[0076] In addition, since the enable signal is effective later than the activation command, when the first switch module 122 is turned on, each first data in the first address and each second data in the second address have reached the corresponding detection module 112, and each detection module 112 is ready based on the received first data and second data to make the path between the ground terminal GND and the feedback node netr conductive or cut off. Even if the arrival time of each data in the first address and the second address is different, and / or the conductive capabilities of each detection module 112 are different (or called rising edge time / falling edge time is different), the time point when the address comparison result affects the level of the feedback node netr can also be unified, and this time point is when the first switch module 112 is turned on.

[0077] Compared with the solution that the first switch module is turned on when the activation command is valid, in the embodiment of the present disclosure, the feedback node netr is less disturbed, and the signal of the feedback node netr will not have glitches due to different arrival times of various data or different rising edge times / falling edge times. Therefore, the address comparison judgment result in the embodiment of the present disclosure is more accurate.

[0078] In some examples, the enable signal RFUET_EN is valid when it is 1, and invalid when it is 0. It is understandable that in some examples, it can also be set that the enable signal RFUET_EN is valid when it is 0, and invalid when it is 1.

[0079] It can be understood that the transmission path between the feedback node netr and the ground terminal GND is composed of N sub-transmission paths connected in parallel; when at least one sub-transmission path is turned on, the transmission path is turned on; when each sub-transmission path is turned off, the transmission path is turned off. For each detection module 112, if the first data and the second data received by the detection module 112 are different, the detection module 112 is turned on, so that the sub-transmission path between the feedback node netr and the ground terminal GND connected via the detection module 112 is turned on; if the first data and the second data received by the detection module 112 are the same, the detection module 112 is turned off (also called disconnected), so that the sub-transmission path between the feedback node netr and the ground terminal GND connected via the detection module 112 is turned off.

[0080] Each detection module 112 has a comparison terminal Compare and a ground terminal gnd. The comparison terminal Compare is directly connected to the feedback node netr, and the ground terminal gnd can be directly connected to the ground terminal GND. <0> , R.A. <1> , R.A. <2> , ……RA <n-2>and RA <n-1>The second data received and compared by each detection module 112 are FA <0> , FA <1> , FA <2> ,……FA <n-2>Japanese FA <n-1>.

[0081] In some examples, when the level of the feedback node netr is the first level, the logic level of the feedback node netr is 1, referred to as feedback node netr 1; when the level of the feedback node netr is the second level, the logic level of the feedback node netr is 0, referred to as feedback node netr 0.

[0082] If the first data is different from the second data, the sub-transmission path between the feedback node netr and the ground terminal GND is turned on, so that the level of the feedback node netr is pulled down from the first level to the second level, wherein the second level may be 0 or a level value greater than 0. It can be understood that even if the sub-transmission path between the feedback node netr and the ground terminal GND is turned on, this sub-transmission path also has an equivalent resistance, and in the case of considering the current introduced by the equivalent resistance, the second level of the feedback node netr is greater than 0.

[0083] If the first data is the same as the second data, the sub-transmission path between the feedback node netr and the ground terminal GND is cut off, so that the level of the feedback node netr can be maintained at the first level.

[0084] It can be understood that if the first data and the second data are different, the detection module 112 is turned on to connect the feedback node netr to the ground GND; if the first data and the second data are the same, the detection module 112 is turned off to disconnect the feedback node netr from the ground.

[0085] Therefore, according to the level change of the feedback node netr, it can be known whether the first data and the second data are the same. Each detection module 112 is used to detect whether one bit of the first data and the second data are the same, and all the detection modules 112 are connected in parallel between the feedback node netr and the ground. If at least one of the detection modules 112 is turned on, or the sub-transmission path between the feedback node netr and the ground corresponding to at least one detection module 112 is turned on, the level of the feedback node netr will change from the first level to the second level; only when all the detection modules 112 are turned off, that is, all the first data and the second data are the same, the level of the feedback node netr will remain at the first level.

[0086] Thus, in the stage of comparing the first address RA[N-1:0] with the second address FA[N-1:0], if the level of the feedback node netr remains at the first level, it indicates that each first data is the same as the corresponding second data, and the first address RA[N-1:0] is consistent with the second address FA[N-1:0]; if the level of the feedback node netr drops from the first level to the second level, it indicates that at least one first data is different from the corresponding second data, and the first address RA[N-1:0] is inconsistent with the second address FA[N-1:0].

[0087] Figure 7 FIG. 1 is a functional block diagram of the detection module 112, taking the detection module 112 comparing the first data and the second data of the nth bit as an example. Figure 7 The first comparison circuit 201 and / or the second comparison circuit 202 are both connected between the comparison terminal Compare and the ground terminal gnd, and the ground terminal gnd can be connected to the ground terminal GND via the first switch module 122.

[0088] The first comparison circuit 201 and / or the second comparison circuit 202 may also receive second inverted data, wherein the second inverted data is data in a second inverted address, and the second inverted address includes N-bit second inverted data, wherein each second inverted data is the inverted code of the corresponding second data, in other words, the second data of the nth bit is the inverted code of the second inverted data of the nth bit. If the second data of the nth bit is 0, the second inverted data of the nth bit is 1, and if the second data of the nth bit is 1, the second inverted data of the nth bit is 0, 0≤n≤N-1.

[0089] If the first data is the same as the corresponding second data, then the first data is different from the corresponding second inverted data, and the first inverted data is different from the corresponding second data. For example, if the first data and the corresponding second data are both 0, then the first inverted data and the second inverted data are both 1; if the first data and the corresponding second data are both 1, then the first inverted data and the second inverted data are 0.

[0090] If the first data is different from the corresponding second data, the first data is the same as the corresponding second inverted data, and the first inverted data is the same as the corresponding second data. For example, if the first data is 1 and the corresponding second data is 0, the first inverted data is 0 and the second inverted data is 1; if the first data is 0 and the corresponding second data is 1, the first inverted data is 1 and the second inverted data is 0.

[0091] From the above analysis, it can be known that whether the first data is the same as the second data can be determined by comparing whether the first data is the same as the second inverted data; or whether the first data is the same as the second data can be determined by comparing whether the first inverted data is the same as the second data.

[0092] For ease of illustration and explanation, Figure 7 In the example, the first data is marked as RA <n>, the second inverse code data is marked as FAB <n>, the first inverted data is marked as RAB <n>, the second data identifier is FA <n>, respectively refer to the first data of the n-th bit, the second inverse data of the n-th bit, the first inverse data of the n-th bit, and the second data of the n-th bit.

[0093] In some examples, the detection module 112 may include: a first comparison circuit 201 connected between the feedback node netr and the ground terminal, configured to receive the first data RA <n>And the second inverted data FAB <n>, if the first data RA <n>With the second inverted data FAB <n>The sub-transmission path is turned on if the first data RA <n>With the second inverted data FAB <n>If different, the sub-transmission path is terminated; wherein, the second inverted code data FAB <n>The second data FA <n>The inverse code of .

[0094] If the first data RA <n>With the second inverted data FAB <n>The same, that is, the first data RA <n>and the corresponding second data FA <n>different, the first comparison circuit 201 is turned on to connect the sub-transmission path between the feedback node netr and the ground, so that the level of the feedback node netr is pulled down from the first level to the second level.

[0095] If the first data RA <n>With the second inverted data FAB <n>Different, that is, the first data RA <n>and the corresponding second data FA <n>If the first comparison circuit 201 is the same, the first comparison circuit 201 is turned off to cut off the sub-transmission path between the feedback node netr and the ground, so that the level of the feedback node netr is maintained at the first level.

[0096] The first data RA is obtained by the first comparison circuit 201. <n>With the second inverted data FAB <n>The comparison is beneficial to further reduce the circuit complexity of the detection module 112, further reduce the area occupied by the address comparison circuit, and further improve the comparison speed to reduce the transmission delay caused by the address comparison.

[0097] In some other examples, the detection module 112 may also include: a second comparison circuit 202 connected between the feedback node netr and the ground terminal, configured to receive the first inverted data RAB <n>and the second data FA <n>, if the first inverted data RAB <n>With the second data FA <n>If the first inverted data RAB <n>With the second data FA <n>different, the sub-transmission path is terminated; wherein, the first inverted data RAB <n>The first data RA <n>The inverse code of .

[0098] If the first inverted data RAB <n>With the second data FA <n>The same, that is, the first data RA <n>and the corresponding second data FA <n>different, the second comparison circuit 202 is turned on to connect the sub-transmission path between the feedback node netr and the ground, so that the level of the feedback node netr is pulled down from the first level to the second level.

[0099] If the first inverted data RAB <n>With the second data FA <n>Different, that is, the first data RA <n>and the corresponding second data FA <n>If the feedback node netr and the ground terminal are the same, the second comparison circuit is turned off to cut off the sub-transmission path between the feedback node netr and the ground terminal, so that the level of the feedback node netr is maintained at the first level.

[0100] The first inverted data RAB is obtained by the first comparison circuit 202 <n>With the second data FA <n>The comparison is beneficial to further reduce the circuit complexity of the detection module 112, further reduce the area occupied by the address comparison circuit, and further improve the comparison speed to reduce the transmission delay caused by the address comparison.

[0101] In some other examples, reference Figure 5 The detection module 112 may also include: a first comparison circuit 201, connected between the feedback node netr and the ground terminal, configured to receive the first data RA <n>And the second inverted data FAB <n>, if the first data RA <n>With the second inverted data FAB <n>The sub-transmission path is turned on if the first data RA <n>With the second inverted data FAB <n>different, the sub-transmission path is cut off; the second comparison circuit 202 is connected between the feedback node netr and the ground terminal, and is configured to receive the first inverted data RAB <n>and the second data FA <n>, if the first inverted data RAB <n>With the second data FA <n>If the first inverted data RAB <n>With the second data FA <n>different, the sub-transmission path is terminated; wherein, the first inverted data RAB <n>The first data RA <n>The second inverse code data FAB <n>The second data FA <n>The inverse code of .

[0102] The detection module 112 includes a first comparison circuit 201 and a second comparison circuit 202, which is helpful to avoid the first inverted data RAB <n>Or the second inverted data FAB <n>The comparison error caused by the error further ensures the accuracy of the comparison result. <n>Take an error as an example, if the first inverted data RAB <n>Errors may result in the first inverted data RAB <n>and the first data RA <n>Both are 1 or both are 0. In this case, compare the first inverted data RAB <n>With the second data FA <n>The result cannot truly reflect the first data RA <n>With the second data FA <n>but in this case, further compare the first data RA <n>With the second inverted data FAB <n>, the first data RA <n>With the second inverted data FAB <n>The result can truly reflect the first data RA <n>With the second data FA <n>In this way, the accuracy of the comparison result can be improved.

[0103] Figure 8 Schematic diagram of a circuit structure of a first comparison circuit and a second comparison circuit. Figure 8 The first comparison circuit 201 may include: a first NMOS tube MN1, a drain connected to the feedback node netr, and a gate receiving the first data RA <n>The second NMOS tube MN2, the drain is connected to the source of the first NMOS tube MN1, and the gate receives the second inverted data FAB <n>, the source is connected to the ground terminal gnd; the second comparison circuit 202 may include: a third NMOS tube MN3, the drain is connected to the feedback node netr, and the gate receives the first inverted data RAB <n>The fourth NMOS tube MN4, the drain is connected to the source of the third NMOS tube, and the gate receives the second data FA <n>, the source is connected to the ground GND.

[0104] The drain of the first NMOS transistor MN1 and the drain of the third NMOS transistor MN3 are connected to the feedback node netr via the comparison terminal Compare, and the source of the second NMOS transistor MN2 and the source of the fourth NMOS transistor MN4 can be connected to the ground terminal GND via the ground terminal gnd.

[0105] If the first data RA <n>With the second data FA <n>If both are 0, the first inverted data RAB <n>And the second inverted data FAB <n>are all 1. Accordingly, the first NMOS transistor MN1 is turned off and the second NMOS transistor MN2 is turned on, and the first comparison circuit 201 is turned off; the third NMOS transistor MN3 is turned on and the fourth NMOS transistor MN4 is turned off, and the second comparison circuit 202 is turned off. Therefore, the sub-transmission path between the feedback node netr and the ground terminal GND is turned off, and the level of the feedback node netr can be maintained at the first level.

[0106] If the first data RA <n>With the second data FA <n>If both are 1, the first inverted data RAB <n>And the second inverted data FAB <n>are all 0. Accordingly, the first NMOS transistor MN1 is turned on and the second NMOS transistor MN2 is turned off, and the first comparison circuit 201 is turned off; the third NMOS transistor MN3 is turned off and the fourth NMOS transistor MN4 is turned on, and the second comparison circuit 202 is turned off. Therefore, the sub-transmission path between the feedback node netr and the ground terminal GND is turned off, and the level of the feedback node netr can be maintained at the first level.

[0107] If the first data RA <n>is 1 and the second data FA <n>If it is 0, the first inverted data RAB <n>is 0 and the second inverted data FAB <n>is 1. Accordingly, the first NMOS transistor MN1 and the second NMOS transistor MN2 are both turned on, and the first comparison circuit 201 is turned on; the third NMOS transistor MN3 and the fourth NMOS transistor MN4 are both turned off, and the second comparison circuit 202 is turned off. Since the first comparison circuit 201 is turned on, the sub-transmission path between the feedback node netr and the ground terminal GND is turned on, and the level of the feedback node netr can be pulled down from the first level to the second level.

[0108] If the first data RA <n>is 0 and the second data FA <n>is 1, the first inverted data RAB <n>is 1 and the second inverted data FAB <n>is 0. Accordingly, the first NMOS transistor MN1 and the second NMOS transistor MN2 are both turned off, and the first comparison circuit 201 is turned off; the third NMOS transistor MN3 and the fourth NMOS transistor MN4 are both turned on, and the second comparison circuit 202 is turned on. Since the second comparison circuit 202 is turned on, the transmission path between the feedback node netr and the ground is turned on, and the level of the feedback node netr can be pulled down from the first level to the second level.

[0109] In the above-mentioned first comparison circuit 201 and second comparison circuit 202, De Morgan's law is used to construct the first comparison circuit 201 and second comparison circuit 202. Four NMOS tubes can constitute the above-mentioned first comparison circuit 201 and second comparison circuit 202, which is beneficial to reduce circuit resource occupation and circuit area.

[0110] It can be understood that, for the solution in which the detection module 112 only includes the first comparison circuit, the first comparison circuit is composed of the first NMOS tube and the second NMOS tube; for the solution in which the detection module 112 only includes the second comparison circuit, the second comparison circuit is composed of the third NMOS tube and the fourth NMOS tube.

[0111] Fig. 9 is another functional block diagram of the detection module 112. Fig. 9 The detection module 112 may further include: a latch 203, receiving a second data FA <n>, and output the second inverted data FAB <n>.

[0112] That is, the latch 203 is used to generate the second inverted address based on the second address. It should be noted that, in some examples, if the register can provide both the second address and the second inverted address, the detection module 112 does not need to set a latch.

[0113] Fig.10 This is a schematic diagram of a latch circuit structure. Fig.10 The latch 203 may include: a first trigger 21, the first trigger 21 receives the second data FA <n>, and outputs the second data FA via the output terminal n1 in response to the clock signal CK <n>; The first inverter 22, the input end of the first inverter 22 receives the second data FA <n>The output terminal n2 outputs the second inverted data FAB <n>The clock-controlled inverter 23 is connected between the output terminal n1 of the first flip-flop 21 and the output terminal n2 of the first inverter 22, and is turned on in response to the clock signal CK.

[0114] The first trigger 21 may have a first clock trigger terminal and a second clock trigger terminal, the first clock trigger terminal receives the inverted clock signal CKB, and the second clock trigger terminal receives the clock signal CK. When the clock signal CK is 0, i.e., a low level, the input terminal of the first trigger 21 and the output terminal n1 are cut off, and when the clock signal CK is 1, i.e., a high level, the input terminal of the first trigger 21 and the output terminal n1 are connected, and the output terminal n1 outputs the second data FA <n>The second data FA <n>After being inverted by the first inverter 22, the second inverted data FAB is outputted. <n>.

[0115] in addition, Fig.10 A specific circuit structure diagram of the clock control inverter 23 is also shown. Fig.10 The clock-controlled inverter 23 may include: a first sub-PMOS tube M1, whose source is connected to the working power supply VDD, and whose gate receives the clock signal CK; a second sub-PMOS tube M2, whose source is connected to the drain of the first sub-PMOS tube M1; a third sub-NMOS tube M3, whose gate is connected to the gate of the second sub-PMOS tube M2 and connected to the output terminal n2 of the first inverter 22, and whose drain is connected to the drain of the second sub-PMOS tube M2 and connected to the output terminal n1 of the first trigger 21; a fourth sub-NMOS tube M4, whose drain is connected to the source of the third sub-NMOS tube M4, whose gate receives the inverted clock signal CKB, and whose source is connected to the preset voltage VSS, wherein the preset voltage VSS may be a ground voltage.

[0116] The output terminal n2 of the first inverter 22 is connected to the input terminal of the clock-controlled inverter 23, and the output terminal n1 of the first trigger 21 is connected to the output terminal of the clock-controlled inverter 23. The clock-controlled inverter 23 may have a third clock trigger terminal and a fourth clock trigger terminal, the third clock trigger terminal receives the clock signal CK, and the fourth clock trigger terminal receives the inverted clock signal CKB. When the clock signal CK is 0, that is, a low level, the input terminal and the output terminal of the clock-controlled inverter 23 are connected, that is, the clock-controlled inverter 23 is turned on; when the clock signal CK is 1, that is, a high level period, the input terminal and the output terminal of the clock-controlled inverter 23 are cut off, that is, the clock-controlled inverter 23 is cut off.

[0117] Fig.11 is a schematic diagram of a circuit structure of the detection module 112, referring to Fig.11 The first comparison circuit 201 receives the second inverted data FAB outputted from the output terminal of the first inverter 22. <n>, and the second comparison circuit 202 receives the second data FA outputted from the output terminal of the first trigger 21 <n>Since the second data FA received by the second comparison circuit 202 <n>The second data FA is not directly from the register, but is triggered and output by the first trigger 21. <n>, which is helpful to reduce the detection module 112 receiving the second data FA <n>And the second inverted data FAB <n>and reduce the delay between the detection module 112 receiving the first inverted data RAB <n>With the second data FA <n>The delay between the detection module 112 and the first inverted data RAB is increased. <n>With the second data FA <n>duration, and avoid comparing the first data RA <n>With the second data FA <n>The problem of bit misalignment between the two data sets is beneficial to further improve the accuracy of the comparison results.

[0118] Fig.12 Schematic diagram of a circuit structure of the first switch module. Fig.12 The first switch module 122 may include: a fifth NMOS transistor MN5, a drain of the fifth NMOS transistor MN5 is connected to the ground terminal gnd, a gate receives an enable signal RFUET_EN, and a source is connected to the ground terminal GND.

[0119] When the enable signal RFUET_EN is valid, the enable signal RFUET_EN is 1, and the fifth NMOS transistor MN5 is turned on to connect the ground terminal gnd to the ground terminal GND. When the enable signal RFUET_EN is invalid, the enable signal RFUET_EN is 0, so that the fifth NMOS transistor MN5 is turned off, and the ground terminal gnd is disconnected from the ground terminal GND.

[0120] Fig.13 Another functional block diagram of the address comparison circuit.

[0121] refer to Fig.13 The detection circuit 102 may further include: a second switch module 132, connected between the ground terminal gnd and the feedback node netr of each detection module 112, and configured to be turned on in response to the invalid control command Master to conduct between the feedback node netr and the ground terminal gnd.

[0122] Among them, the second switch module 132 receives the inverted signal MasterB of the control command, and the inverted signal MasterB of the control command is identified as MasterB. During the period when the control command Master is valid, it means that the first address RA[N-1:0] needs to be compared with the second address FA[N-1:0]. During the period when the control command Master is invalid, it means that the first address RA[N-1:0] does not need to be compared with the second address FA[N-1:0]. In some examples, the control command Master is valid when it is 1, and invalid when it is 0. It can be understood that in some examples, it can also be designed as: the control command Master is valid when it is 0, and invalid when it is 1.

[0123] The second switch module 132 is further configured to be turned off in response to a valid control command Master, so that during the period when the control command Master is valid, the second switch module 132 will not affect the level of the feedback node netr. The second switch module 132 is set so that during the period when the control command Master is invalid, that is, during the period when the first address RA[N-1:0] and the second address FA[N-1:0] are not required to be compared, the second switch module 132 is turned on so that the feedback node netr is connected to the ground terminal gnd via the second switch module 132, thereby reducing the level of the feedback node netr, so as to further reduce the power consumption of the address comparison circuit.

[0124] like Fig.13 As shown, a first switch module 122 is further arranged between the ground terminal gnd and the ground terminal GND. During the period when the control command Master is invalid and the enable signal RFUET_EN is invalid, the first switch module 122 is turned off and the second switch module 132 is turned on. Since the ground terminal gnd is disconnected from the ground terminal, the level of the feedback node netr will be pulled down but higher than the second level. The advantages of such a setting include: although the level of the feedback node netr is pulled down, compared with the solution in which the level of the feedback node netr is pulled down to the second level, since the first switch module 122 is turned off, the level of the feedback node netr will be higher than the second level; in this way, after the control command Master changes from invalid to valid, the level of the feedback node netr will be more easily pulled up to the first level again, which can reduce the time required for the level of the feedback node netr to be reset to the first level, thereby further shortening the time required for comparing the first address and the second address.

[0125] Continue to refer Fig.13 The second switch module 132 may include: a sixth NMOS transistor MN6, a gate of the sixth NMOS transistor MN6 receives an inverted signal MasterB of a control command, a drain connected to a feedback node netr, and a source connected to a ground terminal gnd.

[0126] In some examples, if the control command Master is valid, the control command Master is 1, the inverted signal MasterB of the control command is 0, and the sixth NMOS tube MN6 is cut off, which will not affect the level of the feedback node netr; if the control command Master is invalid, the control command Master is 0, the inverted signal MasterB of the control command is 1, the sixth NMOS tube MN6 is turned on, and the feedback node netr is connected to the ground terminal gnd via the sixth NMOS tube MN6, thereby reducing the level of the feedback node netr.

[0127] Fig.14 for Fig.13 The corresponding timing diagram of each signal in the address comparison circuit and the level change diagram of the feedback node netr, where: Fig.14 In the figure, ADD1 is used to indicate the consistent first address and second address, and ADD1 and ADD2 are used to indicate the inconsistent first address and second address, respectively. For simplicity, Fig.14 The control signals mentioned later are also shown. Fig.13 and Fig.14 , the working principle of the address comparison circuit is explained:

[0128] During the period from the first period T1 to the fourth period T4 when the control command Master is always invalid, the second switch module 132 is turned on in response to the inverted signal MasterB of the control command:

[0129] In the first period T1, the activation command ACT is invalid, the enable signal RFUET_EN is invalid, the first switch module 122 is turned off, and the ground terminal gnd is disconnected from the ground terminal GND. At this time, the level of the feedback node netr is lower than the first level and higher than the second level. This state can be recorded as an invalid state.

[0130] In the second period T2, the activation command ACT is valid, and the detection circuit 102 receives the first address RA[N-1:0] and the second address FA[N-1:0]; the enable signal RFUET_EN is delayed compared to the activation command ACT, so the enable signal RFUET_EN becomes valid only after the activation command ACT is valid, the first switch module 122 is turned on, and the ground terminal gnd is conductively connected to the ground terminal. At this time, the feedback node netr is connected to the ground terminal, so that the level of the feedback node netr is pulled down to the second level, that is, the level of the feedback node netr is pulled down to 0, and the output node OUT is high level, that is, "1".

[0131] The third period T3 is similar to the first period T1, both are invalid periods of the activation command ACT; the fourth period T4 is similar to the second period T2, both are valid periods of the activation command ACT. Take the first address RA[N-1:0] and the second address FA[N-1:0] actually received in the second period T2 as an example, that is, they are both ADD1, and the feedback node netr is always 0; take the first address RA[N-1:0] and the second address FA[N-1:0] actually received in the fourth period T4 as an example, that is, they are not the same, that is, they are ADD1 and ADD2, respectively, and the feedback node netr is also always 0, and the output node OUT remains "1".

[0132] It can be seen that during the period when the control command Master is invalid, no matter whether the first address RA[N-1:0] and the second address FA[N-1:0] are consistent, the levels of the feedback node netr and the output node OUT are not affected by whether the addresses are consistent.

[0133] During the period from the fifth period T5 to the eighth period T8 when the control command Master is always valid, that is, the first address needs to be compared with the second address FA[N-1:0], the second switch module 132 is turned off in response to the inverted signal MasterB of the control command:

[0134] In the fifth period T5: the activation command ACT is invalid and the enable signal RFUET_EN is invalid, the first switch module 122 is turned off, and the ground terminal gnd is disconnected from the ground terminal; the control command Master is valid, and the level of the feedback node netr is reset to the first level, that is, the feedback node netr is 1, and the corresponding output node OUT is 0.

[0135] In the sixth period T6, the activation command ACT is valid, and the detection circuit 102 receives the first address RA[N-1:0] and the second address FA[N-1:0]; and the enable signal RFUET_EN is delayed compared to the activation command ACT, so the enable signal RFUET_EN becomes valid only after the activation command ACT is valid, the first switch module 122 is turned on, and the ground terminal gnd is connected to the ground terminal; the first address RA[N-1:0] is inconsistent with the second address FA[N-1:0], then the level of the feedback node netr is pulled down from the first level to the second level, that is, the feedback node netr becomes 0, and the corresponding output node OUT is "1". This level change of the feedback node netr indicates that the first address RA[N-1:0] is inconsistent with the second address FA[N-1:0], and the address data of the first address RA[N-1:0] and the second address FA[N-1:0] are not fully matched.

[0136] In the sixth period T6, after each detection module 112 has received the corresponding first data and second data, that is, after the detection circuits are ready for the first data and second data for comparison, the first switch module 122 is turned on in response to the enable signal RFUET_EN, so that the time point when the comparison results of all the first data and all the second data affect the feedback node netr can be unified to the turn-on moment of the first switch module 122, and the time point when the comparison results of all the first data and all the second data affect the output node OUT can be unified to the moment when the latch circuit 100 receives the valid enable signal RFUET_EN, so as to avoid the problem of glitches on the feedback node netr caused by the different arrival times of each data in the first address RA[N-1:0] and the second address FA[N-1:0] at the detection circuit 102, thereby improving the signal accuracy of the output node OUT.

[0137] Therefore, in the early stage of the sixth period T6 (ie, during the period when the enable signal RFUET_EN is invalid), the feedback node netr remains at 1, and the feedback node netr changes from 1 to 0 when the enable signal RFUET_EN is valid.

[0138] The seventh period T7 is similar to the fifth period T5 , both periods are periods when the activation command ACT and the enable signal RFUET_EN are invalid, the feedback node netr is reset to the first level, that is, 1, and the output node OUT is 0.

[0139] In the eighth period T8, the activation command ACT is valid, and the detection circuit 102 receives the first address RA[N-1:0] and the second address FA[N-1:0]; and the enable signal RFUET_EN is delayed compared to the activation command ACT, so the enable signal RFUET_EN becomes valid only after the activation command ACT is valid, the first switch module 122 is turned on, and the ground terminal gnd is connected to the ground terminal; the first address RA[N-1:0] and the second address FA[N-1:0] are consistent with each other and are both ADD1, then the level of the feedback node netr remains at the first level, that is, the feedback node netr remains at 1. The first level of the feedback node netr is maintained, indicating that the first address RA[N-1:0] is consistent with the second address FA[N-1:0], and all address data of the first address RA[N-1:0] and the second address FA[N-1:0] are matched.

[0140] For the specific description of the eighth period T8, please refer to the sixth period T6, which will not be repeated below.

[0141] Fig.15 This is another functional block diagram of the address comparison circuit. Fig.15 The reset circuit 101 may include: a control module 111, configured to receive a control command Master and output a control signal RC; a pull-up module 121, connected between a working power supply VDD and a feedback node netr, and configured to, during a period when the control command Master is valid, the pull-up module 121 is turned on in response to the control signal RC to connect the working power supply VDD to the feedback node netr, and during a period when the control command Master is invalid, the pull-up module 121 is turned off in response to the control signal RC.

[0142] In some examples, if the control command Master is valid, the control signal RC is 0, and the pull-up module 121 is turned on; if the control command Master is invalid, the control signal RC is 1, and the pull-up module 121 is turned off.

[0143] Continue to refer Fig.15 The control module 111 may be further configured to receive an inverted signal RFUETB_EN of the enable signal, the control signal RC is generated based on the control command Master and the enable signal RFUET_EN, and when both the enable signal RFUET_EN and the control command Master are valid, the pull-up module 121 is turned off in response to the control signal RC.

[0144] Among them, when the control command Master is valid and the enable signal RFUET_EN is invalid, the pull-up module 121 is turned on to connect the feedback node netr to the working power supply VDD; after the control command Master is valid and the enable signal RFUET_EN changes from invalid to valid, the pull-up module 121 is turned off to disconnect the feedback node netr from the working power supply VDD, so as to avoid the working power supply VDD affecting the level of the feedback node netr during the address comparison stage.

[0145] It is understandable that, in some embodiments, the control module 111 may not receive the inverted signal RFUETB_EN of the enable signal, but may receive the inverted signal of the activation command.

[0146] Fig.16 A circuit structure diagram of a reset module.

[0147] refer to Fig.16 The control module 111 may include: a second trigger 31, the second trigger 31 receives the control command Master, and in response to the clock signal CK, outputs the inverted signal MasterB of the control command from the negative output terminal; a second inverter 32, the input terminal of which is connected to the negative output terminal of the second trigger 31; a first NAND gate 33, one input terminal of which is connected to the output terminal of the second inverter 32, the other input terminal of which receives the inverted signal RFUETB_EN of the enable signal, and the output terminal of which outputs the control signal RC.

[0148] The second trigger 31 includes a fifth clock trigger terminal and a sixth clock trigger terminal. The fifth clock trigger terminal receives the inverted clock signal CKB, and the sixth clock trigger terminal receives the clock signal CK.

[0149] During the period when the control command Master is valid, that is, 1, the inverted signal MasterB of the control command is 0, and the output end of the second inverter 32 is 1: if the enable signal RFUET_EN is invalid, that is, 0, the inverted signal RFUETB_EN of the enable signal is 1, the control signal RC is 0, and the pull-up module 121 is turned on; if the enable signal RFUET_EN is valid, that is, 1, the inverted signal RFUETB_EN of the enable signal is 0, the control signal RC is 1, and the pull-up module 121 is turned off.

[0150] When the control command Master is invalid, that is, 0, the inverted signal MasterB of the control command is 1, and the output of the second inverter 32 is 0. Regardless of whether the enable signal RFUET_EN is valid or invalid, the control signal RC is 1, that is, the pull-up module 121 is always turned off.

[0151] Continue to refer Fig.16 The pull-up module 121 may include: a first PMOS tube MP1, a gate receiving a control signal RC, a source connected to a working power supply VDD, and a drain connected to a feedback node netr.

[0152] If the control signal RC is 0, that is, the control signal RC is at a low level, the first PMOS tube MP1 is turned on; if the control signal is 1, that is, the control signal RC is at a high level, the first PMOS tube MP1 is turned off.

[0153] Fig.17 A specific circuit structure diagram of the address comparison circuit provided in the embodiment of the present disclosure is shown below. Fig.14 and Fig.17 Explain the working principle of the address comparison circuit:

[0154] During the period when the control command Master is invalid and the activation command ACT is invalid, that is, the first period T1 and the third period T3, the control command Master, the activation command ACT and the enable signal RFUET_EN are all 0, the inverted signal MasterB of the control command and the inverted signal RFUETB_EN of the enable signal are both 1, the control signal RC outputted from the output end of the first NAND gate 33 is 1, the first PMOS tube MP1 is turned off, and the feedback node netr will not be reset to the first level; the sixth NMOS tube MN6 is turned on and the fifth NMOS tube MN5 is turned off, and the level of the feedback node netr is between the first level and the second level, which is recorded as an invalid state.

[0155] During the period when the control command Master is invalid and the activation command ACT is valid, that is, the second period T2 and the fourth period T4, the control command Master is 0 and the activation command ACT is 1, the enable signal RFUET_EN becomes 1 later than the activation command ACT, the inverted signal MasterB of the control command is 1, the inverted signal ACTB of the activation command is 0, and the inverted signal RFUETB_EN of the enable signal becomes 0 later than the inverted signal ACTB of the activation command. The control signal RC outputted from the output end of the first NAND gate 33 is 1, the first PMOS tube MP1 is turned off, and the feedback node netr is not reset to the first level; the sixth NMOS tube MN6 and the fifth NMOS tube MN5 are turned on, and the level of the feedback node netr is pulled down to the second level, that is, the feedback node netr becomes 0.

[0156] That is to say, when the inverted signal MasterB of the control command is 1, the first PMOS tube MP1 will not be turned on, and the level of the feedback node netr will not be reset to the first level.

[0157] When the control command Master is 1, the inverted signal MasterB of the control command is 0, and the activation command ACT is 0, that is, the fifth period T5 and the seventh period T7, it means that the preparation work before the comparison between the first address RA[N-1:0] and the second address FA[N-1:0] will be performed. At this time, the control signal RC outputted from the output end of the first NAND gate 33 is 0, the first PMOS tube MP1 is turned on, the level of the feedback node netr is the first level, that is, the feedback node netr is 1, and the output node OUT is 0; at the same time, the sixth NMOS tube MN6 is turned off and the fifth NMOS tube MN5 is turned off. Correspondingly, the feedback node netr will remain at 1, and the output node is 0.

[0158] When the control command Master is 1, the inverted signal MasterB of the control command is 0, and the activation command ACT is 1, that is, the sixth period T6 and the eighth period T8, it indicates that the comparison stage of the first address RA[N-1:0] and the second address FA[N-1:0] has begun. At this time, the control signal RC outputted from the output end of the first NAND gate 33 is 1, the first PMOS transistor MP1 is turned off, the sixth NMOS transistor MN6 is turned off, and the fifth NMOS transistor MN5 is turned on. According to the comparison result, there are the following two situations:

[0159] In the sixth period T6, at least one detection module 112 is turned on, that is, at least one first data is different from the second data, then the transmission path between the feedback node netr and the ground is turned on, and the level of the feedback node netr is pulled down from the first level to the second level, the second level is the level of the ground, and accordingly, the feedback node netr changes from 1 to 0, indicating that the first address RA[N-1:0] is inconsistent with the second address FA[N-1:0]. Since the feedback node netr is 0, the output end of the latch NAND gate 1031 is 1, and the latch PMOS tube 1032 will not be turned on.

[0160] In the eighth period T8, all detection modules 112 are not turned on, that is, the transmission paths between the feedback node netr and the ground are cut off, and the level of the feedback node netr will be maintained at the first level, that is, the feedback node netr is maintained at 1, indicating that the first address RA[N-1:0] is consistent with the second address FA[N-1:0]. In addition, since both input terminals of the latch NAND gate 1031 are 1, the output terminal of the latch NAND gate 1031 is 0, and the latch PMOS tube 1032 is turned on, so that the feedback node netr is connected to the working power supply VDD, further ensuring that the level of the feedback node netr is maintained at the first level.

[0161] In addition, since the enable signal RFUET_EN received at one input end of the latch NAND gate 1031 changes to 1 later than the activation command ACT, before the enable signal RFUET_EN changes to 1, even if the detection circuit 102 compares the address of part of the first address RA[N-1:0] and part of the second address FA[N-1:0], the comparison result will not affect the level of the output node OUT, until the enable signal RFUET_EN received at one input end of the latch NAND gate 1031 changes to 1, the signal level of the output node OUT will change with the signal level of the feedback node netr. Therefore, after the detection circuit 102 completes the comparison of all data in the first address RA[N-1:0] and the second address FA[N-1:0], the signal level of the output node OUT will change with the comparison result, so that the signal of the output node OUT can more accurately represent the comparison result, avoiding the burr problem caused by different data arrival times or different comparison speeds of different detection modules 112.

[0162] The address comparison circuit provided in the above embodiment includes a reset circuit 101 and a detection circuit 102. The reset circuit 101 is used to reset the level of the feedback node netr to the first level in response to the effective control command Master; the detection circuit 102 is used to detect whether the first address RA[N-1:0] and the second address FA[N-1:0] are consistent. If the first address RA[N-1:0] and the second address FA[N-1:0] are inconsistent, the transmission path between the feedback node netr and the ground end is turned on, so that the level of the feedback node netr is pulled down from the first level to the second level. If the first address RA[N-1:0] and the second address FA[N-1:0] are consistent, the transmission path between the feedback node netr and the ground end is cut off, and the level of the feedback node netr is maintained at the first level. Therefore, by monitoring the level of the feedback node netr in the address comparison stage, it can be known whether the first address RA and the second address FA are consistent.

[0163] The address comparison circuit has a simple circuit structure, which can not only reduce the area occupied by the circuit, but also reduce the transmission delay of the address comparison circuit and improve the address comparison efficiency.

[0164] In addition, in the above embodiment, the detection circuit 102 includes a plurality of detection modules 112, each detection module 112 is used to detect whether a first data bit in the first address and a second data bit in the second address are the same, and all the detection modules 112 are connected in parallel between the feedback node netr and the ground terminal GND, so that the comparison result of each first data and the second data is output in parallel, and there is no need to comprehensively compare the comparison result of each data with the second data again, thereby further reducing the comparison transmission delay.

[0165] Even if different first data and different second data arrive at the corresponding detection module 112 at different arrival times, or different detection modules 112 have different conduction times, in the address comparison stage, the signal of the feedback node netr may be subject to fluctuations and produce glitches, which may cause the problem of wrong address comparison result judgment. In the embodiment of the present disclosure, the latch circuit 100 is operated by the enable signal RFUET_EN obtained by delaying the activation command ACT, so that before the latch circuit 100 responds to the effective enable signal RFUET_EN, the detection circuit 102 has completed the comparison of each data. Therefore, during the period when the enable signal RFUET_EN is effective, the signal of the output node OUT no longer faces the glitches caused by the different arrival times and / or different conduction times mentioned above, so the result of the address comparison can be accurately judged by the change of the signal level of the output node OUT.

[0166] In addition, the reset circuit 101 is independent of the detection circuit 102, and the level of the feedback node netr is reset by the reset circuit 101, that is, in the preparation stage of address comparison (that is, the activation command ACT is invalid and the control command Master is valid), the level of the feedback node netr is reset to the first level by the reset circuit 101, which is conducive to further reducing the comparison transmission delay. And in the stage of address comparison (that is, the activation command ACT is valid and the control command Master is valid), the reset circuit 101 will not affect the level of the feedback node netr, so that the level of the feedback node netr is only affected by the comparison result of the detection circuit 102.

[0167] Fig.18 Another circuit diagram of the address comparison circuit provided in the embodiment of the present disclosure, Fig.18 The circuit shown is roughly the same as above, the main difference is that Fig.18 In the embodiment, the ground terminal gnd of each detection module 112 is directly connected to the ground terminal GND, and each first switch module 122 is connected between each detection module 112 and the feedback node netr. The first switch module 122 is controlled by the enable signal RFUET_ENK. When the enable signal RFUET_ENK is valid, the first switch module 122 is turned on. To avoid redundancy, the description of the rest of the parts other than the first switch module 122 can refer to the aforementioned detailed description.

[0168] Similarly, before the first switch module 122 is turned on, each detection module 112 has received the corresponding first data and second data, and completed the comparison of the first data and the second data. Therefore, after the first switch module 122 is turned on, the comparison result will affect the level of the feedback node netr, thereby reducing the burr of the feedback node netr, so that the signal of the feedback node netr can more accurately represent the comparison result.

[0169] Accordingly, the embodiment of the present disclosure also provides a storage system, including the address comparison circuit provided in the above embodiment. The storage system will be described below. It should be noted that the address comparison circuit described in the above embodiment is applicable to the following storage system. To avoid repetition, the parts that are the same or corresponding to the above embodiment will not be described in detail below.

[0170] The memory system may be a random access memory system (RAM), a read-only memory system (ROM), a dynamic random access memory system (DRAM), a synchronous dynamic random access memory system (SDRAM), a resistive random access memory system (RRAM), a double data rate memory system (DDR), a low power double data rate memory system (LPDDR), a phase change memory system (PCM) or a flash memory system.

[0171] From the above analysis, it can be seen that the address comparison circuit in the storage system has a simple circuit structure, which can not only improve the accuracy of the comparison result, but also reduce the circuit area occupied, reduce the circuit complexity, and reduce the transmission delay of the address comparison.

[0172] It should be noted that, unless otherwise specified, "1" in the embodiments of the present disclosure refers to a high signal level, and "0" refers to a low signal level, and the embodiments of the present disclosure do not limit the specific level values ​​of the high level and the low level.

[0173] Those skilled in the art can understand that the above-mentioned embodiments are specific examples for implementing the present disclosure, and in practical applications, various changes can be made to them in form and detail without departing from the spirit and scope of the embodiments of the present disclosure. Any person skilled in the art can make their own changes and modifications without departing from the spirit and scope of the embodiments of the present disclosure, so the protection scope of the embodiments of the present disclosure shall be based on the scope defined in the claims.< / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n>

Claims

1. An address comparison circuit, characterized in that: include: A delay circuit is configured to receive an activation command and perform a delay operation to generate and output an enable signal; A reset circuit having a feedback node, configured to receive a control command, and in response to a valid control command, adjust a level of the feedback node to a first level before receiving a valid enable signal; a detection circuit connected between the feedback node and the ground terminal, configured to receive a first address and a second address, compare the first address with the second address, and select whether to conduct a transmission path between the feedback node and the ground terminal based on the comparison result of the first address with the second address during the validity period of the enable signal; Wherein, when the enable signal is valid, the first address and the second address have both been received by the detection circuit, and if the first address is inconsistent with the second address, the transmission path is turned on to adjust the level of the feedback node to a second level, and the level value of the second level is less than the level value of the first level; If the first address is consistent with the second address, the transmission path is cut off so that the level of the feedback node is maintained at the first level.

2. The address comparison circuit according to claim 1, characterized in that: The first address includes N-bit first data, and the second address includes N-bit second data; the delay circuit is configured so that when the enable signal is valid, all the first data and the second data have been received by the detection circuit.

3. The address comparison circuit according to claim 1, characterized in that: The delay circuit includes: an even number of cascaded first sub-inverters, the input end of the first sub-inverter at the first position receives the activation command, and the output end of the first sub-inverter at the last position outputs the enable signal.

4. The address comparison circuit according to claim 1, characterized in that: The delay circuit comprises: An even number of cascaded second sub-inverters, the input end of the first second sub-inverter receiving the activation command; A first sub-PMOS tube, wherein the source of the first sub-PMOS tube is connected to the working power supply, and the gate is connected to the output end of the second sub-inverter at the tail position; A second sub-NMOS transistor, wherein the gate of the second sub-NMOS transistor is connected to the output end of the second sub-inverter at the tail position, and the source of the second sub-NMOS transistor is connected to the ground end; A plurality of third sub-NMOS tubes connected in series between the first sub-PMOS tube and the second sub-NMOS tube, wherein the gate of each of the third sub-NMOS tubes is connected to a working power supply, the drain of one of the third sub-NMOS tubes is connected to the drain of the first sub-PMOS tube, and the source of another of the third sub-NMOS tubes is connected to the drain of the second sub-NMOS tube; The third sub-inverter has an input end connected to the drain of the first sub-PMOS tube and an output end outputting the enable signal.

5. The address comparison circuit according to claim 1, characterized in that: The address comparison circuit also includes: a latch circuit, connected to the feedback node, configured to receive the enable signal, and if the first address is consistent with the second address during the validity period of the enable signal, latch the signal of the feedback node and output a detection signal via an output node, the detection signal and the signal of the feedback node are in an inverse relationship with each other.

6. The address comparison circuit according to claim 5, characterized in that: The latch circuit comprises: A latched NAND gate, one input end of which is connected to the feedback node, and the other input end of which receives the enable signal; A latch PMOS tube, with a gate connected to the output end of the latch NAND gate, a source connected to a working power supply, and a drain connected to the feedback node.

7. The address comparison circuit according to claim 1, wherein: The first address includes N-bit first data, and the second address includes N-bit second data; the detection circuit includes: N detection modules, each of which is connected between the feedback node and the ground terminal to form a sub-transmission path connecting the feedback node and the ground terminal, and each of which is configured to receive a first data and a corresponding second data, and compare the first data with the second data. If the first data is different from the second data, the sub-transmission path is turned on; if the first data is the same as the second data, the sub-transmission path is turned off.

8. The address comparison circuit according to claim 7, characterized in that: The detection module comprises: a first comparison circuit connected between the feedback node and the ground terminal, and configured to receive the first data and the second inverted data, and if the first data is the same as the second inverted data, the sub-transmission path is turned on, and if the first data is different from the second inverted data, the sub-transmission path is turned off; and / or, a second comparison circuit, connected between the feedback node and the ground terminal, configured to receive the first inverted data and the second data, and if the first inverted data is the same as the second data, the sub-transmission path is turned on, and if the first inverted data is different from the second data, the sub-transmission path is turned off; The first inverted data is the inverted code of the first data, and the second inverted data is the inverted code of the second data.

9. The address comparison circuit according to claim 8, characterized in that: The first comparison circuit comprises: A first NMOS tube, a drain of which is connected to the feedback node, and a gate of which receives the first data; A second NMOS tube, wherein the drain is connected to the source of the first NMOS tube, the gate receives the second inverted data, and the source is connected to the ground terminal; The second comparison circuit comprises: A third NMOS tube, a drain of which is connected to the feedback node, and a gate of which receives the first inverted data; A fourth NMOS tube has a drain connected to the source of the third NMOS tube, a gate receiving the second data, and a source connected to the ground.

10. The address comparison circuit according to claim 7, characterized in that: Each of the detection modules has a ground terminal; the detection circuit also includes: The first switch module is connected between the ground terminal and the ground terminal of each detection module, and is configured to be turned on in response to the valid enable signal to enable conduction between the ground terminal and the ground terminal. If the activation command is invalid, the first switch module is turned off to disconnect the ground terminal and the ground terminal.

11. The address comparison circuit according to claim 10, characterized in that: The first switch module comprises: A fifth NMOS tube, wherein a drain of the fifth NMOS tube is connected to the ground terminal, a gate receives the enable signal, and a source is connected to the ground terminal.

12. The address comparison circuit according to claim 1, wherein: The reset circuit comprises: A control module is configured to receive the control command and output a control signal; The pull-up module is connected between the working power supply and the feedback node, and is configured such that, during the period when the control command is valid, the pull-up module is turned on in response to the control signal to connect the working power supply to the feedback node, and during the period when the control command is invalid, the pull-up module is turned off in response to the control signal.

13. The address comparison circuit according to claim 12, wherein: The control module is further configured to receive an inverted signal of an enable signal, wherein the control signal is generated based on the control command and the enable signal, and when both the enable signal and the control command are valid, the pull-up module is turned off in response to the control signal.

14. The address comparison circuit according to claim 12, wherein: The pull-up module comprises: The first PMOS tube has a gate receiving the control signal, a source connected to the working power supply, and a drain connected to the feedback node.

15. A storage system, characterized in that: include: An address comparison circuit as claimed in any one of claims 1 to 14.

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