8T-SRAM storage computing unit, in-memory computing array and in-memory computing circuit

Abstract

The present application relates to an 8T-SRAM storage and calculation unit, an in-memory calculation array and an in-memory calculation circuit, wherein the in-memory calculation array includes: a cell array and a bipolar calculation unit distributed in rows, the cell array includes a plurality of 8T-SRAM storage and calculation units distributed in rows, the bipolar calculation unit includes a first inverter, a second inverter, a seventh NMOS tube, an eighth NMOS tube, a ninth NMOS tube, a tenth NMOS tube, a first capacitor and a second capacitor, the output end of the first inverter is connected to the input end of the second inverter, the gate, the drain and the source of the seventh NMOS tube are respectively connected to the output end of the first inverter, the upper plate of the first capacitor and the drain of the eighth NMOS tube, the gate, the drain and the source of the ninth NMOS tube are respectively connected to the output end of the second inverter, the upper plate of the second capacitor and the drain of the tenth NMOS tube, and the first capacitor and the second capacitor are also respectively connected to the first calculation bit line and the second calculation bit line.

Description

Technical Field

[0001] The present application relates to the field of integrated circuits, and in particular to an 8T-SRAM storage computing unit, an in-memory computing array, and an in-memory computing circuit. Background Art

[0002] Convolutional Neural Network (CNN) is the foundation of current AI applications. Since CNN has achieved breakthrough applications in speech recognition, image recognition, and the Internet of Things, the application scenarios of CNN have exploded. The core operation of a convolutional neural network is to implement the convolution operation of the activation value and the convolution kernel, which is mapped to the circuit level to implement the multiply-and-accumulation (MAC) operation of the input and the pre-trained weights. When traditional all-digital AI edge processors based on the von Neumann architecture perform MAC operations, a large amount of energy overhead and delay will be generated due to the movement of data between the processing unit and the memory, which hinders the further improvement of chip performance. Figure 1 As shown in (a), this problem is called the "memory wall".

[0003] Compute in Memory (CIM) is a method to overcome the "memory wall" problem and improve energy efficiency by allowing parallel data processing within the memory module. This advantage is particularly evident when performing multi-bit MAC operations, such as Figure 1 In addition, CNN has high requirements for memory capacity and large resource overhead, and is not suitable for edge device applications. The Binary Weight Network (BWN) greatly improves the energy efficiency of the network by binarizing the weights in the MAC process at the expense of a small degree of accuracy. Therefore, BWN has become one of the most promising neural networks in edge devices.

[0004] Analog CIM operations are performed in SRAM bit cells (i.e., multiplication) and a column or row of bit cells connected to bit lines (BLs) to perform calculations in the memory array. Positive and negative calculations correspond to charging and discharging the same bit line. PMOS tubes are used for charging and NMOS tubes are used for discharging. There are differences in the processes of the two types of MOS tubes, so there will be inconsistent charging and discharging. Specifically, analog CIM has high energy and area efficiency, but it is affected by various analog non-idealities. CIM macros in the voltage domain form are affected by inconsistent charging and discharging rates caused by factors such as threshold loss and different carrier mobilities, resulting in inaccurate calculation results.

[0005] There is no effective solution to the problem that the existing SRAM memory calculation circuit has inconsistent charging and discharging rates during positive and negative calculations, resulting in inaccurate calculation results. Summary of the invention

[0006] The present invention provides an 8T-SRAM storage calculation unit, an in-memory calculation array and an in-memory calculation circuit to solve the problem that the existing SRAM in-memory calculation circuit has inconsistent charging and discharging rates during positive and negative calculations, resulting in inaccurate calculation results.

[0007] In a first aspect, the present invention provides an in-memory computing array, comprising a row-distributed cell array and a bipolar computing unit, wherein the cell array comprises a plurality of row-distributed 8T-SRAM memory computing units;

[0008] Each of the 8T-SRAM storage and calculation units includes a 6T-SRAM storage and calculation structure, a fifth NMOS tube and a sixth NMOS tube, the source and gate of the fifth NMOS tube are respectively connected to the first storage node and the first symbol input word line of the 6T-SRAM storage and calculation structure, the source and gate of the sixth NMOS tube are respectively connected to the second storage node and the second symbol input word line of the 6T-SRAM storage and calculation structure, and the drain of the fifth NMOS tube is connected to the drain of the sixth NMOS tube and forms a judgment node;

[0009] The bipolar calculation unit includes a first inverter, a second inverter, a seventh NMOS tube, an eighth NMOS tube, a ninth NMOS tube, a tenth NMOS tube, a first capacitor and a second capacitor. The output end of the first inverter is connected to the input end of the second inverter. The gate, drain and source of the seventh NMOS tube are respectively connected to the output end of the first inverter, the upper plate of the first capacitor and the drain of the eighth NMOS tube. The gate, drain and source of the ninth NMOS tube are respectively connected to the output end of the second inverter, the upper plate of the second capacitor and the drain of the tenth NMOS tube. The first capacitor and the second capacitor are also connected to the first calculation bit line and the second calculation bit line respectively. The lower plates of the first capacitor and the second capacitor are both grounded. The gates of the eighth NMOS tube and the tenth NMOS tube are both connected to the numerical input word line. The drains of the eighth NMOS tube and the tenth NMOS tube are both grounded.

[0010] In each of the cell arrays, a plurality of the determination nodes are connected to the input end of the first inverter through the same determination bit line.

[0011] In a second aspect, the present invention provides an 8T-SRAM storage and computing unit, including a first PMOS tube, a second PMOS tube, a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube and a sixth NMOS tube;

[0012] The gate, source and drain of the first PMOS tube are respectively connected to the gate, power supply voltage and drain of the first NMOS tube, and the source of the first NMOS tube is connected to the power ground; the gate, source and drain of the second PMOS tube are respectively connected to the gate, power supply voltage and drain of the second NMOS tube, and the source of the second NMOS tube is connected to the power ground;

[0013] The gates of the second PMOS transistor and the second NMOS transistor and the drains of the first PMOS transistor and the first NMOS transistor are connected to form a first storage node, and the gates of the first PMOS transistor and the first NMOS transistor and the drains of the second PMOS transistor and the second NMOS transistor are connected to form a second storage node;

[0014] The gate, source and drain of the third NMOS tube are respectively connected to the storage word line, the first storage node and the first bit line, and the gate, source and drain of the fourth NMOS tube are respectively connected to the storage word line, the second storage node and the second bit line;

[0015] The source and gate of the fifth NMOS tube are connected to the first storage node and the first sign input word line INP respectively, the source and gate of the sixth NMOS tube are connected to the second storage node and the second sign input word line INN respectively, and the drain of the fifth NMOS tube and the drain of the sixth NMOS tube are connected to form a judgment node.

[0016] In the third aspect, the present invention provides an in-memory computing circuit, including a main memory computing array, the main memory computing array includes a pair of main storage modules, each of the main storage modules includes a plurality of sub-storage modules distributed in columns, each of the sub-storage modules includes a plurality of sub-storage computing arrays distributed in rows, a voltage delay converter, a TDC, a counter and a digital subtractor, the sub-storage computing arrays are the in-memory computing arrays described in the first aspect.

[0017] In a fourth aspect, the present invention provides an in-memory computing chip, which integrates the in-memory computing circuit described in the second aspect.

[0018] In a fifth aspect, the present invention provides a static random access memory, comprising the in-memory computing chip described in the third aspect.

[0019] Compared with the related art, the present invention calculates the positive and negative calculation results respectively through the first calculation bit line (negative) and the second calculation bit line (positive). Since the discharge paths of the positive and negative calculation bit lines are completely consistent, the circuit structure is mirrored, and they are controlled by the same numerical input word line, the calculation results are equal in absolute value, and the discharge amount is also completely consistent, so this structure greatly improves the accuracy of MAC operation. Therefore, the problem of inaccurate calculation results caused by inconsistent charging and discharging rates in the existing SRAM memory calculation circuit during positive and negative calculations is solved.

[0020] Details of one or more embodiments of the present application are set forth in the following drawings and description to make other features, objects, and advantages of the present application more readily apparent. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 It is a schematic diagram of the von Neumann architecture and the in-memory computing architecture in the prior art;

[0022] Figure 2 is a schematic diagram of an 8T-SRAM storage and computing unit in some embodiments of the present invention;

[0023] Figure 3 is a schematic diagram of a bipolar computing unit in some embodiments of the present invention;

[0024] Figure 4 is a schematic diagram of a sub-storage module in some embodiments of the present invention;

[0025] Figure 5 is a schematic diagram of an in-memory computing circuit (two columns are used as an example) in some embodiments of the present invention;

[0026] Figure 6 is a flow chart of multiplication and multiplication-accumulation operations of multi-bit input and weights of an in-memory computing circuit in some embodiments of the present invention;

[0027] Figure 7 is the same or functional simulation result of the in-memory computing circuit in some embodiments of the present invention;

[0028] Figure 8 is a product simulation result of an in-memory computing circuit in some embodiments of the present invention;

[0029] Fig. 9 is a MAC simulation result of an in-memory computing circuit in some embodiments of the present invention;

[0030] Fig.10 It is a schematic diagram of the linearity simulation of positive and negative MAC values ​​of the in-memory calculation circuit in some embodiments of the present invention. DETAILED DESCRIPTION

[0031] In order to more clearly understand the purpose, technical solutions and advantages of the present application, the present application is described and illustrated below in conjunction with the accompanying drawings and embodiments.

[0032] Unless otherwise defined, the technical terms or scientific terms involved in this application shall have the general meaning understood by people with general skills in the technical field to which this application belongs. The words "one", "a", "the", "these" and the like in this application do not indicate a quantitative limitation, and they may be singular or plural. The terms "include", "comprise", "have" and any variants thereof involved in this application are intended to cover non-exclusive inclusions; for example, a process, method and system, product or device comprising a series of steps or modules (units) is not limited to the listed steps or modules (units), but may include unlisted steps or modules (units), or may include other steps or modules (units) inherent to these processes, methods, products or devices. The words "connect", "connected", "coupled" and the like involved in this application are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The "multiple" involved in this application refers to two or more. "And / or" describes the association relationship of associated objects, indicating that there may be three relationships, for example, "A and / or B" may mean: A exists alone, A and B exist at the same time, and B exists alone. Generally, the character " / " indicates that the objects associated with each other are in an "or" relationship. The terms "first", "second", "third", etc. in this application are only used to distinguish similar objects and do not represent a specific ordering of the objects.

[0033] In an embodiment of the present invention, an in-memory computing array is provided, which includes a row-distributed cell array and a bipolar computing unit. The cell array includes a plurality of row-distributed 8T-SRAM memory computing units.

[0034] Reference Figure 2 Each 8T-SRAM storage and computing unit includes a 6T-SRAM storage and computing structure, a fifth NMOS tube N5 and a sixth NMOS tube N6. The source and gate of the fifth NMOS tube N5 are respectively connected to the first storage node Q of the 6T-SRAM storage and computing structure and the first symbol input word line INP, the source and gate of the sixth NMOS tube N6 are respectively connected to the second storage node QB of the 6T-SRAM storage and computing structure and the second symbol input word line INN, the drain of the fifth NMOS tube N5 and the drain of the sixth NMOS tube N6 are connected to form a judgment node Judge.

[0035] Among them, the 6T-SRAM storage and computing structure can adopt the traditional 6T-SRAM storage and computing unit.

[0036] In some of the embodiments, the 6T-SRAM storage and computing structure includes a first inverting structure, a second inverting structure, a third NMOS tube N3 and a fourth NMOS tube N4. The first inverting structure and the second inverting structure are inversely cross-coupled to form a first storage node Q and a second storage node QB. The gate, source and drain of the third NMOS tube N3 are respectively connected to the storage and computing word line WL, the first storage node Q and the first bit line BL. The gate, source and drain of the fourth NMOS tube N4 are respectively connected to the storage and computing word line WL, the second storage node QB and the second bit line BLB.

[0037] The first inverting structure includes a first PMOS tube and a first NMOS tube, and the second inverting structure includes a second PMOS tube and a second NMOS tube. The gate, source and drain of the first PMOS tube are respectively connected to the gate, power supply voltage and drain of the first NMOS tube, and the source of the first NMOS tube is connected to the power ground; the gate, source and drain of the second PMOS tube are respectively connected to the gate, power supply voltage and drain of the second NMOS tube, and the source of the second NMOS tube is connected to the power ground.

[0038] The gates of the second PMOS tube and the second NMOS tube and the drains of the first PMOS tube and the first NMOS tube are connected to form a first storage node, and the gates of the first PMOS tube and the first NMOS tube and the drains of the second PMOS tube and the second NMOS tube are connected to form a second storage node.

[0039] For the above 8T-SRAM storage and calculation unit, the 6T-SRAM storage and calculation structure provides basic data reading, writing and holding functions, and the judgment node provides the judgment signal Judge of the logical calculation of the weight data stored in the 6T-SRAM storage and calculation structure and the input data. Specifically:

[0040] Before the write operation, the voltage of the first bit line BL and the second bit line BLB is precharged to VDD. When the external address signal is valid, the 6T-SRAM storage structure to be written is determined by the address decoding circuit, and the written data is sent to the bit line by the write drive circuit. When the third NMOS tube N3 and the fourth NMOS tube N4 are turned on, the data is written into the 6T-SRAM storage structure, and the write operation is completed.

[0041] Before the read operation, the voltage of the first bit line BL and the second bit line BLB is precharged to VDD. When the external address signal is valid, the 6T-SRAM storage structure of the data to be read is determined by the address decoding circuit. When the storage word line WL is at a high level, the first bit line BL and the second bit line BLB have a certain voltage difference. The voltage difference between the first bit line BL and the second bit line BLB is amplified by the sensitive amplifier and the data output drive circuit, so that the data of the 6T-SRAM storage structure is read out, and the read operation is completed.

[0042] Hold operation: When the storage word line WL of the 6T-SRAM storage structure is at a low level, the bit line signal of the 6T-SRAM storage structure is isolated from the storage node. The core of the 6T-SRAM storage structure is a latch structure formed by a pair of inverters, which keeps the first storage node Q and the second storage node QB in a bistable state, and the hold operation is completed.

[0043] Furthermore, the logical function supported by the 8T-SRAM storage and calculation unit is the XOR operation, and the XOR result is represented on the judgment node Judge, which is used as the symbol judgment result to control the next level. The symbol judgment result is expressed as follows:

[0044]

[0045] Here, we take the weight as 1 and the sign input (input by the sign input word line) as 1 as an example. Before the sign calculation starts, the first sign input word line INP and the second sign input word line INN are at a low level, and the fifth NMOS tube N5 and the sixth NMOS tube N6 are not turned on. At the beginning of the sign calculation, the weight is 1, then the first storage node Q=1, and the second storage node QB=0; when the sign input is 1, the first sign input word line INP turns to a high level, and the second sign input word line INN is still at a low level, corresponding to the fifth NMOS tube N5 turning on, the sixth NMOS tube N6 turning off, and the judgment node Judge is charged by the first PMOS tube P1 and the fifth NMOS tube N5 to a high level, so the sign is judged to be positive, and the rest of the calculations are shown in the following table:

[0046] Table 1 Symbol judgment example

[0047]

[0048] As above, this is a detailed description of the 8T-SRAM storage and computing unit.

[0049] Reference Figure 3The bipolar calculation unit includes a first inverter INV1, a second inverter IVN2, a seventh NMOS tube N7, an eighth NMOS tube N8, a ninth NMOS tube N9, a tenth NMOS tube N20, a first capacitor C1 and a second capacitor C2. The output end of the first inverter INV1 is connected to the input end of the second inverter INV2. The gate, drain and source of the seventh NMOS tube N7 are respectively connected to the output end of the first inverter INV1, the upper plate of the first capacitor C1 and the drain of the eighth NMOS tube N8. The ninth NMOS tube The gate, drain and source of N9 are respectively connected to the output end of the second inverter INV2, the upper plate of the second capacitor C2 and the drain of the tenth NMOS tube N10, the first capacitor C1 and the second capacitor C2 are also connected to the first calculation bit line NCC and the second calculation bit line PCC respectively, the lower plates of the first capacitor C1 and the second capacitor C2 are both grounded to VSS, the gates of the eighth NMOS tube N8 and the tenth NMOS tube N10 are both connected to the numerical input word line CEN, and the drains of the eighth NMOS tube N8 and the tenth NMOS tube N10 are both grounded to VSS.

[0050] In each cell array, a plurality of judging nodes Judge are connected to the input end of the first inverter INV1 through the same judging bit line.

[0051] In the above bipolar calculation unit, the positive and negative calculation results are calculated respectively through the first calculation bit line NCC (negative) and the second calculation bit line PCC (positive). Since the discharge paths of the positive and negative calculation bit lines are completely consistent, the circuit structure is mirrored, and they are controlled by the same numerical input word line WL, the calculation results are equal in absolute value, and the discharge amount is also completely consistent. Therefore, this structure greatly improves the accuracy of MAC operation. Therefore, the problem of inaccurate calculation results caused by inconsistent charging and discharging rates in the existing SRAM memory calculation circuit during positive and negative calculations is solved.

[0052] The above-mentioned 8T-SRAM storage and computing unit is used for symbolic calculation in binary weighted neural network, and can complete the convolution calculation of binary weighted neural network in conjunction with the bipolar computing unit.

[0053] Reference Figure 4 and Figure 5In an embodiment of the present invention, an in-memory computing circuit is also provided, including a main memory computing array, a row decoder, a word line driver, a column decoder, a precharge module, a mode selection module, a PWM, a sensitive amplifier, an input and output port, and an in-memory computing timing control module. The main memory computing array includes a pair of main storage modules, each main storage module includes a plurality of sub-storage modules distributed in columns, each sub-storage module includes a plurality of sub-memory computing arrays distributed in rows, a voltage delay converter, a TDC, a counter, and a digital subtractor. The sub-memory computing array is the in-memory computing array provided by the present invention. The bipolar computing unit is connected to the voltage delay converter through a computing bit line pair (a first and a second computing bit line), and the conversion result of the voltage delay converter is quantized by the TDC and the calculator.

[0054] In the main storage module, 8T-SRAM storage and computing units in the same row share the same storage and computing word line WL, the first symbol input word line INP and the second symbol input word line INN, the bipolar computing units in the same row share the same value input word line CEN, the 8T-SRAM storage and computing units in the same column share the same first bit line BL and the second bit line BLB, and the bipolar computing units in the same column share the same first computing bit line NCC and the second computing bit line PCC.

[0055] In some of the embodiments, the number of sub-storage modules in each main storage module is 64, and the number of sub-storage and computing arrays in each sub-storage module is 16.

[0056] It should be noted that in the above-mentioned in-memory computing circuit, a new main memory computing array is mainly adopted. Modules such as row decoder, word line driver, column decoder, pre-charge module, mode selection module, PWM, sensitive amplifier, input and output ports and in-memory computing timing control module are standard modules of the in-memory computing circuit, so the present invention will not be introduced in detail.

[0057] Reference Figure 2 In an embodiment of the present invention, an 8T-SRAM storage and computing unit is also provided, including a first PMOS tube P1, a second PMOS tube P2, a first NMOS tube N1, a second NMOS tube N2, a third NMOS tube N3, a fourth NMOS tube N4, a fifth NMOS tube N5 and a sixth NMOS tube N6.

[0058] The gate, source and drain of the first PMOS tube are respectively connected to the gate, power supply voltage and drain of the first NMOS tube, and the source of the first NMOS tube is connected to the power ground; the gate, source and drain of the second PMOS tube are respectively connected to the gate, power supply voltage and drain of the second NMOS tube, and the source of the second NMOS tube is connected to the power ground.

[0059] The gates of the second PMOS tube and the second NMOS tube and the drains of the first PMOS tube and the first NMOS tube are connected to form a first storage node, and the gates of the first PMOS tube and the first NMOS tube and the drains of the second PMOS tube and the second NMOS tube are connected to form a second storage node.

[0060] The gate, source and drain of the third NMOS tube N3 are connected to the storage word line WL, the first storage node Q and the first bit line BL respectively, and the gate, source and drain of the fourth NMOS tube N4 are connected to the storage word line WL, the second storage node QB and the second bit line BLB respectively.

[0061] The source and gate of the fifth NMOS tube N5 are connected to the first storage node Q and the first sign input word line INP respectively, the source and gate of the sixth NMOS tube N6 are connected to the second storage node QB and the second sign input word line INN respectively, and the drain of the fifth NMOS tube N5 and the drain of the sixth NMOS tube N6 are connected to form a judgment node Judge.

[0062] The above provides a new 8T-SRAM storage unit. For the above 8T-SRAM storage unit, the 6T-SRAM storage structure provides basic data reading, writing, and holding functions, and the judgment node provides a judgment signal for the logical calculation of the weight data stored in the 6T-SRAM storage structure and the input data. Specifically, you can refer to the description of the 8T-SRAM storage unit in the in-memory computing array.

[0063] As follows, the in-memory computing circuit and the in-memory computing array therein provided by the present invention are specifically described through a specific embodiment.

[0064] Reference Figures 2 to 5 In one embodiment (in this embodiment, for simplicity, each device, bit line and word line is expressed by abbreviated form), a signed in-memory computing circuit is provided, which includes: a main memory computing array, a bit line group, a word line group, a row decoder, a word line driver, a column decoder, a precharge module, a mode selection module, a PWM, a voltage delay converter, a TDC, a counter, a digital subtractor, a sensitive amplifier, an input and output port, an in-memory computing timing control module, and an in-memory computing module.

[0065] The main memory computing array includes two main storage modules, each main storage module includes 64 sub-storage modules distributed in columns, each sub-storage module includes 16 sub-storage computing arrays distributed in rows, a voltage delay converter VTC, a digital subtraction circuit, TDC, and a counter, each sub-storage computing array includes a cell array distributed in rows, a bipolar computing unit, and the cell array includes multiple 8T-SRAM memory computing units.

[0066] The 8T-SRAM storage unit is composed of a traditional 6T-SRAM unit and a 2T symbol judgment port. It contains 2 PMOS tubes P1~P2 and 6 NMOS tubes N1~N6, among which P1, P2, N1, N2, N3, and N4 are cross-coupled to form a basic 6T-SRAM unit with two storage nodes Q and QB, and the remaining two NMOS tubes N5 and N6 constitute the symbol judgment port. Among them, the 6T-SRAM storage unit in the 8T-SRAM unit provides basic data reading, writing, and holding functions; the symbol judgment port provides the judgment signal Judge for the logical calculation of the weight data stored in the 6T-SRAM unit and the input data.

[0067] The circuit connection relationship of the 6T-SRAM unit in the 8T-SRAM storage and calculation unit is as follows: P1 and N1 form an inverter, and P2 and N2 form another inverter; the two are inversely cross-coupled to form storage nodes Q and QB; the storage node Q is connected to the bit line BL through the transmission tube N3, and the storage node QB is connected to the bit line BLB through the transmission tube N4, and the gates of N3 and N4 are connected to the word line WL; the circuit connection relationship of the 2T symbol judgment port is as follows: the source of N5 is connected to the storage node Q of the 6T-SRAM, the gate of N5 is connected to the word line INP, the source of N6 is connected to the storage node QB of the 6T-SRAM, the gate of N6 is connected to the word line INP, and the drain of N5 and the drain of N6 are connected to the judgment node Judge.

[0068] The bipolar calculation unit is characterized in that the input end of the inverter INV1 is connected to the judgment node Judge, the output node NCE is connected to the gate of N7 and the input end of the inverter INV2, and the output node PCE of INV2 is connected to the gate of N9; the drain of N7 is connected to the upper plate of the capacitor C1, the source of N7 is connected to the drain of N8, and the source of N8 is grounded VSS; the drain of N9 is connected to the upper plate of the capacitor C2, the source of N9 is connected to the drain of N10, and the source of N10 is grounded VSS; the gates of N8 and N10 are connected to the numerical input word line CEN; the lower plates of C1 and C2 are grounded VSS.

[0069] The word line group includes 256 storage word lines WL, 256 pairs of sign input word lines INP and INN, and 16 value input word lines CEN.

[0070] In each main storage module, the cell arrays in the same row are connected to the same word line WL, all bipolar computing cells in the same row are connected to the same sign input word line pair INP and INN, and all bipolar computing cells in the same row are connected to the same value input word line CEN.

[0071] The bit line group includes 128 pairs of bit lines BL and BLB, 128 pairs of calculation bit lines PCC and NCC, and 128 judgment bit lines Judge. The upper plate of the bipolar calculation unit capacitor in each column is connected to the unified calculation bit line PCC (NCC).

[0072] In each sub-storage and computing array, the cell array is connected to the same bit line pair, the judgment node of the cell array is connected to the same judgment bit line Judge, and the bipolar computing unit is connected to the same computing bit line pair; the bipolar computing unit is connected to the voltage delay converter through the computing bit line pair, and the conversion result of the voltage delay converter is quantized by the TDC and the calculator.

[0073] The row decoder is used to control the word line driving of each word line.

[0074] The word line driver is used to control the opening or closing of each word line according to the decoding result of the row decoder.

[0075] The column decoder is used to address the target unit for the read operation.

[0076] The precharge module is used to charge each bit line in the bit line group.

[0077] The mode selection module is used to select the read-write mode or the calculation mode.

[0078] PWM is used to convert input data into pulse width delay of corresponding length.

[0079] The voltage delay converter is used to convert the MAC calculated value into the corresponding pulse width delay.

[0080] The TDC is used to convert the pulse width delay converted by the voltage delay converter into a corresponding digital value.

[0081] The counter is used to assist TDC in completing the conversion of the delayed pulse width.

[0082] The digital subtractor subtracts the two quantized digital values ​​in the digital domain.

[0083] The sense amplifier is used to output the data stored in any 8T-SRAM storage unit in read mode.

[0084] The input and output ports are used to obtain input data to be written in the write mode and output the read storage data in the read mode; and the in-memory calculation timing control module is used to generate various clock signals required for MAC operation.

[0085] The timing control module is used to generate various clock signals required for read / write operations and calculation processes.

[0086] The multi-bit multiplication logic and circuit principle of the in-memory computing circuit in this embodiment are as follows:

[0087] 1. Multi-bit multiplication operation.

[0088] The following takes 5bit×1bit operation as an example to illustrate the operation logic and circuit principle of multi-bit multiplication in this embodiment:

[0089] In the 5-bit × 1-bit multiplication operation, only one bipolar calculation unit is needed. <0> It is input as the sign bit value into 8T-SRAM for XNOR operation, and the corresponding calculation result is the judgment basis of Judge as the bipolar calculation unit.

[0090] The following example takes Judge as a high level. Before the "multiplication" operation begins, the calculation bit lines PCC and NCC are precharged to a high level by the precharge module. When Judge=1, PCE is high and NCE is low, corresponding to N7 off and N9 on. At this time, PWM corresponds to the pulse width according to the IN<4:1> input. When IN<4:1>≠0, N8 and N10 are turned on accordingly. The calculation bit line PCC is discharged through the ground path formed by N9 and N10. The discharge amount is determined according to the number of delayed pulse widths formed by PWM. Assume that a delayed pulse width is △T, and each △T corresponds to a discharge of △V. All situations are as follows:

[0091] Table 2 Multiplication table

[0092]

[0093] 2. Multi-bit number accumulation operation.

[0094] The above content introduces the basic logic and principles of implementing multi-bit multiplication. On this basis, the following further introduces the operation process of multi-bit multiplication and accumulation:

[0095] Taking the accumulation of 16 groups of 5bit×1bit as an example, Judge0~Judge7 are 1, and Judge8~Judge15 are 0.

[0096] Before the MAC operation starts, the precharge circuit precharges the calculation bit lines PCC and NCC to a high level; after the MAC operation starts, 16 groups of IN<4:0> are input externally. Since the calculation bit lines of the bipolar calculation units in each column are connected to the same PCC and NCC, the MAC results are as follows:

[0097]

[0098] The above formula is used to calculate the discharge amount of the bit line PCC.

[0099]

[0100] The above formula is used to calculate the discharge amount of the bit line NCC.

[0101] In summary, if Figure 6 As shown, the multiplication and multiplication-accumulation operation process of the multi-bit input and weight of the signed in-memory computing circuit provided in this embodiment is as follows:

[0102] S0: Before the calculation operation starts, the precharge circuit precharges the calculation bit line and precharges all PCC (NCC) to the power supply voltage VDD.

[0103] S1: When the calculation operation starts, the external circuit serially inputs 16 sets of activation values ​​IN0[4:0]~IN15[4:0] through the input and output module.

[0104] S2: According to the sign bit value IN0[0]~IN15[0] of the activation value, the corresponding INP0~INP15, INN0~INN15 are input in parallel, and the Judge represents the sign calculation result of 8TSRAM, and the PCE (NCE) in each sub-storage array is enabled.

[0105] S3: According to the data bit values ​​IN0[4:1]~IN15[4:1] of the activation value, PWM is converted into pulse width delay CEN0[3:0]~CEN15[3:0] of corresponding size, PCC and NCC are discharged to the ground through the bipolar calculation module, and the multi-bit MAC result is represented on the calculation bit line PCC (NCC).

[0106] S4: Convert the result on each PCC and NCC through the voltage delay converter, use the pulse width delay subtraction circuit to subtract the pulse width delay of each column of PCC and NCC, and send the result to the TDC.

[0107] S5: TDC cooperates with the counter to complete the quantization and output of the final result.

[0108] In the signed in-memory computing circuit, during a single MAC operation, only one pair of the 16 pairs of symbol input word line pairs INP0~INP15 and INN0~INN15 in each memory computing array is activated to participate in the calculation, and the symbol pairs in the 16 sub-memory computing arrays in each sub-storage module are correspondingly activated to participate in the calculation, executing multiple sets of parallel MAC operations.

[0109] In order to verify the effectiveness of the above embodiment, the signed in-memory computing circuit mentioned in the embodiment was simulated and performance tested in a simulator and a test platform. The simulation and test results are as follows:

[0110] 1. Same or functional simulation.

[0111] This experiment simulates the symbol judgment function of 8TSRAM based on 28nm process. The simulation results are as follows: Figure 7 As shown in the figure, the analysis shows that the changes of the Judge signal in the four cases are consistent with expectations, so the symbol judgment function can be realized.

[0112] 2. “Product” simulation.

[0113] The product function of the bipolar calculation unit is simulated. The input is a 5-bit number and the weight is a 1-bit number. The voltage level after discharge is as follows: Figure 8 shown.

[0114] From the analysis, it can be seen that the bipolar computing unit provided in this experiment can realize the multiplication function in a sub-storage array. The simulation voltage level is between 900mv and 593mv, and the voltage difference between two adjacent values ​​is about 20mv. Therefore, it can be distinguished and converted by the subsequent quantization unit.

[0115] 3. MAC emulation.

[0116] The MAC computing function of the bipolar computing unit is simulated. The basic unit of the simulation is a sub-storage module and 16 row-distributed sub-storage computing arrays. The voltage level after discharge is as follows: Fig. 9 As shown in the figure, the bipolar computing unit provided in this experiment can realize the MAC function in a column of sub-storage and computing arrays. The simulation voltage level is between 900mv and 597.8mv, and the voltage difference between two adjacent values ​​is also around 20mv, which is consistent with the voltage level of the same value during "product", so it can also be distinguished and converted by subsequent quantization units.

[0117] For simulations with positive and negative MAC results, the basic unit of the simulation is a sub-storage module and 16 row-distributed sub-storage and computing arrays. The voltage level after discharge is as follows: Fig.10 As shown in the figure, the analysis shows that when the absolute value of MAC is the same, the voltage levels of the positive and negative values ​​are exactly the same, achieving a higher linearity.

[0118] In an embodiment of the present invention, an in-memory computing chip is also provided, which integrates the in-memory computing circuit provided by the present invention.

[0119] In an embodiment of the present invention, a static random access memory is also provided, including the in-memory computing chip provided by the present invention.

[0120] It should be understood that the specific embodiments described herein are only used to explain the application, rather than to limit it. Based on the embodiments provided in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the protection scope of this application.

[0121] Obviously, the drawings are only some examples or embodiments of the present application. For ordinary technicians in the field, the present application can also be applied to other similar situations based on these drawings without creative work. In addition, it is understandable that although the work done in this development process may be complicated and lengthy, for ordinary technicians in the field, certain changes in design, manufacturing or production based on the technical content disclosed in this application are only conventional technical means and should not be regarded as insufficient content disclosed in this application.

Claims

1. An in-memory computing array, characterized in that: It includes a cell array distributed in rows and a bipolar computing unit, wherein the cell array includes a plurality of 8T-SRAM storage and computing units distributed in rows; Each of the 8T-SRAM storage and calculation units includes a 6T-SRAM storage and calculation structure, a fifth NMOS tube N5 and a sixth NMOS tube N6, the source and gate of N5 are respectively connected to the first storage node and the first symbol input word line of the 6T-SRAM storage and calculation structure, the source and gate of N6 are respectively connected to the second storage node and the second symbol input word line of the 6T-SRAM storage and calculation structure, and the drain of N5 is connected to the drain of N6 and forms a judgment node; The bipolar calculation unit includes a first inverter INV1, a second inverter INV2, a seventh NMOS tube N7, an eighth NMOS tube N8, a ninth NMOS tube N9, a tenth NMOS tube N10, a first capacitor C1 and a second capacitor C2, the output end of INV1 is connected to the input end of INV2, the gate, drain and source of N7 are respectively connected to the output end of INV1, the upper plate of C1 and the drain of N8, the gate, drain and source of N9 are respectively connected to the output end of INV2, the upper plate of C2 and the drain of N10, C1 and C2 are also connected to the first calculation bit line and the second calculation bit line respectively, the lower plates of C1 and C2 are both grounded, the gates of N8 and N10 are both connected to the numerical input word line, and the drains of N8 and N10 are both grounded; In each of the cell arrays, a plurality of the determination nodes are connected to the input end of INV1 through the same determination bit line.

2. The in-memory computing array according to claim 1, characterized in that: The 6T-SRAM storage and calculation structure includes a first inverting structure, a second inverting structure, a third NMOS tube N3 and a fourth NMOS tube N4. The first inverting structure and the second inverting structure are inversely cross-coupled to form the first storage node and the second storage node. The gate, source and drain of N3 are respectively connected to the storage and calculation word line, the first storage node and the first bit line. The gate, source and drain of N4 are respectively connected to the storage and calculation word line, the second storage node and the second bit line.

3. The in-memory computing array according to claim 2, characterized in that: The first inverting structure includes a first PMOS transistor P1 and a first NMOS transistor N1, and the second inverting structure includes a second PMOS transistor P2 and a second NMOS transistor N2; The gate, source and drain of P1 are connected to the gate, power supply voltage and drain of N1 respectively, and the source of N1 is connected to the power ground; the gate, source and drain of P2 are connected to the gate, power supply voltage and drain of N2 respectively, and the source of N2 is connected to the power ground; The gates of P2 and N2 and the drains of P1 and N1 are connected to form a first storage node, and the gates of P1 and N1 and the drains of P2 and N2 are connected to form a second storage node.

4. An in-memory computing circuit, comprising a main memory computing array, the main memory computing array comprising a pair of main storage modules, each of the main storage modules comprising a plurality of sub-storage modules distributed in columns, each of the sub-storage modules comprising a plurality of sub-storage computing arrays distributed in rows, a voltage delay converter, a TDC, a counter and a digital subtractor, characterized in that: The sub-storage computing array is the in-memory computing array described in any one of claims 1-3.

5. The in-memory computing circuit according to claim 4, characterized in that: The number of the sub-storage modules in each of the main storage modules is 64, and the number of the sub-storage and computing arrays in each of the sub-storage modules is 16.

6. The in-memory computing circuit according to claim 4, characterized in that: In the main storage module, the 8T-SRAM storage and computing units in the same row share the same storage and computing word line, the first symbol input word line and the second symbol input word line, the bipolar computing units in the same row share the same value input word line, the 8T-SRAM storage and computing units in the same column share the same first bit line and second bit line, and the bipolar computing units in the same column share the same first computing bit line and second computing bit line.

7. The in-memory computing circuit according to claim 4, characterized in that: It also includes a row decoder, a word line driver, a column decoder, a precharge module, a mode selection module, a PWM, a sensitive amplifier, an input and output port, and an in-memory calculation timing control module.

8. An in-memory computing chip, characterized in that: An in-memory computing circuit according to any one of claims 4-7 is integrated.

9. A static random access memory, characterized in that: Including the in-memory computing chip as described in claim 8.

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