Memory, memory system, and operating method of memory

Abstract

The invention discloses a memory, a memory system and an operation method of the memory, and belongs to the technical field of storage. The operation method for the memory comprises the following steps: determining the storage state of a reference storage unit, and determining the discharge duration of a sensing node corresponding to a target storage unit based on the storage state of the reference storage unit. And based on the discharge duration of the sensing node corresponding to the target storage unit, reading the target storage unit to obtain a reading result. Wherein the target storage unit and the reference storage unit are located in the same storage string and are adjacent, and the programming sequence of the reference storage unit is behind the target storage unit. By adopting the method and the device, the influence of interlayer interference on reading the memory unit can be reduced, and the accuracy of reading the memory unit can be improved.

Description

Technical Field

[0001] The present application relates to the field of storage technology, and in particular to a memory, a storage system, and a method for operating the memory. Background Art

[0002] With the advancement of memory (eg, 3D NAND flash memory chip) processing technology, in order to increase the storage capacity of the memory, the storage cells in the memory are becoming more and more dense, which causes the inter-layer interference in the memory to become more and more obvious.

[0003] Interlayer interference refers to the fringe electric field generated when programming a memory cell coupled to any word line in the memory, which will affect the number of electrons stored in the adjacent programmed word line coupled memory cell, which may cause the threshold voltage of the programmed memory cell to change. Summary of the invention

[0004] The embodiments of the present application provide a memory, a storage system, and a memory operation method, which can reduce the influence of inter-layer interference on reading storage units and improve the accuracy of reading storage units. The technical solution is as follows:

[0005] In a first aspect, a method for operating a memory is provided, the method comprising:

[0006] determining a storage state of a reference storage unit;

[0007] Determining a discharge duration of a sensing node corresponding to a target storage unit based on a storage state of the reference storage unit;

[0008] Based on the discharge time of the sensing node corresponding to the target storage unit, the target storage unit is read to obtain a reading result; wherein,

[0009] The target memory cell and the reference memory cell are located in the same memory string and are adjacent to each other, and a programming sequence of the reference memory cell is subsequent to that of the target memory cell.

[0010] Optionally, determining the discharge duration of the sensing node corresponding to the target storage unit based on the storage state of the reference storage unit includes:

[0011] Determine a storage state range in which the storage state of the reference storage unit is located, wherein the storage state range includes a first storage state range and a second storage state range, and the storage state in the first storage state range is lower than the storage state in the second storage state range;

[0012] According to the storage state range of the reference memory cell, a discharge time length of the sensing node corresponding to the target memory cell is determined.

[0013] Optionally, the discharge time length corresponding to the first storage state range is shorter than a default discharge time length of the sensing node, and the discharge time length corresponding to the second storage state range is longer than the default discharge time length of the sensing node.

[0014] Optionally, determining the storage state of the reference storage unit includes:

[0015] Based on the default discharge time of the sensing node, the reference storage unit is read to obtain the storage state of the reference storage unit.

[0016] Optionally, before determining the storage state of the reference storage unit, the method further includes:

[0017] Reading a storage page where the target storage unit is located;

[0018] In response to the error bit number FBC of the storage page being greater than a first preset value, performing a default read voltage hard decoding;

[0019] Determining the storage state of the reference storage unit includes:

[0020] In response to the default read voltage hard decoding failing to be performed, a storage state of the reference memory cell is determined.

[0021] Optionally, before determining the storage state of the reference storage unit, the method further includes:

[0022] In response to the default read voltage hard decoding failing to be performed, performing optimal read voltage hard decoding;

[0023] Determining the storage state of the reference storage unit includes:

[0024] In response to the optimal read voltage hard decoding failing to be performed, determining a storage state of the reference memory cell;

[0025] The step of reading the target storage unit based on the discharge duration of the sensing node corresponding to the target storage unit includes:

[0026] The target memory cell is read based on the discharge time length and the optimal read voltage of the sensing node corresponding to the target memory cell.

[0027] Optionally, before determining the storage state of the reference storage unit, the method further includes:

[0028] In response to the default read voltage hard decoding failing to be performed, performing optimal read voltage hard decoding;

[0029] In response to the optimal read voltage hard decoding failing to be performed, performing optimal read voltage soft decoding;

[0030] Determining the storage state of the reference storage unit includes:

[0031] In response to the optimum read voltage soft decoding failing to be performed, a storage state of the reference memory cell is determined.

[0032] Optionally, the reading the target storage unit based on the discharge duration of the sensing node corresponding to the target storage unit to obtain the reading result includes:

[0033] Based on the discharge time of the sensing node corresponding to the target storage cell, a first soft read voltage less than the optimal read voltage, and a second soft read voltage greater than the optimal read voltage, the target storage cell is read to obtain soft data corresponding to the target storage cell;

[0034] Based on the soft data and hard data corresponding to the target storage cell, a reading result corresponding to the target storage cell is determined, wherein the hard data corresponding to the target storage cell is obtained by reading the target storage cell based on the optimal read voltage.

[0035] Optionally, the hard data corresponding to the target memory cell is obtained by reading the target memory cell based on the discharge duration of the sensing node corresponding to the target memory cell and the optimal read voltage.

[0036] In a second aspect, a memory is provided, the memory comprising:

[0037] A memory cell array, the memory cell array comprising a plurality of memory strings, the memory strings comprising a plurality of memory cells;

[0038] A peripheral circuit coupled to the memory cell array, the peripheral circuit being configured to: determine a storage state of a reference memory cell; determine a discharge duration of a sensing node corresponding to a target memory cell based on the storage state of the reference memory cell; and read the target memory cell based on the discharge duration of the sensing node corresponding to the target memory cell to obtain a reading result; wherein the target memory cell and the reference memory cell are located in the same memory string and are adjacent, and the programming order of the reference memory cell is after that of the target memory cell.

[0039] Optionally, the peripheral circuit is configured as:

[0040] Determine a storage state range in which the storage state of the reference storage unit is located, wherein the storage state range includes a first storage state range and a second storage state range, and the storage state in the first storage state range is lower than the storage state in the second storage state range;

[0041] According to the storage state range of the reference memory cell, a discharge time length of the sensing node corresponding to the target memory cell is determined.

[0042] Optionally, the discharge time length corresponding to the first storage state range is shorter than a default discharge time length of the sensing node, and the discharge time length corresponding to the second storage state range is longer than the default discharge time length of the sensing node.

[0043] Optionally, the peripheral circuit is configured as:

[0044] Based on the default discharge time of the sensing node, the reference storage unit is read to obtain the storage state of the reference storage unit.

[0045] Optionally, the peripheral circuit is further configured as:

[0046] Reading a storage page where the target storage unit is located;

[0047] In response to the error bit number FBC of the storage page being greater than a first preset value, performing a default read voltage hard decoding;

[0048] In response to the default read voltage hard decoding failing to be performed, a storage state of the reference memory cell is determined.

[0049] Optionally, the peripheral circuit is further configured as:

[0050] In response to the default read voltage hard decoding failing to be performed, performing optimal read voltage hard decoding;

[0051] In response to the optimal read voltage hard decoding failing to be performed, determining a storage state of the reference memory cell;

[0052] The target memory cell is read based on the discharge time length and the optimal read voltage of the sensing node corresponding to the target memory cell.

[0053] Optionally, the peripheral circuit is further configured as:

[0054] In response to the default read voltage hard decoding failing to be performed, performing optimal read voltage hard decoding;

[0055] In response to the optimal read voltage hard decoding failing to be performed, performing optimal read voltage soft decoding;

[0056] In response to the optimum read voltage soft decoding failing to be performed, a storage state of the reference memory cell is determined.

[0057] Optionally, the peripheral circuit is further configured as:

[0058] Based on the discharge time of the sensing node corresponding to the target storage cell, a first soft read voltage less than the optimal read voltage, and a second soft read voltage greater than the optimal read voltage, the target storage cell is read to obtain soft data corresponding to the target storage cell;

[0059] Based on the soft data and hard data corresponding to the target storage cell, a reading result corresponding to the target storage cell is determined, wherein the hard data corresponding to the target storage cell is obtained by reading the target storage cell based on the optimal read voltage.

[0060] Optionally, the hard data corresponding to the target memory cell is obtained by reading the target memory cell based on the discharge duration of the sensing node corresponding to the target memory cell and the optimal read voltage.

[0061] According to a third aspect, a storage system is provided, comprising: one or more memories as described in the second aspect; and a memory controller coupled to the memories and configured to control the memories.

[0062] The beneficial effects of the technical solution provided by the embodiment of the present application are:

[0063] In an embodiment of the present application, the discharge duration of the sensing node corresponding to the target storage cell can be determined based on the storage state of the reference storage cell, and then the target storage cell can be read based on the determined discharge duration. Since the storage state of the reference storage cell is related to the programming voltage applied to the reference storage cell, the storage state of the reference storage cell can reflect the degree to which the target storage cell is affected by the interlayer interference. Therefore, in an embodiment of the present application, the discharge duration of the sensing node is determined by the storage state of the reference storage cell, and the influence of the interlayer interference on the target storage cell can be reduced by adjusting the discharge duration of the sensing node, thereby improving the accuracy of reading the target storage cell. BRIEF DESCRIPTION OF THE DRAWINGS

[0064] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0065] Figure 1 is a schematic diagram of an exemplary system having a memory device provided in an embodiment of the present application;

[0066] Figure 2 is a diagram of an exemplary memory card having a memory device provided by an embodiment of the present application;

[0067] Figure 3 is a schematic diagram of an exemplary solid-state drive having a memory device provided in an embodiment of the present application;

[0068] Figure 4is a schematic diagram of a memory device including a peripheral circuit provided in an embodiment of the present application;

[0069] Figure 5 is a schematic diagram of an exemplary memory cell array including a NAND memory string provided in an embodiment of the present application;

[0070] Figure 6 is a schematic diagram of an exemplary memory device including a memory cell array and a peripheral circuit provided by an embodiment of the present application;

[0071] Figure 7 is a schematic diagram of a 3D NAND structure provided in an embodiment of the present application;

[0072] Figure 8 is a schematic diagram of a memory device including a sensing circuit provided in an embodiment of the present application;

[0073] Fig. 9 is a schematic diagram of a discharge curve of a sensing node SO provided in an embodiment of the present application;

[0074] Fig.10 A schematic diagram of a hard data reading process provided in an embodiment of the present application;

[0075] Fig.11 A schematic diagram of a soft data reading process provided in an embodiment of the present application;

[0076] Fig.12 is a schematic diagram of threshold voltage distribution of a memory cell provided in an embodiment of the present application;

[0077] Fig.13 This is a threshold voltage distribution diagram of a three-level storage cell provided in an embodiment of the present application;

[0078] Fig.14 is a flow chart of a method for operating a memory provided by an embodiment of the present application;

[0079] Fig.15 is a schematic diagram of threshold voltage distribution of a memory cell provided in an embodiment of the present application;

[0080] Fig.16 is a flow chart of a method for operating a memory provided by an embodiment of the present application;

[0081] Fig.17 It is a flow chart of a memory operation method provided in an embodiment of the present application. DETAILED DESCRIPTION

[0082] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0083] Figure 1 A block diagram of an exemplary system 100 having a memory device according to some aspects of the present application is shown. The system 100 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory device therein. Figure 1 As shown in , the system 100 may include a host 108 and a storage system 102, the storage system 102 having one or more memory devices 104 and a memory controller 106. The host 108 may be a processor (e.g., a central processing unit (CPU)) or a system on chip (SoC) (e.g., an application processor (AP)) of an electronic device. The host 108 may be configured to send data to the memory device 104 or receive data from the memory device 104.

[0084] The memory device 104 can be any memory device disclosed in the present application. As disclosed in detail below, the memory device 104 (e.g., a NAND flash memory device (e.g., a three-dimensional (3D) NAND flash memory device)) can have reduced leakage current from a drive transistor (e.g., a string driver) coupled to an unselected word line during an erase operation, which allows for further size reduction of the drive transistor.

[0085] According to some embodiments, the memory controller 106 is coupled to the memory device 104 and the host 108 and is configured to control the memory device 104. The memory controller 106 can manage data stored in the memory device 104 and communicate with the host 108. In some embodiments, the memory controller 106 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact flash (CF) card, a universal serial bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the memory controller 106 is designed to operate in a high duty cycle environment SSD or embedded multimedia card (eMMC), which is used as a data storage for mobile devices such as smart phones, tablet computers, laptop computers, etc. and enterprise storage arrays. The memory controller 106 can be configured to control the operation of the memory device 104, such as read, erase, and program processes. The memory controller 106 may also be configured to manage various functions regarding data stored or to be stored in the memory device 104, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some embodiments, the memory controller 106 is also configured to process error correction code (ECC) regarding data read from or written to the memory device 104. The memory controller 106 may also perform any other suitable functions, such as formatting the memory device 104. The memory controller 106 may communicate with an external device (e.g., a host 108) according to a specific communication protocol. For example, the memory controller 106 may communicate with the external device through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnect (PCI) protocol, a PCI Express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer small interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a Firewire protocol, etc.

[0086] The memory controller 106 and the one or more memory devices 104 may be integrated into various types of storage devices, for example, included in the same package (e.g., a universal flash storage (UFS) package or an eMMC package). That is, the memory system 102 may be implemented and packaged into different types of terminal electronic products. Figure 2In one example shown in FIG. 1 , the memory controller 106 and the single memory device 104 may be integrated into a memory card 202. The memory card 202 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 202 may also include a processor that connects the memory card 202 to a host (e.g., Figure 1 The memory card connector 204 is coupled to the host 108 in the embodiment. Figure 3 In another example shown in , the memory controller 106 and the plurality of memory devices 104 may be integrated into an SSD 306. The SSD 306 may also include a processor that interfaces the SSD 306 with a host (e.g., Figure 1 In some implementations, the storage capacity and / or operating speed of the SSD 306 is greater than the storage capacity and / or operating speed of the memory card 202.

[0087] Figure 4 1 is a schematic circuit diagram of an exemplary memory device 400 including peripheral circuits according to some aspects of the present application. The memory device 400 may be Figure 1 4. An example of a memory device 104 in FIG. 4. The memory device 400 may include a memory cell array device 401 and a peripheral circuit 402 coupled to the memory cell array device 401. The memory cell array device 401 may be a NAND flash memory cell array, wherein memory cells 406 are provided in the form of an array of NAND memory strings 408, each NAND memory string 408 extending vertically above a substrate (not shown). In some embodiments, each NAND memory string 408 includes a plurality of memory cells 406 coupled in series and stacked vertically. Each memory cell 406 may hold a continuous analog value, such as a voltage or charge, which depends on the number of electrons trapped in the region of the memory cell 406. Each memory cell 406 may be a floating gate type memory cell including a floating gate transistor, or a charge trapping type memory cell including a charge trapping transistor.

[0088] In some embodiments, each memory cell 406 is a single-level cell (SLC) having two possible storage states and can therefore store one bit of data. For example, the first storage state "0" can correspond to a first voltage range, and the second storage state "1" can correspond to a second voltage range. In some embodiments, each memory cell 406 is a multi-level cell (MLC) capable of storing more than a single bit of data in more than four memory states. For example, an MLC can store two bits per cell, three bits per cell (also known as a three-level cell (TLC)), or four bits per cell (also known as a quad-level cell (QLC)). Each MLC can be programmed to take a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed to take one of three possible programming levels from an erased state by writing one of three possible nominal storage values ​​to the cell. A fourth nominal storage value can be used for an erased state.

[0089] like Figure 4 As shown in , each NAND memory string 408 may include a source select gate (SSG) 410 at its source end and a drain select gate (DSG) 412 at its drain end. The SSG 310 and the DSG 412 may be configured to activate a selected NAND memory string 408 (column of the array) during read and program processes. In some embodiments, the sources of the NAND memory strings 408 in the same block 404 are coupled by the same source line (SL) 414 (e.g., a common SL). In other words, according to some embodiments, all NAND memory strings 408 in the same block 404 have an array common source (ACS). According to some embodiments, the DSG 412 of each NAND memory string 308 is coupled to a corresponding bit line 416, and data can be read from or written to the bit line 416 via an output bus (not shown). In some embodiments, each NAND memory string 408 is configured to be selected or deselected by applying a select voltage (e.g., higher than the threshold voltage of a transistor having DSG 412) or a deselect voltage (e.g., 0 V) ​​to a corresponding DSG 412 via one or more DSG lines 413 and / or by applying a select voltage (e.g., higher than the threshold voltage of a transistor having SSG 410) or a deselect voltage (e.g., 0 V) ​​to a corresponding SSG 410 via one or more SSG lines 415.

[0090] like Figure 4As shown in , the NAND memory string 408 can be organized into a plurality of blocks 404, each of which can have a common source line 414 (e.g., coupled to ground). In some embodiments, each block 304 is a basic data unit for an erase operation, i.e., all memory cells 406 on the same block 404 are erased at the same time. To erase the memory cells 406 in a selected block 404a, the source lines 414 coupled to the selected block 404a and the unselected blocks 404b in the same plane as the selected block 404a can be biased with an erase voltage (Vers) (e.g., a high positive voltage (e.g., 20V or higher)). It should be understood that in some examples, the erase operation can be performed at the half-block level, at the quarter-block level, or at a level with any suitable number of blocks or any suitable fraction of blocks. The memory cells 406 of adjacent NAND memory strings 408 can be coupled by word lines 418, which select which row of memory cells 406 is affected by the read and programming process. In some embodiments, each word line 418 is coupled to a page 420 of memory cells 406, which is a basic data unit for a programming process. The size of a page 420 in bits may be related to the number of NAND memory strings 408 coupled by word lines 418 in one block 404. Each word line 418 may include a plurality of control gates (gate electrodes) at each memory cell 406 in a corresponding page 420 and a gate line coupling the control gates.

[0091] Figure 5 4 shows a cross-sectional side view of an exemplary memory cell array 401 including NAND memory strings 408 according to some aspects of the present application. Figure 5 As shown in FIG, NAND memory strings 408 may extend vertically through memory stack layers 504 over substrate 502. Substrate 502 may include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), or any other suitable material.

[0092] The memory stack 504 may include alternating gate conductive layers 506 and gate-to-gate dielectric layers 508. The number of pairs of gate conductive layers 506 and gate-to-gate dielectric layers 508 in the memory stack 504 may determine the number of memory cells 406 in the memory cell array 401. The gate conductive layers 506 may include a conductive material including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate conductive layer 506 includes a metal layer, such as a tungsten layer. In some embodiments, each gate conductive layer 506 includes a doped polysilicon layer. Each gate conductive layer 506 may include a control gate surrounding the memory cell 406 and may extend laterally at the top of the memory stack 504 as a DSG line 413, at the bottom of the memory stack 504 as an SSG line 415, or between the DSG line 413 and the SSG line 415 as a word line 418.

[0093] like Figure 5 As shown in , the NAND memory string 408 includes a channel structure 512 extending vertically through the memory stack layer 504. In some embodiments, the channel structure 512 includes a channel hole filled with (one or more) semiconductor materials (e.g., as a semiconductor channel 520) and (one or more) dielectric materials (e.g., as a memory film 518). In some embodiments, the semiconductor channel 520 includes silicon, for example, polysilicon. In some embodiments, the memory film 518 is a composite dielectric layer including a tunneling layer 526, a storage layer 524 (also referred to as a "charge trapping / storage layer"), and a barrier layer 522. The channel structure 512 can have a cylindrical shape (e.g., a column shape). According to some embodiments, the semiconductor channel 520, the tunneling layer 526, the storage layer 524, and the barrier layer 522 are arranged radially in this order from the center of the column toward the outer surface of the column. The tunneling layer 526 can include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer 524 can include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer 522 may include silicon oxide, silicon oxynitride, a high dielectric constant (high-k) dielectric, or any combination thereof. In one example, the memory film 518 may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0094] According to some embodiments, Figure 5As shown in FIG. 5 , a well 514 (e.g., a P-well and / or an N-well) is formed in the substrate 502, and the source terminal of the NAND memory string 408 is in contact with the well 514. For example, the source line 414 can be coupled to the well 514 to apply an erase voltage to the well 514 (i.e., the source of the NAND memory string 408) during an erase operation. In some embodiments, the NAND memory string 408 also includes a channel plug 516 at the drain terminal of the NAND memory string 408. It should be understood that although in Figure 5 Not shown, but additional components of the memory cell array 401 may be formed, including but not limited to gate line gaps / source contacts, local contacts, interconnect layers, etc.

[0095] Return to reference Figure 4 , the peripheral circuit 402 may be coupled to the memory cell array 401 via the bit line 416, the word line 418, the source line 414, the SSG line 415, and the DSG line 413. The peripheral circuit 402 may include any suitable analog, digital, and mixed signal circuits for facilitating the operation of the memory cell array 401 by applying a voltage signal and / or a current signal to each target memory cell 406 and sensing a voltage signal and / or a current signal from each target memory cell 406 via the bit line 416, the word line 418, the source line 414, the SSG line 415, and the DSG line 413. The peripheral circuit 402 may include various types of peripheral circuits formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 6 Some exemplary peripheral circuits are shown, and the peripheral circuit 402 includes a page buffer / sense amplifier 604, a column decoder / bit line driver 606, a row decoder / word line driver 608, a voltage generator 610, a control logic unit 612, a register 614, an interface 616, and a data bus 618. It should be understood that in some examples, it may also include Figure 6 Additional peripheral circuits not shown.

[0096] The page buffer / sense amplifier 604 may be configured to read data from the memory cell array 401 and program (write) data to the memory cell array 401 according to a control signal from the control logic unit 612. In one example, the page buffer / sense amplifier 404 may store a page of programming data (write data) to be programmed into one page 420 of the memory cell array 401. In another example, the page buffer / sense amplifier 604 may perform a program verification operation to ensure that the data has been correctly programmed into the memory cell 406 coupled to the selected word line 418. In yet another example, the page buffer / sense amplifier 604 may also sense a low-power signal from the bit line 416 representing a data bit stored in the memory cell 406, and amplify a small voltage swing to a recognizable logic level in a read operation. The column decoder / bit line driver 606 may be configured to be controlled by the control logic unit 612, and select one or more NAND memory strings 408 by applying a bit line voltage generated from the voltage generator 610.

[0097] The row decoder / word line driver 608 may be configured to be controlled by the control logic unit 612 and select / deselect the block 404 of the memory cell array 401 and select / deselect the word line 418 of the block 404. The row decoder / word line driver 608 may also be configured to drive the word line 418 using the word line voltage generated from the voltage generator 610. In some embodiments, the row decoder / word line driver 608 may also select / deselect and drive the SSG line 415 and the DSG line 413. As described in detail below, the row decoder / word line driver 608 is configured to perform an erase operation on the memory cell 606 coupled to the selected word line(s) 618. The voltage generator 610 may be configured to be controlled by the control logic unit 612 and generate a word line voltage (e.g., a read voltage, a program voltage, a pass voltage, a local voltage, a verification voltage, etc.), a bit line voltage, and a source line voltage to be supplied to the memory cell array 401.

[0098] The control logic unit 612 may be coupled to each peripheral circuit described above, and is configured to control the operation of each peripheral circuit. The register 614 may be coupled to the control logic unit 612, and includes a status register, a command register, and an address register for storing status information, a command operation code (OP code), and a command address for controlling the operation of each peripheral circuit. The interface 616 may be coupled to the control logic unit 612, and act as a control buffer to buffer control commands received from a host (not shown) and relay them to the control logic unit 612, and to buffer status information received from the control logic unit 612 and relay them to the host. The interface 616 may also be coupled to the column decoder / bit line driver 606 via a data bus 618, and act as a data I / O interface and a data buffer to buffer data and relay them to the memory cell array 401 or relay or buffer data from the memory cell array 401.

[0099] Figure 7 3D NAND is a schematic diagram of a memory device of the present invention. The memory device may be a 3D NAND flash memory chip (hereinafter referred to as 3D NAND). Figure 7 As shown, the 3D NAND includes a plurality of memory strings 701, which are arranged along a support surface (i.e. Figure 7 Each storage string 701 includes a plurality of (for example, 32 or 64) memory cells connected in series, and the plurality of memory cells connected in series are arranged in a direction perpendicular to the supporting surface of the substrate (i.e. Figure 7 Thus, the plurality of memory cells included in the memory cell array device can be arranged in a three-dimensional array on the substrate, thereby forming a memory array.

[0100] like Figure 7As shown, each storage string 701 also includes an upper selection tube connected to the drain of the first storage cell, and a lower selection tube connected to the source of the last storage cell. The upper selection tube is also called a top select gate (TSG) or a drain selection tube. The lower selection tube is also called a bottom select gate (BSG) or a source selection tube. The gate of each TSG is connected to a drain select line (DSL), the source of each TSG is connected to the drain of the first storage cell in the storage string to which it belongs, and the drain of each TSG is connected to a bit line (BL). The gate of each BSG is connected to a source select line (SSL), the drain of each BSG is connected to the source of the last storage cell in the storage string to which it belongs, and the source of each BSG is connected to a source line (SL).

[0101] from Figure 7 It can also be seen that the 3D NAND includes n BLs arranged along the direction X: BL0 to BLn, x DSLs arranged along the direction Y: DSL0 to DSLx, and x SSLs arranged along the direction Y: SSL0 to SSLx. Wherein, n and x are both integers greater than 1. Each DSL is connected to the gates of n TSGs arranged along the direction X, each BL is connected to the drains of x TSGs arranged along the direction Y, and each SSL is connected to the gates of n BSGs arranged along the direction X. In addition, the source of each BSG is connected to the same SL, so the SL is also called an array common source (ACS).

[0102] Continue to refer Figure 7 , the memory cells in each memory string 701 share a set of WLs with the memory cells in other memory strings 701. Assuming that each memory string 701 includes m memory cells, the 3D NAND may include m WLs arranged along direction Z: WL0 to WLm, where m is an integer greater than 1. Each WL is connected to the gates of each memory cell located in the same layer (i.e., having substantially the same height relative to the supporting surface of the substrate). The following is an introduction to the programming process of the memory cell: the programming process can be achieved by applying a programming voltage to the gate of the memory cell, and the programming process can enable the memory cell to complete the storage of the corresponding storage state. Please continue to refer to Figure 7 In the structure shown in FIG. 1 , when programming any memory cell, a voltage can be applied to the DSL corresponding to the memory cell to open the corresponding TSG, so that the memory cell to be programmed can be further selected. Figure 7When programming the storage cell 702, a voltage can be applied to DSL0, and the TSG in the storage string 701 is also turned on; on the other hand, different programming voltages can be applied to the WL corresponding to the storage cell 702, and each time the programming voltage is applied to the WL, a conduction voltage (generally less than 2V) can be applied to the BL corresponding to the storage cell 702, so that the programming voltage applied to the WL can act on the control gate of the storage cell 702; in addition, a shielding voltage (generally greater than or equal to 2V) can be applied to other BLs to shield the programming voltage applied to the WL from acting on the control gates of other storage cells other than the storage cell 702. In this way, each programming voltage applied to the WL can act on different storage cells, so that different storage cells are written into different storage states.

[0103] Figure 8 FIG. 8 is a schematic diagram of a memory device according to an embodiment of the present application. The memory device 800 may include a memory cell array 801 having a plurality of memory cells C(1, 1) to C(M, N) and a sensing circuit 802, where M and N are positive integers. The memory cell array 801 may be any of the memory cell arrays shown in the above embodiments, and the sensing circuit 802 may include a plurality of sensing nodes SO( Figure 8 (not shown), each sensing node SO is coupled to the bit lines BL1 to BLN of the memory cells, respectively, wherein the sensing circuit detects the storage state or threshold voltage of the target memory cell by sensing the voltage or current on the selected bit line BLn.

[0104] Fig. 9 Schematic diagram of a discharge curve of a sensing node SO provided in an embodiment of the present application. Fig. 9 As shown, when performing a read operation, the sensing node SO is first charged to a fixed voltage, and the sensing node SO is connected to the memory cell through a bit line. If the read voltage applied when performing the read operation can turn on the memory cell, then after a period of time (default discharge time △T), the sensing node SO will be discharged due to the conduction of the memory cell; if the read voltage applied when performing the read operation cannot turn on the memory cell or can only turn on the memory cell weakly, then after a period of time (△T), the sensing node SO will hardly be discharged. Based on this, the channel current can be indirectly measured by the voltage change △Vc of the sensing node SO, thereby obtaining the storage state of the memory cell. Generally, the data read to indicate the storage state of the memory cell is called hard data.

[0105] In one example, a page is the smallest unit for reading in a memory. After each page is read, the number of error bits (Fail Bit Count, FBC) corresponding to the reading of the page can be determined through a verification mechanism. Among them, FBC refers to the number of storage cells in the page that have read errors. If after reading the page, it is determined that the corresponding FBC is greater than a preset value, the hard decoding of the page can be triggered, and the hard decoding can be called default read voltage hard decoding (default read hard decoding). If the hard decoding of the page is successful, it means that the storage state of the storage cell in the page that has read errors can be successfully decoded, that is, the hard data of each storage cell can be successfully read. If the hard decoding of the page fails, it means that the storage state of the storage cell in the page that has read errors cannot be successfully decoded, and then the best read voltage hard decoding (best read hard decoding) of the page can be further triggered.

[0106] The best read voltage hard decoding refers to adjusting the read voltage of each storage state to the best read voltage, then re-reading the storage state of each storage cell in the page, and then hard decoding the page according to the reading result. After adjusting the read voltage of each storage state to the best read voltage, re-reading the storage state of each storage cell in the page can reduce the value of FBC to a certain extent. At this time, hard decoding the page again can improve the success rate of hard decoding. If the best read voltage hard decoding of the page is successful, it means that the storage state of the storage cell with a read error in the page can be successfully decoded, that is, the hard data of each storage cell can be successfully read. If the best read voltage hard decoding of the page fails, it means that the storage state of the storage cell with a read error in the page cannot be successfully decoded, and the best read voltage soft decoding (best read hard decoding) of the page can be further triggered.

[0107] The optimal read voltage soft decoding refers to reading the soft data of the page through the soft read voltage, and then performing soft decoding based on the soft data and hard data of the page. Among them, the soft data is used to indicate the position of the threshold voltage of the storage cell in the threshold voltage distribution of the storage cell. The soft data can provide additional reliability information for the above hard data. The value of the soft data indicates the proximity of the threshold voltage of the storage cell to the read voltage corresponding to the above hard data. The soft read voltage corresponding to each storage state may include a first soft read voltage less than the optimal read voltage corresponding to the storage state and a second soft read voltage greater than the optimal read voltage corresponding to the storage state. If the optimal read voltage soft decoding of the page is successful, it means that the storage state of the storage cell with a read error in the page can be successfully decoded, that is, the hard data of each storage cell can be successfully read. If the optimal read voltage soft decoding of the page fails, it means that the storage state of the storage cell with a read error in the page cannot be successfully decoded, that is, the reading of the page fails.

[0108] The following combination Fig.10 and Fig.11 The reading process of hard data and soft data is explained. Fig.10 A schematic diagram of a hard data reading process provided in an embodiment of the present application. Fig.10 As shown, taking a three-level storage cell as an example, each storage cell can be configured to store 3 bits of data in one of 8 storage states (P0 to P7). In a three-level storage cell, each physical page corresponds to 3 logical pages, namely, a low page (LP), a middle page (MP), and an upper page (UP). For example, when performing a read operation on a storage cell to read hard data of a low page, it is necessary to first apply a read voltage V to the word line where the storage cell is located. R1 , read the voltage V R1 It is used to distinguish the P0 state from the P1 to P7 states. By detecting the potential of the sensing node SO after discharge, V R1 In some embodiments, the threshold voltage is less than the read voltage V R1 The hard read value of the memory cell is 1, and the threshold voltage is greater than the read voltage V R1 The hard read value of the memory cell is 0. Of course, in other embodiments, the threshold voltage is greater than the read voltage V R1 The hard read value of the memory cell is 1, and the threshold voltage is less than the read voltage V R1 The hard read value of the storage unit is 0, which is not limited in the embodiments of the present application.

[0109] Then, a read voltage V is applied to the word line where the memory cell is located. R5 , where the read voltage V R5 , used to distinguish between P0~P4 states and P5~P7 states. By detecting the discharge of the sensing node SO, V R5, corresponding to the hard read value. In some embodiments, the threshold voltage is less than the read voltage V R1 The hard read value of the memory cell is 1, and the threshold voltage is greater than the read voltage V R1 The hard read value of the memory cell is 0. Finally, the read voltage V R5 The corresponding hard read value is inverted and compared with the read voltage V R1 The corresponding hard read values ​​are ORed to obtain the hard data corresponding to the lower page.

[0110] Fig.11 A schematic diagram of a soft data reading process provided in an embodiment of the present application. Fig.11 As shown, taking the reading of the soft data of the lower page of TLC as an example, firstly, a read voltage V is applied to the word line where the memory cell to be read is located. R1 -△V to get the read voltage V R1 -△V corresponding to the soft read value. The value of △V can be determined based on the threshold voltage distribution of each storage state in TLC. The threshold voltage of the storage cell is less than the read voltage V R1 -△V, V R1 The soft read value corresponding to -△V is 1, and the threshold voltage of the storage cell is greater than the read voltage V R1 -△V, V R1 The soft read value corresponding to -△V is 0. Then a read voltage V is applied to the word line where the memory cell is located. R1 +△V to get the read voltage V R1 +△V corresponds to the soft read value. The threshold voltage of the memory cell is less than the read voltage V R1 +△V, V R1 +△V corresponds to a soft read value of 1, and the threshold voltage of the storage cell is greater than the read voltage V R1 +△V, V R1 +△V corresponds to a soft read value of 0. The read voltage V R1 -△V corresponding to the soft read value and read voltage V R1 +△V corresponding to the soft read value is XORed to get V R1 The corresponding soft read value. Among them, the threshold voltage of the storage cell is greater than V R1 -△V and less than V R1 +△V, V R1 The corresponding soft read value is 1, and the threshold voltage of the storage cell is greater than V R1 +△V or less than V R1 -△V, V R1 The corresponding soft read value is 0.

[0111] Then, a read voltage V is applied to the word line where the memory cell to be read is located. R5 -△V and read voltage VR5 +△V to get V R5 The corresponding soft read value. It should be understood that V R5 The corresponding soft read value is the same as the V R1 The corresponding soft read value method is similar, so it will not be repeated here. R1 The corresponding soft read value and V R5 The corresponding soft read values ​​are ORed together to obtain the soft data for the lower page.

[0112] As the processing technology of memory devices (such as 3D NAND) advances, the number of stacked layers increases and the distance between layers decreases, which causes the inter-layer interference between adjacent layers of 3D NAND to become more and more obvious.

[0113] Interlayer interference refers to the fringe electric field generated by the programming voltage applied to the memory cell when programming the memory cell in any layer of the 3D NAND flash memory chip, which will affect the number of electrons stored in the programmed memory cell in the adjacent layer (generally increasing the number of electrons stored in the memory cell), especially the memory cells in adjacent layers and corresponding to the same memory string. The change in the number of electrons stored in the programmed memory cell will cause the threshold voltage to change, which will increase the probability of error in reading the memory cell.

[0114] When solving the problem of the influence of interlayer interference on storage cells, the applicant found that the interlayer interference has the following characteristics:

[0115] Feature 1: The greater the programming voltage applied to the memory cell, the greater the impact of the generated fringe electric field on the programmed memory cells in the adjacent layer. Fig.12 This is a schematic diagram of the threshold voltage distribution of a storage cell in a certain storage state after being affected by interlayer interference. Fig.12In the figure, the dotted curve is the threshold voltage distribution of the first storage cell in a storage cell of a certain storage state, and the solid curve is the threshold voltage distribution of the second storage cell in a storage cell of a certain storage state. Among them, the first storage cell is relatively greatly affected by the interlayer interference, that is, the storage state of the storage cell adjacent to the first storage cell and located in the same storage string is higher, and the second storage cell is relatively less affected by the interlayer interference, that is, the storage state of the storage cell adjacent to the second storage cell and located in the same storage string is lower. A high storage state of a storage cell means that the storage cell has a higher threshold voltage, and a higher programming voltage needs to be applied to program the storage cell to the corresponding storage state. A low storage state of a storage cell means that the storage cell has a lower threshold voltage, and a lower programming voltage needs to be applied to program the storage cell to the corresponding storage state. The high and low storage states can be divided by technicians, and are not limited in the embodiments of the present application. For example, in a TLC storage cell, storage states P0~P3 are lower storage states, and storage states P4~P7 are higher storage states, wherein the threshold voltages of storage states P0~P7 increase successively. By Fig.12 It can be seen that the first memory cell is relatively more greatly affected by the interlayer interference, and the threshold voltage increment of the first memory cell is greater than the threshold voltage increment of the second memory cell.

[0116] Feature 2: When the threshold voltage of a programmed memory cell is small (ie, the number of electrons in the memory cell is relatively small), the greater the influence of the fringe electric field generated by the programming voltage applied to the memory cell in the adjacent layer. Fig.13 This is a schematic diagram of the threshold voltage distribution of storage cells in different storage states after being affected by interlayer interference. Fig.13 In FIG. 1 , the dashed curve is the threshold voltage distribution of each storage state without interlayer interference, and the realization curve is the threshold voltage distribution of each storage state with interlayer interference. Fig.13 It can be seen that the lower the storage state of the memory cell is, the greater the corresponding threshold voltage increment will be after being affected by the interlayer interference. Fig.13 This is only a schematic diagram of the threshold voltage distribution of each storage state of the three-level storage cell before and after the interlayer interference is affected. For other types of storage cells, the threshold voltage distribution law before and after the interlayer interference is affected is similar. Fig.13 Similarly, it will not be repeated in the embodiments of the present application.

[0117] In order to avoid the problem of reading errors of storage cells caused by interlayer interference, the present application provides a memory operation method. By adjusting the discharge time of the sensing node, the threshold voltage of the target storage cell can be compensated, thereby reducing the impact of interlayer interference on the storage cell. The principle of the memory operation method provided by the present application is introduced as follows:

[0118] Case 1: During the process of reading a memory cell of any storage state, after applying a read voltage corresponding to the storage state to the memory cell, if the discharge time of the corresponding sensing node SO is shortened, the voltage of the sensing node SO will be higher after the sensing node SO is discharged compared to the case where the discharge time of the sensing node is not shortened.

[0119] If the threshold voltage of a programmed memory cell is increased by some means without changing the storage state of the memory cell, after applying a read voltage corresponding to the storage state of the memory cell, the on-resistance generated by the memory cell will also increase due to the increase in its threshold voltage, thus causing the discharge current of the sensing node SO to decrease. In this way, after the default discharge time, the voltage of the sensing node SO will be higher than when the threshold voltage is not increased.

[0120] Case 2: In the process of reading a memory cell of any storage state, after applying a read voltage corresponding to the storage state to the memory cell, if the discharge time of the corresponding sensing node SO is increased, the voltage of the sensing node SO will be lower after the sensing node SO is discharged compared to the case where the discharge time of the sensing node is not increased.

[0121] If the threshold voltage of a programmed memory cell is reduced by some means, but the storage state of the memory cell is not changed, after applying a read voltage corresponding to the storage state of the memory cell, the on-resistance generated by the memory cell will also decrease due to the reduction of its threshold voltage, thus causing an increase in the discharge current of the sensing node SO. In this way, after the default discharge time, the voltage of the sensing node SO will be lower than when the threshold voltage is not reduced.

[0122] From the above two situations, it can be seen that shortening the discharge time of the sensing node SO is equivalent to increasing the threshold voltage of the storage unit, which will increase the voltage of the sensing node SO after discharge. Increasing the discharge time of the sensing node SO is equivalent to reducing the threshold voltage of the storage unit, which will reduce the voltage of the sensing node SO after discharge.

[0123] Therefore, in the embodiment of the present application, the discharge time of the sensing node SO can be adjusted to adjust the threshold voltage of the memory cell, thereby reducing the influence of the interlayer interference on the threshold voltage of the memory cell.

[0124] Fig.14 is a flow chart of an operation method of a memory provided in an embodiment of the present application. The memory may be any memory device in the above embodiments. Fig.14 The operation method of the memory provided in the embodiment of the present application is introduced, see Fig.14 , the method comprising:

[0125] Step 1401: Before reading the storage state of the target storage cell, determine the storage state of the reference storage cell.

[0126] Before reading the storage state of the target memory cell, the storage state of the reference memory cell may be determined first. In an embodiment of the present application, the target memory cell may be each memory cell included in a page to be read in the memory. The target memory cell and the reference memory cell are located in the same memory string and are adjacent, and the programming order of the reference memory cell is after the target memory cell. That is, in the process of programming the memory, the programming order of the reference memory cell is before the target memory cell, and the fringe electric field generated by the programming voltage applied to the reference memory cell may affect the threshold voltage of the target memory cell.

[0127] In this step 1401, the storage state of the reference storage cell can be obtained by reading the reference storage cell. In one example, the storage state of the reference storage cell can be obtained by reading the reference storage cell by a conventional reading method, that is, the storage state of the reference storage cell can be read according to the default discharge time of the sensing node. After reading the storage state of the storage cell, the reading result can be stored through a latch.

[0128] For example, when reading each memory cell in the first page coupled to WLn, the storage state of each memory cell in the second page coupled to WLn+1 can be read first. The programming order of WLn+1 is before WLn, and the memory cells in the first page and the memory cells in the second page belong to the same memory string. The memory cells in the first page are target memory cells, and the memory cells in the second page are reference memory cells.

[0129] Step 1402: Determine the discharge duration of the sensing node corresponding to the target memory cell based on the storage state of the reference memory cell.

[0130] refer to Fig.12 , the higher the storage state of the reference memory cell, the higher the programming voltage applied when programming the reference memory cell, and therefore the greater the impact of the interlayer interference on the target memory cell, and the greater the increment of the threshold voltage of the target memory cell caused by the interlayer interference. Therefore, the storage state of the reference memory cell can reflect the increment of the threshold voltage of the target memory cell after the interlayer interference. Therefore, in this step, the discharge duration of the sensing node corresponding to the target memory cell can be determined according to the storage state of the reference memory cell, and then the threshold voltage of the target memory cell can be compensated by adjusting the discharge duration of the sensing node to reduce the impact of the interlayer interference on the target memory cell.

[0131] In one feasible manner, the correspondence between the storage state and the discharge duration of the reference memory cell can be stored in the memory controller. After determining the storage state of each reference memory cell, the discharge duration of the sensing node corresponding to each target memory cell can be determined in the process of reading each target memory cell based on the correspondence.

[0132] For example, in this corresponding relationship, the higher the storage state of the reference storage cell, the longer the corresponding discharge time can be, and the corresponding discharge time of each storage state can be greater than the default discharge time. Increasing the discharge time of the sensing node SO in this way is equivalent to reducing the threshold voltage of the target storage cell, which is equivalent to offsetting the increase in the threshold voltage of the target storage cell caused by the interlayer interference. It should be noted that the specific discharge time corresponding to each storage state can be set by a technician, for example, it can be determined by experimental data, and the specific value of the discharge time is not limited in the embodiment of the present application. In one example, since adjusting the discharge time of the sensing node SO is equivalent to adjusting the threshold voltage of the target storage cell, the read voltage of each storage state can be adaptively adjusted in the process of reading the target storage cell to improve the accuracy of reading the target storage cell.

[0133] In another possible implementation, the storage state range of the storage state of the reference storage cell may be determined, and the discharge time length of the sensing node corresponding to the target storage cell may be determined according to the storage state range of the reference storage cell.

[0134] Among them, the reference storage cells in the same storage state range have similar effects on the target storage cells caused by the interlayer interference generated during programming, so that the target storage cells corresponding to the reference storage cells in the same storage state range can be compensated by the same discharge duration. The number of storage state ranges divided by each storage state and the number of storage states included in each storage state range can be pre-set by the technician, and are not limited in the embodiments of the present application. For example, the storage states of the three-level storage cell include P0~P7 states, wherein P0~P2 states can belong to the same storage state range, P3~P5 states can belong to the same storage state range, and P6~P7 states can belong to the same storage state range.

[0135] In one example, the storage state range can be divided into a first storage state range and a second storage state range, wherein the storage state in the first storage state range is lower than the storage state in the second storage state range. For example, for a three-level storage cell, P0-P3 states can belong to the first storage state range, and P4-P7 states can belong to the second storage state range.

[0136] The discharge time corresponding to the first storage state range is shorter than the default discharge time of the sensing node, and the discharge time corresponding to the second storage state range is longer than the default discharge time of the sensing node.

[0137] refer to Fig.12 Since the storage state of the first storage state range is relatively low, the reference storage cell belonging to the first storage state range has little effect on the threshold voltage of the target storage cell during programming. Since the storage state of the second storage state range is relatively high, the reference storage cell belonging to the second storage state range has a greater effect on the threshold voltage of the target storage cell during programming. Fig.15 As shown, dotted line A represents the threshold voltage distribution of a memory cell of a certain storage state after being affected by memory cells in a first storage state range, and dotted line B represents the threshold voltage distribution of a memory cell of the same storage state after being affected by memory cells in a second storage state range. Fig.15 It can be seen that the threshold voltage distribution of the memory cell affected by the programming of the memory cell in the first storage state range is relatively forward, that is, the threshold voltage increment of the memory cell affected by the interlayer interference is small. The threshold voltage distribution of the memory cell affected by the programming of the memory cell in the second storage state range is relatively backward, that is, the threshold voltage increment of the memory cell affected by the interlayer interference is large.

[0138] Thus, in the embodiment of the present application, the discharge time corresponding to the first storage state range is shortened to less than the default discharge time, which is equivalent to further increasing the threshold voltage of the target storage unit. Fig.15 The dotted line A in the second storage state range moves backward as a whole. Extending the discharge time corresponding to the second storage state range to more than the default discharge time is equivalent to lowering the threshold voltage of the target storage cell. Fig.15 The dotted line B in the figure moves forward as a whole. It can be seen that by setting the discharge time corresponding to the first storage state range and the second storage state range in this way, the target storage cell of each storage state can be effectively Fig.15 The middle dotted line A and the dotted line B are moved closer to the middle, so that the threshold voltage distribution of each storage state becomes narrower. In this way, the overlap between the threshold voltage distributions of each storage state can be reduced, the margin can be increased, and the accuracy of reading the target storage cell can be improved.

[0139] In one example, the discharge duration includes verifying the discharge duration of each storage state, wherein the higher the verified storage state is, the smaller the absolute value of the difference between the corresponding discharge duration and the default discharge duration is.

[0140] refer to Fig.13, storage cells with different storage states are affected by interlayer interference to different degrees. Therefore, in the process of reading the target storage cell, when reading each storage state, you can refer to the second characteristic of interlayer interference, the duration of the sensing node for adjustment. In view of the fact that the discharge duration corresponding to the first storage state range is less than the default discharge duration of the sensing node, and the discharge duration corresponding to the second storage state range is greater than the default discharge duration of the sensing node, in an embodiment of the present application, the higher the verified storage state, the smaller the absolute value of the difference between the corresponding discharge duration and the default discharge duration. Taking the target storage cell as a three-level storage cell as an example, in the process of reading each storage state of the target storage cell, the discharge duration of the corresponding sensing node can be shown in Table 1 below:

[0141] Table 1

[0142] WLn read level Group 1 Group 2 R1 T_sodev_r1_grp1 T_sodev_r1_grp2 R2 T_sodev_r2_grp1 T_sodev_r2_grp2 R3 T_sodev_r3_grp1 T_sodev_r3_grp2 R4 T_sodev_r4_grp1 T_sodev_r4_grp2 R5 T_sodev_r5_grp1 T_sodev_r5_grp2 R6 T_sodev_r6_grp1 T_sodev_r6_grp2 R7 T_sodev_r7_grp1 T_sodev_r7_grp2

[0143] Wherein, R1~R7 are read voltages corresponding to different storage states, Group 1 is the first storage state range, and Group 2 is the second storage state range. When T_sodev_r1_grp1~T_sodev_r7_grp1 respectively apply R1~R7, the duration of the sensing node SO of the target storage unit corresponding to the first storage state range. T_sodev_r1_grp1~T_sodev_r7_grp1 are all less than the default discharge duration and increase in sequence. When T_sodev_r1_grp2~T_sodev_r7_grp2 respectively apply R1~R7, the duration of the sensing node SO of the target storage unit corresponding to the second storage state range. T_sodev_r1_grp2~T_sodev_r2_grp1 are all greater than the default discharge duration and shorten in sequence.

[0144] For the target memory cell corresponding to the reference memory cell belonging to the first storage state range, the duration of the corresponding sensing node needs to be shortened, because the higher the storage state of the target memory cell, the less affected by the interlayer interference, and the smaller the increment of the threshold voltage. Therefore, the higher the storage state of the target memory cell, the less the amount of threshold voltage that needs to be compensated, so the discharge duration of the sensing node SO can be closer to the default discharge duration.

[0145] Similarly, for the target memory cell corresponding to the reference memory cell belonging to the second storage state range, the duration of the corresponding sensing node needs to be extended, because the higher the storage state of the target memory cell, the less affected by the interlayer interference, and the smaller the increment of the threshold voltage. Therefore, the higher the storage state of the target memory cell, the less the amount of threshold voltage that needs to be compensated, so the discharge duration of the sensing node SO can be closer to the default discharge duration.

[0146] It can be seen that in the embodiment of the present application, according to the storage state of the target memory cell being read, the discharge duration of the SO of the sensing node when reading the storage state is further adjusted, which can further and accurately reduce the impact of interlayer interference on the target memory cell and improve the accuracy of reading the target memory cell.

[0147] Step 1403: Based on the discharge duration of the sensing node corresponding to the target storage unit, the target storage unit is read to obtain a reading result.

[0148] After determining the discharge time length of the sensing node corresponding to the target memory cell according to the storage state of the reference memory cell, the storage state of the target memory cell can be read according to the determined discharge time length to obtain a reading result.

[0149] The memory operation method provided in the embodiment of the present application can be applied to each memory read process, and can improve the accuracy of the read. In particular, in some scenarios with high security requirements, such as autonomous driving, aerospace, etc., the application of the embodiment of the present application can also improve the stability of the device in the corresponding scenario to a certain extent, and improve the security of the device application.

[0150] The embodiment of the present application also provides another application idea of ​​the memory operation method, that is, after the memory is read and processed by the traditional method and the reading fails, the memory operation method provided by the embodiment of the present application is applied.

[0151] Combined with the above Fig.10 , Fig.11 It can be seen from the content that the traditional reading method includes that after reading the storage page where the target storage unit is located, if it is determined that FBC is greater than the set first preset value, the default read voltage hard decoding can be performed, if the default read voltage hard decoding fails, the optimal read voltage hard decoding can be performed, and if the optimal read voltage hard decoding fails, the optimal read voltage soft decoding can also be performed. In the embodiment of the present application, the target storage unit can be read in combination with hard decoding failure and / or soft decoding. The following are several application solutions provided by the embodiment of the present application:

[0152] Solution 1: Read the storage page where the target storage cell is located, and in response to the number of error bits FBC of the storage page being greater than a first preset value, perform default read voltage hard decoding, and in response to the default read voltage hard decoding failing to be performed, determine the storage state of the reference storage cell.

[0153] In the first solution, the memory can read the storage page where the target storage unit is located according to the traditional reading method. If the default read voltage hard decoding is triggered during the reading process, and it is determined that the default read voltage hard decoding fails, the operation method provided by the present application can be applied to re-read the storage page where the target storage unit is located. When the first solution is applied, the memory will still read the target storage unit according to the traditional reading method in most cases. Only when the default read voltage hard decoding is triggered and the decoding fails, the operation method provided by the present application is used to read the target storage unit. In this way, there is no need to read the storage state of the reference storage unit before reading the target storage unit every time, and the reading efficiency of the memory will not be reduced.

[0154] like Fig.16 As shown, the memory triggers the default read voltage hard decoding after reading the selected WLn string m. If it is determined that the hard decoding is successful, WLn string m+1 can be further read. If it is determined that the hard decoding fails, the solution of the present application to assist in reading WLn through WLn+1 can be triggered. That is, WLn+1 string m is read first, and the reading result is stored in a temporary latch. After reading WLn+1 string m, the storage cells corresponding to WLn string m can be grouped according to the reading result of WLn+1 string m, and then different discharge durations are set for each group of storage cells. In one example, in order to improve the grouping efficiency, SLC read can be performed on WLn+1 string m, so that only one read of WLn+1 string m can divide the storage cells of WLn string m into two groups. After the storage cells of WLn string m are grouped, WLn string m can be read again according to the discharge duration corresponding to each group of storage cells. If the read is successful, WLn string m+1 can be further read.

[0155] It should be noted that string m and string m+1 refer to the memory slices obtained by dividing the memory area by the top selection gate cut line (TSG-CUT). The memory array is divided into a plurality of blocks by the first gate isolation structure, the blocks are divided into more than two finger memory areas by the second gate isolation structure, and the memory area is divided into more than two memory slices (strings) by the top selection gate cut line.

[0156] In addition, if the target storage unit is read using the operating method provided by the present application, the default read voltage hard decoding is triggered again. Since the operating method provided by the present application can solve the influence of inter-layer interference, when the default read voltage hard decoding is triggered again, the corresponding FBC will be reduced, so the probability of successfully performing the default read voltage hard decoding again can be increased.

[0157] Solution 2: In response to the failure of the default read voltage hard decoding, perform the optimal read voltage hard decoding. In response to the failure of the optimal read voltage hard decoding, determine the storage state of the reference memory cell, and read the target memory cell based on the discharge time and the optimal read voltage of the sensing node corresponding to the target memory cell.

[0158] In the second solution, the memory can read the storage page where the target storage unit is located according to the traditional reading method. If the optimal read voltage hard decoding is triggered during the reading process and the hard decoding fails, the operation method provided by this application can be combined with the optimal read voltage hard decoding to perform the optimal read voltage hard decoding again. Fig.10 , Fig.11 It can be seen from the content that the optimal read voltage hard decoding refers to adjusting the read voltage of each storage state to the optimal read voltage, then re-reading the storage state of each storage cell in the page, and then hard decoding the page according to the read result. Therefore, in the second scheme, when the optimal read voltage hard decoding is triggered during the reading of the storage page where the target storage cell is located and the hard decoding fails, the corresponding discharge duration of each target storage cell in the storage page can be determined according to the storage state of the reference storage cell. Then the storage page can be read according to the optimal read voltage, and during the reading process, each target storage cell sensing node SO is discharged according to the determined discharge duration. In this way, the influence of inter-layer interference when reading the storage page according to the optimal read voltage can be reduced, and the success rate of performing the optimal read voltage hard decoding again can be improved.

[0159] like Fig.17As shown, the memory triggers the optimal read voltage hard decoding after reading the selected WLn string m. If it is determined that the hard decoding is successful, WLn string m+1 can be further read. If it is determined that the hard decoding fails, the solution of assisting the reading of WLn by WLn+1 in the present application can be triggered to perform the optimal read voltage hard decoding again. That is, WLn+1 string m is read first, and the reading result is stored in a temporary latch. After reading WLn+1 string m, the storage cells corresponding to WLn string m can be grouped according to the reading result of WLn+1 string m, and then different discharge durations are set for each group of storage cells. In one example, in order to improve the grouping efficiency, SLC read can be performed on WLn+1 string m, so that only one reading of WLn+1 string m is performed, and the storage cells of WLn string m can be divided into two groups. After the storage cells of WLn string m are grouped, WLn string m can be read again according to the discharge duration corresponding to each group of storage cells, and then the optimal read voltage hard decoding is performed again according to the reading result. If the hard decoding is successful, WLnstring m+1 can be further read.

[0160] Solution 3: In response to the failure of the default read voltage hard decoding, perform the optimal read voltage hard decoding. In response to the failure of the optimal read voltage hard decoding, perform the optimal read voltage soft decoding. In response to the failure of the optimal read voltage soft decoding, determine the storage state of the reference memory cell.

[0161] In the third solution, the memory can read the storage page where the target storage unit is located according to the traditional reading method. If the optimal read voltage soft decoding is triggered during the reading process and the hard decoding fails, the operation method provided by the present application can be combined with the optimal read voltage soft decoding. Fig.10 , Fig.11 As can be seen from the content, the optimal read voltage soft decoding refers to reading the soft data of the page through the soft read voltage, and then soft decoding is performed based on the soft data and hard data of the page. Therefore, in the third scheme, when the optimal read voltage soft decoding is triggered during the reading of the storage page where the target storage cell is located and the soft decoding fails, the corresponding discharge duration of each target storage cell in the storage page can be determined according to the storage state of the reference storage cell. Then, the soft data of the target storage cell in the storage page can be read out according to the optimal read voltage, the first soft read voltage, and the second soft read voltage, and during the reading process, each target storage cell sensing node SO is discharged according to the determined discharge duration. In this way, the influence of inter-layer interference when reading the storage page according to the optimal read voltage can be reduced, the accuracy of reading the soft data of the target storage cell can be improved, and then the success rate of soft decoding based on the soft data and hard data of the target storage cell can be improved.

[0162] In one example, the hard data corresponding to the target storage unit can be obtained by reading through a traditional reading method. That is to say, in the third solution, in the process of reading the target storage unit, the default read voltage hard decoding, the optimal read voltage hard decoding and the optimal read voltage hard decoding are triggered successively. When soft decoding is performed again in combination with the operation method provided in the present application, the hard data required for soft decoding can be obtained by reading the target storage unit in the previous optimal read voltage hard decoding stage. In another example, the hard data corresponding to the target storage unit is obtained by reading the target storage unit based on the discharge time and the optimal read voltage of the sensing node corresponding to the target storage unit. That is to say, in the third solution, in the process of reading the target storage unit, the default read voltage hard decoding, the optimal read voltage hard decoding and the optimal read voltage hard decoding are triggered successively. In the optimal read voltage hard decoding stage, the method described in the second solution can be combined with the target storage unit to read the target storage unit through the discharge time and the optimal read voltage of the sensing node corresponding to the target storage unit to obtain the hard data of the target storage unit. In this way, when the optimal read voltage soft decoding is performed again in the third solution, both the soft data and the hard data are obtained by reading based on the adjusted discharge time, so that the success rate of soft decoding can be improved.

[0163] The embodiment of the present application further provides a memory, which may be the memory device shown in the above embodiment, and includes:

[0164] A memory cell array, the memory cell array comprising a plurality of memory strings, the memory strings comprising a plurality of memory cells;

[0165] A peripheral circuit coupled to the memory cell array, the peripheral circuit being configured to: determine a storage state of a reference memory cell; determine a discharge duration of a sensing node corresponding to a target memory cell based on the storage state of the reference memory cell; and read the target memory cell based on the discharge duration of the sensing node corresponding to the target memory cell to obtain a reading result; wherein the target memory cell and the reference memory cell are located in the same memory string and are adjacent, and the programming order of the reference memory cell is after that of the target memory cell.

[0166] Optionally, the peripheral circuit is configured as:

[0167] Determine a storage state range in which the storage state of the reference storage unit is located, wherein the storage state range includes a first storage state range and a second storage state range, and the storage state in the first storage state range is lower than the storage state in the second storage state range;

[0168] According to the storage state range of the reference memory cell, a discharge time length of the sensing node corresponding to the target memory cell is determined.

[0169] Optionally, the discharge time length corresponding to the first storage state range is shorter than a default discharge time length of the sensing node, and the discharge time length corresponding to the second storage state range is longer than the default discharge time length of the sensing node.

[0170] Optionally, the peripheral circuit is configured as:

[0171] Based on the default discharge time of the sensing node, the reference storage unit is read to obtain the storage state of the reference storage unit.

[0172] Optionally, the peripheral circuit is further configured as:

[0173] Reading a storage page where the target storage unit is located;

[0174] In response to the error bit number FBC of the storage page being greater than a first preset value, performing a default read voltage hard decoding;

[0175] In response to the default read voltage hard decoding failing to be performed, a storage state of the reference memory cell is determined.

[0176] Optionally, the peripheral circuit is further configured as:

[0177] In response to the default read voltage hard decoding failing to be performed, performing optimal read voltage hard decoding;

[0178] In response to the optimal read voltage hard decoding failing to be performed, determining a storage state of the reference memory cell;

[0179] The target memory cell is read based on the discharge time length and the optimal read voltage of the sensing node corresponding to the target memory cell.

[0180] Optionally, the peripheral circuit is further configured as:

[0181] In response to the default read voltage hard decoding failing to be performed, performing optimal read voltage hard decoding;

[0182] In response to the optimal read voltage hard decoding failing to be performed, performing optimal read voltage soft decoding;

[0183] In response to the optimum read voltage soft decoding failing to be performed, a storage state of the reference memory cell is determined.

[0184] Optionally, the peripheral circuit is further configured as:

[0185] Based on the discharge time of the sensing node corresponding to the target storage cell, a first soft read voltage less than the optimal read voltage, and a second soft read voltage greater than the optimal read voltage, the target storage cell is read to obtain soft data corresponding to the target storage cell;

[0186] Based on the soft data and hard data corresponding to the target storage cell, a reading result corresponding to the target storage cell is determined, wherein the hard data corresponding to the target storage cell is obtained by reading the target storage cell based on the optimal read voltage.

[0187] Optionally, the hard data corresponding to the target memory cell is obtained by reading the target memory cell based on the discharge duration of the sensing node corresponding to the target memory cell and the optimal read voltage.

[0188] The description of the memory device embodiment is similar to the description of the above method embodiment, and has similar beneficial effects as the method embodiment. For technical details not disclosed in the memory device embodiment of the present application, please refer to the description of the method embodiment of the present application for understanding.

[0189] The embodiment of the present application also provides a memory system, which can be the above-mentioned Figure 1 A memory system in which the memory device provided by the present application may be included, and a memory controller coupled to the storage unit memory device and configured to control the memory device.

[0190] The description of the memory system embodiment is similar to the description of the above method embodiment, and has similar beneficial effects as the method embodiment. For technical details not disclosed in the memory system embodiment of the present application, please refer to the description of the method embodiment of the present application for understanding.

[0191] In the present application, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance. The term "at least one" means one or more, and the term "plurality" means two or more, unless otherwise clearly defined.

[0192] The above description is only an exemplary embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A method for operating a memory, characterized in that: The method comprises: determining a storage state of a reference storage unit; Determining a discharge duration of a sensing node corresponding to a target storage unit based on a storage state of the reference storage unit; Based on the discharge time of the sensing node corresponding to the target storage unit, the target storage unit is read to obtain a reading result; wherein, The target memory cell and the reference memory cell are located in the same memory string and are adjacent to each other, and a programming sequence of the reference memory cell is subsequent to that of the target memory cell.

2. The method according to claim 1, characterized in that The step of determining the discharge duration of the sensing node corresponding to the target storage unit based on the storage state of the reference storage unit includes: Determine a storage state range in which the storage state of the reference storage unit is located, wherein the storage state range includes a first storage state range and a second storage state range, and the storage state in the first storage state range is lower than the storage state in the second storage state range; According to the storage state range of the reference memory cell, a discharge time length of the sensing node corresponding to the target memory cell is determined.

3. The method according to claim 2, characterized in that The discharge time length corresponding to the first storage state range is shorter than the default discharge time length of the sensing node, and the discharge time length corresponding to the second storage state range is longer than the default discharge time length of the sensing node.

4. The method according to claim 1, characterized in that: Determining the storage state of the reference storage unit includes: Based on the default discharge time of the sensing node, the reference storage unit is read to obtain the storage state of the reference storage unit.

5. The method according to any one of claims 1 to 4, characterized in that: Before determining the storage state of the reference storage unit, the method further includes: Reading a storage page where the target storage unit is located; In response to the error bit number FBC of the storage page being greater than a first preset value, performing a default read voltage hard decoding; Determining the storage state of the reference storage unit includes: In response to the default read voltage hard decoding failing to be performed, a storage state of the reference memory cell is determined.

6. The method according to claim 5, characterized in that Before determining the storage state of the reference storage unit, the method further includes: In response to the default read voltage hard decoding failing to be performed, performing optimal read voltage hard decoding; Determining the storage state of the reference storage unit includes: In response to the optimal read voltage hard decoding failing to be performed, determining a storage state of the reference memory cell; The step of reading the target storage unit based on the discharge duration of the sensing node corresponding to the target storage unit includes: The target memory cell is read based on the discharge time length and the optimal read voltage of the sensing node corresponding to the target memory cell.

7. The method according to claim 5, characterized in that Before determining the storage state of the reference storage unit, the method further includes: In response to the default read voltage hard decoding failing to be performed, performing optimal read voltage hard decoding; In response to the optimal read voltage hard decoding failing to be performed, performing optimal read voltage soft decoding; Determining the storage state of the reference storage unit includes: In response to the optimum read voltage soft decoding failing to be performed, a storage state of the reference memory cell is determined.

8. The method according to claim 7, characterized in that The step of reading the target storage unit based on the discharge duration of the sensing node corresponding to the target storage unit to obtain a reading result includes: Based on the discharge time of the sensing node corresponding to the target storage cell, a first soft read voltage less than the optimal read voltage, and a second soft read voltage greater than the optimal read voltage, the target storage cell is read to obtain soft data corresponding to the target storage cell; Based on the soft data and hard data corresponding to the target storage cell, a reading result corresponding to the target storage cell is determined, wherein the hard data corresponding to the target storage cell is obtained by reading the target storage cell based on the optimal read voltage.

9. The method according to claim 8, characterized in that The hard data corresponding to the target memory cell is obtained by reading the target memory cell based on the discharge duration of the sensing node corresponding to the target memory cell and the optimal read voltage.

10. A memory, characterized in that: The memory comprises: A memory cell array, the memory cell array comprising a plurality of memory strings, the memory strings comprising a plurality of memory cells; A peripheral circuit coupled to the memory cell array, the peripheral circuit being configured to: determine a storage state of a reference memory cell; determine a discharge duration of a sensing node corresponding to a target memory cell based on the storage state of the reference memory cell; and read the target memory cell based on the discharge duration of the sensing node corresponding to the target memory cell to obtain a reading result; wherein the target memory cell and the reference memory cell are located in the same memory string and are adjacent, and the programming order of the reference memory cell is after that of the target memory cell.

11. The memory according to claim 10, characterized in that: The peripheral circuit is configured as: Determine a storage state range in which the storage state of the reference storage unit is located, wherein the storage state range includes a first storage state range and a second storage state range, and the storage state in the first storage state range is lower than the storage state in the second storage state range; According to the storage state range of the reference memory cell, a discharge time length of the sensing node corresponding to the target memory cell is determined.

12. The memory according to claim 11, characterized in that: The discharge time length corresponding to the first storage state range is shorter than the default discharge time length of the sensing node, and the discharge time length corresponding to the second storage state range is longer than the default discharge time length of the sensing node.

13. The memory according to claim 10, characterized in that: The peripheral circuit is configured as: Based on the default discharge time of the sensing node, the reference storage unit is read to obtain the storage state of the reference storage unit.

14. The memory according to any one of claims 10 to 13, characterized in that: The peripheral circuit is further configured as: Reading a storage page where the target storage unit is located; In response to the error bit number FBC of the storage page being greater than a first preset value, performing a default read voltage hard decoding; In response to the default read voltage hard decoding failing to be performed, a storage state of the reference memory cell is determined.

15. The memory according to claim 14, characterized in that: The peripheral circuit is further configured as: In response to the default read voltage hard decoding failing to be performed, performing optimal read voltage hard decoding; In response to the optimal read voltage hard decoding failing to be performed, determining a storage state of the reference memory cell; The target memory cell is read based on the discharge time length and the optimal read voltage of the sensing node corresponding to the target memory cell.

16. The memory according to claim 14, characterized in that: The peripheral circuit is further configured as: In response to the default read voltage hard decoding failing to be performed, performing optimal read voltage hard decoding; In response to the optimal read voltage hard decoding failing to be performed, performing optimal read voltage soft decoding; In response to the optimum read voltage soft decoding failing to be performed, a storage state of the reference memory cell is determined.

17. The memory according to claim 16, characterized in that: The peripheral circuit is further configured as: Based on the discharge time of the sensing node corresponding to the target storage cell, a first soft read voltage less than the optimal read voltage, and a second soft read voltage greater than the optimal read voltage, the target storage cell is read to obtain soft data corresponding to the target storage cell; Based on the soft data and hard data corresponding to the target storage cell, a reading result corresponding to the target storage cell is determined, wherein the hard data corresponding to the target storage cell is obtained by reading the target storage cell based on the optimal read voltage.

18. The memory according to claim 17, characterized in that: The hard data corresponding to the target memory cell is obtained by reading the target memory cell based on the discharge duration of the sensing node corresponding to the target memory cell and the optimal read voltage.

19. A storage system, characterized in that: The storage system comprises: One or more memories as claimed in claim 10; A memory controller coupled to the memory and configured to control the memory.

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