Memory, storage system, and operating method of memory

Abstract

The application discloses a memory, a storage system and an operation method of the memory, and belongs to the technical field of storage. The operation method of the memory comprises the following steps: determining the storage state of a reference storage unit; determining the discharge duration of a sensing node corresponding to a target storage unit based on the storage state of the reference storage unit; and reading the target storage unit based on the discharge duration of the sensing node corresponding to the target storage unit, and obtaining a reading result. The target storage unit and the reference storage unit are located in the same storage string and are adjacent, and the programming sequence of the reference storage unit is after that of the target storage unit. By using the application, the influence of interlayer interference on reading a storage unit can be reduced, and the accuracy of reading a storage unit can be improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of storage, in particular to a memory, a storage system and an operation method of the memory. BACKGROUND

[0002] With the advancement of the processing technology of the memory (for example, a 3D NAND flash memory chip), in order to improve the storage capacity of the memory, the storage units in the memory are more and more dense, which leads to more and more obvious interlayer interference in the memory.

[0003] The interlayer interference refers to the edge electric field generated when the storage unit coupled to any word line in the memory is programmed, which has an impact on the number of stored electrons of the storage unit coupled to the adjacent programmed word line, and further may cause the threshold voltage of the programmed storage unit to change. SUMMARY

[0004] The embodiments of the present application provide a memory, a storage system and an operation method of the memory, which can reduce the influence of interlayer interference on reading the storage unit and improve the accuracy of reading the storage unit. The technical solution is as follows:

[0005] In a first aspect, an operation method of a memory is provided, and the method comprises:

[0006] determining a storage state of a reference storage unit;

[0007] determining a discharge duration of a sensing node corresponding to a target storage unit based on the storage state of the reference storage unit;

[0008] reading the target storage unit based on the discharge duration of the sensing node corresponding to the target storage unit to obtain a reading result; wherein

[0009] The target storage unit and the reference storage unit are located in the same storage string and are adjacent, and the programming order of the reference storage unit is after that of the target storage unit.

[0010] Optionally, the determining the discharge duration of the sensing node corresponding to the target storage unit based on the storage state of the reference storage unit comprises:

[0011] determining a storage state range in which the storage state of the reference storage unit is located, wherein the storage state range comprises a first storage state range and a second storage state range, and the storage state in the first storage state range is lower than that in the second storage state range;

[0012] determining the discharge duration of the sensing node corresponding to the target storage unit according to the storage state range of the reference storage unit.

[0013] Optionally, the discharge duration corresponding to the first storage state range is less than the default discharge duration of the sensing node, and the discharge duration corresponding to the second storage state range is greater than the default discharge duration of the sensing node.

[0014] Optionally, determining the storage state of the reference storage cell includes:

[0015] Based on the default discharge duration of the sensing node, the reference storage unit is read to obtain the storage state of the reference storage unit.

[0016] Optionally, before determining the storage state of the reference storage unit, the method further includes:

[0017] Read the storage page containing the target storage unit;

[0018] In response to the number of fault bits (FBC) of the storage page being greater than a first preset value, a default read voltage hard decoding is performed;

[0019] Determining the storage state of the reference storage unit includes:

[0020] In response to the failure of the default read voltage hard decoding execution, the storage state of the reference storage cell is determined.

[0021] Optionally, before determining the storage state of the reference storage unit, the method further includes:

[0022] In response to the failure of the default read voltage hard decoding, the optimal read voltage hard decoding is performed;

[0023] Determining the storage state of the reference storage unit includes:

[0024] In response to the failure of the optimal read voltage hard decoding execution, the storage state of the reference storage cell is determined;

[0025] The step of reading the target storage unit based on the discharge duration of the sensing node corresponding to the target storage unit includes:

[0026] The target storage unit is read based on the discharge duration and optimal read voltage of the sensing node corresponding to the target storage unit.

[0027] Optionally, before determining the storage state of the reference storage unit, the method further includes:

[0028] In response to the failure of the default read voltage hard decoding, the optimal read voltage hard decoding is performed;

[0029] In response to the failure of the optimal read voltage hard decoding, the optimal read voltage soft decoding is performed;

[0030] Determining the storage state of the reference storage unit includes:

[0031] in response to a failure of the soft decoding performed based on the optimal read voltage, determining a storage state of the reference storage unit.

[0032] Optionally, the reading the target storage unit based on the discharge duration of the sensing node corresponding to the target storage unit comprises:

[0033] reading the target storage unit based on the discharge duration of the sensing node corresponding to the target storage unit, a first soft read voltage less than the optimal read voltage, and a second soft read voltage greater than the optimal read voltage, to obtain soft data corresponding to the target storage unit.

[0034] determining a read result corresponding to the target storage unit based on the soft data and the hard data corresponding to the target storage unit, wherein the hard data corresponding to the target storage unit is obtained by reading the target storage unit based on the optimal read voltage.

[0035] Optionally, the hard data corresponding to the target storage unit is obtained by reading the target storage unit based on the discharge duration of the sensing node corresponding to the target storage unit and the optimal read voltage.

[0036] In a second aspect, a memory is provided, comprising:

[0037] a storage unit array comprising a plurality of storage strings, each storage string comprising a plurality of storage units;

[0038] a peripheral circuit coupled to the storage unit array, the peripheral circuit being configured to: determine a storage state of a reference storage unit; determine a discharge duration of a sensing node corresponding to a target storage unit based on the storage state of the reference storage unit; and read the target storage unit based on the discharge duration of the sensing node corresponding to the target storage unit, to obtain a read result; wherein the target storage unit and the reference storage unit are located in the same storage string and are adjacent, and the programming order of the reference storage unit is after that of the target storage unit.

[0039] Optionally, the peripheral circuit is configured to:

[0040] determine a storage state range in which the storage state of the reference storage unit is located, wherein the storage state range comprises a first storage state range and a second storage state range, and the storage states in the first storage state range are lower than those in the second storage state range;

[0041] determine the discharge duration of the sensing node corresponding to the target storage unit according to the storage state range of the reference storage unit.

[0042] Optionally, the first storage state range corresponds to a discharge duration less than a default discharge duration of the sensing node, and the second storage state range corresponds to a discharge duration greater than the default discharge duration of the sensing node.

[0043] Optionally, the peripheral circuit is configured to:

[0044] read the reference storage unit based on a default discharge duration of the sensing node to obtain a storage state of the reference storage unit.

[0045] Optionally, the peripheral circuit is further configured to:

[0046] read the storage page where the target storage unit is located;

[0047] perform default read voltage hard decoding in response to a number of error bits FBC of the storage page being greater than a first preset value.

[0048] determine the storage state of the reference storage unit in response to the default read voltage hard decoding failing.

[0049] Optionally, the peripheral circuit is further configured to:

[0050] perform optimal read voltage hard decoding in response to the default read voltage hard decoding failing.

[0051] determine the storage state of the reference storage unit in response to the optimal read voltage hard decoding failing.

[0052] read the target storage unit based on a discharge duration of the sensing node corresponding to the target storage unit and an optimal read voltage.

[0053] Optionally, the peripheral circuit is further configured to:

[0054] perform optimal read voltage hard decoding in response to the default read voltage hard decoding failing.

[0055] perform optimal read voltage soft decoding in response to the optimal read voltage hard decoding failing.

[0056] determine the storage state of the reference storage unit in response to the optimal read voltage soft decoding failing.

[0057] Optionally, the peripheral circuit is further configured to:

[0058] read the target storage unit based on a discharge duration of the sensing node corresponding to the target storage unit, a first soft read voltage less than an optimal read voltage, and a second soft read voltage greater than the optimal read voltage, to obtain soft data corresponding to the target storage unit.

[0059] determine a read result corresponding to the target storage unit based on the soft data and the hard data corresponding to the target storage unit, wherein the hard data corresponding to the target storage unit is obtained by reading the target storage unit based on the optimal read voltage.

[0060] Optionally, the hard data corresponding to the target storage unit is obtained by reading the target storage unit based on the optimal read voltage and a discharge duration of the sensing node corresponding to the target storage unit.

[0061] In a third aspect, a storage system is provided, and the storage system includes one or more memories according to the second aspect, and a memory controller coupled to the memories and configured to control the memories.

[0062] The technical scheme provided by the embodiments of the present application has the following beneficial effects:

[0063] In the embodiments of the present application, the discharge duration of the sensing node corresponding to the target storage unit can be determined according to the storage state of the reference storage unit, and then the target storage unit can be read according to the determined discharge duration. Since the storage state of the reference storage unit is related to the programming voltage applied to the reference storage unit, the storage state of the reference storage unit can reflect the degree of influence of the interlayer interference on the target storage unit. Therefore, in the embodiments of the present application, the discharge duration of the sensing node is determined according to the storage state of the reference storage unit, the influence of the interlayer interference on the target storage unit can be reduced by adjusting the discharge duration of the sensing node, and the accuracy of reading the target storage unit can be improved. BRIEF DESCRIPTION OF DRAWINGS

[0064] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0065] Figure 1 is a schematic diagram of an exemplary system having a memory device provided by the embodiments of the present application;

[0066] Figure 2 is a diagram of an exemplary memory card having a memory device provided by the embodiments of the present application;

[0067] Figure 3 is a schematic diagram of an exemplary solid state drive having a memory device provided by the embodiments of the present application;

[0068] Figure 4is a schematic diagram of a memory device including a peripheral circuit provided by embodiments of the present application;

[0069] Figure 5 is a schematic diagram of an exemplary memory cell array including a NAND memory string provided by embodiments of the present application;

[0070] Figure 6 is a schematic diagram of an exemplary memory device including a memory cell array and a peripheral circuit provided by embodiments of the present application;

[0071] Figure 7 is a schematic diagram of a 3D NAND structure provided by embodiments of the present application;

[0072] Figure 8 is a schematic diagram of a memory device including a sensing circuit provided by embodiments of the present application;

[0073] Figure 9 is a schematic diagram of a discharge curve of a sensing node SO provided by embodiments of the present application;

[0074] Figure 10 is a schematic diagram of a read process of hard data provided by embodiments of the present application;

[0075] Figure 11 is a schematic diagram of a read process of soft data provided by embodiments of the present application;

[0076] Figure 12 is a schematic diagram of a threshold voltage distribution of a memory cell provided by embodiments of the present application;

[0077] Figure 13 is a schematic diagram of a threshold voltage distribution of a three-level memory cell provided by embodiments of the present application;

[0078] Figure 14 is a flowchart of a method of operating a memory provided by embodiments of the present application;

[0079] Figure 15 is a schematic diagram of a threshold voltage distribution of a memory cell provided by embodiments of the present application;

[0080] Figure 16 is a flowchart of a method of operating a memory provided by embodiments of the present application;

[0081] Figure 17 is a flowchart of a method of operating a memory provided by embodiments of the present application. DETAILED DESCRIPTION

[0082] In order to make the objects, technical solutions and advantages of the present application clearer, the embodiments of the present application will be further described in detail below with reference to the drawings.

[0083] Figure 1 A block diagram of an exemplary system 100 having a memory device in accordance with some aspects of the present application is shown. The system 100 can be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a gaming console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory device therein. As shown in Figure 1 The system 100 can include a host 108 and a memory system 102 having one or more memory devices 104 and a memory controller 106, as shown in

[0084] The memory device 104 can be any memory device disclosed in the present application. As disclosed in detail below, the memory device 104 (e.g., a NAND flash memory device (e.g., a three-dimensional (3D) NAND flash memory device)) can have reduced leakage current from a drive transistor (e.g., a string driver) coupled to an unselected word line during an erase operation, which allows for further scaling of the drive transistor.

[0085] According to some embodiments, the memory controller 106 is coupled to the memory device 104 and the host 108, and is configured to control the memory device 104. The memory controller 106 can manage data stored in the memory device 104, and communicate with the host 108. In some embodiments, the memory controller 106 is designed for operation in a low duty cycle environment, such as a secure digital (SD) card, compact flash (CF) card, universal serial bus (USB) flash drive, or other media for use in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the memory controller 106 is designed for operation in a high duty cycle environment, such as an SSD or embedded multimedia card (eMMC), which is used as a data storage for mobile devices such as smartphones, tablet computers, laptops, etc. and enterprise storage arrays. The memory controller 106 can be configured to control operations of the memory device 104, such as read, erase, and program processes. The memory controller 106 can also be configured to manage various functions related to data stored in or to be stored in the memory device 104, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some embodiments, the memory controller 106 is also configured to handle error correction codes (ECC) related to data read from or written to the memory device 104. The memory controller 106 can also perform any other suitable functions, such as formatting the memory device 104. The memory controller 106 can communicate with external devices (e.g., the host 108) according to a particular communication protocol. For example, the memory controller 106 can communicate with external devices through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnect (PCI) protocol, a PCI express (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer small interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a Firewire protocol, etc.

[0086] The memory controller 106 and the one or more memory devices 104 can be integrated into various types of storage devices, such as included in the same package (e.g., a universal flash storage (UFS) package or an eMMC package). That is, the memory system 102 can be implemented and packaged into different types of end electronic products. For example, the memory system 102 can be implemented and packaged into a mobile phone, a tablet computer, a laptop computer, a digital camera, a digital camcorder, a digital audio player, a digital video player, a digital radio, a global positioning system (GPS) device, a smart watch, a smart home device, a smart car, a smart appliance, a smart city device, a smart grid device, a smart meter, a smart card, a smart card reader, a smart card terminal, a smart card Figure 2In one example shown, the memory controller 106 and a single memory device 104 can be integrated into the memory card 202. The memory card 202 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 202 may also include a connection between the memory card 202 and a host computer (e.g., Figure 1 The host 108) is coupled to the memory card connector 204. In such a... Figure 3 In another example shown, the memory controller 106 and multiple memory devices 104 can be integrated into the SSD 306. The SSD 306 may also include components for connecting the SSD 306 to a host computer (e.g., ...). Figure 1 The SSD connector 308 is coupled to the host 108. In some embodiments, the storage capacity and / or operating speed of the SSD 306 is greater than the storage capacity and / or operating speed of the memory card 202.

[0087] Figure 4 A schematic circuit diagram of an exemplary memory device 400, including peripheral circuitry, is shown according to some aspects of this application. The memory device 400 may be... Figure 1 An example of memory device 104 is shown. Memory device 400 may include a memory cell array device 401 and peripheral circuitry 402 coupled to the memory cell array device 401. The memory cell array device 401 may be a NAND flash memory cell array, wherein memory cells 406 are provided in the form of an array of NAND memory strings 408, each NAND memory string 408 extending vertically above a substrate (not shown). In some embodiments, each NAND memory string 408 includes a plurality of memory cells 406 coupled in series and stacked vertically. Each memory cell 406 may hold a continuous analog value, such as voltage or charge, depending on the number of electrons trapped in the region of the memory cell 406. Each memory cell 406 may be a floating-gate type memory cell including a floating-gate transistor, or a charge-trapping type memory cell including a charge-trapping transistor.

[0088] In some implementations, each storage unit 406 is a single-level cell (SLC) that has two possible storage states and thus can store one bit of data. For example, a first storage state "0" can correspond to a first voltage range, and a second storage state "1" can correspond to a second voltage range. In some implementations, each storage unit 406 is a multi-level cell (MLC) that is capable of storing more than a single bit of data in more than four memory states. For example, an MLC can store two bits per cell, three bits per cell (also referred to as triple-level cell (TLC)), or four bits per cell (also referred to as quad-level cell (QLC)). Each MLC can be programmed to take a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed to take one of three possible program levels from an erased state by writing one of three possible nominal storage values to the cell. A fourth nominal storage value can be used for the erased state.

[0089] As Figure 4 As shown in FIG. 4A, each NAND storage string 408 can include a source select gate (SSG) 410 at its source end and a drain select gate (DSG) 412 at its drain end. The SSG 310 and the DSG 412 can be configured to activate a selected NAND storage string 408 (column of the array) during read and program processes. In some implementations, the sources of the NAND storage strings 408 in the same block 404 are coupled by the same source line (SL) 414 (e.g., a common SL). In other words, according to some implementations, all of the NAND storage strings 408 in the same block 404 have an array common source (ACS). According to some implementations, the DSG 412 of each NAND storage string 308 is coupled to a respective bit line 416 from which data can be read or written via an output bus (not shown). In some implementations, each NAND storage string 408 is configured to be selected or deselected by applying a select voltage (e.g., above the threshold voltage of the transistors with the DSG 412) or a deselect voltage (e.g., 0 V) to the respective DSG 412 via one or more DSG lines 413 and / or by applying a select voltage (e.g., above the threshold voltage of the transistors with the SSG 410) or a deselect voltage (e.g., 0 V) to the respective SSG 410 via one or more SSG lines 415.

[0090] As Figure 4As shown in FIG. 4, the NAND memory strings 408 can be organized into a plurality of blocks 404, each of which can have a common source line 414 (e.g., coupled to ground). In some embodiments, each block 304 is a basic unit of data for erase operations, i.e., all memory cells 406 on the same block 404 are erased at the same time. To erase the memory cells 406 in a selected block 404a, the source lines 414 coupled to the selected block 404a and to unselected blocks 404b in the same face as the selected block 404a can be biased with an erase voltage (Vers) (e.g., a high positive voltage (e.g., 20V or higher)). It should be appreciated that in some examples, erase operations can be performed at a half-block level, at a quarter-block level, or at a level having any suitable fraction of any suitable number of blocks or blocks. The memory cells 406 of adjacent NAND memory strings 408 can be coupled by word lines 418 that select which row of memory cells 406 is affected by read and program processes. In some embodiments, each word line 418 is coupled to a page 420 of memory cells 406, which is a basic unit of data for program processes. The size of a page 420 in bits can be related to the number of NAND memory strings 408 in a block 404 that are coupled by a word line 418. Each word line 418 can include a plurality of control gates (gate electrodes) at each memory cell 406 in the corresponding page 420 and a gate line that couples the control gates.

[0091] Figure 5 A side view of a cross-section of an exemplary memory cell array 401 including NAND memory strings 408 is shown in accordance with some aspects of the present application. As shown in FIG. 4, the NAND memory strings 408 can be vertically extending through the memory stack 504 above a substrate 502. The substrate 502 can include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), or any other suitable material. Figure 5 As shown in FIG. 4, the NAND memory strings 408 can be vertically extending through the memory stack 504 above a substrate 502. The substrate 502 can include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), or any other suitable material.

[0092] The memory stack 504 can include alternating gate conductive layers 506 and gate-to-gate dielectric layers 508. The number of pairs of gate conductive layers 506 and gate-to-gate dielectric layers 508 in the memory stack 504 can determine the number of memory cells 406 in the memory cell array 401. The gate conductive layers 506 can include a conductive material including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate conductive layer 506 includes a metal layer, e.g., a tungsten layer. In some embodiments, each gate conductive layer 506 includes a doped polysilicon layer. Each gate conductive layer 506 can include a control gate that surrounds a memory cell 406 and can extend laterally at a top of the memory stack 504 as a DSG line 413, at a bottom of the memory stack 504 as a SSG line 415, or between the DSG line 413 and the SSG line 415 as a word line 418.

[0093] As shown in Figure 5 The NAND memory string 408 includes a channel structure 512 that extends vertically through the memory stack 504, as shown in FIG. 5A. In some embodiments, the channel structure 512 includes a channel hole that is filled with a semiconductor material(s) (e.g., as a semiconductor channel 520) and a dielectric material(s) (e.g., as a memory film 518). In some embodiments, the semiconductor channel 520 includes silicon, e.g., polysilicon. In some embodiments, the memory film 518 is a composite dielectric layer that includes a tunneling layer 526, a storage layer 524 (also referred to as a “charge-trapping / storage layer”), and a blocking layer 522. The channel structure 512 can have a cylindrical shape (e.g., a column shape). According to some embodiments, the semiconductor channel 520, the tunneling layer 526, the storage layer 524, and the blocking layer 522 are arranged radially from a center of the column toward an outer surface of the column in this order. The tunneling layer 526 can include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer 524 can include silicon nitride, silicon oxynitride, or any combination thereof. The blocking layer 522 can include silicon oxide, silicon oxynitride, a high dielectric constant (high-k) dielectric, or any combination thereof. In one example, the memory film 518 can include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0094] According to some embodiments, as shown in Figure 5As shown in FIG. 5, the well 514 (e.g., P-well and / or N-well) is formed in the substrate 502, and the source end of the NAND memory string 408 is in contact with the well 514. For example, the source line 414 can be coupled to the well 514 to apply an erase voltage to the well 514 (i.e., the source of the NAND memory string 408) during an erase operation. In some embodiments, the NAND memory string 408 also includes a channel plug 516 at the drain end of the NAND memory string 408. It should be appreciated that although not shown in FIG. 5, additional components of the memory cell array 401 can be formed, including but not limited to gate line slits / source contacts, local contacts, interconnect layers, etc. Figure 5

[0095] Referring back to FIG. 5, Figure 4 The peripheral circuitry 402 can be coupled to the memory cell array 401 by the bit lines 416, the word lines 418, the source line 414, the SSG line 415, and the DSG line 413. The peripheral circuitry 402 can include any suitable analog, digital, and mixed-signal circuitry for facilitating operation of the memory cell array 401 by applying voltage signals and / or current signals to and sensing voltage signals and / or current signals from each target memory cell 406 via the bit lines 416, the word lines 418, the source line 414, the SSG line 415, and the DSG line 413. The peripheral circuitry 402 can include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 6 Some example peripheral circuitry is shown, including a page buffer / sense amplifier 604, a column decoder / bit line driver 606, a row decoder / word line driver 608, a voltage generator 610, control logic 612, registers 614, an interface 616, and a data bus 618. It should be appreciated that additional peripheral circuitry not shown in FIG. 6 can also be included in some examples. Figure 6

[0096] ​​The page buffer / sense amplifier 604 can be configured to read data from and program (write) data to the memory cell array 401 according to control signals from the control logic 612. In one example, the page buffer / sense amplifier 404 can store a page of program data (write data) to be programmed into one page 420 of the memory cell array 401. In another example, the page buffer / sense amplifier 604 can perform a program verify operation to ensure that data has been correctly programmed into the memory cells 406 coupled to the selected word line 418. In yet another example, the page buffer / sense amplifier 604 can also sense low power signals from the bit lines 416 representing data bits stored in the memory cells 406 and amplify the small voltage swings to identifiable logic levels in read operations. The column decoder / bit line driver 606 can be configured to be controlled by the control logic 612 and select one or more NAND memory strings 408 by applying bit line voltages generated from the voltage generator 610.

[0097] The row decoder / word line driver 608 can be configured to be controlled by the control logic 612 and select / deselect blocks 404 of the memory cell array 401 and select / deselect word lines 418 of the blocks 404. The row decoder / word line driver 608 can also be configured to drive the word lines 418 using word line voltages generated from the voltage generator 610. In some implementations, the row decoder / word line driver 608 can also select / deselect and drive the SSG line 415 and the DSG line 413. As described in detail below, the row decoder / word line driver 608 is configured to perform erase operations on the memory cells 606 coupled to the selected word line(s) 618. The voltage generator 610 can be configured to be controlled by the control logic 612 and generate word line voltages (e.g., read voltages, program voltages, pass voltages, local voltages, verify voltages, etc.), bit line voltages, and source line voltages to be supplied to the memory cell array 401.

[0098] The control logic unit 612 can be coupled to each of the peripheral circuits described above and configured to control the operation of each of the peripheral circuits. The registers 614 can be coupled to the control logic unit 612 and include status registers, command registers, and address registers for storing status information, command operation codes (OP codes), and command addresses used to control the operation of each of the peripheral circuits. The interface 616 can be coupled to the control logic unit 612 and act as a control buffer to buffer control commands received from a host (not shown) and relay them to the control logic unit 612, and to buffer status information received from the control logic unit 612 and relay them to the host. The interface 616 can also be coupled to the column decoder / bit line driver 606 via the data bus 618 and act as a data I / O interface and data buffer to buffer data and relay them to or from the memory cell array 401.

[0099] Figure 7 is a structural diagram of a memory device of the present application, which can be a 3D NAND flash memory chip (hereinafter can be referred to as 3D NAND for short) Figure 7 As shown, a plurality of memory strings 701 are included in the 3D NAND, which are arranged along a direction parallel to the bearing surface of the substrate (i.e. the XY plane in Figure 7 Among them, each memory string 701 includes a plurality of (for example, 32 or 64) series-connected memory cells, which are arranged along a direction perpendicular to the bearing surface of the substrate (i.e. the direction Z in Figure 7 Thus, the plurality of memory cells included in the memory cell array device can be arranged in a three-dimensional array on the substrate, thereby forming a memory array.

[0100] As shown in Figure 7As shown, each memory string 701 further includes an upper select gate connected to the drain of the first memory cell, and a lower select gate connected to the source of the last memory cell. The upper select gate is also referred to as a top select gate (TSG) or a drain select gate. The lower select gate is also referred to as a bottom select gate (BSG) or a source select gate. As shown, the gate of each TSG is connected to a drain select line (DSL), the source of each TSG is connected to the drain of the first memory cell in the memory string to which the TSG belongs, and the drain of each TSG is connected to a bit line (BL). The gate of each BSG is connected to a source select line (SSL), the drain of each BSG is connected to the source of the last memory cell in the memory string to which the BSG belongs, and the source of each BSG is connected to a source line (SL).

[0101] As shown in Figure 7 It can be further seen that the 3D NAND includes n BLs (BL0 to BLn) arranged along direction X, x DSLs (DSL0 to DSLx) arranged along direction Y, and x SSLs (SSL0 to SSLx) arranged along direction Y. Here, n and x are integers greater than 1. Each DSL is connected to the gates of n TSGs arranged along direction X, each BL is connected to the drains of x TSGs arranged along direction Y, and each SSL is connected to the gates of n BSGs arranged along direction X. Furthermore, the sources of the BSGs are connected to the same SL, and thus the SL is also referred to as an array common source (ACS).

[0102] Continuing to refer to Figure 7 The memory cells in each memory string 701 share a set of WLs with the memory cells in other memory strings 701. Assuming that each memory string 701 includes m memory cells, the 3D NAND can include m WLs (WL0 to WLm) arranged along direction Z, where m is an integer greater than 1. Here, each WL is connected to the gates of the memory cells in the same layer (i.e., having substantially the same height relative to the bearing surface of the substrate). The programming process of the memory cells is described below: the programming process can be implemented by applying a programming voltage to the gates of the memory cells, and through the programming process, the memory cells can complete storage of the corresponding storage state. It can be further referred to Figure 7 As shown in the structure, when programming any memory cell, the corresponding TSG of the memory cell can be opened by applying a voltage to the DSL of the memory cell, and the memory cell to be programmed can be further selected. For example, when programming the memory cell M0 in the memory string 701, the TSG TSG0 can be opened by applying a voltage to the DSL DSL0, and the memory cell M0 can be further selected. Figure 8When programming memory cell 702, a voltage can be applied to DSL0, and the TSG in memory string 701 is also turned on. On the other hand, different programming voltages can be applied to the WL corresponding to memory cell 702. Each time a programming voltage is applied to WL, a conduction voltage (generally less than 2V) can be applied to the BL corresponding to memory cell 702, thereby enabling the programming voltage applied to WL to act on the control gate of memory cell 702. Additionally, a shielding voltage (generally greater than or equal to 2V) can be applied to other BLs to prevent the programming voltage applied to WL from acting on the control gates of other memory cells besides memory cell 702. In this way, each programming voltage applied to WL can act on different memory cells, thereby causing different memory cells to be written with different memory states.

[0103] Figure 8 A schematic diagram of a memory device according to an embodiment of this application is shown. The memory device 800 may include a memory cell array 801 having a plurality of memory cells C(1,1) to C(M,N) and a sensing circuit 802, wherein M and N are positive integers. The memory cell array 801 may be any of the memory cell arrays shown in the above embodiments, and the sensing circuit 802 may include a plurality of sensing nodes SO( Figure 9 (not shown in the diagram), each sensing node SO is coupled to the bit lines BL1 to BLN of the memory cell, wherein the sensing circuit detects the storage state or threshold voltage of the target memory cell by sensing the voltage or current on the selected bit line BLn.

[0104] Figure 9 This is a schematic diagram of the discharge curve of a sensing node SO provided in an embodiment of this application. Figure 10 As shown, during a read operation, the sensing node SO is first charged to a fixed voltage. The sensing node SO is connected to the memory cell via a bit line. If the applied read voltage during the read operation is sufficient to turn on the memory cell, the sensing node SO will discharge after a certain period (default discharge time ΔT) due to the memory cell's conduction. If the applied read voltage is insufficient to turn on the memory cell or only weakly turns it on, the sensing node SO will hardly discharge after a certain period (ΔT). Based on this, the channel current can be indirectly measured by the voltage change ΔVc of the sensing node SO, thereby obtaining the memory cell's storage state. Typically, the data read to indicate the storage state of the memory cell is called hard data.

[0105] In an example, a page is the minimum unit for reading in the memory. After reading the page, a check mechanism can be used to determine the Fail Bit Count (FBC) corresponding to the reading of the page. The FBC refers to the number of storage cells in the page that fail to read. If the FBC corresponding to the reading of the page is greater than a preset value, a hard decoding of the page can be triggered. The hard decoding can be referred to as a default read hard decoding. If the hard decoding of the page is successful, it means that the storage state of the storage cell that fails to read in the page can be successfully decoded, i.e., the hard data of each storage cell can be successfully read. If the hard decoding of the page fails, it means that the storage state of the storage cell that fails to read in the page cannot be successfully decoded, and a best read hard decoding of the page can be further triggered.

[0106] The best read hard decoding refers to adjusting the read voltage of each storage state to the optimal read voltage, then re-reading the storage state of each storage cell in the page, and then hard decoding the page according to the reading result. After adjusting the read voltage of each storage state to the optimal read voltage, re-reading the storage state of each storage cell in the page can reduce the value of the FBC to a certain extent. At this time, hard decoding the page can improve the success rate of the hard decoding. If the best read hard decoding of the page is successful, it means that the storage state of the storage cell that fails to read in the page can be successfully decoded, i.e., the hard data of each storage cell can be successfully read. If the best read hard decoding of the page fails, it means that the storage state of the storage cell that fails to read in the page cannot be successfully decoded, and a best read soft decoding of the page can be further triggered.

[0107] Optimal read voltage soft decoding refers to reading the soft data of a page using a soft read voltage, and then performing soft decoding based on the soft data and hard data of that page. The soft data indicates the position of the threshold voltage of a memory cell within the threshold voltage distribution of that memory cell. The soft data can provide additional reliability information for the hard data, and its value represents how close the threshold voltage of the memory cell is to the read voltage corresponding to the hard data. The soft read voltage for each memory state can include a first soft read voltage lower than the optimal read voltage corresponding to that memory state and a second soft read voltage higher than the optimal read voltage corresponding to that memory state. If the optimal read voltage soft decoding of the page is successful, it means that the memory state of the memory cell that failed to read within the page can be successfully decoded, i.e., the hard data of each memory cell can be successfully read. If the optimal read voltage soft decoding of the page fails, it means that the memory state of the memory cell that failed to read within the page cannot be successfully decoded, i.e., the read of that page has failed.

[0108] The following combination Figure 11 and Figure 10 The process of reading hard data and soft data is explained. Figure 10 This is a schematic diagram illustrating a hard data reading process provided in an embodiment of this application. Figure 11 As shown, taking a three-level memory cell as an example, each memory cell can be configured to store 3 bits of data in one of eight memory states (P0 to P7). In a three-level memory cell, each physical page corresponds to three logical pages: low page (LP), middle page (MP), and high page (UP). For example, when performing a read operation on a memory cell to read the hard data of the low page, a read voltage V needs to be applied to the word line containing that memory cell first. R1 Read voltage V R1 Used to distinguish between the P0 state and the P1 to P7 states. V is obtained by detecting the potential after the sensing node SO discharges. R1 The corresponding hard read value. In some embodiments, the threshold voltage is less than the read voltage V. R1 The hard read value of the memory cell is 1, and the threshold voltage is greater than the read voltage V. R1 The hard read value of the memory cell is 0. Of course, in other embodiments, the threshold voltage is greater than the read voltage V. R1 The hard read value of the memory cell is 1, and the threshold voltage is less than the read voltage V. R1 The hard read value of the storage unit is 0, and this application embodiment does not impose any restrictions on this.

[0109] Then apply a read voltage V to the word line where the memory cell is located. R5 Among them, the voltage V is read. R5 This is used to distinguish between states P0-P4 and states P5-P7. V is obtained by detecting the discharge of the sensing node SO. R5The corresponding hard read value. In some embodiments, the threshold voltage is less than the read voltage V. R1 The hard read value of the memory cell is 1, and the threshold voltage is greater than the read voltage V. R1 The hard read value of the memory cell is 0. Finally, the read voltage V... R5 The corresponding hard read value is inverted and then compared with the read voltage V. R1 The corresponding hard read value is ORed to obtain the hard data corresponding to the lower page.

[0110] Figure 11 This is a schematic diagram illustrating a soft data reading process provided in an embodiment of this application. Figure 12 As shown, taking reading soft data from a lower page in a TLC as an example, the first step is to apply a read voltage V to the word line containing the memory cell to be read. R1 -ΔV, to obtain the reading voltage V R1 -ΔV corresponds to the soft read value. The value of ΔV can be determined based on the threshold voltage distribution of each memory state in the TLC. The threshold voltage of the memory cell is less than the read voltage V. R1 When -△V, V R1 The soft read value corresponding to -ΔV is 1, meaning the threshold voltage of the memory cell is greater than the read voltage V. R1 When -△V, V R1 The soft read value corresponding to -△V is 0. Then, a read voltage V is applied to the word line containing the memory cell. R1 +△V, to obtain the reading voltage V R1 +△V corresponds to the soft read value. The threshold voltage of the memory cell is less than the read voltage V. R1 When +△V, V R1 The soft read value corresponding to +△V is 1, meaning the threshold voltage of the memory cell is greater than the read voltage V. R1 When +△V, V R1 The soft read value corresponding to +△V is 0. Read the voltage V. R1 -ΔV corresponds to the soft read value and the read voltage V R1 XOR the soft read value corresponding to +△V to obtain V. R1 The corresponding soft read value. Among them, the threshold voltage of the memory cell is greater than V. R1 -△V and less than V R1 When +△V, V R1 The corresponding soft read value is 1, and the threshold voltage of the memory cell is greater than V. R1 +△V or less than V R1 When -△V, V R1 The corresponding soft read value is 0.

[0111] Next, a read voltage V is applied to the word line containing the memory cell to be read. R5 -ΔV and reading voltage VR5 + AV, to obtain V R5 corresponding soft read value. It should be understood that V R5 corresponding soft read value and the above-mentioned V R1 corresponding soft read value. Therefore, it will not be described again. Finally, V R1 corresponding soft read value and V R5 corresponding soft read value are or operated to obtain the soft data of the low page.

[0112] With the advancement of the processing technology of memory devices (such as 3D NAND), the number of stacked layers increases, and the distance between layers decreases, which causes the interlayer interference between adjacent layers of 3D NAND to become more and more obvious.

[0113] The interlayer interference refers to that when the storage unit in any layer of the 3D NAND flash memory chip is programmed, the edge electric field generated by the programming voltage applied to the storage unit will affect the number of electrons stored in the programmed storage unit in the adjacent layer (generally, the number of stored electrons in the storage unit will increase), especially the storage unit in the adjacent layer and corresponding to the same storage string. The change of the number of stored electrons in the programmed storage unit will cause the change of the threshold voltage, which will increase the probability of reading the storage unit incorrectly.

[0114] The applicant found that the interlayer interference has the following characteristics when solving the influence of the interlayer interference on the storage unit.

[0115] Characteristic one: the greater the programming voltage applied to the storage unit, the greater the influence of the edge electric field generated by the programming voltage on the programmed storage unit in the adjacent layer. Figure 12 is a schematic diagram of the threshold voltage distribution of the storage unit in a certain storage state after being affected by the interlayer interference. In Figure 12In FIG. 6, the dashed curve is the threshold voltage distribution of the first storage unit in the storage unit in a certain storage state, and the solid curve is the threshold voltage distribution of the second storage unit in the storage unit in a certain storage state. Among them, the first storage unit is relatively greatly affected by the interlayer interference, that is, the storage state of the storage unit adjacent to the first storage unit and located in the same storage string is relatively high, and the second storage unit is relatively less affected by the interlayer interference, that is, the storage state of the storage unit adjacent to the second storage unit and located in the same storage string is relatively low. The higher the storage state of the storage unit is, the higher the threshold voltage of the storage unit will be, and the higher the programming voltage required to program the storage unit to the corresponding storage state will be. The lower the storage state of the storage unit is, the lower the threshold voltage of the storage unit will be, and the lower the programming voltage required to program the storage unit to the corresponding storage state will be. The high and low of the storage state can be divided by the technician, and the embodiments of the present application are not limited. For example, in the TLC storage unit, the storage states P0-P3 are relatively low storage states, and the storage states P4-P7 are relatively high storage states, wherein the threshold voltages of the storage states P0-P7 increase in turn. From Figure 13 It can be seen that the first storage unit is relatively greatly affected by the interlayer interference, and the threshold voltage increment of the first storage unit is greater than that of the second storage unit.

[0116] Feature two: When the threshold voltage of the programmed storage unit is relatively low (that is, the number of electrons in the storage unit is relatively small), the influence of the edge electric field generated by the programming voltage applied to the adjacent layer of the storage unit is greater. Figure 13 is a schematic diagram of the threshold voltage distribution of the storage unit in different storage states after being affected by the interlayer interference. In Figure 13 , the dashed curve is the threshold voltage distribution of each storage state without being affected by the interlayer interference, and the solid curve is the threshold voltage distribution of each storage state after being affected by the interlayer interference. From Figure 13 It can be seen that the lower the storage state of the storage unit is, the greater the increment of the corresponding threshold voltage after being affected by the interlayer interference. Among them, Figure 13 is only a schematic diagram of the threshold voltage distribution of each storage state of the three-level storage unit before and after being affected by the interlayer interference, and the threshold voltage distribution rule of other types of storage units before and after being affected by the interlayer interference is similar to Figure 14 , and details are not repeated in the embodiments of the present application.

[0117] In order to avoid the problem that the interlayer interference causes the reading error of the storage unit, the present application provides an operating method of a memory, which can compensate the threshold voltage of the target storage unit by adjusting the discharge time of the sensing node, and thus can reduce the influence of the interlayer interference on the storage unit. The principle of the operating method of the memory provided by the present application is introduced as follows:

[0118] Case 1: In the process of reading a storage unit in any storage state, if the discharge duration of the corresponding sensing node SO is shortened after the storage unit is applied with the read voltage corresponding to its storage state, the voltage of the sensing node SO will be higher after the discharge, compared with the case that the discharge duration of the sensing node is not shortened.

[0119] If the threshold voltage of the programmed storage unit is increased by some means without changing the storage state of the storage unit, the on-resistance generated by the storage unit will also increase after the storage unit is applied with the read voltage corresponding to its storage state, because the threshold voltage of the storage unit is increased, thus leading to the decrease of the discharge current of the sensing node SO. Thus, the voltage of the sensing node SO will be higher after the default discharge duration, compared with the case that the threshold voltage is not increased.

[0120] Case 2: In the process of reading a storage unit in any storage state, if the discharge duration of the corresponding sensing node SO is increased after the storage unit is applied with the read voltage corresponding to its storage state, the voltage of the sensing node SO will be lower after the discharge, compared with the case that the discharge duration of the sensing node is not increased.

[0121] If the threshold voltage of the programmed storage unit is decreased by some means without changing the storage state of the storage unit, the on-resistance generated by the storage unit will also decrease after the storage unit is applied with the read voltage corresponding to its storage state, because the threshold voltage of the storage unit is decreased, thus leading to the increase of the discharge current of the sensing node SO. Thus, the voltage of the sensing node SO will be lower after the default discharge duration, compared with the case that the threshold voltage is not decreased.

[0122] From the above two cases, it can be seen that shortening the discharge duration of the sensing node SO, or increasing the threshold voltage of the storage unit, will both lead to the increase of the voltage of the sensing node SO after the discharge.

[0123] Therefore, in the embodiments of the present application, the discharge duration of the sensing node SO can be adjusted to achieve the effect of adjusting the threshold voltage of the storage unit, and thus the influence of the interlayer interference on the threshold voltage of the storage unit can be reduced.

[0124] Figure 14 is a flowchart of an operation method of a memory provided by the embodiments of the present application, which can be any memory device in the above embodiments. The operation method of the memory provided by the embodiments of the present application will be described below with reference to Figure 14 The operation method of the memory provided by the embodiments of the present application will be described below with reference to Figure 12 The method comprises the following steps.

[0125] Step 1401, before reading the storage state of the target storage unit, determine the storage state of the reference storage unit.

[0126] Before reading the storage state of the target storage unit, the storage state of the reference storage unit can be determined first. In the embodiment of the present application, the target storage unit can be each storage unit included in the page to be read in the memory. The target storage unit and the reference storage unit are located in the same storage string and are adjacent, and the programming order of the reference storage unit is after that of the target storage unit. That is, in the programming process of the memory, the programming order of the reference storage unit is before that of the target storage unit, and the edge electric field generated by the programming voltage applied to the reference storage unit can affect the threshold voltage of the target storage unit.

[0127] In this step 1401, the storage state of the reference storage unit can be obtained by reading the reference storage unit. In an example, the storage state of the reference storage unit can be obtained by reading the reference storage unit by a conventional reading method, that is, the storage state of the reference storage unit can be read according to the default discharge duration of the sensing node. After reading the storage state of the storage unit, the reading result can be stored by the latch.

[0128] For example, when reading each storage unit in the first page coupled with WLn, the storage state of each storage unit in the second page coupled with WLn+1 can be read first. Wherein, the programming order of WLn+1 is before that of WLn, and the storage units in the first page and the storage units in the second page belong to the same storage string. The storage units in the first page are the target storage units, and the storage units in the second page are the reference storage units.

[0129] Step 1402, based on the storage state of the reference storage unit, determine the discharge duration of the sensing node corresponding to the target storage unit.

[0130] Reference Figure 12 The higher the storage state of the reference storage unit is, the higher the programming voltage applied when programming the reference storage unit is, and thus the greater the influence of the interlayer interference generated thereon on the target storage unit is, and the greater the increment of the threshold voltage of the target storage unit caused by the interlayer interference is. Therefore, the storage state of the reference storage unit can reflect the increment of the threshold voltage of the target storage unit after the target storage unit is interfered by the interlayer interference. Therefore, in this step, the discharge duration of the sensing node corresponding to the target storage unit can be determined according to the storage state of the reference storage unit, and then the threshold voltage of the target storage unit can be compensated by adjusting the discharge duration of the sensing node, so as to reduce the influence of the interlayer interference on the target storage unit.

[0131] In an implementable manner, a correspondence between a storage state of a reference storage unit and a discharge duration can be stored in the memory controller. After determining the storage state of each reference storage unit, the discharge duration of the sensing node corresponding to each target storage unit in the process of reading each target storage unit can be determined according to the correspondence.

[0132] For example, in the correspondence, the higher the storage state of the reference storage unit, the longer the corresponding discharge duration can be, and the corresponding discharge duration of each storage state can be greater than the default discharge duration. Increasing the discharge duration of the sensing node SO is equivalent to reducing the threshold voltage of the target storage unit, which is equivalent to offsetting the increment of the threshold voltage of the target storage unit caused by the interlayer interference. It should be noted that the specific discharge duration corresponding to each storage state can be set by the technician, for example, by experimental data. In the embodiments of the present application, the specific value of the discharge duration is not limited. In an example, since the discharge duration of the sensing node SO is adjusted, which is equivalent to adjusting the threshold voltage of the target storage unit, the read voltage of each storage state can be adjusted adaptively in the process of reading the target storage unit, so as to improve the accuracy of reading the target storage unit.

[0133] In another implementable manner, a storage state range of the storage state of the reference storage unit can be determined, and the discharge duration of the sensing node corresponding to the target storage unit can be determined according to the storage state range of the reference storage unit.

[0134] Wherein, the reference storage units in the same storage state range have similar influences on the target storage unit caused by the interlayer interference generated during programming, so that the target storage units corresponding to the reference storage units in the same storage state range can be compensated by the same discharge duration. The number of storage state ranges divided by each storage state and the number of storage states included in each storage state range can be set by the technician in advance, which is not limited in the embodiments of the present application. For example, the storage states of the three-level storage unit include P0-P7 states, wherein P0-P2 states can belong to the same storage state range, P3-P5 states can belong to the same storage state range, and P6-P7 states can belong to the same storage state range.

[0135] In an example, the storage state range can be divided into a first storage state range and a second storage state range, wherein the storage state in the first storage state range is lower than the storage state in the second storage state range. For example, for a three-level storage unit, P0-P3 states can belong to the first storage state range, and P4-P7 states can belong to the second storage state range.

[0136] Wherein, the discharge duration corresponding to the first storage state range is less than the default discharge duration of the sensing node, and the discharge duration corresponding to the second storage state range can be greater than the default discharge duration of the sensing node.

[0137] Reference Figure 15 Since the storage state of the first storage state range is relatively low, the reference storage cell belonging to the first storage state range has less impact on the threshold voltage of the target storage cell during programming. Since the storage state of the second storage state range is relatively high, the reference storage cell belonging to the second storage state range has greater impact on the threshold voltage of the target storage cell during programming. As shown in Figure 15 , the dashed line A represents the threshold voltage distribution of the storage cell of a certain storage state after being affected by the storage cell of the first storage state range, and the dashed line B represents the threshold voltage distribution of the storage cell of the same storage state after being affected by the storage cell of the second storage state range. It can be seen from Figure 15 that the threshold voltage distribution of the storage cell after being affected by the programming of the storage cell of the first storage state range is relatively in front, that is, the threshold voltage increment of the storage cell affected by the interlayer interference is small. The threshold voltage distribution of the storage cell after being affected by the programming of the storage cell of the second storage state range is relatively behind, that is, the threshold voltage increment of the storage cell affected by the interlayer interference is large.

[0138] In this way, in the embodiment of the present application, the discharge duration corresponding to the first storage state range is shortened to below the default discharge duration, which is equivalent to further increasing the threshold voltage of the target storage cell. In terms of the effect brought about, it is equivalent to moving the dashed line A in Figure 15 as a whole to the rear. The discharge duration corresponding to the second storage state range is extended to above the default discharge duration, which is equivalent to reducing the threshold voltage of the target storage cell. In terms of the effect brought about, it is equivalent to moving the dashed line B in Figure 15 as a whole to the front. It can be seen that by setting the discharge duration corresponding to the first storage state range and the second storage state range, the threshold voltage distribution of each storage state can be narrowed in the middle, so that the threshold voltage distribution of each storage state is narrowed. In this way, the coincidence degree between the threshold voltage distributions of the storage states can be reduced, the margin can be improved, and the accuracy of reading the target storage cell can be improved. Figure 13

[0139] In an example, the discharge duration includes a discharge duration for verifying each storage state, wherein the higher the verified storage state, the smaller the absolute value of the difference between the corresponding discharge duration and the default discharge duration.

[0140] Reference WLn read level ​, the storage cells with different storage states are not affected by the interlayer interference to different extents. Therefore, in the process of reading the target storage cell, the length of the sensing node can be adjusted in reference to the characteristics of the interlayer interference when reading each storage state. In combination with the fact that the discharge length corresponding to the first storage state range is less than the default discharge length of the sensing node, and the discharge length corresponding to the second storage state range is greater than the default discharge length of the sensing node, in the embodiments of the present application, the higher the verified storage state is, the smaller the absolute value of the difference between the corresponding discharge length and the default discharge length is. Taking the target storage cell as a three-level storage cell as an example, the discharge length of the corresponding sensing node in the process of reading each storage state of the target storage cell can be shown in Table 1 as follows:

[0141] Table 1

[0142] Group 1 Group 2 T_sodev_r1_grp1 R1 T_sodev_r1_grp2 T_sodev_r2_grp1 R2 T_sodev_r2_grp2 T_sodev_r3_grp1 R3 T_sodev_r3_grp2 T_sodev_r4_grp1 R4 T_sodev_r4_grp2 T_sodev_r5_grp1 R5 T_sodev_r5_grp2 T_sodev_r6_grp1 R6 T_sodev_r6_grp2 T_sodev_r7_grp1 R7 T_sodev_r7_grp2 Figure 10

[0143] wherein R1-R7 are read voltages corresponding to different storage states, Group 1 is the first storage state range, and Group 2 is the second storage state range. T_sodev_r1_grp1-T_sodev_r7_grp1 are the lengths of the sensing node SO of the target storage cell corresponding to the first storage state range when R1-R7 are applied respectively. T_sodev_r1_grp1-T_sodev_r7_grp1 are all less than the default discharge length and increase successively. T_sodev_r1_grp2-T_sodev_r7_grp2 are the lengths of the sensing node SO of the target storage cell corresponding to the second storage state range when R1-R7 are applied respectively. T_sodev_r1_grp2-T_sodev_r7_grp2 are all greater than the default discharge length and decrease successively.

[0144] For the target storage cell corresponding to the reference storage cell belonging to the first storage state range, the length of the corresponding sensing node needs to be shortened. Since the higher the storage state of the target storage cell is, the less the target storage cell is affected by the interlayer interference, the smaller the increment of the threshold voltage is. Therefore, the higher the storage state of the target storage cell is, the less the amount of threshold voltage that needs to be compensated is, and therefore the discharge length of the sensing node SO can be closer to the default discharge length.

[0145] Similarly, for the target storage cell corresponding to the reference storage cell belonging to the second storage state range, the length of the corresponding sensing node needs to be lengthened. Since the higher the storage state of the target storage cell is, the less the target storage cell is affected by the interlayer interference, the smaller the increment of the threshold voltage is. Therefore, the higher the storage state of the target storage cell is, the less the amount of threshold voltage that needs to be compensated is, and therefore the discharge length of the sensing node SO can be closer to the default discharge length.

[0146] It can be seen that, in the embodiment of the present application, the discharge duration of the SO of the sensing node when reading the storage state is further adjusted according to the storage state of the target storage unit, which can further and accurately reduce the influence of interlayer interference on the target storage unit and improve the accuracy of reading the target storage unit.

[0147] In step 1403, the target storage unit is read based on the discharge duration of the sensing node corresponding to the target storage unit, and a read result is obtained.

[0148] After determining the discharge duration of the sensing node corresponding to the target storage unit according to the storage state of the reference storage unit, the storage state of the target storage unit can be read according to the determined discharge duration, and a read result is obtained.

[0149] The operation method of the memory provided in the embodiment of the present application can be applied in each reading process of the memory, which can improve the accuracy of reading. Especially in some high-security scenarios such as autonomous driving, aerospace, etc., the application of the embodiment of the present application can also improve the stability of the device in the corresponding scenario to a certain extent and improve the security of the device application.

[0150] The embodiment of the present application also provides another application idea of the operation method of the memory, that is, after the memory is read by the traditional method and the reading fails, the operation method of the memory provided in the embodiment of the present application is applied.

[0151] According to the above Figure 11 , Figure 16 It can be seen that the traditional reading method includes reading the storage page where the target storage unit is located, and if it is determined that the FBC is greater than the first preset value, the default read voltage hard decoding can be performed, if the default read voltage hard decoding fails, the optimal read voltage hard decoding can be performed, and if the optimal read voltage hard decoding fails, the optimal read voltage soft decoding can be performed. The embodiment of the present application can read the target storage unit in combination with hard decoding failure and / or soft decoding. The following are several application schemes provided by the embodiment of the present application:

[0152] Scheme one: reading the storage page where the target storage unit is located, in response to the number of error bits FBC of the storage page being greater than the first preset value, performing default read voltage hard decoding, and in response to the default read voltage hard decoding failing, determining the storage state of the reference storage unit.

[0153] In this first scheme, the memory can read the memory page containing the target memory cell using the conventional read method. If a default read voltage hard decoding is triggered during the read process, and it is determined that the default read voltage hard decoding has failed, the operation method provided in this application can be used to reread the memory page containing the target memory cell. Using this first scheme, in most cases, the memory will still read the target memory cell using the conventional read method; only when the default read voltage hard decoding is triggered and decoding fails will the operation method provided in this application be used to read the target memory cell. This eliminates the need to read the storage state of the reference memory cell before reading the target memory cell each time, thus not reducing the memory's read efficiency.

[0154] like Figure 10 As shown, after reading the selected WLn string m, the memory triggers a default read voltage hard decode. If the hard decode is successful, WLn string m+1 can be read further. If the hard decode fails, the scheme of assisting in reading WLn through WLn+1 can be triggered. That is, WLn+1 string m is read first, and the read result is stored in a temporary latch. After reading WLn+1 string m, the memory cells corresponding to WLn string m can be grouped according to the read result of WLn+1 string m, and then a different discharge duration is set for each group of memory cells. In one example, to improve the grouping efficiency, SLC read can be performed on WLn+1 string m, so that WLn string m can be divided into two groups with only one read. After grouping the memory cells of WLn string m, WLn string m can be read again according to the discharge duration corresponding to each group of memory cells. If the read is successful, WLn string m+1 can be read further.

[0155] It should be noted that string m and string m+1 refer to the memory slices obtained after dividing the memory area by the top selected gate cut (TSG-CUT). Specifically, the memory array is divided into multiple blocks by the first gate isolation structure, each block is divided into two or more finger memory areas by the second gate isolation structure, and each finger memory area is divided into two or more memory slices by the top selected gate cut.

[0156] In addition, if the read operation is performed on the target storage unit by using the operation method provided in the present application, the default read voltage hard decoding is triggered again, and due to the operation method provided in the present application, the influence of the interlayer interference can be solved, so that the corresponding FBC is reduced when the default read voltage hard decoding is triggered again, and thus the success probability of the default read voltage hard decoding can be improved.

[0157] Option two: in response to the failure of the default read voltage hard decoding, performing the optimal read voltage hard decoding, in response to the failure of the optimal read voltage hard decoding, determining the storage state of the reference storage unit, and performing the read operation on the target storage unit based on the discharge time of the sensing node corresponding to the target storage unit and the optimal read voltage.

[0158] In the present option two, the memory can perform the read operation on the storage page in which the target storage unit is located according to the conventional read method. If the optimal read voltage hard decoding is triggered during the read operation and the hard decoding fails, the operation method provided in the present application can be combined with the optimal read voltage hard decoding to perform the optimal read voltage hard decoding again. According to the above Figure 11 , Figure 17 It can be known from the above content that the optimal read voltage hard decoding refers to adjusting the read voltage of each storage state to the optimal read voltage, then performing the read operation on the storage state of each storage unit in the page again, and then performing the hard decoding on the page according to the read result. Therefore, in the present option two, after the optimal read voltage hard decoding is triggered during the read operation of the storage page in which the target storage unit is located and the hard decoding fails, the corresponding discharge time of each target storage unit in the storage page can be determined according to the storage state of the reference storage unit. Then, the read operation can be performed on the storage page according to the optimal read voltage, and during the read operation, each target storage unit sensing node SO discharges according to the determined discharge time. In this way, the influence of the interlayer interference on the read operation of the storage page according to the optimal read voltage can be reduced, and the success probability of the optimal read voltage hard decoding can be improved.

[0159] As Figure 10As shown, the memory triggers the optimal read voltage hard decoding after reading the selected WLn string m, and if it is determined that the hard decoding is successful, WLn string m+1 can be further read. If it is determined that the hard decoding fails, the optimal read voltage hard decoding is triggered again by the scheme of the present application for assisting reading WLn through WLn+1. That is, WLn+1 string m is read first, and the read result is stored in a temporary latch. After reading WLn+1 string m, the storage cells corresponding to WLn string m can be grouped according to the read result of WLn+1 string m, and then different discharge durations are set for each group of storage cells. In an example, to improve the grouping efficiency, SLC read can be performed on WLn+1 string m, so that only one reading of WLn+1 string m can divide the storage cells of WLn string m into two groups. After grouping the storage cells of WLn string m, WLn string m is read again according to the discharge duration corresponding to each group of storage cells, and then the optimal read voltage hard decoding is performed again according to the read result. If the hard decoding is successful, WLn string m+1 can be further read.

[0160] Scheme three: in response to the failure of the default read voltage hard decoding, the optimal read voltage hard decoding is performed. In response to the failure of the optimal read voltage hard decoding, the optimal read voltage soft decoding is performed. In response to the failure of the optimal read voltage soft decoding, the storage state of the reference storage cell is determined.

[0161] In the present scheme three, the memory can read the storage page in which the target storage cell is located according to the conventional reading method. If the optimal read voltage soft decoding is triggered during the reading process and the hard decoding fails, the operation method provided by the present application can be combined with the optimal read voltage soft decoding. As described above Figure 11 、 Figure 1 From the above content, it can be known that the optimal read voltage soft decoding refers to reading the soft data of the page through the soft read voltage, and then performing soft decoding according to the soft data and the hard data of the page. Therefore, in the present scheme three, after the optimal read voltage soft decoding is triggered during the reading process of the storage page in which the target storage cell is located and the soft decoding fails, the discharge duration corresponding to each target storage cell in the storage page can be determined according to the storage state of the reference storage cell. Then the soft data of the target storage cell in the storage page can be read according to the optimal read voltage, the first soft read voltage and the second soft read voltage, and during the reading process, each target storage cell sensing node SO discharges according to the determined discharge duration. In this way, the influence of the interlayer interference when reading the storage page according to the optimal read voltage can be reduced, the accuracy of reading the soft data of the target storage cell can be improved, and then the success rate of soft decoding according to the soft data and the hard data of the target storage cell can be improved.

[0162] In an example, the hard data corresponding to the target storage unit can be obtained by a conventional read method. That is, in the third scheme, the default read voltage hard decoding, the optimal read voltage hard decoding and the optimal read voltage hard decoding are triggered in sequence during the reading of the target storage unit. When the optimal read voltage soft decoding is performed again according to the operation method provided in the present application, the hard data required for the soft decoding can be obtained in the optimal read voltage hard decoding stage. In another example, the hard data corresponding to the target storage unit is obtained by reading the target storage unit based on the discharge duration of the sensing node corresponding to the target storage unit and the optimal read voltage. That is, in the third scheme, the default read voltage hard decoding, the optimal read voltage hard decoding and the optimal read voltage hard decoding are triggered in sequence during the reading of the target storage unit. In the optimal read voltage hard decoding stage, the target storage unit can be read by the optimal read voltage based on the discharge duration of the sensing node corresponding to the target storage unit according to the manner described in the second scheme. In this way, when the optimal read voltage soft decoding is performed again in the third scheme, the soft data and the hard data are both obtained based on the discharge duration after adjustment, so that the success rate of soft decoding can be improved.

[0163] The embodiments of the present application also provide a memory, which can be the memory device shown in the above embodiments. The memory comprises:

[0164] a storage unit array, the storage unit array comprising a plurality of storage strings, the storage string comprising a plurality of storage units;

[0165] a peripheral circuit coupled to the storage unit array, the peripheral circuit being configured to: determine a storage state of a reference storage unit; determine a discharge duration of a sensing node corresponding to a target storage unit based on the storage state of the reference storage unit; and read the target storage unit based on the discharge duration of the sensing node corresponding to the target storage unit to obtain a read result, wherein the target storage unit and the reference storage unit are located in the same storage string and are adjacent, and the programming order of the reference storage unit is after that of the target storage unit.

[0166] Optionally, the peripheral circuit is configured to:

[0167] determine a storage state range in which the storage state of the reference storage unit is located, wherein the storage state range comprises a first storage state range and a second storage state range, and the storage state in the first storage state range is lower than that in the second storage state range;

[0168] determine the discharge duration of the sensing node corresponding to the target storage unit according to the storage state range of the reference storage unit.

[0169] Optionally, the first storage state range corresponds to a discharge duration less than a default discharge duration of the sensing node, and the second storage state range corresponds to a discharge duration greater than the default discharge duration of the sensing node.

[0170] Optionally, the peripheral circuit is configured to:

[0171] read the reference storage unit based on a default discharge duration of the sensing node to obtain a storage state of the reference storage unit.

[0172] Optionally, the peripheral circuit is further configured to:

[0173] read a storage page where the target storage unit is located;

[0174] perform default read voltage hard decoding in response to a number of error bits FBC of the storage page being greater than a first preset value.

[0175] determine the storage state of the reference storage unit in response to the default read voltage hard decoding failing to be performed.

[0176] Optionally, the peripheral circuit is further configured to:

[0177] perform optimal read voltage hard decoding in response to the default read voltage hard decoding failing to be performed.

[0178] determine the storage state of the reference storage unit in response to the optimal read voltage hard decoding failing to be performed.

[0179] read the target storage unit based on a discharge duration of the sensing node corresponding to the target storage unit and an optimal read voltage.

[0180] Optionally, the peripheral circuit is further configured to:

[0181] perform optimal read voltage hard decoding in response to the default read voltage hard decoding failing to be performed.

[0182] perform optimal read voltage soft decoding in response to the optimal read voltage hard decoding failing to be performed.

[0183] determine the storage state of the reference storage unit in response to the optimal read voltage soft decoding failing to be performed.

[0184] Optionally, the peripheral circuit is further configured to:

[0185] read the target storage unit based on a discharge duration of the sensing node corresponding to the target storage unit, a first soft read voltage less than an optimal read voltage, and a second soft read voltage greater than the optimal read voltage to obtain soft data corresponding to the target storage unit.

[0186] determine a read result corresponding to the target storage unit based on the soft data and the hard data corresponding to the target storage unit, wherein the hard data corresponding to the target storage unit is obtained by reading the target storage unit based on the optimal read voltage.

[0187] Optionally, the hard data corresponding to the target storage unit is obtained by reading the target storage unit based on the optimal read voltage and a discharge duration of a sensing node corresponding to the target storage unit.

[0188] The description of the memory device embodiments is similar to the description of the method embodiments, and has similar beneficial effects as the method embodiments. For technical details not disclosed in the memory device embodiments of the present application, please refer to the description of the method embodiments for understanding.

[0189] The embodiments of the present application also provide a memory system. The memory system can be the memory system as described above, for example, the memory system can include the memory device provided by the present application, and a memory controller coupled to the memory device and configured to control the memory device. ​

[0190] The description of the memory system embodiments is similar to the description of the method embodiments, and has similar beneficial effects as the method embodiments. For technical details not disclosed in the memory system embodiments of the present application, please refer to the description of the method embodiments for understanding.

[0191] In the present application, the terms "first" and "second" are only for descriptive purposes, and cannot be understood as indicating or implying relative importance. The term "at least one" means one or more, and the term "multiple" means two or more, unless otherwise explicitly limited.

[0192] The above description is only exemplary embodiments of the present application, and is not intended to limit the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.​

Claims

1. A method for operating a memory, characterized in that, The method includes: Determine the storage state of the reference memory cell; Based on the storage state of the reference storage cell, the discharge duration of the sensing node corresponding to the target storage cell is determined; Based on the discharge duration of the sensing node corresponding to the target storage unit, the target storage unit is read to obtain the reading result; wherein, The target storage unit and the reference storage unit are located in the same storage string and are adjacent to each other, and the programming order of the reference storage unit is after that of the target storage unit.

2. The method according to claim 1, characterized in that, Determining the discharge duration of the sensing node corresponding to the target storage unit based on the storage state of the reference storage unit includes: Determine the range of storage states in which the storage state of the reference storage cell is located, wherein the range of storage states includes a first storage state range and a second storage state range, and the storage states in the first storage state range are lower than the storage states in the second storage state range; The discharge duration of the sensing node corresponding to the target storage unit is determined based on the storage state range of the reference storage unit.

3. The method according to claim 2, characterized in that, The discharge duration corresponding to the first storage state range is less than the default discharge duration of the sensing node, and the discharge duration corresponding to the second storage state range is greater than the default discharge duration of the sensing node.

4. The method according to claim 1, characterized in that, Determining the storage state of the reference storage unit includes: Based on the default discharge duration of the sensing node, the reference storage unit is read to obtain the storage state of the reference storage unit.

5. The method according to any one of claims 1 to 4, characterized in that, Before determining the storage state of the reference storage unit, the method further includes: Read the storage page containing the target storage unit; In response to the number of fault bits (FBC) of the storage page being greater than a first preset value, a default read voltage hard decoding is performed; Determining the storage state of the reference storage unit includes: In response to the failure of the default read voltage hard decoding execution, the storage state of the reference storage cell is determined.

6. The method according to claim 5, characterized in that, Before determining the storage state of the reference storage unit, the method further includes: In response to the failure of the default read voltage hard decoding, the optimal read voltage hard decoding is performed; Determining the storage state of the reference storage unit includes: In response to the failure of the optimal read voltage hard decoding execution, the storage state of the reference storage cell is determined; The step of reading the target storage unit based on the discharge duration of the sensing node corresponding to the target storage unit includes: The target storage unit is read based on the discharge duration and optimal read voltage of the sensing node corresponding to the target storage unit.

7. The method according to claim 5, characterized in that, Before determining the storage state of the reference storage unit, the method further includes: In response to the failure of the default read voltage hard decoding, the optimal read voltage hard decoding is performed; In response to the failure of the optimal read voltage hard decoding, the optimal read voltage soft decoding is performed; Determining the storage state of the reference storage unit includes: In response to the failure of the optimal read voltage soft decoding execution, the storage state of the reference storage cell is determined.

8. The method according to claim 7, characterized in that, The step of reading the target storage unit based on the discharge duration of the sensing node corresponding to the target storage unit to obtain the reading result includes: Based on the discharge duration of the sensing node corresponding to the target storage unit, the first soft read voltage which is less than the optimal read voltage, and the second soft read voltage which is greater than the optimal read voltage, the target storage unit is read to obtain the soft data corresponding to the target storage unit. Based on the soft data and hard data corresponding to the target storage unit, the read result corresponding to the target storage unit is determined, wherein the hard data corresponding to the target storage unit is obtained by reading the target storage unit based on the optimal read voltage.

9. The method according to claim 8, characterized in that, The hard data corresponding to the target storage unit is obtained by reading the target storage unit based on the discharge duration of the sensing node corresponding to the target storage unit and the optimal read voltage.

10. A memory, characterized in that, The memory includes: A storage cell array, wherein the storage cell array comprises multiple storage strings, and the storage string comprises multiple storage cells; A peripheral circuit coupled to the memory cell array is configured to: determine the storage state of a reference memory cell; determine the discharge duration of a sensing node corresponding to a target memory cell based on the storage state of the reference memory cell; and read the target memory cell based on the discharge duration of the sensing node corresponding to the target memory cell to obtain a read result; wherein the target memory cell and the reference memory cell are located in the same memory string and are adjacent to each other, and the programming order of the reference memory cell is after that of the target memory cell.

11. The memory according to claim 10, characterized in that, The peripheral circuit is configured as follows: Determine the range of storage states in which the storage state of the reference storage cell is located, wherein the range of storage states includes a first storage state range and a second storage state range, and the storage states in the first storage state range are lower than the storage states in the second storage state range; The discharge duration of the sensing node corresponding to the target storage unit is determined based on the storage state range of the reference storage unit.

12. The memory according to claim 11, characterized in that, The discharge duration corresponding to the first storage state range is less than the default discharge duration of the sensing node, and the discharge duration corresponding to the second storage state range is greater than the default discharge duration of the sensing node.

13. The memory according to claim 10, characterized in that, The peripheral circuit is configured as follows: Based on the default discharge duration of the sensing node, the reference storage unit is read to obtain the storage state of the reference storage unit.

14. The memory according to any one of claims 10 to 13, characterized in that, The peripheral circuit is also configured to: Read the storage page containing the target storage unit; In response to the number of fault bits (FBC) of the storage page being greater than a first preset value, a default read voltage hard decoding is performed; In response to the failure of the default read voltage hard decoding execution, the storage state of the reference storage cell is determined.

15. The memory according to claim 14, characterized in that, The peripheral circuit is also configured to: In response to the failure of the default read voltage hard decoding, the optimal read voltage hard decoding is performed; In response to the failure of the optimal read voltage hard decoding execution, the storage state of the reference storage cell is determined; The target storage unit is read based on the discharge duration and optimal read voltage of the sensing node corresponding to the target storage unit.

16. The memory according to claim 14, characterized in that, The peripheral circuit is also configured to: In response to the failure of the default read voltage hard decoding, the optimal read voltage hard decoding is performed; In response to the failure of the optimal read voltage hard decoding, the optimal read voltage soft decoding is performed; In response to the failure of the optimal read voltage soft decoding execution, the storage state of the reference storage cell is determined.

17. The memory according to claim 16, characterized in that, The peripheral circuit is also configured to: Based on the discharge duration of the sensing node corresponding to the target storage unit, a first soft read voltage that is less than the optimal read voltage, and a second soft read voltage that is greater than the optimal read voltage, the target storage unit is read to obtain the soft data corresponding to the target storage unit. Based on the soft data and hard data corresponding to the target storage unit, the read result corresponding to the target storage unit is determined, wherein the hard data corresponding to the target storage unit is obtained by reading the target storage unit based on the optimal read voltage.

18. The memory according to claim 17, characterized in that, The hard data corresponding to the target storage unit is obtained by reading the target storage unit based on the discharge duration of the sensing node corresponding to the target storage unit and the optimal read voltage.

19. A storage system, characterized in that, The storage system includes: One or more memories as described in claim 10; A memory controller coupled to the memory and configured to control the memory.

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