Memory controller performing efficient error correction code decoding and memory device including same

Abstract

A memory controller performing efficient error correction code coding and a memory device including the same are provided. The memory controller includes: a data formatter receiving first to Nth hard decision data and first to Nth soft decision data, and performing a formatting operation on the first to Nth hard decision data and the first to Nth soft decision data; and an error correction code (ECC) circuit receiving the first to Nth hard decision data and the first to Nth soft decision data from the data formatter, and correcting an error on the first page by an ECC decoding process, in which the data formatter performs a formatting operation, the first to Nth hard decision data and the first to Nth soft decision data are provided to the ECC circuit in an order different from an order in which they are received from the memory device.

Description

Technical Field

[0001] The inventive concept relates to a memory controller, and more particularly, to a memory controller for performing efficient error correction code (ECC) decoding, a memory device communicating with the memory controller, and a method of operating the memory controller. Background Art

[0002] A non-volatile memory device includes a plurality of memory cells capable of storing data in a non-volatile manner. Flash memory, an example of such a device, is widely used in cell phones, digital cameras, personal digital assistants (PDAs), mobile computing devices, and stationary computing devices, among others.

[0003] Memory devices are capable of writing or reading data by various methods. For example, in response to a read request, these devices may generate hard decision data and soft decision data. The hard decision data is obtained by using a normal read level having a specific voltage level, while the soft decision data is obtained by using an offset read level having a specific value deviating from the normal read level. To correct data errors, a memory controller may perform soft decision error correction by using the hard decision data and the soft decision data from the memory device.

[0004] However, in soft decision error correction, the memory controller performs error correction after both hard decision data and soft decision data are received. Therefore, this method may cause a longer error correction time and require additional buffer space to temporarily store hard decision data and / or soft decision data. Summary of the invention

[0005] The inventive concept provides a memory controller having improved error correction code (ECC) decoding process efficiency using hard decision data and soft decision data, and a memory device including the memory controller.

[0006] According to an embodiment of the inventive concept, a memory controller is provided, the memory controller comprising: a data formatter, the data formatter being configured to receive, for first to N-th sectors on a first page of a memory device, first to N-th hard decision data read based on a normal read level and first to N-th soft decision data read based on an offset read level, and perform a formatting operation on the first to N-th hard decision data and the first to N-th soft decision data (where N is an integer of 2 or greater); and an error correction code (ECC) circuit, the ECC The circuit is configured to receive the first to Nth hard decision data and the first to Nth soft decision data from the data formatter, and to correct errors on the first page through an ECC decoding process, wherein the data formatter performs the formatting operation so that the first to Nth hard decision data and the first to Nth soft decision data are provided to the ECC circuit in an order different from an order in which the first to Nth hard decision data and the first to Nth soft decision data are received from the memory device.

[0007] According to an embodiment of the present invention, a memory controller is provided, the memory controller comprising: a data formatter, the data formatter being configured to receive, for a first sector to an Nth sector on a first page of a memory device, first hard decision data to an Nth hard decision data read based on a normal read level and first soft decision data to an Nth soft decision data read based on an offset read level, and perform a formatting operation on the first hard decision data to the Nth hard decision data and the first soft decision data to the Nth soft decision data (where N is an integer of 2 or greater); and an ECC circuit, the ECC circuit being configured to receive the first hard decision data to the Nth hard decision data from the data formatter and format the first soft decision data to the Nth soft decision data. The memory device comprises a memory controller and a data formatter, wherein the first soft decision data to the Nth soft decision data are compressed in the memory device and provided to the memory controller so that the size of each of the first soft decision data to the Nth soft decision data is smaller than the size of the corresponding first hard decision data to the Nth hard decision data, and the data formatter continuously provides the first hard decision data and the first soft decision data of the first sector to the ECC circuit and performs the formatting operation so that the first dummy data is provided to the ECC circuit after the first soft decision data.

[0008] According to an embodiment of the inventive concept, a storage device is provided, the storage device comprising: a memory device, the memory device comprising one or more pages, each page comprising a first sector to an Nth sector (where N is an integer of 2 or greater); and a memory controller, the memory controller being configured to control a storage operation of the memory device and receive first hard decision data to Nth hard decision data and first soft decision data to Nth soft decision data of the first sector to the Nth sector on each page of the memory device, wherein the memory controller comprises: an ECC circuit, the ECC circuit being configured to receive the first hard decision data to the Nth hard decision data and the first soft decision data to the Nth soft decision data, and correct an error on each page through an ECC decoding process; and a data formatter, the data formatter being configured to perform a formatting operation so that the first hard decision data to the Nth hard decision data and the first soft decision data to the Nth soft decision data are provided to the ECC circuit in an order different from an order in which the first hard decision data to the Nth hard decision data and the first soft decision data to the Nth soft decision data are received from the memory device. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Embodiments of the present invention will be more clearly understood through the following detailed description in conjunction with the accompanying drawings, in which:

[0010] Figure 1 is a block diagram illustrating a memory system according to an embodiment;

[0011] Figure 2A and Figure 2B is a diagram illustrating example generation of hard decision data and soft decision data;

[0012] Figure 3 is a flow chart illustrating a method of operating a storage device according to an embodiment;

[0013] Figure 4A , Figure 4B and Figure 4C is a diagram illustrating various formatting operations according to an embodiment;

[0014] Figure 5A , Figure 5B , Figure 5C and Figure 5D is a diagram showing the time required for error correction code (ECC) decoding processing according to the embodiment;

[0015] Figure 6 and Figure 7 is a block diagram showing an example of a data formatter according to an embodiment;

[0016] Figure 8 It shows the operation Figure 7 A flowchart of a method for a memory device;

[0017] Fig. 9 and Fig.10 It is shown separately Figure 7 FIG. 1 is a diagram showing an example of a data formatting operation in a memory device of FIG. 1 and an example of a time required for an ECC decoding process;

[0018] Fig.11 is a schematic diagram showing a Figure 1 A diagram of a structure of a memory device;

[0019] Fig.12 is a diagram showing a method according to an embodiment of the present invention. Figure 1 A diagram of a memory cell array;

[0020] Fig.13 is a perspective view showing a memory block according to an embodiment;

[0021] Fig.14 is a block diagram illustrating a memory system according to another embodiment;

[0022] Fig.15 , Fig.16 and Fig.17 is a diagram showing an example of an ECC decoding process and the time required for the ECC decoding process according to some embodiments;

[0023] Fig.18A and Fig.18B An example of a memory system according to an embodiment is shown;

[0024] Fig.19 is a block diagram showing an example in which a memory device according to an embodiment is applied to a solid state drive system. DETAILED DESCRIPTION

[0025] Hereinafter, embodiments of the inventive concept will be described in detail with reference to the accompanying drawings.

[0026] Figure 1 is a block diagram showing a memory system 10 according to an embodiment.

[0027] refer to Figure 1 , the memory system 10 may include a memory controller 100 and a memory device 200. The memory device 200 may include a memory cell array 210, a page buffer circuit 220, and a control logic 230. The control logic 230 may include a data output setting unit 231. In addition, the memory controller 100 may include a command generator 110, an error correction code (ECC) circuit 120, and a data formatter 130.

[0028] For example, the memory system 10 can communicate with the host via various interfaces such as Universal Serial Bus (USB), MultiMediaCard (MMC), embedded MMC (eMMC), Peripheral Component Interconnect (PCI), PCI-Express (PCI-E), Advanced Technology Attachment (ATA), Serial-ATA, Parallel-ATA, Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), Firewire, Universal Flash Storage (UFS), and Non-Volatile Memory Express (NVMe).

[0029] According to an embodiment, the memory device 200 may include a non-volatile memory device such as a flash memory. In some embodiments, the memory system 10 may be embedded in an electronic device or provided as a removable memory. For example, the memory system 10 may be provided in various forms such as an embedded UFS memory device, an embedded multimedia card (eMMC), a solid state drive (SSD), a UFS memory card, a compact flash card (CF), a secure digital (SD) card, a micro secure digital (Micro-SD) card, a mini secure digital (Mini-SD) card, an extreme digital (xD) card, and a memory stick. In addition, the memory system 10 stores data in a non-volatile manner and can therefore be referred to as a storage device.

[0030] The memory controller 100 may control the memory device 200 to read data stored in the memory device 200 or write data on the memory device 200 in response to a write / read request from the host HOST. For example, the memory controller 100 may provide an address ADD, a command CMD, and a control signal CTRL to the memory device 200, and control a program operation, a read operation, and an erase operation of the memory device 200. In addition, data DATA to be stored in the memory device 200 and data DATA read from the memory device 200 may be transmitted and received between the memory controller 100 and the memory device 200. For example, the memory controller 100 may include a processor, and the processor may control all operations in the memory controller 100 and a storage operation of the memory device 200.

[0031] The memory cell array 210 may include a plurality of memory cells, and the plurality of memory cells may include, for example, flash memory cells. Hereinafter, an embodiment in which the plurality of memory cells include Not AND (NAND) flash memory cells is described in detail as an example. However, the inventive concept is not limited thereto. In some embodiments, the plurality of memory cells may include resistive memory cells, such as resistive RAM (ReRAM) memory cells, phase change RAM (PRAM) memory cells, and magnetic RAM (MRAM) memory cells.

[0032] In an embodiment, the memory cell array 210 may include a three-dimensional memory cell array, the three-dimensional memory cell array may include a plurality of NAND strings, and each NAND string may include memory cells respectively connected to word lines vertically stacked on a substrate. However, the inventive concept is not limited thereto. In some embodiments, the memory cell array 210 may include a two-dimensional memory cell array, and the two-dimensional memory cell array may include a plurality of NAND strings arranged in row and column directions.

[0033] In response to a read command provided from the memory controller 100 to the memory device 200, a read operation may be performed under the control of the control logic 230. For example, when each memory cell stores a plurality of bits, the memory cells of the memory cell array 210 may include a plurality of threshold voltage distributions, and data including two or more bits may be read from each memory cell.

[0034] The page buffer circuit 220 may store data read from the memory cell array 210 in units of specific pages, and may include a plurality of page buffers respectively arranged to correspond to a plurality of bit lines. In addition, each page buffer may include one or more latches, and information read from each memory cell during a read process may be stored in the one or more latches.

[0035] When determining the data stored in the memory cell, a read operation using one or more read levels may be performed. For example, hard decision data and soft decision data may be read from each memory cell. The hard decision data may correspond to data based on a normal read level in a normal read operation. The soft decision data may correspond to data based on an offset read level, and the offset read level has a characteristic offset value from the normal read level. For example, compared to the normal read level, the offset read level may include a read level having a positive (+) offset value and a read level having a negative (-) offset value, and the soft decision data may be generated based on a combination of read results according to the positive (+) offset value and the negative (-) offset value.

[0036] The control logic 230 may control all operations of the memory device 200. For example, based on the command CMD, address ADD, and control signal CTRL received from the memory controller 100, the control logic 230 may output various internal control signals for programming data in the memory cell array 210 or reading data from the memory cell array 210. In addition, according to an embodiment, the control logic 230 may control the internal operation of the memory device 200 in response to a read command provided from the memory controller 100 to generate hard decision data and soft decision data. The memory controller 100 may perform an ECC decoding process using the received hard decision data and soft decision data. For example, the memory controller 100 may perform an error correction operation such as a low-density parity check (LDPC).

[0037] The hard decision data and soft decision data described above may be provided to the memory controller 100 according to various strategies. For example, when an error occurs in normal data (e.g., hard decision data) read from the memory device 200, the memory device 200 may generate soft decision data under the control of the memory controller 100. In addition, regardless of the error detection result of the normal data, the memory device 200 may generate and provide hard decision data and soft decision data in response to a read command from the memory controller 100. In addition, a separate read command different from a read command for requesting normal data may be established. Upon receiving the separate read command, the memory device 200 may generate hard decision data and soft decision data, and output the hard decision data and soft decision data to the memory controller 100.

[0038] As described above, hard decision data and soft decision data can be generated according to various strategies. Regardless of the error detection result of normal data, the memory device 200 described in the following embodiments generates hard decision data and soft decision data in response to a read command from the memory controller 100, and provides the hard decision data and soft decision data to the memory controller 100.

[0039] A specific operation example according to the embodiment is described below.

[0040] In addition to the read command, the command generator 110 may also generate various types of commands for requesting to write data and erase data. The command generator 110 may provide a read command to the memory device 200, and receive hard decision data and soft decision data from the memory device 200. For example, the memory device 200 may output hard decision data to the memory controller 100, and then output soft decision data. In other words, the hard decision data may be output before the soft decision data. Alternatively, the memory device 200 may output soft decision data to the memory controller 100, and then output hard decision data. In other words, the soft decision data may be output before the hard decision data. For example, the memory device 200 may adjust the output order of the hard decision data and the soft decision data according to an internal setting operation, a setting operation controlled by the memory controller 100, or a command type received from the memory controller 100. In an embodiment, when the command generator 110 generates a first type of read command, the memory device 200 may output the hard decision data first. In addition, when the command generator 110 generates a second type of read command, the memory device 200 may output the soft decision data first. As an example, Figure 1 The embodiment shows a case where the data output setting unit 231 performs an internal setting operation according to the setting information stored in the memory device 200, thereby setting the output order of the hard decision data and the soft decision data.

[0041] The ECC circuit 120 may correct data errors by performing an ECC decoding process using hard decision data and / or soft decision data. For example, the ECC circuit 120 may include an ECC decoder, and the ECC decoder may correct errors using only hard decision data, or use hard decision data and soft decision data together to correct errors. In an embodiment, the ECC decoding process using only hard decision data may be referred to as normal decoding, and the ECC decoding process using hard decision data and soft decision data together may be referred to as soft decision decoding.

[0042] In addition, the data formatter 130 may optimize the data format of the ECC decoding process of the ECC circuit 120. The data formatter 130 may use the hard decision data and the soft decision data provided from the memory device 200, format them accordingly, and provide the formatted hard decision data and the soft decision data to the ECC circuit 120. For example, the data formatter 130 may perform a formatting operation to change the order in which the hard decision data and the soft decision data are input to the ECC circuit 120. For example, when one page includes a plurality of sectors and hard decision data and soft decision data are generated for each sector, the data formatter 130 may perform a formatting operation that changes the order in which the hard decision data and the soft decision data of the plurality of sectors are provided to the ECC circuit 120.

[0043] For example, if the set mode is to output hard decision data first, hard decision data of a plurality of sectors may be output to the memory controller 100 first, and then soft decision data may be output to the memory controller 100. Alternatively, if the set mode is to output soft decision data first, soft decision data of a plurality of sectors may be output to the memory controller 100 first, and then hard decision data may be output to the memory controller 100. When receiving the hard decision data and the soft decision data of each sector, the memory controller 100 may perform an ECC decoding operation on the corresponding sector.

[0044] The data formatter 130 may perform a formatting operation on the hard decision data and the soft decision data received from the memory device 200. The data formatter 130 provides the formatted data to the ECC circuit 120 to shorten the time required for the ECC decoding process. For example, the data formatter 130 may perform a formatting operation so that for each sector, the hard decision data and the soft decision data are continuously provided to the ECC circuit 120. In addition, the data formatter 130 may determine that error correction using soft decision decoding does not need to be performed on a specific sector. Based on this determination, data formatting may be performed so that the soft decision data of at least one sector is not provided to the ECC circuit 120.

[0045] According to the above-described embodiment, the memory controller 100 can provide the ECC circuit 120 with formatted data capable of performing a fast ECC decoding process using a formatting operation on hard decision data and soft decision data of a plurality of sectors provided from the memory device 200. Therefore, the operation performance of the memory system 10 employing the memory device 200 can be improved.

[0046] In addition, the memory controller 100 may perform the formatting operation according to the embodiment based on hardware, software or a combination thereof. For example, the memory controller 100 may include a processor, an operation memory, and a module (e.g., a data formatting module) containing a set of commands related to the formatting operation stored in the operation memory, and the processor may perform the formatting operation by running the data formatting module.

[0047] Figure 2A and Figure 2B is a diagram showing generation of hard decision data and soft decision data as an example.

[0048] In an embodiment, hard decision data and soft decision data may be generated together in the same read operation. For example, hard decision data and soft decision data may be determined by different read levels, and hard decision data corresponding to a normal read level and soft decision data corresponding to an offset read level may be generated using different sensing timings in one sensing section. For example, when the sensing timing is relatively fast, a data value may be determined based on a relatively low threshold voltage level. On the other hand, when the sensing timing is relatively slow, a data value may be determined based on a relatively high threshold voltage level.

[0049] refer to Figure 1 as well as Figure 2A and Figure 2B , the memory device 200 may output data as hard decision data HD based on the normal read level, and may output data as soft decision data SD based on the offset read level. The offset read level may include a first offset read level (offset 1) and a second offset read level (offset 2), the level of the first offset read level (offset 1) being smaller than the normal read level by a first offset value, and the level of the second offset read level (offset 2) being larger than the normal read level by a second offset value. The memory device 200 may generate soft decision data SD based on a value determined using the first offset read level (offset 1) and the second offset read level (offset 2). The first offset value and the second offset value may be equal to or different from each other.

[0050] For example, the value of the hard decision data HD of a memory cell having a threshold voltage lower than the normal read level may be "1", while the value of the hard decision data HD of a memory cell having a threshold voltage higher than the normal read level may be "0". The value of the soft decision data SD of a memory cell having a threshold voltage lower than the first offset read level (Offset 1) or higher than the second offset read level (Offset 2) may be "0". On the other hand, the value of the soft decision data SD of a memory cell having a threshold voltage between the first offset read level (Offset 1) and the second offset read level (Offset 2) may be "1". For example, the soft decision data SD having a value of "0" may have a strong error, while the soft decision data SD having a value of "1" may have a weak error. When detecting / correcting a data error, various parameters such as coefficients used in error correction calculations may be calculated based on the hard decision data HD and the soft decision data SD generated as described above.

[0051] Figure 2B An example is shown in which hard decision data HD and soft decision data SD are generated through the same sensing operation.

[0052] The read operation may include multiple sections, such as a precharge section, a development section, and a sensing section. The precharge section, the development section, and the sensing section may be arranged sequentially. In the precharge section, the voltage applied to the bit line may rise to a precharge voltage having a specific level. The voltage level of the bit line may change according to the data stored in the memory cell during the development section. For example, when the memory cell is programmed with a relatively low threshold voltage corresponding to the on-cell, the voltage level of the bit line may drop rapidly. On the other hand, when the memory cell is programmed with a relatively high threshold voltage corresponding to the off-cell, the voltage level of the bit line may drop slowly.

[0053] In the sensing section, at least two different sensing operations may be performed to determine hard decision data HD and soft decision data SD. For example, as the sensing timing is early, the data value may be determined based on a relatively low read level. On the other hand, as the sensing timing is delayed, the data value may be determined based on a relatively high read level. According to the sensing timing performed in the sensing section, the data value may be determined based on a first offset read level (offset 1), a normal read level, and a second offset read level (offset 2). In addition, the hard decision data HD and the soft decision data SD may be generated by the sensing operation.

[0054] Figure 3 is a flowchart illustrating a method of operating a storage device according to an embodiment. Figure 3 The embodiment of shows such an example that one page includes the first sector to the Nth sector, and the hard decision data HD and the soft decision data SD of each sector are provided to the memory controller. When describing the following embodiments, the term "data" may refer to normal data (or hard decision data) provided to the host, or may include hard decision data and soft decision data. In addition, the term "data" may refer to the data of one sector or may include data of a plurality of sectors belonging to one page.

[0055] The memory controller may receive the hard decision data HD and the soft decision data SD on the page in a random order (S11). For example, according to the setting of the memory device or the read command provided from the memory controller to the memory device, the memory controller may first receive the hard decision data HD of the first sector to the Nth sector, or may first receive the soft decision data SD of the first sector to the Nth sector. The memory controller may include a data formatter, and the data formatter may perform a formatting operation on the received hard decision data HD and the soft decision data SD.

[0056] For example, the data formatter may continuously (or sequentially) provide the hard decision data HD and the soft decision data SD of the first sector to the ECC circuit (S12). The ECC circuit may perform an ECC decoding process on the first sector, and the data formatter may continuously provide the hard decision data HD and the soft decision data SD of the second sector to the ECC circuit (S13). In other words, the ECC decoding process may be performed on the first sector while receiving the hard decision data HD and the soft decision data SD of the second sector. For example, the ECC decoding process of the first sector may be performed in parallel with the operation of providing the hard decision data HD and the soft decision data SD of the second sector to the ECC circuit, and then, the ECC circuit may perform the ECC decoding process on the second sector after the ECC decoding process on the first sector is completed.

[0057] According to the above process, the ECC decoding process can be performed on all sectors of a page. For example, the ECC decoding process can be performed on the (N-1)th sector, and the data formatter can provide the hard decision data HD and the soft decision data SD of the Nth sector to the ECC circuit (S14). When the ECC circuit performs the ECC decoding process on the Nth sector (S15), the ECC decoding process on the first sector to the Nth sector on the page may have been completed.

[0058] According to the related art, when the ECC circuit performs ECC decoding processing on a specific sector, the ECC decoding of the sector needs to wait until the hard decision data HD or the soft decision data SD of another sector is received. However, according to the above embodiment, the ECC circuit can serve as an ECC decoding unit to receive the hard decision data HD and the soft decision data SD of each sector from the first sector to the Nth sector together, and therefore, the ECC decoding processing speed can be improved.

[0059] Figure 4A , Figure 4B and Figure 4C is a diagram showing various formatting operations according to an embodiment. When describing the following embodiment, the following case is described as an example, that is, one page of the memory device includes a first sector, a second sector, a third sector, and a fourth sector, and hard decision data and soft decision data are generated for each sector. In addition, the size of one page can be 16 kilobytes (KB), and the sizes of the first sector to the fourth sector can all be 4KB.

[0060] In an embodiment, the soft decision data of the first to fourth sectors may be compressed in the memory device and provided to the memory controller 300. Various types of compression algorithms such as lossy compression and lossless compression may be applied to the compression operation. For example, assuming that the compression ratio is 1 / 4, the size of the hard decision data of each sector may be 4KB, but the size of the soft decision data of each sector may be 1KB. The hard decision data of the first to fourth sectors may correspond to the first hard decision data HD0, the second hard decision data HD1, the third hard decision data HD2, and the fourth hard decision data HD3, respectively, and the soft decision data of the first to fourth sectors may correspond to the first soft decision data SD0, the second soft decision data SD1, the third soft decision data SD2, and the fourth soft decision data SD3, respectively.

[0061] The soft decision data compressed from the first sector to the fourth sector may be decompressed in the memory controller 300. For example, Figure 4A , Figure 4B and Figure 4C As shown, the decompression operation may be performed in the ECC circuit 320, and the ECC circuit 320 may include a decompressor. Figure 4A , Figure 4B and Figure 4C In the example shown, the decompressor and the ECC decoder are shown as separate components, but the decompressor may be provided in the ECC decoder.

[0062] like Figure 4A As shown, the memory controller 300 may receive first to fourth hard decision data HD0 to HD3 and first to fourth soft decision data SD0 to SD3 read from one page. The memory controller 300 may sequentially receive the first to fourth hard decision data HD0 to HD3 and the first to fourth soft decision data SD0 to SD3. For example, the memory controller 300 may receive the first to fourth hard decision data HD0 to HD3, and then receive the first to fourth soft decision data SD0 to SD3. The data formatter 310 may receive a data input Data_IN having a format corresponding to the order of data provided from the memory device, generate a data output Data_OUT by changing the order of data received as the data input Data_IN by performing a formatting operation, and provide the generated data output Data_OUT to the ECC circuit 320.

[0063] For example, Figure 4AAs shown, the data formatter 310 may provide the first hard decision data HD0 and the first soft decision data SD0 to the ECC circuit 320, and then provide the second hard decision data HD1 and the second soft decision data SD1 to the ECC circuit 320. In addition, sequentially, the data formatter 310 may provide the third hard decision data HD2 and the third soft decision data SD2 to the ECC circuit 320, and then provide the fourth hard decision data HD3 and the fourth soft decision data SD3 to the ECC circuit 320. In this case, the ECC circuit 320 may continuously receive the hard decision data and the soft decision data by sector, and immediately perform an ECC decoding process on them. For example, the ECC circuit 320 may perform an ECC decoding process on the first sector when the first soft decision data SD0 is completely received. In this case, the first sector may correspond to the first hard decision data HD0 and the first soft decision data SD0.

[0064] The memory controller 300 may generate the following based on its own formatting operation: Figure 4A The formatting results shown are independent of the order in which the data is provided from the memory device. Figure 4B As shown, the memory controller 300 may receive the first soft decision data SD0 to the fourth soft decision data SD3, and then receive the first hard decision data HD0 to the fourth hard decision data HD3. The memory controller 300 may perform a formatting operation on the received data to Figure 4A The same sequence is used to provide data output Data_OUT. For example, Figure 4B As shown, the data formatter 310 may provide the first hard decision data HD0 and the first soft decision data SD0 to the ECC circuit 320, and then provide the second hard decision data HD1 and the second soft decision data SD1 to the ECC circuit 320. In addition, sequentially, the third hard decision data HD2 and the third soft decision data SD2 may be provided to the ECC circuit 320, and then the fourth hard decision data HD3 and the fourth soft decision data SD3 may be provided to the ECC circuit 320.

[0065] The memory controller 300 may perform various other formatting operations on the first to fourth hard decision data HD0 to HD3 and the first to fourth soft decision data SD0 to SD3 provided from the memory device. Figure 4CAs shown, the memory controller 300 may receive the first hard decision data HD0 to the fourth hard decision data HD3, and then receive the first soft decision data SD0 to the fourth soft decision data SD3. The data formatter 310 may provide the first soft decision data SD0 to the fourth soft decision data SD3 to the ECC circuit 320 by performing a formatting operation on the received data, and then provide the first hard decision data HD0 to the fourth hard decision data HD3 to the ECC circuit 320. In this case, the ECC circuit 320 may receive the first soft decision data SD0 to the fourth soft decision data SD3 having a size of 4KB, and then immediately perform an ECC decoding process upon receiving the hard decision data of each sector, instead of starting the ECC decoding process after receiving all the first hard decision data HD0 to the fourth hard decision data HD3 having a size of 16KB. Therefore, the ECC decoding process for the sectors of one page may be performed more quickly.

[0066] In addition, in an embodiment, when the memory device first provides soft decision data of a plurality of sectors, the memory controller 300 may skip the formatting operation described in the above embodiment. For example, when the operating environment of the memory device is set to output soft decision data first, the memory controller 300 may skip the formatting operation described in the above embodiment. Figure 4C The data is received from the memory device in the order corresponding to the formatting result shown. Therefore, the ECC decoding process can be performed according to the order of the data received from the memory device without performing a separate formatting operation.

[0067] Figure 5A , Figure 5B , Figure 5C and Figure 5D is a diagram showing the time required for ECC decoding processing according to an embodiment. Figure 5A , Figure 5B , Figure 5C and Figure 5D In FIG. 1 , data input Data_IN and data output Data_OUT represent data provided to the ECC circuit and data output from the ECC circuit, respectively. Figure 5A , Figure 5B , Figure 5C and Figure 5D In the example shown, the first soft decision decoding SD0_DECODE, the second soft decision decoding SD1_DECODE, the third soft decision decoding SD2_DECODE and the fourth soft decision decoding SD3_DECODE can be performed corresponding to the first sector to the fourth sector. Figure 5A , Figure 5B , Figure 5C and Figure 5DThe t_DMA shown represents the time required to input and output data of 4KB in size. For example, it is assumed that the time required for each soft decision decoding corresponds to 1×t_DMA.

[0068] Figure 5A and Figure 5B A case where the formatting operation according to the embodiment is not performed is shown.

[0069] Figure 5A FIG. 2 shows a case where hard decision data and soft decision data are provided to the ECC circuit in units of 4 KB for each sector without performing compression on the soft decision data. Figure 5A , the first hard decision data HD0 and the first soft decision data SD0 of the first sector may be provided to the ECC circuit, and the ECC circuit may perform the first soft decision decoding SD0_DECODE on the first sector. In this case, it may take 3×t_DMA for the ECC circuit to receive the first hard decision data HD0 and the first soft decision data SD0 and perform the first soft decision decoding SD0_DECODE.

[0070] The error in the first hard decision data HD0 can be corrected according to the result of the soft decision decoding, and the error-corrected first data HD0_OUT (hereinafter referred to as the error-corrected first data HD0_OUT) can be output. In addition, the second hard decision data HD1 and the second soft decision data SD1 of the second sector can be provided to the ECC circuit, and the reception of the second hard decision data HD1 and the output of the error-corrected first data HD0_OUT can be performed in parallel. Next, the second data HD1_OUT in which the error is corrected according to the result of the second soft decision decoding SD1_DECODE can be output. According to the above process, the error-corrected third data HD2_OUT and the error-corrected fourth data HD3_OUT can be output. In the above-described Figure 5A In the example shown, it takes 13×t_DMA to output all error-corrected data from the first to fourth sectors, and 11×t_DMA to receive all first to fourth hard decision data HD0 to HD3 and first to fourth soft decision data SD0 to SD3.

[0071] Figure 5B 1 shows a case where the first to fourth soft decision data SD0 to SD3 are compressed, and then the first to fourth hard decision data HD0 to HD3 and the first to fourth soft decision data SD0 to SD3 are sequentially provided to the ECC circuit. Figure 5B, it takes 5×t_DMA time to provide the first hard decision data HD0 to the fourth hard decision data HD3 and the first soft decision data SD0 to the fourth soft decision data SD3 to the ECC circuit. In an embodiment, the first soft decision data SD0 to the fourth soft decision data SD3 can be decompressed in the ECC circuit, and the decompressed first soft decision data SD0 to the fourth soft decision data SD3 can be used for soft decision decoding.

[0072] The ECC circuit can perform soft decision decoding by using both hard decision data and soft decision data, and therefore, soft decision decoding can only be performed after the first soft decision data SD0 to the fourth soft decision data SD3 are completely received. For example, after the first soft decision data SD0 to the fourth soft decision data SD3 are completely received, the ECC circuit can sequentially perform the first soft decision decoding SD0_DECODE to the fourth soft decision decoding SD3_DECODE on the first sector to the fourth sector. After completing the soft decision decoding for each sector, the ECC circuit can immediately output the error-corrected data. For example, after executing the first soft decision decoding SD0_DECODE, the error-corrected first data HD0_OUT can be output, and after executing the second soft decision decoding SD1_DECODE, the error-corrected second data HD1_OUT can be output, and so on. According to Figure 5B In the example shown, it takes 10×t_DMA time to output all error-corrected data from the first sector to the fourth sector.

[0073] Figure 5C and Figure 5D A case where a formatting operation according to an embodiment is performed is shown.

[0074] refer to Figure 5C , the memory controller can perform a formatting operation on the first hard decision data HD0 to the fourth hard decision data HD3 and the first soft decision data SD0 to the fourth soft decision data SD3 received from the memory device, and can provide the formatted data to the ECC circuit to reduce the time required for the ECC decoding process. For example, the first hard decision data HD0 and the first soft decision data SD0 can be continuously provided to the ECC circuit through the formatting operation, and the time taken to perform the process can correspond to 1.25×t_DMA. When the first soft decision decoding SD0_DECODE is performed on the first sector, the second hard decision data HD1 can be provided to the ECC circuit. Then, the second soft decision data SD1 can be continuously provided to the ECC circuit. According to Figure 5C In the embodiment shown, it takes 2.25×t_DMA to provide the ECC circuit with the hard decision data and soft decision data of a sector and then complete the soft decision decoding of the sector. Figure 5CIn the illustrated embodiment, it takes 7×t_DMA time to output all error-corrected data of the first sector to the fourth sector.

[0075] refer to Figure 5D , the memory controller may perform a formatting operation on the first to fourth hard decision data HD0 to HD3 and the first to fourth soft decision data SD0 to SD3 received from the memory device. The first to fourth soft decision data SD0 to SD3 may be provided to the ECC circuit, and then, the first to fourth hard decision data HD0 to HD3 may be provided to the ECC circuit. Since the size of each soft decision data is 1KB, it may take 1×t_DMA time to provide the first to fourth soft decision data SD0 to SD3 to the ECC circuit.

[0076] The ECC circuit may perform the first soft decision decoding SD0_DECODE after receiving the first hard decision data HD0. The ECC circuit may perform the second soft decision decoding SD1_DECODE after receiving the second hard decision data HD1. Through the above process, it takes 7×t_DMA time to output all error-corrected data from the first sector to the fourth sector.

[0077] According to the embodiments described above, when soft decision data is compressed and a formatting operation is performed on data supplied to an ECC circuit, the time required for ECC decoding processing can be shortened compared to a case where neither compression nor formatting operation is performed.

[0078] Figure 6 and Figure 7 is a block diagram illustrating an example of data formatters 300A and 300B according to an embodiment.

[0079] refer to Figure 6 , the data formatter 300A may include a data control unit 310A and one or more buffers. The data control unit 310A may receive the first hard decision data HD0 to the fourth hard decision data HD3 and the first soft decision data SD0 to the fourth soft decision data SD3, and perform a formatting operation on the first hard decision data HD0 to the fourth hard decision data HD3 and the first soft decision data SD0 to the fourth soft decision data SD3. The buffer of the data formatter 300A may include a buffer storing the first hard decision data HD0 to the fourth hard decision data HD3 and a buffer storing the first soft decision data SD0 to the fourth soft decision data SD3. Figure 6 A case is shown where the first to fourth soft decision data SD0 to SD3 are provided to the memory controller, and then the first to fourth hard decision data HD0 to HD3 are provided to the memory controller, but the inventive concept is not necessarily limited thereto.

[0080] According to the above-described embodiment, the data control unit 310A may perform a formatting operation according to various methods. For example, the formatting operation may be performed so that the hard decision data and the soft decision data of each sector are continuously provided to the ECC circuit. For example, the data control unit 310A may provide the first hard decision data HD0 and the first soft decision data SD0 of the first sector to the ECC circuit, provide the second hard decision data HD1 and the second soft decision data SD1 of the second sector to the ECC circuit, provide the third hard decision data HD2 and the third soft decision data SD2 of the third sector to the ECC circuit, and provide the fourth hard decision data HD3 and the fourth soft decision data SD3 of the fourth sector to the ECC circuit.

[0081] Figure 7 A case is shown where the data formatter 300B does not output soft decision data of at least one sector based on the ECC decoding result.

[0082] refer to Figure 7 , the data formatter 300B may include a data control unit 310B, one or more buffers, and a counter 320B. According to the above embodiment, the one or more buffers may include buffers HD0_BUFFER to HD3_BUFFER storing the first hard decision data HD0 to the fourth hard decision data HD3 and buffers SD0_BUFFER to SD3_BUFFER storing the first soft decision data SD0 to the fourth soft decision data SD3. In an embodiment, the counter 320B may count the strong error information (or weak error information) of each of the first soft decision data SD0 to the fourth soft decision data SD3, and provide the counting result to the data control unit 310B. In addition, the data control unit 310B may receive at least one decoding information according to the ECC decoding result. For example, the at least one decoding information may include information indicating the location of the data where the actual error determined by the ECC decoding process occurs (or whether the location where the actual error occurs corresponds to a strong error or a weak error) and information indicating the number of errors occurring in one sector. In addition, a loop counter for counting the number of loop operations during the soft decision decoding process may be provided in the memory controller, and the data control unit 310B may further receive a count value of the loop counter.

[0083] In an embodiment, when there are no soft errors or the number of soft errors is very small in any one sector (e.g., the first sector), these errors can be corrected by an ECC decoding process that relies solely on hard decision data without performing soft decision decoding on the first sector. In addition, the first to fourth sectors belonging to one page may have the same or similar error patterns. Therefore, based on the ECC decoding result of at least one sector on one page on which the ECC decoding process has been performed, it can be determined whether to perform soft decision decoding on subsequent sectors.

[0084] In an embodiment, the data control unit 310B may compare the count value from the counter 320B with the first reference value, and determine whether to perform soft decision decoding based on the comparison result. For example, the data control unit 310B may compare the value obtained by calculating the number of strong errors (or weak errors) in each of the first sector to the fourth sector with the first reference value, and perform a formatting operation for some of the first sector to the fourth sector, so as not to provide soft decision data to the ECC circuit. In addition, in an embodiment, when it is determined to perform soft decision decoding based on the count value provided from the counter 320B, the data control unit 310B may randomly select a sector in the first sector to the fourth sector where soft decision decoding is not performed, without referring to the ECC decoding result of the previous sector.

[0085] In addition, in an embodiment, the data control unit 310B may refer to the ECC decoding result of at least one sector on which the ECC decoding process has been performed. Figure 7 The embodiment of the present invention describes a case where whether to perform soft decision decoding on the third sector and the fourth sector is determined based on the decoding information of the first sector and the second sector. According to the ECC decoding results of the first sector and the second sector, when one or more pieces of data where an actual error occurs correspond to a position of a strong error of the soft decision data or are likely to correspond to a position of a strong error, it may be advantageous to perform ECC decoding processing using only hard decision data. In this case, if Figure 7 As shown, the data control unit 310B may selectively provide hard decision data only for the third sector and the fourth sector without providing soft decision data.

[0086] When the number of errors occurring in each of the first sector and the second sector is less than or equal to the second reference value, the errors are corrected by or more likely to be corrected by a normal decoding process. Figure 7 As shown, the data control unit 310B may provide hard decision data only for the third sector and the fourth sector.

[0087] When the compression loss is large during the compression process performed on the first soft decision data SD0 to the fourth soft decision data SD3 in the memory device, or when the information of the first soft decision data SD0 to the fourth soft decision data SD3 is incorrect due to a compression error, the number of times the loop is run during the soft decision decoding process may increase significantly. The data control unit 310B compares the number of loop runs with a specific threshold. Based on the comparison result, the data control unit 310B may provide hard decision data only for the third sector and the fourth sector. In other words, when the compression characteristics of the soft decision data are not good, the decoding operation using the soft decision data may not be performed in some sectors.

[0088] In addition, when the number of times the loop is run during the soft decision decoding process is relatively small or less than a specific threshold, the number of errors that occur in the read data may be small. In this case, for the read data, the error is corrected or may be corrected only by the decoding process using the hard decision data. Therefore, in an embodiment, it may be determined whether the number of times the loop is run is less than a specific threshold. Based on this determination, the decoding operation using the soft decision data may not be performed in some sectors.

[0089] Figure 8 It shows the operation Figure 7 A flow chart of a method for a memory device.

[0090] refer to Figure 8 , the memory controller may receive first to fourth hard decision data and first to fourth soft decision data of the first sector to the fourth sector from the memory device, and perform a formatting operation on the first to fourth hard decision data and the first to fourth soft decision data. According to the formatting result, the hard decision data and the soft decision data of each sector may be continuously provided to the ECC circuit. For example, the ECC circuit may perform soft decision decoding on the first sector (S21).

[0091] The ECC circuit can correct the error in the first sector by performing soft decision decoding on the first sector, and provide at least one decoding information according to the decoding result. The data formatter can determine the decoding result (S22) through the at least one decoding information, and control the formatting operation related to the subsequent ECC decoding process of the second sector based on the determination result.

[0092] For example, the number of loop runs during the soft decision decoding process of the first sector may be compared with at least one threshold value. For example, the number of loop runs may be compared with a first threshold value or a second threshold value (S23). In an embodiment, the first threshold value may be greater than the second threshold value. When the number of loop runs is greater than the first threshold value or when the number of loop runs is less than the second threshold value, a formatting operation may be performed so that the soft decision data of the second sector is not provided to the ECC circuit. Therefore, a normal decoding operation may be performed on the second sector without using the soft decision data (S27). In an embodiment, the number of loop runs may be compared only with the first threshold value, the number of loop runs may be compared only with the second threshold value, or the number of loop runs may be compared with both the first threshold value and the second threshold value.

[0093] When the number of loop operations is not greater than the first threshold or not less than the second threshold, the number of errors occurring in the first sector can be compared with the reference value (S24). When the number of errors occurring in the first sector is less than the reference value, a normal decoding operation can be performed on the second sector without using the soft decision data (S27). On the other hand, when the number of errors occurring in the first sector is not less than the reference value, the position of the actual error occurring in the first sector is determined. By referring to the value of the soft decision data of the first sector, it can be determined whether the data where the actual error occurs corresponds to the position of the strong error in the soft decision data (S25). When the position where the error occurs corresponds to the strong error, the error can be corrected by using the normal decoding operation of the hard decision data without performing the soft decision decoding operation. Therefore, a normal decoding operation can be performed on the second sector using the soft decision data (S27). On the other hand, when the position where the error occurs corresponds to the weak error, it is also necessary to perform soft decision decoding on the subsequent sectors. Therefore, the hard decision data and the soft decision data of the second sector are continuously provided to the ECC circuit, and soft decision decoding can be performed on the second sector (S26).

[0094] Fig. 9 and Fig.10 It is shown separately Figure 7 FIG. 1 is a diagram of an example of a data formatting operation in a memory device and an example of time required for an ECC decoding process.

[0095] refer to Fig. 9 , assuming that first soft decision data SD0 to fourth soft decision data SD3 and first hard decision data HD0 to fourth hard decision data HD3 of one page are sequentially received from a memory device, the data formatter can receive the first soft decision data SD0 to fourth soft decision data SD3 and the first hard decision data HD0 to fourth hard decision data HD3 as data input DATA_IN, and provide data output DATA_OUT to the ECC circuit according to the formatting result.

[0096] First, the data formatter may output first hard decision data HD0 and first soft decision data SD0 of a first sector to the ECC circuit, and the ECC circuit may perform soft decision decoding using the first hard decision data HD0 and the first soft decision data SD0. The ECC circuit may provide the data formatter with at least one piece of decoding information indicating a decoding result of the first hard decision data HD0 and the first soft decision data SD0, and then, the data formatter may perform a formatting operation so as not to provide the ECC circuit with soft decision data of at least one sector based on the decoding information.

[0097] In an embodiment, the data formatter may provide the first soft decision data SD0 and the second soft decision data SD1 of the first sector and the second sector among the first sector to the fourth sector to the ECC circuit, and determine whether to provide the third soft decision data SD2 and the fourth soft decision data SD3 of the third sector and the fourth sector to the ECC circuit based on the decoding information of the first sector and the second sector. For example, according to the above-mentioned embodiment, when the normal decoding process using the hard decision data is determined to be suitable for both the first sector and the second sector, the formatting operation may be performed so that the third soft decision data SD2 and the fourth soft decision data SD3 are not provided to the ECC circuit. In addition, according to an embodiment, even when the normal decoding process using the hard decision data is determined to be suitable for the first sector or the second sector, the formatting operation may be performed so that the third soft decision data SD2 and the fourth soft decision data SD3 are not provided to the ECC circuit.

[0098] According to the above embodiment, the ECC decoding process of one sector and the operation of providing the data of the subsequent sector to the ECC circuit can be performed in parallel, so whether to provide the third soft decision data SD2 and the fourth soft decision data SD3 to the ECC circuit can be determined based on the decoding information of the first sector. In other words, the ECC circuit can provide the decoding information of the first sector to the data formatter while receiving the second hard decision data HD1 and the second soft decision data SD1 of the second sector. In this case, the data formatter can perform a formatting operation based on the decoding information of the first sector, so as not to provide the third soft decision data SD2 and the fourth soft decision data SD3 to the ECC circuit.

[0099] Fig.10 It shows that for Figure 7 A diagram illustrating the time required for an ECC decoding operation of one page in a memory device of an embodiment shown.

[0100] refer to Fig.10, the first hard decision data HD0 and the second hard decision data HD1 of the first sector and the second sector and the first soft decision data SD0 and the second soft decision data SD1 may be provided to the ECC circuit, and the time required to provide the hard decision data of each of the first sector and the second sector to the ECC circuit may correspond to 1.25×t_DMA. In addition, for the third sector and the fourth sector, the soft decision data is not provided to the ECC circuit, and therefore, the time required to provide the data of the first sector to the fourth sector on one page to the ECC circuit may correspond to 4.5×t_DMA.

[0101] Soft decision decoding is not performed on the third sector and the fourth sector. For example, the ECC circuit may perform normal decoding processing on the third sector when the third hard decision data HD2 is completely received. In addition, the ECC circuit may perform normal decoding processing on the fourth sector when the fourth hard decision data HD3 is completely received. Fig.10 In the illustrated embodiment, it takes 6.5×t_DMA to output all error-corrected data from the first sector to the fourth sector.

[0102] According to the above embodiment, the formatting operation is performed to exclude the soft decision data of the sector or page suitable for performing normal decoding from being provided to the ECC circuit. Therefore, this method can prevent the unnecessary number of cycles from occurring during the soft decision decoding process and eliminate the time required to provide some soft decision data to the ECC circuit. Therefore, the total time required for the ECC decoding process can be shortened.

[0103] Fig.11 is a schematic diagram showing a Figure 1 FIG. 2 is a diagram of a memory device 200 .

[0104] refer to Figure 1 and Fig.11 , the memory device 200 may include a first semiconductor layer L1 and a second semiconductor layer L2, and the first semiconductor layer L1 may be stacked on the second semiconductor layer L2 in the vertical direction VD. For example, the second semiconductor layer L2 may be located below the first semiconductor layer L1 in the vertical direction VD. In an embodiment, Figure 1 The memory cell array 210 may be formed in the first semiconductor layer L1, and the peripheral circuit driving the memory cell array 210 may be formed in the second semiconductor layer L2. Therefore, the memory device 200 may have a structure in which the memory cell array 210 is located above the peripheral circuit, for example, a cell-on-periphery (COP) structure. The COP structure may reduce the area in the horizontal direction and improve the integration of the memory device 200.

[0105] In an embodiment, a peripheral circuit is formed in the second semiconductor layer L2, and then the first semiconductor layer L1 including the memory cell array 210 may be formed thereon. In addition, a metal pattern may be formed to electrically connect the word lines WL and the bit lines BL of the memory cell array 210 to the peripheral circuit formed in the second semiconductor layer L2. For example, the bit lines BL may extend in a first horizontal direction or the first direction H1, and the word lines WL may extend in a second horizontal direction or the second direction H2.

[0106] Fig.12 is a diagram showing a method according to an embodiment of the present invention. Figure 1 FIG. 2 is a diagram of a memory cell array 210 .

[0107] refer to Fig.12 , the memory cell array 210 may include a plurality of memory blocks BLK0 to BLKi, and i may be a positive integer. The plurality of memory blocks BLK0 to BLKi may each have a three-dimensional structure (or a vertical structure). The plurality of memory blocks BLK0 to BLKi may each include a plurality of NAND strings extending in a vertical direction VD. Here, the plurality of NAND strings may be spaced apart from each other by a certain distance in the first direction HD1 and the second direction HD2.

[0108] Fig.13 is a stereoscopic diagram showing a memory block BLKa according to an embodiment.

[0109] refer to Fig.13 , the memory block BLKa may correspond to Fig.12 One of the multiple memory blocks BLK0 to BLKi in the vertical direction VD. The memory block BLKa is formed on a substrate SUB of a first conductivity type (e.g., p-type) in the vertical direction VD. In an embodiment, a common source line CSL doped with impurities of a second conductivity type (e.g., n-type) may be provided on the substrate SUB. In an embodiment, the substrate SUB may include polycrystalline silicon, and the common source line CSL having a plate shape may be provided on the substrate SUB. A plurality of insulating films IL extending in the second direction HD2 are sequentially provided above the substrate SUB in the vertical direction VD, and the plurality of insulating films IL are spaced apart from each other at a specific distance in the vertical direction VD. For example, the plurality of insulating films IL may include an insulating material such as silicon oxide.

[0110] A plurality of pillars P are sequentially arranged on a substrate SUB in a first direction HD1 and pass through a plurality of insulating films IL in a vertical direction VD. For example, a plurality of pillars P may pass through a plurality of insulating films IL and contact the substrate SUB. For example, a surface layer S of each pillar P may include a first type of silicon material and may be used as a channel region. Therefore, the pillars P may be referred to as a vertical channel structure. In addition, an inner layer I of each pillar P may include an insulating material (such as silicon oxide) and an air gap.

[0111] The charge storage layer CS is arranged along the exposed surfaces of the insulating film IL, the pillars P and the substrate SUB. The charge storage layer CS may include a gate insulating layer, a charge trapping layer and a blocking insulating layer. For example, the charge storage layer CS may have an oxide-nitride-oxide (ONO) structure. In addition, a gate electrode GE including a ground selection line GSL, a string selection line SSL and word lines WL0, WL1, WL2, WL3, WL4, WL5, WL6 and WL7 is arranged on the exposed surface of the charge storage layer CS. The drain DR is arranged on each of the plurality of pillars p. For example, the drain DR may include a silicon material doped with second conductive type impurities. The bit lines BL1, Bl2 and BL3 are arranged on the drain DR, and the bit lines BL1 to BL3 extend in the first direction HD1 and are spaced apart from each other at a specific distance in the second direction HD2.

[0112] Fig.14 is a block diagram illustrating a memory system 500 according to another embodiment.

[0113] refer to Fig.14 , the memory system 500 may include a memory controller 510 and a memory device 520. The memory device 520 may include a memory cell array 521, a page buffer circuit 522, and a control logic 523. The memory controller 510 may include a command generator 511, a data formatter 512, and an ECC circuit 513, and the data formatter 512 may include a dummy data generator 512_1.

[0114] The command generator 511 may generate various types of commands CMD, such as a read command for reading data. In addition, in an embodiment, the memory device 520 may determine the output order of the hard decision data and the soft decision data according to the command provided from the command generator 511. If a first read command RD_H is provided, the memory device 520 may first output the hard decision data HD based on the control of the control logic 523. If a second read command RD_S is provided, the memory device 520 may first output the soft decision data SD. The data formatter 512 may receive the hard decision data and the soft decision data from the memory device 520, and provide the hard decision data and the soft decision data to the ECC circuit 513. The ECC circuit 513 may include a buffer whose size is sufficient to store the hard decision data and / or the soft decision data.

[0115] In an embodiment, a page includes a plurality of sectors (e.g., four). In each sector, the size of the hard decision data may be 4KB, and the size of the soft decision data may be 1KB, depending on the compression used. In addition, the memory controller 510 may transmit data internally based on the size of the unit. For example, data may be transmitted to the data formatter 512 and the ECC circuit 513 in units of 4KB, or data may be transmitted to the data formatter 512 and the ECC circuit 513 in units of 1KB. In addition, the data transmission size inside the memory controller 510 may correspond to the data read size of the memory controller 510 and the memory device 520. The memory controller 510 may perform internal data transmission corresponding to the read unit of the memory device 520. The embodiment is not necessarily limited to the above-mentioned 4KB or 1KB size, and the memory controller 510 may transmit data in units of various sizes.

[0116] exist Fig.14 In the illustrated embodiment, the data formatter 512 may continuously provide the hard decision data HD and the soft decision data SD for each sector to the ECC circuit 513. When providing the soft decision data SD in a 4KB read environment, the data formatter 512 may add 3KB of dummy data to the 1KB of soft decision data SD and provide the data to the ECC circuit 513. In other words, for data of a size corresponding to the read environment, dummy data and soft decision data of a sector for which soft decision decoding is to be actually performed may be provided to the ECC circuit instead of providing a plurality of pieces of soft decision data to the ECC circuit.

[0117] According to the above embodiment, in a reading environment of different sizes, the hard decision data and soft decision data of the sector to be actually subjected to the ECC decoding process can be provided to the ECC circuit. Therefore, the speed of the ECC decoding process can be improved. For example, during the ECC decoding process of a sector at a specific position, the soft decision data of the sector transmitted to the ECC circuit will not be delayed due to communication constraints such as due to the unit size of 4KB. Therefore, the time required for the ECC decoding process of all sectors of a page can be shortened.

[0118] Figures 15 to 17 is a diagram illustrating an example of an ECC decoding process and an example of the time required for the ECC decoding process according to some embodiments.

[0119] refer to Fig.15, the memory controller may receive first hard decision data HD0 to fourth hard decision data HD3 and first soft decision data SD0 to fourth soft decision data SD3 from the memory device. Each piece of hard decision data may have a size of 4KB, and each piece of soft decision data may have a size of 1KB. Assuming that the size of the read environment is 4KB, the memory controller may continuously provide the hard decision data and soft decision data of each sector to the ECC circuit by performing a formatting operation on the first hard decision data HD0 to fourth hard decision data HD3 and the first soft decision data SD0 to fourth soft decision data SD3. Here, when 1KB of soft decision data is provided in response to a 4KB read environment, 1KB of soft decision data and 3KB of dummy data may be continuously provided to the ECC circuit.

[0120] For example, the memory controller may sequentially provide the first hard decision data HD0, the first soft decision data SD0, and the first dummy data Dummy0 to the ECC circuit based on the formatting operation. The ECC circuit may perform soft decision decoding on the first sector when the first soft decision data SD0 is completely received, regardless of whether the first dummy data Dummy0 is received. For example, soft decision decoding may be performed on the first sector while the first dummy data Dummy0 is received.

[0121] Similarly, the soft decision decoding of the second sector to the fourth sector can also be performed in the same manner as described above. For example, the second virtual data Dummy1 can be provided to the ECC circuit successively after the second soft decision data SD1, and the ECC circuit can perform soft decision decoding on the second sector when the second soft decision data SD1 is completely received. In addition, the third virtual data Dummy2 can be provided to the ECC circuit successively after the third soft decision data SD2, and the fourth virtual data Dummy3 can be provided to the ECC circuit successively after the fourth soft decision data SD3. In both cases, soft decision decoding can be performed while receiving virtual data. According to the above method, compared with the case where soft decision data from multiple sectors are provided to the ECC circuit during the soft decision decoding process of one sector, the time required for the ECC decoding process can be reduced by a time corresponding to the data input time of 3 / 4×4KB.

[0122] Fig.16 FIG. (a) shows a case where the memory controller performs a random read of 4KB size on the memory device. For example, a case where the fourth sector among the first to fourth sectors belonging to a page is selectively read is described. In response to a read command from the memory controller, the memory device may output to the memory controller the fourth hard decision data HD3 corresponding to the fourth sector of 4KB and the first soft decision data SD0 to the fourth soft decision data SD3 corresponding to the first to fourth sectors of 4KB.

[0123] Based on the above formatting operation, the memory controller can provide the fourth soft decision data SD3 among the first soft decision data SD0 to the fourth soft decision data SD3 to the ECC circuit, and provide the dummy data Dummy of 3KB size to the ECC circuit after providing the fourth soft decision data SD3. In addition, the ECC circuit can perform soft decision decoding on the fourth sector when the fourth soft decision data SD3 is completely received.

[0124] On the other hand, Fig.16 FIG. 10( b ) shows a case where the embodiment is not applied. Here, the ECC circuit may receive the fourth hard decision data HD3 and the first soft decision data SD0 to the fourth soft decision data SD3 provided from the memory device, and perform soft decision decoding on the fourth sector when the first soft decision data SD0 to the fourth soft decision data SD3 are completely received. In other words, when the embodiment is applied, Fig.16 Compared with the case shown in (b), the time required for the ECC decoding process can be reduced by the time corresponding to 3 / 4×4KB.

[0125] Fig.17 1 is a diagram showing a case where an embodiment is applied in a read environment of 1 KB size. In an embodiment, a memory controller may perform a read operation on a memory device in units of 1 KB. In addition, the memory controller may transfer data between internal components (e.g., a data formatter and an ECC circuit) in units of 1 KB.

[0126] As in Fig.17 In the illustrated embodiment, the memory controller may continuously provide the hard decision data and the soft decision data of each sector to the ECC circuit based on the formatting operation. In addition, when performing soft decision decoding on each sector, the ECC circuit may perform soft decision decoding when the soft decision data of the corresponding sector is completely received. For example, Fig.17 As shown, the ECC circuit can receive the first hard decision data HD0 and the first soft decision data SD0, and perform soft decision decoding. In addition, when the ECC circuit performs soft decision decoding on the first sector, the ECC circuit can receive the second hard decision data HD1 of the second sector in parallel with the soft decision decoding of the first sector. In other words, the second hard decision data HD1 can be received while the soft decision decoding is performed on the first sector. When the ECC decoding process is performed on the sectors of one page through the above process, Fig.16 Compared with the embodiment shown in FIG. (a), the time required for the ECC decoding process can be further reduced to a time corresponding to 3 / 4×4KB.

[0127] Fig.18A and Fig.18BExamples of memory systems 600A and 600B according to embodiments are shown, respectively. Fig.18A and Fig.18B In the embodiment, only the ECC circuit related to the configuration of the memory controller is shown, but various other components according to the above-mentioned embodiment can be further arranged in Fig.18A and Fig.18B in the memory controller.

[0128] The memory system 600A may include a memory device 610A and an ECC circuit 620A, and the memory device 610A may include a memory cell array 611A, a page buffer circuit 612A, and a compressor 613A. The ECC circuit 620A may include a buffer 621A and an ECC decoder 622A.

[0129] The memory device 610A may output page data in response to a command from a memory controller. Assuming that one page includes four sectors and each sector includes data of 4KB size, the memory device 610A may output hard decision data HD of 16KB size (16KB HD data) and soft decision data SD of 4KB size (4KB compressed SD data). Assuming that the hard decision data HD is first output from the memory device 610A, the buffer 621A may have a size of 16KB to store the hard decision data HD of the four sectors. Subsequently, the soft decision data SD of the first sector to the fourth sector may be sequentially provided to the ECC decoder 622A. While the first soft decision data of the first sector is provided to the ECC decoder 622A, the first hard decision data of the first sector stored in the buffer 621A may be provided to the ECC decoder 622A together. Therefore, the ECC decoder 622A may perform soft decision decoding on the first sector. Similarly, in response to the remaining soft decision data of the second to fourth sectors being sequentially provided to the ECC decoder 622A, the hard decision data of the second to fourth sectors stored in the buffer 621A are provided to the ECC decoder 622A. Therefore, the ECC decoder 622A can perform soft decision decoding on the second to fourth sectors.

[0130] refer to Fig.18B , the memory system 600B may include a memory device 610B and an ECC circuit 620B, and the memory device 610B may include a memory cell array 611B, a page buffer circuit 612B, and a compressor 613B. The ECC circuit 620B may include a buffer 621B and an ECC decoder 622B. Fig.18B A case is shown in which the memory device 610B outputs soft decision data SD of 4 KB size (4 KB compressed SD data) and then outputs hard decision data HD of 16 KB size (16 KB HD data).

[0131] exist Fig.18B In the illustrated embodiment, the buffer 621B stores the soft decision data SD and thus may have a size of 4KB. While providing the first hard decision data of the first sector to the ECC decoder 622B, the first soft decision data of the first sector stored in the buffer 621B may be provided to the ECC decoder 622B together. Therefore, the ECC decoder 622B may perform soft decision decoding on the first sector. According to the above process, soft decision decoding may be sequentially performed on the remaining second to fourth sectors.

[0132] According to the above embodiments, the buffer in the ECC circuit can selectively store only hard decision data or soft decision data without having a relatively large size to store both hard decision data and soft decision data. Therefore, the size of the buffer can be reduced. In addition, in order to enable the memory system to support various output modes, the ECC circuit may include a 16KB buffer, such as Fig.18A In addition, the memory system may be configured such that a single buffer in the ECC circuit is used to store 16KB of hard decision data or 4KB of soft decision data according to the output mode.

[0133] Fig.19 is a block diagram showing an example in which a memory device according to an embodiment is applied to an SSD system 700 .

[0134] refer to Fig.19 , the SSD system 700 may include a host 710 and an SSD 720. The SSD 720 exchanges signals (SIG) with the host 710 through a signal connector and receives power (PWR) via a power connector. The SSD 720 may include an SSD controller 721, an auxiliary power supply 722, and memory devices 723, 724, and 725. The memory devices 723 to 725 may include vertically stacked NAND flash memory devices. The memory devices 723 to 725 may be connected to the SSD controller 721 via a plurality of channels Ch1, Ch2, ..., Chn. Here, the SSD 720 may use the above reference Figures 1 to 19 The described embodiments are implemented.

[0135] For example, the SSD controller 721 may correspond to the memory controller described in the above embodiment, and the memory devices 723 to 725 may correspond to the memory devices according to the above embodiment. Hard decision data and soft decision data may be sent and received between the SSD controller 721 and the memory devices 723 to 725. The SSD controller 721 may include a data formatter 721_1 and an ECC circuit 721_2. The data formatter 721_1 may perform a formatting operation on the hard decision data and soft decision data provided from the memory devices 723 to 725, thereby providing the ECC circuit 721_2 with data in a format optimized for ECC decoding processing. For example, the data formatter 721_1 may perform a formatting operation to change the order of the data provided from the memory devices 723 to 725, and thereby provide the ECC circuit 721_2 with hard decision data and soft decision data of multiple sectors in the changed order.

[0136] While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the inventive concept as set forth in the following claims.

Claims

1. A memory controller, the memory controller comprising: a data formatter configured to receive, for first to N-th sectors on a first page of a memory device, first to N-th hard decision data read based on a normal read level and first to N-th soft decision data read based on an offset read level, and perform a formatting operation on the first to N-th hard decision data and the first to N-th soft decision data, wherein N is an integer of 2 or greater; and an error correction code circuit configured to receive the first to N-th hard decision data and the first to N-th soft decision data from the data formatter, and to correct an error on the first page through an error correction code decoding process, The data formatter performs the formatting operation so that the first to N-th hard decision data and the first to N-th soft decision data are provided to the error correction code circuit in an order different from the order in which the first to N-th hard decision data and the first to N-th soft decision data are received from the memory device.

2. The memory controller according to claim 1, wherein: The first to Nth soft decision data are compressed in the memory device and provided to the memory controller, so that the size of each of the first to Nth soft decision data is smaller than the size of its corresponding first to Nth hard decision data.

3. The memory controller according to claim 2, wherein: The hard decision data and the soft decision data of each of the first sector to the Nth sector are continuously provided from the data formatter to the error correction code circuit.

4. The memory controller according to claim 2, wherein: After the first to N-th soft decision data are provided from the data formatter to the error correction code circuit, the first to N-th hard decision data are provided from the data formatter to the error correction code circuit.

5. The memory controller according to claim 2, wherein: In order to perform a normal decoding process using the hard decision data on at least one sector from the first sector to the Nth sector on the first page, the data formatter performs the formatting operation so as not to provide the soft decision data corresponding to the at least one sector to the error correction code circuit.

6. The memory controller according to claim 1, wherein: The data formatter receives the first to Nth soft decision data after receiving the first to Nth hard decision data, and performs the formatting operation so that the soft decision data of one sector from the first to Nth sectors is provided to the error correction code circuit before the hard decision data of another sector from the first to Nth sectors is provided to the error correction code circuit.

7. The memory controller according to claim 1, wherein: The data formatter receives at least one piece of decoding information based on a result of the error correction code decoding process, and performs the formatting operation based on the decoding information, thereby not providing the soft decision data of some sectors from the first sector to the Nth sector to the error correction code circuit.

8. The memory controller according to claim 7, wherein: When the number of errors occurring in a sector among the first sector to the Nth sector on which the error correction code decoding process is first performed is less than a reference value, the formatting operation is performed so that the soft decision data of another sector among the first sector to the Nth sector is not provided to the error correction code circuit.

9. The memory controller according to claim 7, wherein: When the number of loop operations in the error correction code decoding process using the soft decision data of one of the first sector to the Nth sector exceeds a threshold value, the formatting operation is performed so that the soft decision data of another sector of the first sector to the Nth sector is not provided to the error correction code circuit.

10. The memory controller according to claim 1, wherein: The data formatter receives first to N-th hard decision data and first to N-th soft decision data of the first sector to the N-th sector on the second page of the memory device, and performs the formatting operation so that the hard decision data, the soft decision data, and the dummy data of any sector from the first sector to the N-th sector on the second page are continuously provided to the error correction code circuit, and Each of the first to N-th soft decision data is compressed in the memory device, and a size thereof is smaller than a size of its corresponding first to N-th hard decision data, and a sum of a size of the soft decision data and a size of the virtual data of any one of the first sector to the N-th sector on the second page is equal to a size of the hard decision data of the sector.

11. A memory controller, the memory controller comprising: a data formatter configured to receive, for first to N-th sectors on a first page of a memory device, first to N-th hard decision data read based on a normal read level and first to N-th soft decision data read based on an offset read level, and perform a formatting operation on the first to N-th hard decision data and the first to N-th soft decision data, wherein N is an integer of 2 or greater; and an error correction code circuit configured to receive the first to N-th hard decision data and the first to N-th soft decision data from the data formatter, and to correct an error on the first page through an error correction code decoding process, wherein the first to the Nth soft decision data are compressed in the memory device and provided to the memory controller, so that the sizes of the first to the Nth soft decision data are each smaller than the sizes of the corresponding first to the Nth hard decision data, and The data formatter continuously provides the first hard decision data and the first soft decision data of the first sector to the error correction code circuit, and performs the formatting operation so that first dummy data is provided to the error correction code circuit subsequent to the first soft decision data.

12. The memory controller according to claim 11, wherein: The size of the first hard decision data is equal to the sum of the size of the first soft decision data and the size of the first dummy data.

13. The memory controller according to claim 11, wherein: When the first soft decision data is completely received, the error correction code circuit performs the error correction code decoding process on the first sector.

14. The memory controller according to claim 11, wherein: After outputting the first dummy data, the data formatter continuously provides the error correction code circuit with second hard decision data, second soft decision data, and second dummy data of the second sector, and When the second soft decision data is completely received, the error correction code circuit performs the error correction code decoding process on the second sector.

15. The memory controller according to claim 11, wherein: The memory controller outputs a read command to the memory device to read a Kth sector among the first sector to the Nth sector on a second page of the memory device, and receives Kth hard decision data of the Kth sector and the first soft decision data to the Nth soft decision data of the first sector to the Nth sector from the memory device, wherein K is an integer from 1 to N, The data formatter provides the received first soft decision data to the Kth soft decision data among the Nth soft decision data to the error correction code circuit, and provides the Kth dummy data to the error correction code circuit following the Kth soft decision data, and When the Kth soft decision data is completely received, the error correction code circuit performs the error correction code decoding process on the Kth sector.

16. The memory controller according to claim 11, wherein: The memory controller first receives the first hard decision data to the Nth hard decision data from the memory device, or first receives the first soft decision data to the Nth soft decision data from the memory device, and The data formatter is configured so that the first to Nth hard decision data and the first to Nth soft decision data are provided to the error correction code circuit in an order different from the order in which the first to Nth hard decision data and the first to Nth soft decision data are received from the memory device.

17. A storage device, comprising: A memory device comprising one or more pages, each page comprising a first sector to an Nth sector, wherein N is an integer of 2 or more; and a memory controller configured to control a storage operation of the memory device and receive first to N-th hard decision data and first to N-th soft decision data of the first sector to the N-th sector on each page of the memory device, Wherein, the memory controller comprises: an error correction code circuit configured to receive the first to Nth hard decision data and the first to Nth soft decision data and to correct an error on each page through an error correction code decoding process; and A data formatter configured to perform a formatting operation so that the first to Nth hard decision data and the first to Nth soft decision data are provided to the error correction code circuit in an order different from an order in which the first to Nth hard decision data and the first to Nth soft decision data are received from the memory device.

18. The storage device according to claim 17, wherein: After receiving the first to the Nth hard decision data from the memory device, the memory controller receives the first to the Nth soft decision data, and The data formatter performs the formatting operation so that the first to Nth hard decision data are provided to the error correction code circuit after the first to Nth soft decision data are provided to the error correction code circuit.

19. The storage device according to claim 17, wherein: After receiving the first to the Nth soft decision data from the memory device, the memory controller receives the first to the Nth hard decision data, and The data formatter performs the formatting operation so that the hard decision data and the soft decision data of each sector are continuously provided to the error correction code circuit.

20. The storage device according to claim 17, wherein: Based on the result of error correction code decoding processing of at least one sector from the first sector to the Nth sector, the data formatter performs the formatting operation so as not to provide the soft decision data of at least one other sector from the first sector to the Nth sector to the error correction code circuit.

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