Preparation method of semiconductor packaging structure and semiconductor packaging structure

Abstract

The invention provides a preparation method of a semiconductor packaging structure and the semiconductor packaging structure, and the method comprises the steps: manufacturing a plurality of crystal grains on the surface of a selected semiconductor material, and cutting out the crystal grains to obtain a bare chip; etching wiring on the packaging substrate to obtain a wiring substrate, and mounting the bare chip to a corresponding position of the wiring substrate; the bare chip bonding pad is communicated with the wires on the wiring substrate, an initial semiconductor packaging structure is obtained, and the initial semiconductor packaging structure is provided with a filling part used for eliminating the height difference between the bare chip and the wiring substrate; the initial semiconductor packaging structure is sealed, an external connection terminal is reserved, the semiconductor packaging structure is obtained, and the external connection terminal is used for being connected with an external circuit; compared with the prior art, under the condition that a lead bonding mode is not needed, the height difference between the bare chip and the wiring substrate is eliminated through the filling part, staggered stacking of wires can be avoided, signal crosstalk is reduced, signal quality is improved, and more reasonable layout is facilitated.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor packaging, and in particular to a method for preparing a semiconductor packaging structure and a semiconductor packaging structure. Background Art

[0002] Traditional packaging technologies, such as wire bonding technology, have matured in the IC manufacturing industry and are used in power products such as DC-DC (DCDC), analog-to-digital converters (ADC), storage and other signal transmission products. Wire bonding technology uses heat, pressure, or ultrasonic energy to tightly weld thin metal wires to pads on the surface of the chip and substrate to connect the chip to the signal network or power network of the substrate.

[0003] However, this technology requires reserving pads larger than the diameter of the metal wire on the bare chip and substrate, and then placing the gold wire on the pad with a fixture for soldering to achieve electrical connection. In addition, this technology requires more gold wires for connection of products with large power and multiple signals. However, the size of the bare chip is limited, and the number of pads arranged around the bare chip is insufficient, so they will inevitably be arranged in the inner circle. At this time, the height difference of the metal wires between the inner and outer layers is small, and the wire spacing between the same layer is even smaller, that is, the spacing of the gold wires in the routing space is small, which can easily lead to high crosstalk and affect signal quality. Summary of the invention

[0004] The present invention provides a method for preparing a semiconductor packaging structure and a semiconductor packaging structure, the purpose of which is to reduce the crosstalk of signals in the connection area between a bare chip and a substrate and improve the signal quality.

[0005] In order to achieve the above object, the present invention provides a method for preparing a semiconductor packaging structure, comprising:

[0006] Step 1, making a plurality of uniformly arranged grains on the surface of a selected semiconductor material, and cutting out all the grains to obtain a bare chip;

[0007] Step 2, etching wiring on the packaging substrate to obtain a wiring substrate, and mounting the bare chip to a corresponding position of the wiring substrate;

[0008] Step 3, connecting the bare chip pad with the wiring on the wiring substrate to obtain an initial semiconductor packaging structure, wherein the initial semiconductor packaging structure is provided with a filling portion for eliminating the height difference between the bare chip and the wiring substrate;

[0009] Step 4: seal the initial semiconductor package structure and reserve external connection terminals to obtain a semiconductor package structure, wherein the external connection terminals are used to connect to an external circuit.

[0010] More specifically, step 1 includes:

[0011] By repeatedly performing photolithography, etching, and deposition operations on the selected semiconductor material, a plurality of uniformly arranged grains are formed on the surface of the selected semiconductor material;

[0012] By grinding, cleaning and slicing the selected semiconductor material, multiple grains are cut out one by one to obtain bare chips.

[0013] More specifically, step 3 includes:

[0014] Step 31, determining a connection path between the bare chip and the wiring substrate according to the pad positions of the bare chip and the wiring substrate, and filling the height of the connection path at the intersection of the connection path and the edge of the bare chip to form a filling part for eliminating the height difference between the bare chip and the wiring substrate;

[0015] Step 32, based on the filling part, connect the bare chip with the wiring on the wiring substrate to obtain an initial semiconductor packaging structure.

[0016] Specifically, step 31 includes:

[0017] Step 311, determining a connection path between the bare chip and the wiring substrate according to pad positions of the bare chip and the wiring substrate;

[0018] Step 312, determining the intersection position and non-intersection position of the connection path and the edge of the bare chip;

[0019] Step 313, covering the upper surfaces of the bare chip and the wiring substrate with photoresist;

[0020] Step 314, using a mask corresponding to the polarity of the photoresist to cover the photoresist, exposing the intersection position or the non-intersection position, removing the mask, and removing the photoresist at the intersection position by development;

[0021] Step 315, sputtering a conductive metal film on the upper surface of the bare chip covered with photoresist and the upper surface of the wiring substrate covered with photoresist and the upper surface of the wiring substrate not covered with photoresist;

[0022] Step 316, removing the photoresist on the bare chip and the wiring substrate, so that the conductive metal film is patterned;

[0023] Step 317, re-covering the upper surfaces of the bare chip and the wiring substrate with photoresist;

[0024] Step 318, using a mask corresponding to the polarity of the photoresist to cover the photoresist, exposing the intersection position or the non-intersection position, removing the mask, and removing the photoresist at the intersection position by development;

[0025] Step 319, electroplating a conductive material at the intersection position to fill the height of the connection path to form a filling portion for eliminating the height difference between the bare chip and the wiring substrate.

[0026] Further, the top of the conductive material is flush with the top of the bare die.

[0027] Specifically, step 32 includes:

[0028] Step 321, using a mask corresponding to the polarity of the photoresist to cover the photoresist, exposing the connection path or the non-connection path area, removing the mask, and removing the photoresist on the connection path by development;

[0029] Step 322, sputtering a conductive metal on the upper surface of the bare chip covered with photoresist and not covered with photoresist, the upper surface of the wiring substrate covered with photoresist and not covered with photoresist, and the upper surface of the filling portion, so as to connect the bare chip and the wiring substrate;

[0030] Step 323, removing the remaining photoresist to obtain an initial semiconductor packaging structure.

[0031] Furthermore, the initial semiconductor package structure is sealed by a molding compound.

[0032] Furthermore, the external connection terminals are packaged using ball grid array packaging, land grid array packaging, or pin grid array packaging technology.

[0033] The present invention also provides a semiconductor packaging structure, which is manufactured by a method for manufacturing a semiconductor packaging structure. The semiconductor packaging structure comprises:

[0034] Bare chip, wiring substrate, filling part, external connection terminal, sealing layer;

[0035] The bare chip is arranged on the upper surface of the wiring substrate;

[0036] The wiring substrate is provided with wiring;

[0037] The filling part is arranged on the wiring substrate, the filling part is located at a position where a height difference occurs in a connection path between the bare chip and the wiring substrate, one side wall of the filling part is connected to one side wall of the bare chip, and the top of the filling part is flush with the top of the bare chip;

[0038] The pads on the surface of the bare chip are electrically connected to the pads on the surface of the wiring substrate through the filling portion;

[0039] The external connection terminals include a plurality of terminals, which are all arranged at the bottom of the wiring substrate and are used to connect to an external circuit;

[0040] The sealing layer is arranged on the upper part of the bare chip and is used for sealing the bare chip, the upper surface of the wiring substrate and the filling part.

[0041] Furthermore, the material of the filling portion is a conductive material.

[0042] The above scheme of the present invention has the following beneficial effects:

[0043] The present invention manufactures a plurality of evenly arranged grains on the surface of a selected semiconductor material, and cuts out all the grains to obtain a bare chip; etches wiring on a packaging substrate to obtain a wiring substrate, and mounts the bare chip to a corresponding position on the wiring substrate; connects the bare chip pad with the wiring on the wiring substrate to obtain an initial semiconductor packaging structure, and the initial semiconductor packaging structure is provided with a filling portion for eliminating the height difference between the bare chip and the wiring substrate; seals the initial semiconductor packaging structure and reserves external connection terminals to obtain a semiconductor packaging structure, and the external connection terminals are used to connect to an external circuit; compared with the prior art, the present invention connects the bare chip pad with the wiring on the wiring substrate through the filling portion, and eliminates the height difference between the bare chip and the wiring substrate without the need for wire bonding, which can not only avoid the staggered stacking of the wiring, reduce signal crosstalk, and improve signal quality, but also facilitate a more reasonable layout.

[0044] Other beneficial effects of the present invention will be described in detail in the subsequent specific implementation section. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 A schematic diagram of a flow chart of an embodiment of the present invention;

[0046] Figure 2 A schematic diagram of a packaging process according to an embodiment of the present invention;

[0047] Figure 3 31 is a flow chart of step 31 in an embodiment of the present invention;

[0048] Figure 4 This is a schematic diagram of a partial processing process of step 31 in an embodiment of the present invention;

[0049] Figure 5 This is a schematic diagram of a partial processing process of step 31 in an embodiment of the present invention;

[0050] Figure 6 Schematic diagram of the processing process of step 32 in an embodiment of the present invention;

[0051] Figure 7 Schematic diagram of the semiconductor packaging structure in an embodiment of the present invention.

[0052] [Description of Reference Numerals]

[0053] 1- bare chip 2- wiring substrate 3- filling part

[0054] 4- External connection terminals 5- Sealing layer. DETAILED DESCRIPTION

[0055] In order to make the technical problems, technical solutions and advantages to be solved by the present invention clearer, the following will be described in detail with reference to the accompanying drawings and specific embodiments. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0056] In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0057] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installation", "connection" and "connection" should be understood in a broad sense, for example, it can be a locking connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0058] In addition, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0059] In view of the existing problems, the present invention provides a method for preparing a semiconductor packaging structure and a semiconductor packaging structure.

[0060] like Figure 1 and Figure 2 As shown, an embodiment of the present invention provides a method for preparing a semiconductor packaging structure, comprising:

[0061] Step 1: Make multiple uniformly arranged grains on the surface of the selected semiconductor material, and cut out all the grains to obtain a bare chip. Figure 2 As shown in (a);

[0062] Step 2, etching wiring on the packaging substrate to obtain a wiring substrate, such as Figure 2As shown in (a), the bare chip is mounted to the corresponding position of the wiring substrate. Figure 2 As shown in (b), the corresponding position is the position where the bare chip can be connected to the wiring on the wiring substrate;

[0063] Step 3, connecting the bare chip pad with the wiring on the wiring substrate to obtain an initial semiconductor packaging structure, wherein the initial semiconductor packaging structure is provided with a filling portion for eliminating the height difference between the bare chip and the wiring substrate, Figure 2 As shown in (c);

[0064] Step 4, sealing the initial semiconductor package structure and reserving external connection terminals to obtain a semiconductor package structure, Figure 2 As shown in (d)-(e) in FIG. 1 , the external connection terminals are used to connect to an external circuit.

[0065] Most preferably, step 1 comprises:

[0066] By repeatedly performing photolithography, etching, and deposition operations on the selected semiconductor material, a plurality of uniformly arranged crystal grains are formed on the surface of the selected semiconductor material, and the crystal grains are silicon wafers etched with circuit patterns;

[0067] By grinding, cleaning and slicing the selected semiconductor material, multiple grains are cut out one by one to obtain bare chips.

[0068] In an embodiment of the present invention, the selected semiconductor material is a silicon wafer. The designed circuit diagram is projected onto the surface of the silicon wafer through a photolithography process, the portion not covered by the photoresist is removed through an etching process to form a desired structure, and a new material is deposited on the already fabricated structure through a deposition process. A plurality of evenly arranged grains are grown on the surface of the silicon wafer, and the arrangement and size of the grains depend on the requirements of the integrated circuit. The grains on the silicon wafer are cut out one by one through a grinding process, a cleaning process, and a slicing process to form a plurality of independent bare chips, each of which is mounted on a wiring substrate and electrically connected to the corresponding traces on the wiring substrate.

[0069] In an embodiment of the present invention, the photolithography process generally uses a photosensitive photoresist to protect or expose specific areas of the surface, and the deposition process can be a chemical vapor deposition process or a physical vapor deposition process; the grinding process is generally used to flatten the surface of the silicon wafer for more precise processing and cutting, and the cleaning process is to remove residues from the processing process to ensure the cleanliness and quality of the bare chip surface.

[0070] In an embodiment of the present invention, a packaging substrate is used to make circuit routing, and is usually made of a specific type of dielectric material (such as BT material). Its surface is subjected to processes such as etching to form a desired wiring pattern. These routing connections are used to subsequently connect the circuit of the bare chip to the external connection terminal. The circuit on the bare chip is connected to the external connection terminal through the routing on the wiring substrate. The external connection terminal serves as the pin of the semiconductor packaging structure and is electrically connected to the external circuit.

[0071] It should be noted that in step 2, the wiring is etched on the packaging substrate to obtain the wiring substrate using a conventional etching method in the technical field. The embodiment of the present invention does not involve improvements to the etching process, so the etching process will not be described in detail in the embodiment. The bare chip is mounted to the corresponding position of the wiring substrate also using conventional technical means in the technical field, so the mounting process will not be described in detail.

[0072] Most preferably, step 3 comprises:

[0073] Step 31, determining a connection path between the bare chip and the wiring substrate according to the pad positions of the bare chip and the wiring substrate, and filling the height of the connection path at the intersection of the connection path and the edge of the bare chip to form a filling part for eliminating the height difference between the bare chip and the wiring substrate;

[0074] Step 32, based on the filling part, connect the bare chip with the wiring on the wiring substrate to obtain an initial semiconductor packaging structure.

[0075] like Figure 3-Figure 5 As shown, most preferably, step 31 includes:

[0076] Step 311, determining the connection path between the bare chip and the wiring substrate according to the pad positions of the bare chip and the wiring substrate, such as Figure 4 As shown in (a);

[0077] Step 312, determining the intersection position and non-intersection position of the connection path and the edge of the bare chip;

[0078] Step 313, covering the upper surface of the bare chip and the wiring substrate with photoresist, such as Figure 4 As shown in (b);

[0079] Step 314, using a mask corresponding to the polarity of the photoresist to cover the photoresist, exposing the intersection position or the non-intersection position, removing the mask, and removing the photoresist at the intersection position by development, such as Figure 4 As shown in (c)-(d);

[0080] Step 315, sputtering a conductive metal film on the upper surface of the bare chip covered with photoresist and not covered with photoresist and the upper surface of the wiring substrate covered with photoresist and not covered with photoresist, such as Figure 4 As shown in (e);

[0081] Step 316, removing the photoresist on the bare chip and the wiring substrate, so that the conductive metal film is patterned, such as Figure 4 As shown in (f);

[0082] Step 317, re-cover the upper surface of the bare chip and the wiring substrate with photoresist, such as Figure 5 As shown in (a);

[0083] Step 318, using a mask corresponding to the polarity of the photoresist to cover the photoresist, exposing the intersection position or the non-intersection position, removing the mask, and removing the photoresist at the intersection position by development, such as Figure 5 As shown in (b)-(c);

[0084] Step 319, electroplating conductive material at the intersection position to fill the height of the connection path to form a filling portion for eliminating the height difference between the bare chip and the wiring substrate, such as Figure 5 As shown in (d) in .

[0085] The embodiment of the present invention first determines the intersection and non-intersection positions of the connection path and the edge of the bare chip, and then designs a mask corresponding to the polarity of the photoresist to be used. If a positive photoresist is used subsequently, the opaque mask pattern is consistent with the non-intersection area pattern; if a negative photoresist is used subsequently, the opaque mask pattern is consistent with the intersection area pattern. Then, using a mask corresponding to the polarity of the photoresist, the exposure area on the photoresist is limited by the transparent area and opaque area of ​​the mask. For example, the mask corresponding to the positive photoresist will cover the non-intersection area and only expose the intersection area; the mask corresponding to the negative photoresist will cover the intersection area and only expose the non-intersection area. Then remove the mask, and finally remove the photoresist at the intersection by developing.

[0086] In the embodiment of the present invention, the purpose of step 317 and step 318 is to prevent other exposed metals (such as pads) from changing during the subsequent electroplating process.

[0087] The preparation method provided in the embodiment of the present invention has the following advantages:

[0088] 1. The cross-sectional width of the routing can be equal to the width of the pad. There is no need to reserve the solder joint position and process space, which makes the cross-sectional area of ​​the routing larger. At the same time, there is no need for three-dimensional routing, which makes the routing shorter, thereby reducing the voltage drop, reducing energy loss, reducing heat generation, and improving the service life of the product;

[0089] 2. There is no need to reserve solder joint positions and process space on the pads for routing. While meeting the voltage drop requirements of the wiring substrate, the pad size can be reduced, which is conducive to miniaturization of the product;

[0090] 3. The gold wire can be directly connected to the wiring on the wiring substrate along the edge of the bare chip, without the need to route the wire in a three-dimensional space, making the connection path between the bare chip and the wiring substrate controllable. The routing path can be designed and determined in advance, reducing the uncertainty of routing, which is conducive to maintaining the consistency of product manufacturing, reducing the difficulty of subsequent plastic packaging processes, and reducing the risk of product failure;

[0091] 4. No need for three-dimensional spatial routing, avoiding the staggered stacking of routing, thereby reducing signal crosstalk.

[0092] In the embodiment of the present invention, the exposure process is to selectively irradiate the photoresist covering the substrate with light of a specific wavelength. Under the irradiation of light, the irradiated area (photosensitive area) of the photoresist undergoes a photodegradation reaction (positive photoresist) or a photocuring reaction (negative photoresist), so that the solubility of the photosensitive area of ​​the photoresist in the developer changes. The positive or negative image transfer of the mask pattern is achieved by utilizing the different solubilities of the photosensitive area and the non-photosensitive area of ​​the photoresist in the developer.

[0093] In the embodiment of the present invention, by adding a developer after the exposure, the photosensitive area of ​​the positive photoresist and the non-photosensitive area of ​​the negative photoresist will be dissolved in the developer. After this step is completed, the pattern in the photoresist layer can be revealed.

[0094] In the embodiment of the present invention, the process of removing the photoresist may be wet stripping, using an organic solvent or an inorganic solvent to remove the photoresist; or dry stripping, using plasma to strip the photoresist.

[0095] Most preferably, the top of the conductive material is flush with the top of the die.

[0096] like Figure 6 As shown, most preferably, step 32 includes:

[0097] Step 321, using a mask corresponding to the polarity of the photoresist to cover the photoresist, exposing the connection path or the non-connection path area, removing the mask, and removing the photoresist on the connection path by development, such as Figure 6 As shown in (a)-(b);

[0098] Step 322, sputtering a conductive metal on the upper surface of the bare chip covered with photoresist and not covered with photoresist, the upper surface of the wiring substrate covered with photoresist and not covered with photoresist, and the upper surface of the filling portion, so as to connect the bare chip and the wiring substrate. Figure 6 As shown in (c);

[0099] Step 323, remove the remaining photoresist to obtain an initial semiconductor packaging structure, such as Figure 6 As shown in (d) in .

[0100] In step 323, while removing the remaining photoresist, the sputtered conductive metal on the photoresist is also removed, and the conductive metal film on the obtained initial semiconductor package structure is patterned.

[0101] Most preferably, the initial semiconductor package structure is sealed by a molding compound.

[0102] In the embodiment of the present invention, the plastic encapsulation material is used to cover and protect the bare chip and its connection circuits, and provide mechanical support and electrical isolation. The sealing process includes:

[0103] Select appropriate plastic encapsulation materials, whose physical properties should be able to meet the requirements of semiconductor packaging structure, such as good mechanical strength, chemical stability and heat resistance;

[0104] The prepared plastic encapsulation material is coated or poured on the surface of the bare chip and the wiring substrate to form a certain thickness, ensuring that the bare chip and the wiring substrate are covered;

[0105] Curing is accomplished by heating or chemical reaction, transforming the molding compound from a liquid or semi-solid state to a solid state.

[0106] Most preferably, the external connection terminals are packaged using ball grid array packaging, planar grid array packaging, or pin grid array packaging technology, and the external connection terminals are arranged at the bottom of the wiring substrate and are electrically connected to the bare chip through the wiring on the wiring substrate.

[0107] In the embodiments of the present invention, a ball grid array package (BGA) is a ball array, such as a solder ball array, manufactured at the bottom of a packaging substrate, and the solder balls are used as connection terminals with an external circuit; a land grid array package (LGA) is a planar grid array manufactured at the bottom of a packaging substrate, and the planar contacts are used as connection terminals with an external circuit; and a pin grid array package (PGA) is a pin array manufactured at the bottom of a packaging substrate, and the pins are used as connection terminals with an external circuit.

[0108] In the embodiment of the present invention, a suitable packaging method can be selected according to actual product requirements, and is not limited to the above packaging methods.

[0109] like Figure 7 As shown, an embodiment of the present invention further provides a semiconductor packaging structure, and a method for preparing the semiconductor packaging structure is applied. The semiconductor packaging structure includes:

[0110] Bare chip 1, wiring substrate 2, filling part 3, external connection terminal 4, sealing layer 5;

[0111] The bare chip 1 is arranged on the upper surface of the wiring substrate 2;

[0112] The wiring substrate 2 is provided with wiring;

[0113] The filling part 3 is made through the above step 31 and is arranged on the wiring substrate 2. The filling part 3 is located at a position where a height difference occurs in the connection path between the bare chip 1 and the wiring substrate 2. One side wall of the filling part 3 is connected to one side wall of the bare chip 1, and the top of the filling part 3 is flush with the top of the bare chip 1. The pads on the surface of the bare chip 1 are electrically connected to the pads on the surface of the wiring substrate 2 through the filling part 3.

[0114] The external connection terminals 4 include a plurality of terminals, all of which are disposed at the bottom of the wiring substrate 2 and are used to connect to an external circuit.

[0115] The sealing layer 5 is prepared through the above step 4 and is disposed on the upper part of the bare chip 1 to seal the bare chip 1 , the upper surface of the wiring substrate 2 and the filling part 3 .

[0116] Most preferably, the material of the filling part 3 is a conductive material.

[0117] In the embodiment of the present invention, the conductive material used for the filling portion 3 may be the same as the material of the wiring on the wiring substrate, for example, both are copper metal.

[0118] In the embodiment of the present invention, the routing cross section of the filling portion 3 can be controlled by the area of ​​the electroplating region. By increasing the area, the voltage drop can be reduced, the energy loss can be reduced, the heat generation can be reduced, and the service life of the product can be improved.

[0119] In the embodiment of the present invention, the semiconductor packaging structure may be a power chip, an analog-to-digital converter, or a memory chip.

[0120] The present invention manufactures a plurality of evenly arranged grains on the surface of a selected semiconductor material, and cuts out all the grains to obtain a bare chip; etches wiring on a packaging substrate to obtain a wiring substrate, and mounts the bare chip to a corresponding position on the wiring substrate; connects the bare chip pad with the wiring on the wiring substrate to obtain an initial semiconductor packaging structure, and the initial semiconductor packaging structure is provided with a filling portion for eliminating the height difference between the bare chip and the wiring substrate; seals the initial semiconductor packaging structure and reserves external connection terminals to obtain a semiconductor packaging structure, and the external connection terminals are used to connect to an external circuit; compared with the prior art, the present invention connects the bare chip pad with the wiring on the wiring substrate through the filling portion, and eliminates the height difference between the bare chip and the wiring substrate without the need for wire bonding, which can not only avoid the staggered stacking of the wiring, reduce signal crosstalk, and improve signal quality, but also facilitate a more reasonable layout, and realize chip integration and miniaturization.

[0121] The above are preferred embodiments of the present invention. It should be pointed out that, for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be regarded as within the scope of protection of the present invention.

Claims

1. A method for preparing a semiconductor packaging structure, characterized in that: include: Step 1, making a plurality of uniformly arranged grains on the surface of a selected semiconductor material, and cutting out all the grains to obtain a bare chip; Step 2, etching wiring on the packaging substrate to obtain a wiring substrate, and mounting the bare chip to a corresponding position of the wiring substrate; Step 3, connecting the bare chip pad with the wiring on the wiring substrate to obtain an initial semiconductor packaging structure, wherein the initial semiconductor packaging structure is provided with a filling portion for eliminating the height difference between the bare chip and the wiring substrate; Step 4: sealing the initial semiconductor package structure and reserving external connection terminals to obtain a semiconductor package structure, wherein the external connection terminals are used to connect to an external circuit.

2. The method for preparing a semiconductor packaging structure according to claim 1, characterized in that: The step 1 comprises: Repeating photolithography, etching, and deposition operations on the selected semiconductor material to form a plurality of uniformly arranged grains on the selected semiconductor material; The selected semiconductor material is ground, cleaned and sliced, and the plurality of crystal grains are cut out one by one to obtain bare chips.

3. The method for preparing a semiconductor packaging structure according to claim 2, characterized in that: The step 3 comprises: Step 31, determining a connection path between the bare chip and the wiring substrate according to pad positions of the bare chip and the wiring substrate, and filling the height of the connection path at the intersection of the connection path and the edge of the bare chip to form a filling portion for eliminating the height difference between the bare chip and the wiring substrate; Step 32: Based on the filling portion, the bare chip is connected to the wiring on the wiring substrate to obtain an initial semiconductor packaging structure.

4. The method for preparing a semiconductor packaging structure according to claim 3, characterized in that: The step 31 comprises: Step 311, determining a connection path between the bare chip and the wiring substrate according to pad positions of the bare chip and the wiring substrate; Step 312, determining the intersection position and non-intersection position of the connection path and the edge of the bare chip; Step 313, covering the upper surfaces of the bare chip and the wiring substrate with photoresist; Step 314, using a mask corresponding to the polarity of the photoresist to cover the photoresist, exposing the intersection position or the non-intersection position, removing the mask, and removing the photoresist at the intersection position by development; Step 315, sputtering a conductive metal film on the upper surface of the bare chip covered with photoresist and the upper surface of the wiring substrate covered with photoresist and the upper surface of the wiring substrate not covered with photoresist; Step 316, removing the photoresist on the bare chip and the wiring substrate, so that the conductive metal film is patterned; Step 317, re-covering the upper surfaces of the bare chip and the wiring substrate with photoresist; Step 318, using a mask corresponding to the polarity of the photoresist to cover the photoresist, exposing the intersection position or the non-intersection position, removing the mask, and removing the photoresist at the intersection position by development; Step 319, electroplating a conductive material at the intersection position to fill the height of the connection path to form a filling portion for eliminating the height difference between the bare chip and the wiring substrate.

5. The method for preparing a semiconductor packaging structure according to claim 4, characterized in that: The top of the conductive material is flush with the top of the bare chip.

6. The method for preparing a semiconductor packaging structure according to claim 5, characterized in that: The step 32 comprises: Step 321, using a mask corresponding to the polarity of the photoresist to cover the photoresist, exposing the connection path or the non-connection path area, removing the mask, and removing the photoresist on the connection path by development; Step 322, sputtering a conductive metal on the upper surface of the bare chip covered with photoresist and not covered with photoresist, the upper surface of the wiring substrate covered with photoresist and not covered with photoresist, and the upper surface of the filling portion, so as to connect the bare chip and the wiring substrate; Step 323, removing the remaining photoresist to obtain an initial semiconductor packaging structure.

7. The method for preparing a semiconductor packaging structure according to claim 6, characterized in that: The initial semiconductor packaging structure is sealed by a molding compound.

8. The method for preparing a semiconductor packaging structure according to claim 7, characterized in that: The external connection terminals are packaged by ball grid array packaging, plane grid array packaging or pin grid array packaging technology.

9. A semiconductor packaging structure, characterized in that: The semiconductor package structure is manufactured by the method for manufacturing the semiconductor package structure according to any one of claims 1 to 8, wherein the semiconductor package structure comprises: Bare chip (1), wiring substrate (2), filling part (3), external connection terminal (4), sealing layer (5); The bare chip (1) is arranged on the upper surface of the wiring substrate (2); The wiring substrate (2) is provided with wiring; The filling portion (3) is arranged on the wiring substrate (2), the filling portion (3) is located at a position where a height difference occurs in the connection path between the bare chip (1) and the wiring substrate (2), a side wall of one side of the filling portion (3) is connected to a side wall of one side of the bare chip (1), and the top of the filling portion (3) is flush with the top of the bare chip (1); The pads on the surface of the bare chip (1) are electrically connected to the pads on the surface of the wiring substrate (2) via the filling portion (3); The external connection terminals (4) include a plurality of terminals, all of which are arranged at the bottom of the wiring substrate (2) and are used for connecting to an external circuit; The sealing layer (5) is arranged on the upper part of the bare chip (1) and is used to seal the bare chip (1), the upper surface of the wiring substrate (2) and the filling part (3).

10. The semiconductor package structure according to claim 9, wherein: The material of the filling part (3) is a conductive material.

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