Semiconductor gate sidewall thickness testing method, structure, device and storage medium

Abstract

The present invention provides a semiconductor gate sidewall thickness testing method, comprising: measuring the active area resistance value between gates at different gate spacings, establishing a data relationship between the active area resistance value and the gate spacing based on a plurality of the active area resistance values, and calculating the gate sidewall thickness based on the data relationship; measuring at least two gate resistance values ​​with different gate widths but the same gate length, and calculating the gate deviation based on the gate resistance value and the gate width; and correcting the gate sidewall thickness using the gate deviation to obtain the actual gate sidewall thickness. The beneficial effect of this technical solution is that, by using an electrical testing method, the disadvantage of only detecting the gate sidewall thickness at the gate process site is solved, and the gate sidewall thickness can be detected more efficiently. The present invention also provides a semiconductor gate sidewall thickness testing structure, device, and computer-readable storage medium, which can realize rapid detection of gate sidewall thickness.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology, and in particular relates to a method, structure, device and storage medium for testing the thickness of a semiconductor gate sidewall. Background Art

[0002] The gate spacer process is a critical process in semiconductor CMOS manufacturing technology. Figure 1 Schematic diagram of the gate sidewall structure in the prior art, the gate sidewalls are formed on both sides of the gate on the well region, and have a certain thickness, and the two sides of the gate sidewalls are the source and drain regions respectively. The thickness of the gate sidewalls will affect the depth of subsequent source and drain region ion implantation into the channel, thereby affecting the performance of the MOS device.

[0003] In the prior art, wafer manufacturing plants generally use optical key dimension measurement technology to monitor the thickness of the gate sidewall. This measurement needs to be performed at the current process site of the gate sidewall, and the measurement time is relatively long. The wafer waiting time is time-limited, so the inspection of the gate sidewall in the prior art is usually spot-checked, and not every wafer is measured. At the same time, if the wafer passes the current process site, the change in the thickness of the gate sidewall cannot be tracked later.

[0004] Therefore, it is necessary to design a new gate sidewall detection method that can test all wafers without the need for measurement at the sidewall process site. Summary of the invention

[0005] The present invention provides a semiconductor gate sidewall thickness testing method, which utilizes an electrical property detection method to quickly and accurately track and monitor the gate sidewall thickness.

[0006] The present invention also provides a semiconductor gate sidewall thickness test structure, device and storage medium. The test structure, test device and storage medium are adapted to the above-mentioned test method and can more conveniently track and monitor the gate sidewall thickness.

[0007] Other purposes and advantages of the present invention can be further understood from the technical features disclosed in the present invention.

[0008] In order to achieve one or part or all of the above purposes or other purposes, a semiconductor gate sidewall thickness testing method provided by a technical solution of the present invention includes: measuring the active area resistance value between gates under different gate spacings, establishing a data relationship between the active area resistance value and the gate spacing based on multiple active area resistance values, and calculating the gate sidewall thickness based on the data relationship; measuring at least two gate resistance values ​​with different gate widths but the same gate length, and calculating the gate deviation based on the gate resistance value and the gate width; correcting the gate sidewall thickness using the gate deviation to obtain the actual gate sidewall thickness. The beneficial effect of the technical solution is that the present invention is based on the data relationship between the active area resistance value and the gate spacing, by repeatedly measuring the actual resistance value in the active area under different active area widths between gates, and then obtaining the gate sidewall thickness, and performing gate deviation correction to obtain the actual value of the gate sidewall thickness. The solution uses an electrical testing method to get rid of the disadvantage of only detecting the gate sidewall thickness at the gate process site, and can more efficiently detect the gate sidewall thickness.

[0009] In some of the embodiments, at least three gate active region resistance values ​​are measured under different gate spacings, and the active regions have the same length and the same gate width.

[0010] In some of the embodiments, a data relationship between the active area resistance value and the gate spacing is established, and a method for calculating the gate sidewall thickness based on the data relationship includes: drawing a two-dimensional scatter plot based on multiple groups of measured active area resistance values ​​between gates under different gate spacings; performing linear fitting on multiple points in the two-dimensional scatter plot, and obtaining the gate sidewall thickness based on the fitted straight line; wherein the two-dimensional scatter plot is drawn based on the X-axis being the gate spacing and the Y-axis being the inverse of the active area resistance value; and the gate sidewall thickness is half of the intercept of the fitted straight line with the X-axis.

[0011] In some embodiments, the gate deviation is calculated based on the gate resistance value and the gate width, including: constructing a relationship between the gate deviation, the gate width and the gate resistance value; based on the relationship, using the gate resistance values ​​at two different gate widths to calculate the gate deviation; wherein the gate resistance values ​​at the two different gate widths are: two gate resistance values ​​with different gate widths and the same gate length obtained by measuring, and two gate resistance values ​​with different gate widths and the same gate length obtained by screening and / or calculating multiple pairs of data.

[0012] In some embodiments, the constructing of the relationship between the gate deviation and the gate width and the gate resistance value includes: determining the relationship between the gate deviation and the gate spacing deviation based on the gate pitch determined by the design rule; based on the determined gate block resistance, and setting the gate deviation to be a fixed value under the same gate length and different gate widths; using two sets of corresponding variables of the gate width and the gate resistance, constructing the relationship between the gate deviation and the gate width and the gate resistance value:

[0013]

[0014] in, is the gate bias; and , and are the corresponding variables of two sets of gate width and gate resistance respectively.

[0015] In some embodiments, the actual gate spacer thickness is the calculated gate spacer thickness minus half of the gate deviation.

[0016] Another technical solution of the present invention provides a semiconductor gate sidewall thickness test structure, comprising multiple first test structures and at least two second test structures; the first test structure comprises two adjacent gates and at least two test pins arranged on an active area, and the at least two test pins are used to connect the target active area between the two adjacent gates on the active area for testing; the multiple first test structures have the same target active area length and gate width, and the multiple first test structures include at least three first test structures with different gate spacings; the second test structure includes a gate, and at least two test pins arranged on the gate; at least two of the second test structures have the same gate length, and at least two of the second test structures include at least two second test structures with different gate widths.

[0017] In some of the embodiments, the test structure is used for measuring electrical parameters in the semiconductor gate sidewall thickness test method described above; the first test structure and the second test structure are manufactured under the same manufacturing process; wherein the same manufacturing process includes the same gate sidewall process.

[0018] In some of the embodiments, in the first test structure, the test pin includes a metal contact hole arranged on the active area and a metal wire connected to the metal contact hole; the metal contact hole is arranged on the center line of the target active area, and the test pin is respectively arranged at the upper edge and the lower edge of the active area; wherein the center line is parallel to the two adjacent gates; in the second test structure, the test pin includes a metal contact hole arranged on the gate and a metal wire connected to the metal contact hole; the metal contact holes are respectively arranged at the upper end and the lower end of the gate.

[0019] Another technical solution of the present invention provides a semiconductor gate sidewall thickness testing device, the testing device comprising a gate sidewall thickness calculation module, a gate deviation calculation module and a gate sidewall thickness correction module;

[0020] The gate sidewall thickness calculation module is used to measure the active area resistance value between gates at different gate spacings, establish a data relationship between the active area resistance value and the gate spacing according to a plurality of active area resistance values, and calculate the gate sidewall thickness based on the data relationship;

[0021] The gate deviation calculation module is used to measure the gate resistance values ​​of at least two gates with different gate widths but the same gate lengths, and calculate the gate deviation based on the gate resistance values ​​and the gate widths;

[0022] The gate sidewall thickness correction module is used to correct the gate sidewall thickness using the gate deviation to obtain an actual gate sidewall thickness.

[0023] Another technical solution of the present invention provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the semiconductor gate sidewall thickness testing method described above are implemented.

[0024] Compared with the prior art, the beneficial effects of the present invention mainly include: 1. Providing a testing method, a testing structure, a device and a storage medium, which can measure the thickness of the gate side wall through electrical testing, and can monitor the thickness of the gate side wall at any time as needed, solving the inconvenience of the prior art that the thickness of the gate side wall can only be detected at the gate side wall process site.

[0025] 2. The gate sidewall electrical property testing method, testing structure, device and storage medium of the present invention also include a gate sidewall thickness correction step, which can correct the measured gate sidewall to make the measurement result accurate.

[0026] In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solutions in the specific embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0028] Figure 1 It is a schematic diagram of the gate sidewall structure in the prior art of the present invention;

[0029] Figure 2 This is a schematic diagram of a gate sidewall thickness test structure of the present invention;

[0030] Figure 3 It is a schematic diagram of the inverse linear fitting of the gate spacing and the active area resistance value in the gate sidewall thickness testing method of the present invention;

[0031] Figure 4 It is a schematic diagram of a gate sidewall thickness correction test structure in the gate sidewall thickness test structure of the present invention. DETAILED DESCRIPTION

[0032] The above and other technical contents, features and effects of the present invention will be clearly presented in the following detailed description of a preferred embodiment with reference to the drawings. The directional terms mentioned in the following embodiments, such as up, down, left, right, front or back, etc., are only referenced to the directions of the attached drawings. Therefore, the directional terms used are used to illustrate and not to limit the present invention.

[0033] This embodiment 1 provides a method for testing the thickness of a semiconductor gate sidewall, comprising the steps of:

[0034] Step S1: measuring the active area resistance value between gates at different gate spacings, establishing a data relationship between the active area resistance value and the gate spacing according to a plurality of the active area resistance values, and calculating the gate sidewall thickness based on the data relationship.

[0035] In this embodiment, the four-terminal method is used to measure the resistance values ​​of the active area between gates under five different gate spacings: R1, R2, R3, R4, R5, and the active area lengths are the same and the gate widths are the same; the four-terminal method resistance test method, which is a commonly used test method in the prior art, the main operation steps are to use four test pins to connect to the active area between the gates to be tested, and the four test pins include a pair of current test pins for testing current, and a pair of voltage test pins for testing voltage. In other embodiments, the number of active area resistance values ​​to be measured can be determined according to the needs of the application scenario, but it is necessary to measure at least three active area resistance values ​​between gates under different gate spacings, and the active area lengths are the same and the gate widths are the same; based on the requirements of measurement accuracy, the four-terminal method can be used to measure the active area resistance value, and the two-terminal method can also be used to measure the active area resistance value, and this application does not make specific limitations.

[0036] In this embodiment, a data relationship between the active area resistance value and the gate spacing is established, and the gate sidewall thickness is calculated based on the data relationship, including the following steps:

[0037] Step S1-1: Draw a two-dimensional scatter plot based on the measured active area resistance values ​​between multiple groups of gates under different gate spacings; wherein the two-dimensional scatter plot is drawn based on the X-axis being the gate spacing and the Y-axis being the inverse of the active area resistance value.

[0038] Specifically, assuming that the sheet resistance of the active area is a fixed value R SAA , the active area length is a fixed value L, the gate spacing is S, and t is the gate sidewall thickness, i.e., Spacer CD;

[0039] The active area width W between gates AA =S-2*t;

[0040] The total number of blocks in the active area num=L / W AA =L / (S-2*t);

[0041] The total resistance of the active area R AA =R SAA *num=R SAA *L / (S-2*t); after taking the inverse of the whole, we get: ; Due to R SAA *L is a fixed constant value, the reciprocal of the active area resistance 1 / R AA It is linearly positively correlated with the gate spacing S.

[0042] like Figure 3, make a two-dimensional scatter plot of the gate spacing and the inverse of the active area resistance, with the X-axis being the gate spacing and the Y-axis being the inverse of the active area resistance value; draw a two-dimensional scatter plot based on five sets of data (S1, 1 / R1), (S2, 1 / R2), (S3, 1 / R3), (S4, 1 / R4), and (S5, 1 / R5).

[0043] Step S1-2: performing linear fitting on multiple points in the two-dimensional scatter plot, and obtaining the gate sidewall thickness based on the fitted straight line; the gate sidewall thickness is half of the intercept of the fitted straight line with the X-axis.

[0044] Specifically, Figure 3 As shown, a linear fit is performed on the five points in the figure, and the intercept of the fitted straight line and the X-axis is X0, that is, X0= *2, and then the gate sidewall thickness can be calculated , that is, the gate sidewall thickness is half of the intercept of the fitted straight line and the X-axis. In actual operation, the number of two-dimensional scattered points formed by the gate spacing and the inverse of the resistance value is not less than 3 for fitting, and the specific number of two-dimensional scattered points can be determined based on the specific limitations of the application scenario.

[0045] Since there are certain process fluctuations in the gate yellow light process and etching in the gate manufacturing process, there is a certain deviation between the actual gate width and the designed width. If this deviation is not taken into account, the gate side wall thickness calculated by the method of step S1 cannot reflect the actual gate side wall thickness. When there are requirements for the measurement accuracy of the gate side wall thickness, it is necessary to perform correction processing on the calculated gate side wall thickness value in subsequent steps.

[0046] Step S2: measuring at least two gate resistance values ​​with different gate widths but the same gate lengths, and calculating the gate deviation based on the gate resistance values ​​and the gate widths.

[0047] In this embodiment, the gate deviation is calculated based on the gate resistance value and the gate width, including the following steps:

[0048] Step S2-1: construct a relationship between gate deviation, gate width and gate resistance.

[0049] Specifically, based on the gate pitch determined by the design rules, the relationship between the gate deviation and the gate spacing deviation is determined. The gate pitch is equal to the sum of the gate width and the gate spacing. The gate pitch is determined by the design rules and will not change with process fluctuations. The deviation (W0-W) between the actual gate width W0 and the designed width W is equal to the deviation (S-S0) between the actual gate spacing S0 and the designed spacing S. Therefore, the deviation of the gate spacing can be reflected by calculating the gate width deviation.

[0050] Based on the determined gate sheet resistance R SPO , and set the gate length L to be the same, and the gate deviation is a fixed value under different gate widths ; Using two sets of gate width and gate resistance as corresponding variables: and , and , construct the relation:

[0051]

[0052] After transforming the relationship, the relationship between gate deviation, gate width and gate resistance is obtained:

[0053] ;

[0054] Step S2-2: Based on the relationship, the gate deviation is calculated using gate resistance values ​​at two different gate widths.

[0055] In this embodiment, the gate resistance values ​​under two different gate widths are the gate resistance values ​​with two different gate widths and the same gate length measured by the four-terminal method; in other embodiments, based on different application scenario requirements, the gate resistance values ​​with two different gate widths and the same gate length can be obtained by screening multiple pairs of data, or even the gate resistance values ​​with two different gate widths and the same gate length can be obtained by calculating multiple pairs of data, and this application does not make specific limitations.

[0056] Step S3: Correcting the gate sidewall thickness using the gate deviation to obtain an actual gate sidewall thickness.

[0057] Specifically, the actual gate spacer thickness Spacer CD (t0) is the calculated gate spacer thickness Subtract half of the gate bias, which is: .

[0058] The semiconductor gate sidewall thickness testing method described in this embodiment can test all wafers by means of rapid monitoring of electrical tests, and can achieve rapid and accurate monitoring of gate sidewall thickness without the need for measurement at the sidewall process site.

[0059] Embodiment 2 provides a semiconductor gate sidewall thickness test structure, which is used for measuring electrical parameters in the semiconductor gate sidewall thickness test method in embodiment 1. The gate sidewall thickness test structure includes a plurality of first test structures and at least two second test structures, and the first test structures and the second test structures are manufactured under the same manufacturing process; wherein the same manufacturing process includes the same gate sidewall process.

[0060] The first test structure includes two adjacent gates and at least two test pins arranged on the active area, and the at least two test pins are used to connect the target active area between the two adjacent gates on the active area for testing. Figure 2 , Figure 2 The device comprises a well region and an active region in the well region, wherein the well region and the active region have different doping types, wherein a pair of gates parallel to each other are arranged on the active region, and the two gates have the same width.

[0061] In the first test structure of the present embodiment, four test pins for implementing the four-terminal resistance test are arranged on the active area between the gates, and the four test pins are connected to the active area through four metal contact holes to connect the target active area between the gates; however, in other embodiments, based on different application scenario requirements, two test pins can also be set to connect the target active area between two adjacent gates on the active area to measure the resistance using the two-terminal method, but the resistance test accuracy is not as good as the four-terminal method, but this application does not make specific restrictions. In the present embodiment, the four metal contact holes used for connection are on the center line of the target active area between the two gates, and the center line is parallel to the two adjacent gates. The voltage test pins and the current test pins on the same side are arranged at intervals. The distance between the two voltage test pins is the length of the target active area. In order to ensure the accuracy of the test method in Example 1, the length of the target active area between the gates should be as large as possible. Therefore, a pair of test pins in the first test structure in this embodiment 2 should be arranged close to the upper edge or lower edge of the active area so that the difference between the length of the target active area and the length of the active area meets the preset threshold. The current test pins and the voltage test pins in the first test structure are symmetrically arranged at the upper and lower ends of the active area. A plurality of first test structures are arranged, and the plurality of first test structures have the same target active area length L and the same gate width, and the plurality of first test structures include at least three first test structures with different gate spacings; the plurality of first test structures measure at least three gate active area resistance values ​​under different gate spacings.

[0062] In order to ensure the accuracy of the test, the number of the first test structures should be no less than 3. In step S1, the gate active area resistance values ​​under five different gate spacings: R1, R2, R3, R4, R5, can be measured based on the first test structure in this embodiment by setting five first test structures with the same target active area length L, the same gate width, and gate spacings of S1, S2, S3, S4, and S5, respectively, using the four-terminal method.

[0063] The second test structure includes a gate and at least two test pins arranged on the gate. Figure 4 , Figure 4The second test structure includes a gate located in the active area, and both ends of the gate extend out of the active area. A pair of voltage test pins and a pair of current test pins are provided at the upper and lower ends of the gate. The pair of voltage test pins and a pair of current test pins in the second test structure are connected to the gate through contact holes, and the center line of the contact hole overlaps with the center line of the gate. In order to ensure the test effect, the metal contact hole on the gate should be as close to the upper end or lower end of the gate as possible. That is, in the second test structure in this embodiment, four test pins for implementing four-terminal resistance testing are provided on the gate, and the four test pins are connected to the gate through four metal contact holes to connect the gate; but in other embodiments, based on different application scenario requirements, two test pins can also be set to connect the gates to measure resistance using the two-terminal method, but the resistance test accuracy is not as good as the four-terminal method, but this application does not make specific limitations.

[0064] At least two second test structures are provided, and at least two second test structures have different gate widths W and the same gate length; at least two second test structures measure two gate resistance values ​​with different gate widths. In step S2, two gate resistances: and , that is, based on the second test structure in this embodiment, two gates are set to have the same length and a gate width of and The first test structure is measured using the four-terminal method.

[0065] The semiconductor gate sidewall thickness test structure provided in Example 2 includes multiple first test structures and at least two second test structures, which can be used to measure the electrical parameters required for calculating the gate sidewall thickness and the electrical parameters required for calculating the gate deviation in Example 1, thereby realizing a tool for quickly detecting the gate sidewall thickness using electrical testing, improving test efficiency, and being able to test all wafers without the need for measurement at the sidewall process site.

[0066] Embodiment 3 provides a semiconductor gate sidewall thickness testing device, which is used to implement the above embodiments and preferred implementations, and will not be repeated hereafter. The terms "module", "unit", "subunit", etc. used below can implement a combination of software and / or hardware for a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, the implementation of hardware, or a combination of software and hardware, is also possible and conceivable.

[0067] The semiconductor gate sidewall thickness testing device comprises a gate sidewall thickness calculation module, a gate deviation calculation module and a gate sidewall thickness correction module; the gate sidewall thickness calculation module is used to measure the active area resistance value between gates under different gate spacings, establish a data relationship between the active area resistance value and the gate spacing according to a plurality of active area resistance values, and calculate the gate sidewall thickness based on the data relationship; the gate deviation calculation module is used to measure at least two gate resistance values ​​with different gate widths but the same gate lengths, and calculate the gate deviation based on the gate resistance value and the gate width; the gate sidewall thickness correction module is used to correct the gate sidewall thickness using the gate deviation to obtain the actual gate sidewall thickness.

[0068] In some of the embodiments, the gate spacer thickness calculation module is further used to measure the resistance value of the active area between gates under at least three different gate spacings, and the active areas have the same length and the same gate width.

[0069] In some of the embodiments, the gate sidewall thickness calculation module is also used to draw a two-dimensional scatter plot based on multiple groups of measured active area resistance values ​​between gates under different gate spacings; perform linear fitting on multiple points in the two-dimensional scatter plot, and obtain the gate sidewall thickness based on the fitted straight line; wherein the two-dimensional scatter plot is drawn based on the X-axis being the gate spacing and the Y-axis being the inverse of the active area resistance value; the gate sidewall thickness is half of the intercept of the fitted straight line with the X-axis.

[0070] In some of the embodiments, the gate deviation calculation module is further used to construct a relationship between the gate deviation, the gate width and the gate resistance value; based on the relationship, the gate deviation is calculated using the gate resistance values ​​at two different gate widths; wherein the gate resistance values ​​at the two different gate widths are: two gate resistance values ​​with different gate widths and the same gate length obtained by measuring, two gate resistance values ​​with different gate widths and the same gate length obtained by screening and / or calculating multiple pairs of data.

[0071] In some of the embodiments, the gate deviation calculation module is further used to determine the relationship between the gate deviation and the gate spacing deviation based on the gate pitch determined by the design rules; based on the determined gate block resistance, and setting the gate deviation to be a fixed value under the same gate length and different gate widths; using two sets of corresponding variables of gate width and gate resistance, construct a relationship between the gate deviation and the gate width and gate resistance value:

[0072]

[0073] in, is the gate bias; and , and are the corresponding variables of two sets of gate width and gate resistance respectively.

[0074] In some of the embodiments, the gate spacer thickness correction module is further used to realize: the actual gate spacer thickness is the calculated gate spacer thickness minus half of the gate deviation.

[0075] A semiconductor gate sidewall thickness test device provided in Example 3 can use the gate sidewall thickness calculation module to obtain the electrical parameters measured by the test structure of Example 2, and meet the data required by the gate sidewall thickness calculation module, the gate deviation calculation module and the gate sidewall thickness correction module. The semiconductor gate sidewall thickness test device can quickly calculate the value of the gate sidewall thickness and the corrected gate sidewall thickness value, and has the advantages of efficient and fast testing.

[0076] In combination with the semiconductor gate sidewall thickness testing method provided in Example 1, Example 4 provides a computer-readable storage medium to implement the semiconductor gate sidewall thickness testing method in Example 1. The storage medium stores a computer program, and when the computer program is executed by a processor, steps S1 to S3 of the semiconductor gate sidewall thickness testing method in Example 1 are implemented.

[0077] The above is a detailed introduction to a semiconductor gate sidewall thickness testing method, structure, device and computer-readable storage medium provided by the present invention. This article uses specific examples to illustrate the structure and working principle of the present invention. The description of the above embodiments is only used to help understand the method and core idea of ​​the present invention. It should be pointed out that for ordinary technicians in this technical field, without departing from the principle of the present invention, the present invention can also be improved and modified, and these improvements and modifications also fall within the scope of protection of the claims of the present invention.

Claims

1. A method for testing the thickness of a semiconductor gate sidewall, characterized in that: include: The method comprises the following steps: measuring the active area resistance value between gates at different gate spacings, establishing a data relationship between the active area resistance value and the gate spacing according to a plurality of active area resistance values, and calculating the gate sidewall thickness based on the data relationship; drawing a two-dimensional scatter plot based on a plurality of groups of active area resistance values ​​between gates at different gate spacings obtained by measurement; performing linear fitting on a plurality of points in the two-dimensional scatter plot, and obtaining the gate sidewall thickness based on the fitted straight line; measuring at least two gate resistance values ​​with different gate widths but the same gate length, and calculating a gate deviation based on the gate resistance value and the gate width; The gate sidewall thickness is corrected using the gate deviation to obtain an actual gate sidewall thickness.

2. A semiconductor gate sidewall thickness testing method according to claim 1, characterized in that: At least three gate active region resistance values ​​are measured under different gate spacings, wherein the active regions have the same length and the same gate width.

3. A semiconductor gate sidewall thickness testing method according to claim 1, characterized in that: The two-dimensional scatter plot is drawn based on the X-axis being the gate spacing and the Y-axis being the inverse of the active area resistance value; the gate sidewall thickness is half of the intercept of the fitted straight line and the X-axis.

4. A semiconductor gate sidewall thickness testing method according to claim 1, characterized in that: Based on the gate resistance value and the gate width, a gate deviation is calculated, including: Construct the relationship between gate deviation, gate width and gate resistance value; Based on the relationship, the gate deviation is calculated using gate resistance values ​​at two different gate widths; Among them, the gate resistance values ​​under the two different gate widths are: the gate resistance values ​​with different gate widths and the same gate length obtained by measurement, and the gate resistance values ​​with different gate widths and the same gate length obtained by screening and / or calculating multiple pairs of data.

5. A semiconductor gate sidewall thickness testing method according to claim 4, characterized in that: The relationship between the gate deviation, the gate width and the gate resistance value is constructed, including: Determine the relationship between gate deviation and gate pitch deviation based on the gate pitch determined by the design rule; Based on the determined gate block resistance and the same gate length, the gate deviation under different gate widths is a fixed value; Using two sets of corresponding variables of gate width and gate resistance, the relationship between gate deviation and gate width and gate resistance value is constructed: in, is the gate bias; and , and are the corresponding variables of two sets of gate width and gate resistance respectively.

6. The method for testing the thickness of a semiconductor gate sidewall according to claim 1, characterized in that: The actual gate sidewall thickness is the calculated gate sidewall thickness minus half of the gate deviation.

7. A semiconductor gate sidewall thickness test structure, the test structure is used for measuring electrical parameters in the semiconductor gate sidewall thickness test method according to any one of claims 1 to 6, characterized in that: comprising a plurality of first test structures and at least two second test structures; The first test structure includes two adjacent gates and at least two test pins arranged on the active area, and the at least two test pins are used to connect the target active area between the two adjacent gates on the active area for testing; The plurality of first test structures have the same target active area length and gate width, and the plurality of first test structures include at least three first test structures with different gate pitches; The second test structure includes a gate, and at least two test pins arranged on the gate; At least two of the second test structures have the same gate length, and the at least two of the second test structures include at least two second test structures with different gate widths.

8. The semiconductor gate sidewall thickness testing structure according to claim 7, characterized in that: The first test structure and the second test structure are manufactured using the same manufacturing process; wherein the same manufacturing process includes the same gate spacer process.

9. The semiconductor gate sidewall thickness testing structure according to claim 8, characterized in that: In the first test structure, the test pin includes a metal contact hole arranged on the active area and a metal wire connecting the metal contact hole; the metal contact hole is arranged on the center line of the target active area, and the test pin is arranged on the upper edge and the lower edge of the active area respectively; wherein the center line is parallel to the two adjacent gates; In the second test structure, the test pin includes a metal contact hole arranged on the gate and a metal wire connecting the metal contact hole; the metal contact holes are respectively arranged at the upper end and the lower end of the gate.

10. A semiconductor gate sidewall thickness testing device, characterized in that: It includes a gate sidewall thickness calculation module, a gate deviation calculation module and a gate sidewall thickness correction module; The gate sidewall thickness calculation module is used to measure the active area resistance value between gates at different gate spacings, draw a two-dimensional scatter plot, fit multiple points in the two-dimensional scatter plot, and obtain the gate sidewall thickness based on the fitted straight line; the gate deviation calculation module is used to measure the gate resistance value of at least two gates with different gate widths but the same gate length, and calculate the gate deviation based on the gate resistance value and the gate width; The gate sidewall thickness correction module is used to correct the gate sidewall thickness using the gate deviation to obtain an actual gate sidewall thickness.

11. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the semiconductor gate sidewall thickness testing method according to any one of claims 1 to 6 are implemented.

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