Preparation method of multi-chip interconnection packaging structure and multi-chip interconnection packaging structure

Abstract

The invention relates to a preparation method of a multi-chip interconnection packaging structure and the multi-chip interconnection packaging structure. The preparation method of the multi-chip interconnection packaging structure comprises the following steps: providing a packaging substrate and a plurality of chips; a substrate circuit is arranged in the packaging substrate; providing an interconnection chip; a chip interconnection circuit is arranged in the interconnection chip; forming a plurality of grooves in one side of the packaging substrate; mounting interconnection chips in the plurality of grooves in a one-to-one correspondence manner, wherein the thickness of the interconnection chips is smaller than or equal to the depth of the grooves; a plurality of chips are inversely arranged on the side, where the interconnection chips are exposed, of the packaging substrate, the interconnection chips are connected with at least two chips at the same time, and meanwhile the chips are connected with the substrate circuits respectively. According to the preparation method of the multi-chip interconnection packaging structure, the height of the packaging structure can be reduced, the process can be simplified, the reliability and the yield of the packaging structure can be improved, the test cost can be reduced, and the parasitic effect between the chips can be reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of chip interconnection, and in particular to a method for preparing a multi-chip interconnection packaging structure and the multi-chip interconnection packaging structure. Background Art

[0002] With the rise of industries such as artificial intelligence, high-performance computing, and data centers, the demand for high-end chips such as CPUs (central processing units) and GPUs (graphics processing units) is becoming increasingly significant. As the requirements for high speed and high bandwidth of chips become higher and higher, there is an urgent need to achieve interconnection between high-density chips. The commonly used method is to install multiple chips on a silicon adapter to achieve multiple chip interconnection, and then lead out other pins (pins) through TSV (silicon through vias), and then weld the silicon adapter to the substrate. However, the silicon adapter involves TSV technology, which is complex to design and implement. At present, the maturity of TSV technology among domestic manufacturers is not high, and the silicon adapter involves many problems in 2.5D / 3D packaging process, which will lead to packaging yield problems and low yield. In addition, TSV design will increase testing costs.

[0003] Therefore, a process method is needed to prepare a multi-chip interconnect packaging structure, which can reduce the packaging height and simplify the process while realizing multi-chip interconnection, while improving the reliability and yield of the packaging structure and reducing the testing cost. Summary of the invention

[0004] Therefore, the present invention provides a method for preparing a multi-chip interconnect packaging structure to solve the problems in the prior art of complex preparation process, low yield and high testing cost of an adapter plate used for chip interconnection.

[0005] The present invention provides a method for preparing a multi-chip interconnect packaging structure, comprising:

[0006] A packaging substrate and a plurality of chips are provided; a substrate circuit is arranged in the packaging substrate;

[0007] Providing an interconnection chip; wherein the interconnection chip is provided with a chip interconnection line;

[0008] forming a plurality of grooves on one side of the packaging substrate;

[0009] Mounting the interconnection chips in the plurality of grooves in a one-to-one correspondence, wherein the thickness of the interconnection chips is less than or equal to the depth of the grooves;

[0010] A plurality of the chips are flip-chip mounted on a side of the packaging substrate where the interconnection chip is exposed, wherein the interconnection chip at least simultaneously connects two of the chips, and each of the chips is respectively connected to the substrate circuit.

[0011] Optionally, a plurality of interconnect pads are provided on one side of the interconnect chip, and a plurality of chip pads are provided on one side of the chip;

[0012] When the interconnection chip is located in the groove, the interconnection pad is located on a surface of the interconnection chip facing away from the packaging substrate;

[0013] When the chip is arranged on a side of the packaging substrate that exposes the interconnected chip, the chip pad faces the packaging substrate;

[0014] In the step of flip-chipping a plurality of the chips on the side of the packaging substrate where the interconnection chip is exposed, the plurality of interconnection pads of the interconnection chip are respectively connected to the plurality of chip pads.

[0015] Optionally, the surface of the interconnection chip is divided into a plurality of regions, each region respectively including a portion of the plurality of interconnection pads;

[0016] In each of the regions, the interconnection pads in the same region are connected to the chip pads of the same chip, and the interconnection pads in different regions are respectively connected to the chip pads of different chips.

[0017] Optionally, the interconnect pad is connected to the chip pad by welding.

[0018] Optionally, the method for providing an interconnect chip includes:

[0019] Provide wafers;

[0020] forming an interconnection circuit layer on one side of the wafer;

[0021] A plurality of interconnect pads are formed on a side of the interconnect circuit layer facing away from the wafer to connect the interconnect circuit layer.

[0022] Optionally, the step of forming an interconnection circuit layer on one side of the wafer includes:

[0023] Sputtering to form a seed layer on the surface of the wafer;

[0024] forming a photoresist layer on the surface of the seed layer, and exposing and developing the photoresist layer to form a patterned photoresist layer;

[0025] The patterned photoresist layer is used as a mask, and the interconnection circuit layer is formed by electroplating on the side of the seed layer facing away from the wafer.

[0026] Optionally, the step of forming a plurality of interconnect pads on a side of the interconnect circuit layer facing away from the wafer includes:

[0027] forming an electrical insulation layer on a side of the interconnection line layer facing away from the wafer;

[0028] Etching the electrical insulation layer to form a plurality of openings;

[0029] Sputtering to form lower interconnect pads in the plurality of openings; the height of the lower interconnect pads being equal to the depth of the openings;

[0030] Forming a photoresist layer on the surface of the electrical insulation layer, exposing and developing the photoresist layer to form a patterned photoresist layer; using the patterned photoresist layer as a mask, forming an upper interconnect pad by electroplating on the side of the lower interconnect pad facing away from the interconnect line layer;

[0031] The lower interconnect pad and the upper interconnect pad together constitute the interconnect pad;

[0032] The upper interconnection pad has an area larger than that of the lower interconnection pad, and the upper interconnection pad also extends to cover the electrical insulation layer at the side of the opening.

[0033] Optionally, it further includes: installing a heat dissipation cover plate on a side of the plurality of chips facing away from the packaging substrate;

[0034] The heat dissipation cover plate comprises a top plate and a side plate. The top plate covers a surface of a side of the plurality of chips which faces away from the packaging substrate, and the side plate is arranged around the edge of the packaging substrate.

[0035] Optionally, the heat dissipation cover plate and the chip are bonded together by TIM glue;

[0036] The heat dissipation cover plate and the edge of the packaging substrate are bonded together by TIM glue;

[0037] The interconnection chip is mounted in the groove through a DAF film.

[0038] The present invention also provides a multi-chip interconnect packaging structure prepared according to the method for preparing the multi-chip interconnect packaging structure, comprising:

[0039] A packaging substrate, wherein a plurality of grooves are arranged on one side of the packaging substrate, and a substrate circuit is arranged inside the packaging substrate;

[0040] A plurality of interconnection chips are located in the plurality of grooves and correspond to the plurality of grooves one by one, the thickness of the interconnection chips is less than or equal to the depth of the grooves; and chip interconnection circuits are arranged in the interconnection chips;

[0041] A plurality of chips are flip-chip mounted on a side of the interconnection chip facing away from the packaging substrate, wherein the interconnection chip at least simultaneously connects two of the chips, and each of the chips is respectively connected to the substrate circuit.

[0042] The technical solution of the present invention has the following advantages:

[0043] (1) The preparation method of the multi-chip interconnection packaging structure provided by the present invention, first, a groove is formed on the packaging substrate, and the interconnection chip is mounted in the groove, which has a simple design, can effectively reduce the packaging height, simplify the process, improve the yield of the packaging structure, and reduce the testing cost; second, the chip interconnection line is arranged in the interconnection chip, so that the number of interconnection chip layers, the pad size and the line width and line spacing of the interconnection line can be unaffected by the substrate process, thereby making the line width and line spacing of the interconnection line smaller, which is conducive to the arrangement of dense lines, and there is no need to make the interconnection line on the packaging substrate, which can reduce the process steps of the packaging substrate, reduce the warping of the packaging substrate, and improve the reliability of the packaging structure; third, the interconnection chip is directly connected to the chip in the vertical direction, which can effectively reduce the parasitic effect. Therefore, the preparation method of the multi-chip interconnection packaging structure provided by the present invention can reduce the height of the packaging structure, simplify the process, and at the same time improve the reliability and yield of the packaging structure, reduce the testing cost, and reduce the parasitic effect between chips.

[0044] (2) The present invention provides a method for preparing a multi-chip interconnection packaging structure, wherein a plurality of interconnection pads are arranged on one side of the interconnection chip, and a plurality of chip pads are arranged on one side of the chip; when the interconnection chip is located in the groove, the interconnection pads are located on the surface of the interconnection chip facing away from the packaging substrate; when the chip is arranged on the side of the packaging substrate where the interconnection chip is exposed, the chip pads face the packaging substrate; in the step of flip-chipping a plurality of chips on the side of the packaging substrate where the interconnection chip is exposed, the plurality of interconnection pads of the interconnection chip are respectively connected to the plurality of chip pads, thereby realizing interconnection between the plurality of chips without making interconnection lines on the packaging substrate, thereby reducing the process steps for the packaging substrate, reducing the warping of the packaging substrate, and improving the reliability of the packaging structure.

[0045] (3) The method for preparing a multi-chip interconnect packaging structure provided by the present invention, when preparing an interconnect chip, sets the interconnect circuit layer and the interconnect pad inside the interconnect chip, which can simplify the process of preparing the multi-chip interconnect packaging structure subsequently. The preparation process of the interconnect circuit layer and the interconnect pad is not limited by the substrate and can be prepared under the optimal process. At the same time, the line width and line spacing of the interconnect circuit can be smaller, which is conducive to the arrangement of dense lines, thereby improving the reliability and yield of the packaging structure prepared subsequently. In addition, the interconnect chip can be tested and quality monitored separately, which can reduce the testing cost.

[0046] (4) The multi-chip interconnect packaging structure provided by the present invention, first, the interconnect chip is arranged in the groove on the surface of the packaging substrate, which can effectively reduce the height of the package and reduce the testing cost; second, the interconnect chip is provided with a chip interconnect line, and the line width and line spacing of the interconnect line can be smaller, which is conducive to the arrangement of dense lines and improves the reliability of the packaging structure; third, the interconnect chip is directly connected to the chip in the vertical direction, which can effectively reduce the parasitic effect. Therefore, the multi-chip interconnect packaging structure provided by the present invention can reduce the height of the packaging structure, improve the reliability of the packaging structure, reduce the testing cost, and reduce the parasitic effect between chips. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0048] Figure 1 A schematic flow chart of a method for preparing a multi-chip interconnect packaging structure according to an embodiment of the present invention;

[0049] Figure 2a , Figure 2b , Figure 2c , Figure 2d , Figure 2e and Figure 2f A schematic diagram of the structures of the steps in a specific process of a method for preparing a multi-chip interconnect packaging structure according to an embodiment of the present invention;

[0050] Figure 3 A schematic top view of interconnection pads and electrical connections on the surface of interconnected chips in a method for preparing a multi-chip interconnection packaging structure according to an embodiment of the present invention;

[0051] Figure 4 A schematic diagram of a process for preparing an interconnect chip according to an embodiment of the present invention;

[0052] Figure 5 A schematic diagram of a specific process of a method for preparing an interconnect chip according to an embodiment of the present invention;

[0053] Figure 6a , Figure 6b , Figure 6c , Figure 6d and Figure 6e It is a structural schematic diagram of each step in a specific process of a method for preparing an interconnect chip according to an embodiment of the present invention;

[0054] Figure 7The figure is a schematic diagram of a multi-chip interconnect packaging structure according to an embodiment of the present invention.

[0055] Description of reference numerals:

[0056] 1-Packaging substrate; 2-Interconnection chip; 3-Chip; 4-Heat dissipation cover; 5-TIM glue; 6-Substrate pad; 11-Groove; 21-Interconnection pad; 31-Chip pad; 201-Wafer; 202-Interconnection line layer; 203-Electrical insulation layer; 204-Opening; 205-Lower interconnection pad; 206-Upper interconnection pad. DETAILED DESCRIPTION

[0057] In order to solve the problems of complicated preparation process, low yield and high testing cost of the adapter plate used for chip interconnection in the prior art, the present invention provides a preparation method of a multi-chip interconnection packaging structure, comprising the following steps: providing a packaging substrate and a plurality of chips; a substrate circuit is arranged in the packaging substrate; providing an interconnection chip; a chip interconnection circuit is arranged in the interconnection chip; forming a plurality of grooves on one side of the packaging substrate; mounting the interconnection chips in the plurality of grooves one by one, wherein the thickness of the interconnection chips is less than or equal to the depth of the grooves; and flip-chipping a plurality of the chips on the side of the packaging substrate where the interconnection chips are exposed, wherein the interconnection chip is connected to at least two of the chips at the same time, and each of the chips is respectively connected to the substrate circuit.

[0058] The present invention also provides a multi-chip interconnection packaging structure prepared according to the preparation method of the above-mentioned multi-chip interconnection packaging structure, comprising: a packaging substrate, a plurality of grooves are arranged on one side of the packaging substrate, and a substrate circuit is arranged in the packaging substrate; a plurality of interconnection chips are located in the plurality of grooves and correspond one-to-one to the plurality of grooves, and the thickness of the interconnection chip is less than or equal to the depth of the grooves; a chip interconnection circuit is arranged in the interconnection chip; a plurality of chips are flip-chip arranged on the side of the interconnection chip facing away from the packaging substrate, wherein the interconnection chip is connected to at least two of the chips at the same time, and each of the chips is respectively connected to the substrate circuit.

[0059] The technical solution of the present invention will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention. In the description of the present invention, it should be noted that the terms "first", "second" and "third" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance.

[0060] Example 1

[0061] refer to Figure 1 This embodiment provides a method for preparing a multi-chip interconnect packaging structure, comprising:

[0062] S101, providing a packaging substrate and a plurality of chips; the packaging substrate is provided with a substrate circuit;

[0063] S102, providing an interconnection chip; the interconnection chip is provided with a chip interconnection circuit;

[0064] S103, forming a plurality of grooves on one side of the packaging substrate;

[0065] S104, mounting the interconnection chips in the plurality of grooves in a one-to-one correspondence, wherein the thickness of the interconnection chips is less than or equal to the depth of the grooves;

[0066] S105 , flip-chipping a plurality of the chips on a side of the packaging substrate where the interconnection chip is exposed, wherein the interconnection chip at least simultaneously connects two of the chips, and each of the chips is respectively connected to the substrate circuit.

[0067] When implementing it, refer to Figure 2a to Figure 2d First, a packaging substrate 1 is provided, such as Figure 2a As shown, the package substrate 1 is provided with a substrate circuit (not shown in the figure); then, an interconnection chip 2 is provided, and the interconnection chip 1 is provided with a chip interconnection circuit (not shown in the figure); secondly, a plurality of grooves 11 are formed on one side of the package substrate 1, such as Figure 2b As shown; again, as Figure 2c As shown, the interconnection chips 2 are mounted one by one in the plurality of the grooves 11, and the thickness of the interconnection chips 1 is less than or equal to the depth of the grooves 11; finally, as shown Figure 2d As shown, a plurality of chips 3 are flip-chip mounted on a side of the packaging substrate 1 where the interconnection chip 2 is exposed, wherein the interconnection chip 2 is connected to at least two of the chips 3 at the same time, and each of the chips 3 is connected to the substrate circuit 1 respectively.

[0068] The preparation method of the multi-chip interconnection packaging structure provided in this embodiment, first, a groove is formed in the packaging substrate, and the interconnection chip is mounted in the groove, which has a simple design, can effectively reduce the packaging height, simplify the process, improve the yield of the packaging structure, and reduce the testing cost; second, the chip interconnection circuit is arranged in the interconnection chip, so that the number of interconnection chip layers, the pad size and the line width and line spacing of the interconnection circuit can be unaffected by the substrate process, thereby making the line width and line spacing of the interconnection circuit smaller, which is conducive to the arrangement of dense lines, and there is no need to make the interconnection circuit on the packaging substrate, which can reduce the process steps of the packaging substrate, reduce the warping of the packaging substrate, and improve the reliability of the packaging structure; third, the interconnection chip is directly connected to the chip in the vertical direction, which can effectively reduce the parasitic effect. Therefore, the preparation method of the multi-chip interconnection packaging structure provided by the present invention can reduce the height of the packaging structure, simplify the process, and at the same time improve the reliability and yield of the packaging structure, reduce the testing cost, and can also reduce the parasitic effect between chips.

[0069] Further, in some embodiments, Figure 2d As shown, a plurality of interconnect pads 21 are provided on one side of the interconnect chip 2, and a plurality of chip pads 31 are provided on one side of the chip 3;

[0070] When the interconnection chip 2 is located in the groove 11, the interconnection pad 21 is located on the surface of the interconnection chip 2 facing away from the packaging substrate 1;

[0071] When the chip 3 is arranged on a side of the package substrate 1 that exposes the interconnection chip 2, the chip pad 21 faces the package substrate 1;

[0072] In the step of flip-chipping a plurality of the chips on the side of the package substrate that exposes the interconnection chip, the plurality of interconnection pads 21 of the interconnection chip 2 are respectively connected to the plurality of chip pads 31 .

[0073] During specific implementation, since the interconnection chip 2 is already provided with chip interconnection lines and chip pads 21, after the step of mounting the interconnection chips in the plurality of grooves one by one, it is not necessary to make interconnection lines on the packaging substrate. Instead, the plurality of chips 3 can be directly flip-chip mounted on the side of the packaging substrate 1 where the interconnection chip 2 is exposed, and the plurality of interconnection pads 21 of the interconnection chip 2 are respectively connected to the plurality of chip pads 31, thereby realizing interconnection between the plurality of chips 3, reducing the process steps for the packaging substrate, reducing the warping of the packaging substrate, and improving the reliability of the packaging structure.

[0074] Further, in some embodiments, the surface of the interconnection chip 2 is divided into a plurality of regions, each region respectively including a portion of the plurality of interconnection pads;

[0075] In each of the regions, the interconnection pads in the same region are connected to the chip pads of the same chip, and the interconnection pads in different regions are respectively connected to the chip pads of different chips.

[0076] In a specific implementation, in an example, Figure 3 As shown, the surface of the interconnection chip 2 is divided into two areas (area A and area B), each area respectively includes a part of a plurality of interconnection pads; wherein the interconnection pads 21 in area A are connected to the chip pads 31 of one chip, and the interconnection pads 21 in area B are connected to the chip pads 31 of another chip. The interconnection pads 21 in area A and the interconnection pads 21 in area B are respectively connected to the chip pads 31 of different chips 3.

[0077] Furthermore, in some embodiments, the interconnect pad 21 is connected to the chip pad 31 by welding.

[0078] In a specific implementation, the interconnect pad 21 is a metal pad / pin (PAD) with a relatively small protrusion, and the material is generally titanium copper, copper, aluminum, etc.; the chip pad 31 is a metal bump with a relatively large protrusion, such as a copper column, a tin bump, etc. The interconnect pad 21 and the chip pad 31 are connected together by welding, thereby realizing the interconnection of the interconnection chip 2 and the plurality of chips 3.

[0079] Furthermore, in some embodiments, the method for providing an interconnection chip can directly use an existing interconnection chip, or can be based on the following example: Figure 4 The interconnection chip is prepared by the method for preparing the interconnection chip shown, and the method for preparing the interconnection chip comprises the following steps:

[0080] S201, providing a wafer;

[0081] S202, forming an interconnection circuit layer on one side of the wafer;

[0082] S203, forming a plurality of interconnect pads on a side of the interconnect circuit layer facing away from the wafer to connect the interconnect circuit layer.

[0083] The method for preparing the interconnection chip provided in this embodiment arranges the interconnection circuit layer and the interconnection pad inside the interconnection chip, which can simplify the process of the subsequent preparation of the multi-chip interconnection packaging structure. The preparation process of the interconnection circuit layer and the interconnection pad is not limited by the substrate and can be prepared under the optimal process. At the same time, the line width and line spacing of the interconnection circuit can be smaller, which is conducive to the arrangement of dense lines, thereby improving the reliability and yield of the subsequent packaging structure. In addition, the interconnection chip can be tested and quality-monitored separately, which can reduce the testing cost.

[0084] Furthermore, in some embodiments, the step of forming an interconnection circuit layer on one side of the wafer includes:

[0085] Sputtering to form a seed layer on the surface of the wafer;

[0086] forming a photoresist layer on the surface of the seed layer, and exposing and developing the photoresist layer to form a patterned photoresist layer;

[0087] The patterned photoresist layer is used as a mask, and the interconnection circuit layer is formed by electroplating on the side of the seed layer facing away from the wafer.

[0088] In a specific implementation, the material of the seed layer is metal, the material of the interconnection line layer is metal, and the material of the photoresist layer is PR.

[0089] In a specific example, the material of the seed layer is TiCu, and the seed layer is formed by sputtering TiCu on the surface of the wafer.

[0090] Furthermore, in some embodiments, the step of forming a plurality of interconnect pads on a side of the interconnect circuit layer facing away from the wafer includes:

[0091] forming an electrical insulation layer on a side of the interconnection line layer facing away from the wafer;

[0092] Etching the electrical insulation layer to form a plurality of openings;

[0093] Sputtering to form lower interconnect pads in the plurality of openings; the height of the lower interconnect pads being lower than the depth of the openings;

[0094] Forming a photoresist layer on the surface of the electrical insulation layer, exposing and developing the photoresist layer to form a patterned photoresist layer; using the patterned photoresist layer as a mask, forming an upper interconnect pad by electroplating on the side of the lower interconnect pad facing away from the interconnect line layer;

[0095] The lower interconnect pad and the upper interconnect pad together constitute the interconnect pad;

[0096] The upper interconnection pad has an area larger than that of the lower interconnection pad, and the upper interconnection pad also extends to cover the electrical insulation layer at the side of the opening.

[0097] In a specific implementation, the material of the electrical insulation layer is PI (Polyimide), the photoresist is PR (Photoresist) photoresist, and the material of the lower interconnection pad and the upper interconnection pad is metal. Using PI as the electrical insulation layer can relieve the stress of the interconnection pad.

[0098] In a specific example, the material of the lower interconnect pad is TiCu, and the material of the upper interconnect pad is Cu or SnAg. The lower interconnect pad is formed by sputtering TiCu in the plurality of openings, and the upper interconnect pad is formed by electroplating Cu or SnAg on the side of the seed layer facing away from the wafer.

[0099] In a specific implementation, the size of the upper interconnect pad can be determined based on the height difference between the interconnected chip and the chip pad of the chip; the size of the upper interconnect pad is about 10um larger than the single side of the upper interconnect pad, which can facilitate welding between the chip and the interconnected chip.

[0100] refer to Figure 5 and Figure 6a to Figure 6e The following provides a specific process of a method for preparing an interconnection chip 2, including steps S301-S309.

[0101] S301, providing a wafer 201, such as Figure 6a shown.

[0102] S302 , sputtering TiCu on the surface of the wafer 201 to form a seed layer.

[0103] S303, forming a photoresist layer on the surface of the seed layer, exposing and developing the photoresist layer to form a patterned photoresist layer.

[0104] S304, using the patterned photoresist layer as a mask, forming the interconnection circuit layer 202 by electroplating Cu on the side of the seed layer facing away from the wafer, such as Figure 6b shown.

[0105] S306, forming a PI electrical insulation layer 203 on the side of the interconnection line layer 202 facing away from the wafer 201, such as Figure 6c shown.

[0106] S306 , etching the electrical insulation layer 203 to form a plurality of openings 204 .

[0107] S307, sputtering TiCu in the plurality of openings 204 to form lower interconnect pads 205; the height of the lower interconnect pads 205 is equal to the depth of the openings 204, such as Figure 6d shown.

[0108] S308, forming a photoresist layer on the surface of the electrical insulation layer 203, exposing and developing the photoresist layer to form a patterned photoresist layer; using the patterned photoresist layer as a mask, electroplating SnAg on the side of the lower interconnect pad 205 facing away from the interconnect line layer 202 to form an upper interconnect pad 206; the lower interconnect pad 205 and the upper interconnect pad 206 together constitute the interconnect pad 21, and the interconnect pad 21 is connected to the interconnect line layer 202, such as Figure 6d shown.

[0109] The area of ​​the upper interconnect pad 206 is larger than that of the lower interconnect pad 205 , and the upper interconnect pad 206 also extends to cover the electrical insulation layer 203 at the side of the opening 204 .

[0110] S309, thinning the side of the wafer 201 facing away from the interconnection pad 21, such as Figure 6e shown.

[0111] Further, in some embodiments, Figure 2e As shown, after the step of flip-chipping a plurality of the chips on the side of the packaging substrate exposing the interconnected chips, the step further includes:

[0112] A heat dissipation cover plate 4 is installed on a side of the plurality of chips 3 facing away from the packaging substrate 1;

[0113] The heat dissipation cover plate 4 includes a top plate and a side plate. The top plate covers a surface of a side of the plurality of chips facing away from the packaging substrate, and the side plate is disposed around the edge of the packaging substrate.

[0114] In specific implementation, the heat dissipation cover plate 4 can be designed to be hollow to provide heat dissipation for the chip. At the same time, the warping problem of multi-chip large-size packaging is also relatively serious, which may cause a cold solder joint problem when the package is welded to the PCB board. Therefore, the heat dissipation cover plate can also significantly improve the package warping.

[0115] Further, in some embodiments, Figure 2e As shown, the heat dissipation cover plate 4 and the chip 3 are bonded together by TIM glue 5;

[0116] The heat dissipation cover plate 4 and the edge of the packaging substrate 1 are also bonded together by TIM glue (not shown in the figure).

[0117] In specific implementation, since TIM glue has good bonding effect and good thermal conductivity, TIM glue is used to bond the heat dissipation cover plate 4 to the chip 2, and to bond the heat dissipation cover plate 5 to the edge of the packaging substrate 1, which can make the bonding of the heat dissipation cover plate more stable and improve the heat dissipation effect.

[0118] Furthermore, in some embodiments, the interconnection chip 2 is mounted in the groove 11 using a DAF film.

[0119] In specific implementation, since the DAF film is a prefabricated dry adhesive film, it can be directly adhered to the back side of the interconnection chip 2 for mounting, which has simple process, fast heat dissipation and strong corrosion resistance.

[0120] Furthermore, in some embodiments, the thickness of the DAF film is less than or equal to 30 μm.

[0121] In some embodiments, the thickness of the interconnection chip is equal to the depth of the groove. After the interconnection chips are mounted one by one in the plurality of grooves, the upper surface of the interconnection chip is higher than the upper surface of the package substrate by less than 30 μm. The height difference here can be increased by less than 30 μm by substrate surface treatment SOP (solder on pad) to make the pad surface of the interconnection chip and the substrate surface pad substantially in the same plane, which is conducive to welding multiple chips with the substrate and the interconnection chip.

[0122] In other embodiments, the thickness of the interconnection chip is within 30 μm less than the depth of the groove. After the interconnection chips are mounted one by one in the plurality of grooves, the upper surface of the interconnection chip is substantially in the same plane as the upper surface of the packaging substrate, which facilitates welding of multiple chips with the substrate and the interconnection chip.

[0123] Further, in some embodiments, Figure 2f As shown, after the step of installing a heat dissipation cover plate on a side of the plurality of chips facing away from the packaging substrate, the step further includes:

[0124] A substrate pad 6 is formed on a surface of the packaging substrate 1 which is opposite to the interconnection chip 2 .

[0125] Example 2

[0126] refer to Figure 7 The present invention also provides a multi-chip interconnect packaging structure prepared according to the above-mentioned method for preparing the multi-chip interconnect packaging structure, comprising:

[0127] A packaging substrate 1, wherein a plurality of grooves 11 are provided on one side of the packaging substrate, and a substrate circuit is provided inside the packaging substrate 1;

[0128] A plurality of interconnection chips 2 are located in the plurality of grooves 11 and correspond to the plurality of grooves 11 one by one. The thickness of the interconnection chip 2 is less than or equal to the depth of the groove 11. The interconnection chip 2 is provided with a chip interconnection circuit.

[0129] A plurality of chips 3 are flip-chip mounted on a side of the interconnection chip 2 facing away from the packaging substrate 1, wherein the interconnection chip 2 is connected to at least two of the chips 3 at the same time, and each of the chips 3 is connected to the substrate circuit respectively.

[0130] The multi-chip interconnection packaging structure provided in this embodiment has the following characteristics: first, the interconnection chip is arranged in a groove on the surface of the packaging substrate, which can effectively reduce the height of the packaging and reduce the testing cost; second, the interconnection chip is provided with a chip interconnection line, and the line width and line spacing of the interconnection line can be smaller, which is conducive to the arrangement of dense lines and improves the reliability of the packaging structure; third, the interconnection chip is directly connected to the chip in the vertical direction, which can effectively reduce the parasitic effect. Therefore, the multi-chip interconnection packaging structure provided in this embodiment can reduce the height of the packaging structure, improve the reliability of the packaging structure, reduce the testing cost, and reduce the parasitic effect between chips.

[0131] Obviously, the above embodiments are merely examples for the purpose of clear explanation, and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived therefrom are still within the scope of protection of the invention.

Claims

1. A method for preparing a multi-chip interconnect packaging structure, characterized in that: include: Providing a packaging substrate and a plurality of chips; A substrate circuit is arranged in the packaging substrate; Providing interconnect chips; The interconnection chip is provided with a chip interconnection circuit; forming a plurality of grooves on one side of the packaging substrate; Mounting the interconnection chips in the plurality of grooves in a one-to-one correspondence, wherein the thickness of the interconnection chips is less than or equal to the depth of the grooves; A plurality of the chips are flip-chip mounted on a side of the packaging substrate where the interconnection chip is exposed, wherein the interconnection chip at least simultaneously connects two of the chips, and each of the chips is respectively connected to the substrate circuit.

2. The method for preparing a multi-chip interconnect packaging structure according to claim 1, characterized in that: A plurality of interconnect pads are provided on one side of the interconnect chip, and a plurality of chip pads are provided on one side of the chip; When the interconnection chip is located in the groove, the interconnection pad is located on a surface of the interconnection chip facing away from the packaging substrate; When the chip is arranged on a side of the packaging substrate that exposes the interconnected chip, the chip pad faces the packaging substrate; In the step of flip-chipping a plurality of the chips on the side of the packaging substrate where the interconnection chip is exposed, the plurality of interconnection pads of the interconnection chip are respectively connected to the plurality of chip pads.

3. The method for preparing a multi-chip interconnect packaging structure according to claim 2, characterized in that: The interconnect chip surface is divided into a plurality of regions, each region respectively including a portion of the plurality of interconnect pads; In each of the regions, the interconnection pads in the same region are connected to the chip pads of the same chip, and the interconnection pads in different regions are respectively connected to the chip pads of different chips.

4. The method for preparing a multi-chip interconnect packaging structure according to claim 3, characterized in that: The interconnect pad is connected to the chip pad by welding.

5. The method for preparing a multi-chip interconnect packaging structure according to claim 1, characterized in that: The method for providing an interconnect chip comprises: Provide wafers; forming an interconnection circuit layer on one side of the wafer; A plurality of interconnect pads are formed on a side of the interconnect circuit layer facing away from the wafer to connect the interconnect circuit layer.

6. The method for preparing a multi-chip interconnect packaging structure according to claim 5, characterized in that: The step of forming an interconnection circuit layer on one side of the wafer includes: Sputtering to form a seed layer on the surface of the wafer; forming a photoresist layer on the surface of the seed layer, and exposing and developing the photoresist layer to form a patterned photoresist layer; The patterned photoresist layer is used as a mask, and the interconnection circuit layer is formed by electroplating on the side of the seed layer facing away from the wafer.

7. The method for preparing a multi-chip interconnect packaging structure according to claim 5, characterized in that: The step of forming a plurality of interconnect pads on a side of the interconnect circuit layer facing away from the wafer includes: forming an electrical insulation layer on a side of the interconnection line layer facing away from the wafer; Etching the electrical insulation layer to form a plurality of openings; Sputtering to form lower interconnect pads in the plurality of openings; the height of the lower interconnect pads being equal to the depth of the openings; forming a photoresist layer on the surface of the electrical insulation layer, exposing and developing the photoresist layer to form a patterned photoresist layer; using the patterned photoresist layer as a mask, forming an upper interconnect pad by electroplating on the side of the lower interconnect pad facing away from the interconnect line layer; The lower interconnect pad and the upper interconnect pad together constitute the interconnect pad; The upper interconnection pad has an area larger than that of the lower interconnection pad, and the upper interconnection pad also extends to cover the electrical insulation layer at the side of the opening.

8. The method for preparing a multi-chip interconnect packaging structure according to claim 1, characterized in that: After the step of flip-chipping a plurality of the chips on the side of the package substrate that exposes the interconnection chip, the step further includes: Installing a heat dissipation cover plate on a side of the plurality of chips facing away from the packaging substrate; The heat dissipation cover plate comprises a top plate and a side plate. The top plate covers a surface of a side of the plurality of chips which faces away from the packaging substrate, and the side plate is arranged around the edge of the packaging substrate.

9. The method for preparing a multi-chip interconnect packaging structure according to claim 8, characterized in that: The heat dissipation cover plate and the chip are bonded together by TIM glue; The heat dissipation cover plate and the edge of the packaging substrate are bonded together by TIM glue; The interconnection chip is mounted in the groove through a DAF film.

10. A multi-chip interconnect packaging structure, prepared by the method for preparing a multi-chip interconnect packaging structure according to claims 1 to 9, characterized in that: include: A packaging substrate, wherein a plurality of grooves are arranged on one side of the packaging substrate, and a substrate circuit is arranged inside the packaging substrate; A plurality of interconnection chips are located in the plurality of grooves and correspond to the plurality of grooves one by one, the thickness of the interconnection chips is less than or equal to the depth of the grooves; and chip interconnection circuits are arranged in the interconnection chips; A plurality of chips are flip-chip mounted on a side of the interconnection chip facing away from the packaging substrate, wherein the interconnection chip at least simultaneously connects two of the chips, and each of the chips is respectively connected to the substrate circuit.

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