Ggnmos electrostatic discharge protection device and method of manufacturing the same

Abstract

This invention provides a GGNMOS electrostatic discharge (ESD) protection device and its fabrication method, comprising: a P-type substrate, an N-type buried layer, a first N-type deep well, a second N-type deep well, and a first P-type well; the first N-type deep well and the second N-type deep well are further provided with a first N+ injection region and a fourth N+ injection region; the first P-type well is provided with a P-type semiconductor substrate and a gate region, a source region, and a drain region of a first NMOS, wherein the drain region of the first NMOS is widened; the first N-type deep well, the second N-type deep well, and the first N+ injection region, the fourth N+ injection region, and the N-type buried layer constitute an N-type isolation band; the P-type semiconductor substrate is connected to the source region of the first NMOS and serves as the cathode of the device, and the drain region of the first NMOS is connected to the first N+ injection region and the fourth N+ injection region on the first N-type deep well and the second N-type deep well and serves as the anode of the device; the gate region of the first NMOS is located between the second N+ and third N+ injection regions; the gate region of the first NMOS is connected to a coupling circuit of a first PMOS, a capacitor C, and an inverter.

Description

Technical Field

[0001] This invention relates to the field of electrostatic discharge (ESD) protection, and more particularly to an ESD protection device for a gate-grounded NMOS (GGNMOS) transistor and its fabrication method. Background Technology

[0002] With advancements in semiconductor manufacturing processes, integrated circuit feature sizes are shrinking and chip integration is increasing, making electrostatic discharge (ESD)-induced failures in chips and electronic products more severe. ESD protection for electronic products and integrated circuit chips has become one of the major challenges faced by product engineers.

[0003] Gate-grounded NMOS (GGNMOS) is a commonly used ESD protection device. Traditional MOSFETs are four-port devices, inherently compatible with manufacturing processes, simple in structure, easy to simulate, and exhibit hysteresis characteristics, resulting in strong robustness. However, they typically require external auxiliary circuitry, thus occupying a large silicon area. Furthermore, MOSFETs are prone to thermal failure when discharging large currents at the surface, requiring careful consideration during design. GGNMOS is an improvement upon traditional MOSFETs, primarily relying on avalanche breakdown at the drain to achieve NPN transistor conduction. This invention adds an inverter to the GGNMOS, preventing false triggering, reducing the trigger voltage, enhancing the GGNMOS's driving capability, and making its conduction more uniform. It also uses a PMOS and capacitively coupled detection circuit. Due to the extremely fast response speed of PMOS, the GGNMOS can turn on more quickly, preventing ESD pulses from damaging the internal circuitry of the ESD protection device due to a slow turn-on speed.

[0004] A cross-sectional view of a traditional RC-coupled electrostatic discharge (ESD) device is shown below. Figure 1 Its equivalent circuit diagram is shown in Figure 2 When an ESD pulse is applied to the anode of the device, the RC circuit couples a voltage onto the gate of the NMOS transistor. This gate voltage turns on the NMOS channel, allowing current to flow from the drain to the source. The voltage between the drain and source then rises to a certain current value, causing a current to flow from the channel to the substrate. The MOS transistor enters the hysteresis region without undergoing avalanche breakdown, and the parasitic transistor turns on. However, a larger value for R in the RC coupling circuit results in slower voltage and current discharge from the NMOS gate, acting as a delay. Ideally, the MOS transistor should remain on throughout the ESD event. However, a large value for C can easily cause false triggering, while a large value for R can cause the transistor to remain on even after the ESD event has passed, resulting in additional power consumption. Therefore, a trade-off needs to be struck. Summary of the Invention

[0005] This invention provides a simple PMOS and capacitively coupled GGNMOS electrostatic protection device that enables rapid turn-on and prevents false triggering, and its fabrication method.

[0006] To achieve the above objectives, the technical solution of this invention is implemented as follows:

[0007] An embodiment of the present invention provides a GGNMOS electrostatic discharge protection device, comprising:

[0008] P-type substrate;

[0009] The P-type substrate has an N-type buried layer;

[0010] Above the N-type buried layer are a first N-type deep well, a second N-type deep well, and a first P-type well;

[0011] The first N-type deep well and the second N-type deep well are further provided with a first N+ injection region and a fourth N+ injection region;

[0012] The first P-type well is provided with a P-type semiconductor substrate and a gate region, a source region, and a drain region of a first NMOS, wherein the drain region of the first NMOS is widened;

[0013] The first N-type deep well, the second N-type deep well, the first N+ injection region, the fourth N+ injection region, and the N-type buried layer together constitute an N-type isolation zone;

[0014] The P-type semiconductor substrate is connected to the source region of the first NMOS and serves as the cathode of the device. The drain region of the first NMOS is connected to the first N-type deep well, the first N+ injection region on the second N-type deep well, and the fourth N+ injection region and serves as the anode of the device.

[0015] The gate region of the first NMOS is located between the second N+ and the third N+ injection region;

[0016] The gate region of the first NMOS is connected to the coupling circuit of the first PMOS, capacitor C, and inverter.

[0017] The second N+ injection region and the third N+ injection region are separated by the gate region of the first NMOS, and any two injection regions are separated by field oxygen isolation regions, which are the first field oxygen isolation region, the second field oxygen isolation region, the third field oxygen isolation region, the fourth field oxygen isolation region and the fifth field oxygen isolation region from left to right.

[0018] Wherein, the left side of the first field oxygen isolation region is located at the left edge of the P-type substrate, the right side of the first field oxygen isolation region is located at the left side of the first N+ implantation region, the left side of the second field oxygen isolation region is located at the right side of the first N+ implantation region, the right side of the second field oxygen isolation region is located at the left side of the second N+ implantation region, the left side of the third field oxygen isolation region is located at the right side of the third N+ implantation region, the right side of the third field oxygen isolation region is located at the left side of the first P+ implantation region, the left side of the fourth field oxygen isolation region is located at the right side of the first P+ implantation region, the right side of the fourth field oxygen isolation region is located at the left side of the fourth N+ implantation region, the left side of the fifth field oxygen isolation region is located at the right side of the fourth N+ implantation region, and the right side of the fifth field oxygen isolation region is located at the right edge of the P-type substrate.

[0019] The inverter includes a second PMOS and a second NMOS; the substrate and source region of the second PMOS are connected to the anode, and the substrate and source region of the second NMOS are connected to the cathode; the drain regions of the second PMOS and the drain regions of the second NMOS are connected as the F terminal of the inverter; the gate regions of the second PMOS and the gate regions of the second NMOS are connected as the E terminal of the inverter.

[0020] This invention also provides a method for manufacturing a GGNMOS electrostatic discharge protection device, characterized in that the method includes:

[0021] Step 1: Form an N-type buried layer in a P-type substrate;

[0022] Step 2: Generate a first N-type deep well and a second N-type deep well above the N-type buried layer;

[0023] Step 3: Above the N-type buried layer, at the same depth as the N-type deep well, a first P-well is generated, with the distance between the first P-well and the N-type deep well being zero;

[0024] Step 4: Generate a first P+ injection, a second N+ injection, and a third N+ injection on the first P-well; generate a first N+ injection on the first N-type deep well; and generate a fourth N+ injection on the third N-type deep well.

[0025] Step 5: Generate a POLY gate between the second N+ injection and the third N+ injection;

[0026] Step Six: Generate the first to fifth oxygen isolation zones sequentially from left to right;

[0027] Step 7: Anneal all injection zones to eliminate the migration of impurities within the injection zones;

[0028] Step 8: Connect the substrate and source region of the second PMOS together with metal and connect them to the anode of the device; connect the substrate and source region of the second NMOS together and connect them to the cathode of the device; connect the drain region of the second PMOS and the drain region of the second NMOS together with metal and use them as the F terminal of the inverter; connect the gate region of the second PMOS and the gate region of the second NMOS together and use them as the E terminal of the inverter.

[0029] Step 9: Connect the first P+ injection region and the third N+ injection region together with a metal layer to serve as the cathode of the device. Connect the first N+ injection region, the second N+ injection region, and the fourth N+ injection region together to serve as the anode of the device. Connect the gate terminal to the F terminal of the inverter. Connect a capacitor between the E terminal of the inverter and the cathode. Connect the first PMOS between the E terminal of the inverter and the anode. Connect the gate of the first PMOS to the cathode.

[0030] The method further includes the following steps prior to the above:

[0031] A silicon dioxide thin film is grown on the P-type substrate, followed by the deposition of a silicon nitride layer; a photoresist layer is spin-coated onto the wafer, and a mask is used to expose and develop it to form a shallow isolation trench; the silicon dioxide, silicon nitride, and shallow isolation trench are etched to remove the photoresist layer, a silicon dioxide layer is deposited, and then chemical polishing is performed until the silicon nitride layer is removed.

[0032] This invention provides a GGNMOS electrostatic discharge protection device and its fabrication method, with the following advantages:

[0033] 1. The widened drain region of the GGNMOS in this invention can improve the secondary failure current.

[0034] 2. This invention adds an inverter, which can prevent false triggering due to excessive capacitance value and reduce the trigger voltage, making the conduction of GGNMOS more uniform and enhancing the driving capability of GGNMOS.

[0035] 3. This invention can simulate the gate coupling voltage under different processes to obtain the appropriate PMOS and capacitor coupling value and the appropriate gate coupling voltage under the process, so that the channel is slightly opened, thereby reducing the device trigger voltage and improving the device turn-on speed.

[0036] 4. The use of the first and second N-type deep traps and the N-type buried layer in this invention not only has a good isolation effect, but also reduces unnecessary parasitic effects. Attached Figure Description

[0037] Figure 1 This is a cross-sectional view of a known RC-coupled electrostatic discharge protection device for GGNMOS.

[0038] Figure 2 The equivalent circuit diagram of the currently known RC-coupled electrostatic discharge protection device for GGNMOS;

[0039] Figure 3 This is a cross-sectional view of a GGNMOS electrostatic protection device provided in an embodiment of the present invention;

[0040] Figure 4 The equivalent circuit diagram of a GGNMOS electrostatic discharge protection device provided in an embodiment of the present invention. Detailed Implementation

[0041] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0042] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.

[0043] like Figure 3 As shown, a GGNMOS electrostatic discharge (ESD) protection device with fast PMOS and capacitive coupling for preventing false triggering includes a P-type substrate 101; an N-type buried layer 201 is provided in the substrate; above the N-type buried layer are a first N-type deep well 301, a second N-type deep well 302, and a first P-type well 401; a first N+ injection region 501 is provided on the first N-type deep well, and a fourth N+ injection region 504 is provided on the second N-type deep well; a second N+ injection region 502, a third N+ injection region 503, and a first P+ injection region 601 are provided in the first P-well;

[0044] A gate region 701 is located between the second N+ injection region 502 and the third N+ injection region 503; the first and second N-type deep wells (301, 302) and the N-type buried layer 201 form an N-type isolation band, surrounding the core area of ​​the device; the first, second, and fourth N+ injection regions (501, 502, 504) are connected together and serve as the anode of the device, and the third N+ injection region 503 is connected together with the first P+ injection region 601 and serves as the cathode of the device; the gate region 701 is located between the second N+ 502 and the third N+ injection region 503; the gate region is connected to the F port of the inverter INV801, the drain region of the first PMOS (P802) and the upper plate of the capacitor C803 are connected to the E terminal of the inverter, the source region of the first PMOS (P802) is connected to the anode, and the gate region of the first PMOS (P802) and the lower plate of the capacitor C803 are connected to the cathode.

[0045] The aforementioned GGNMOS electrostatic discharge protection device, which couples PMOS, capacitor, and inverter for fast turn-on and prevents false triggering, is characterized in that: the second N+ injection region and the third N+ injection region are separated by a gate region 701, and a first field oxygen isolation region to a fifth field oxygen isolation region are generated sequentially from left to right between the other injection regions; the first and second N+ injection regions (503, 504) are separated by a gate region 701, and in addition, each injection region is separated by a field oxygen FOX, which are the first to fifth field oxygen isolation regions (602-606) sequentially from left to right;

[0046] The aforementioned field oxygen regions are characterized in that: the left side of the first field oxygen isolation region 602 is located at the left edge of the P-type substrate, the right side of the first field oxygen isolation region 602 is located at the left side of the first N+ implantation region 501, the left side of the second field oxygen isolation region 603 is located at the right side of the first N+ implantation region 501, the right side of the second field oxygen isolation region 603 is located at the left side of the second N+ implantation region 502, the left side of the third field oxygen isolation region 604 is located at the right side of the third N+ implantation region 503, the right side of the third field oxygen isolation region 604 is located at the left side of the first P+ implantation region 601, the left side of the fourth field oxygen isolation region 605 is located at the right side of the first P+ implantation region 601, the right side of the fourth field oxygen isolation region 605 is located at the left side of the fourth N+ implantation region 504, the left side of the fifth field oxygen isolation region 606 is located at the right side of the fourth N+ implantation region 504, and the right side of the fifth field oxygen isolation region 606 is located at the right edge of the P-type substrate.

[0047] The aforementioned GGNMOS electrostatic discharge (ESD) protection device, which uses PMOS, capacitor, and inverter coupling for rapid turn-on and prevention of false triggering, is characterized by: the source region (503) and substrate (601) of the GGNMOS being grounded, the gate region (701) being connected to the F terminal of the inverter (INV801), and the drain region (502) being connected to the anode; when a high-voltage ESD pulse reaches the anode of the device and the cathode of the device is connected to a low potential, the first GGNMOS (P802), capacitor C803, and inverter (INV801) are coupled together to enable fast turn-on and prevent false triggering. The gate terminal 701 of the MOS transistor generates a high gate voltage, which enables the NMOS transistor to conduct through the channel, allowing current to flow from the drain region to the source region. The GGNMOS transistor initially forms a channel and conducts, with the voltage between the drain terminal 502 and the source terminal 503 continuously rising. When a certain voltage value is reached, due to the channel conduction, a certain current flows to the substrate, and the MOS transistor enters the hysteresis region without undergoing avalanche breakdown, turning on the parasitic transistor. Finally, the channel conduction changes to the parasitic transistor conduction, discharging the current. The drain region of the GGNMOS transistor is widened to enhance the secondary breakdown current.

[0048] The inverter (INV801) is characterized in that: the inverter of the device includes a second PMOS (P702) and a second NMOS (N703); the substrate and source region of the second PMOS (P702) are connected to the anode, and the substrate and source region of the second NMOS (N703) are connected to the cathode; the drain region of the second PMOS (P702) and the drain region of the second NMOS (N703) are connected as the F terminal of the inverter; the gate region of the second PMOS (P702) and the gate region of the second NMOS (N703) are connected as the E terminal of the inverter; the addition of the inverter (INV801) can prevent false triggering events, reduce the trigger voltage, enhance the conduction uniformity of the GGNMOS, and enhance the driving capability of the GGNMOS, so that the first GGNMOS can turn on faster, and prevent the ESD protection device from being damaged by ESD pulses due to the slow turn-on speed.

[0049] The first PMOS (P802) and capacitor C803 are characterized by the following: the gate ground of the first PMOS (P802) is considered as a resistor, and the network coupled between the PMOS (P802) and capacitor C803 is responsible for ESD pulse detection and signal delay. For ordinary RC coupling, in order to ensure that the clamped MOS transistor remains on throughout the entire ESD event, the RC constant is usually greater than or equal to the pulse width of HBM. However, the larger the R is, the slower the voltage and current discharge capability on the gate region of the GGNMOS transistor, which plays a delaying role. To prevent the ESD protection device from being damaged by the ESD pulse due to its slow turn-on speed, a PMOS transistor with a faster response speed is selected.

[0050] The aforementioned GGNMOS electrostatic discharge (ESD) protection device, which is coupled with a PMOS, capacitor, and inverter for rapid turn-on and prevention of false triggering, is characterized in that: when a high-voltage ESD pulse reaches the anode of the device, the cathode is connected to a low potential. The network coupled with the first PMOS (P802) and capacitor C803 detects the ESD event. The first PMOS (P802) has an extremely fast response speed, and the voltage on capacitor C803 abruptly drops to a low potential. Capacitor C803 is connected to the emitter (E) terminal of the inverter (INV801), and the emitter (F) terminal of the inverter (INV801) is connected to the emitter (F). The terminal becomes a high potential and is connected to the gate region 701 of the first GGNMOS. Therefore, a high gate voltage is generated at the gate terminal 701 of the first GGNMOS. This gate voltage can turn on the NMOS channel, and the current flows from the drain region 502 to the source region 503. The GGNMOS will initially form a channel and turn on. The voltage between the drain terminal 502 and the source terminal 503 continues to rise. When it reaches a certain voltage value, a certain current will flow to the substrate 601 because the channel is turned on. The MOS transistor does not need to go through avalanche breakdown and enters the hysteresis region. The parasitic transistor turns on and discharges the current.

[0051] The first and second N-type deep wells (301, 302) and the first and fourth N+ injection regions (501, 504) together with the N-type buried layer (201) form an N-type isolation zone that surrounds the core area of ​​the device and reduces parasitic paths.

[0052] The fabrication method of the aforementioned GGNMOS electrostatic discharge protection device, which is coupled with a PMOS, capacitor, and inverter for rapid turn-on and prevents false triggering, includes the following steps:

[0053] Step 1: Form an N-type buried layer 201 in a P-type substrate 101;

[0054] Step 2: Generate a first N-type deep well 301 and a second N-type deep well 302 above the N-type buried layer 201;

[0055] Step 3: Above the N-type buried layer 201, at the same depth as the N-type deep traps (301, 302), generate the first P-trap 401. The distance between the first P-trap 401 and the N-type deep traps (301, 302) is zero.

[0056] Step 4: Generate a first P+ injection 601, a second N+ injection 502, and a third N+ injection 503 on the first P-well 401; generate a first N+ injection 501 on the first N-type deep well 301; and generate a fourth N+ injection 504 on the third N-type deep well 302.

[0057] Step 5: Generate POLY gate 701 between the second and third N+ injections (502 / 503);

[0058] Step 6: Except between the second N+ injection region 502 and the third N+ injection region 503, generate the first to fifth oxygen isolation regions (602 to 606) sequentially from left to right between the other injection regions;

[0059] Step 7: Anneal all injection zones to eliminate the migration of impurities within the injection zones;

[0060] Step 8: Connect the substrate and source region of the second PMOS (P702) together with metal and connect them to the anode of the device; connect the substrate and source region of the second NMOS (N703) together and connect them to the cathode of the device; connect the drain region of the second PMOS (P702) and the drain region of the second NMOS (N703) together with metal and use them as the F terminal of the inverter; connect the gate region of the second PMOS (P702) and the gate region of the second NMOS (N703) together and use them as the E terminal of the inverter.

[0061] Step 9: Connect the first P+ injection region 601 and the third N+ injection region 503 together with a metal layer to serve as the cathode of the device. Connect the first, second, and fourth N+ injection regions (501, 502, 504) together to serve as the anode of the device. Connect the gate terminal 701 to the F terminal of the inverter (INV801). Connect a capacitor C803 between the E terminal of the inverter (INV801) and the cathode. Connect the first PMOS (P802) between the E terminal of the inverter and the anode. Connect the gate of the first PMOS (P802) to the cathode.

[0062] The fabrication method of this invention for a GGNMOS electrostatic discharge (ESD) device with fast turn-on and anti-false triggering via PMOS, capacitor, and inverter coupling is simple and easy to operate. The fabricated GGNMOS ESD device structure with fast turn-on and anti-false triggering via PMOS, capacitor, and inverter coupling is not fixed. The appropriate values ​​for RC, inverter, and gate voltage coupling under different process conditions can be obtained through gate coupling voltage simulation. This allows for slight channel opening before transitioning to parasitic transistor conduction, reducing the trigger voltage and ensuring uniform MOS transistor triggering. Adding an inverter prevents false triggering, further reduces the trigger voltage, enhances the MOS transistor's driving capability, and makes conduction more uniform. The device in this example uses a 0.25μm BCDMOS process.

[0063] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention are included within the scope of protection of the present invention.

Claims

1. A GGNMOS electrostatic discharge protection device, characterized in that, include: P-type substrate; The P-type substrate has an N-type buried layer; Above the N-type buried layer are a first N-type deep well, a second N-type deep well, and a first P-type well; The first N-type deep well and the second N-type deep well are further provided with a first N+ injection region and a fourth N+ injection region; The first P-type well is provided with a P-type semiconductor substrate and a gate region, a source region, and a drain region of a first NMOS, wherein the drain region of the first NMOS is widened; The first N-type deep well, the second N-type deep well, the first N+ injection region, the fourth N+ injection region, and the N-type buried layer together constitute an N-type isolation zone; The P-type semiconductor substrate is connected to the source region of the first NMOS and serves as the cathode of the device. The drain region of the first NMOS is connected to the first N-type deep well, the first N+ injection region on the second N-type deep well, and the fourth N+ injection region and serves as the anode of the device. The gate region of the first NMOS is located between the second N+ and the third N+ injection regions; The gate region of the first NMOS is connected to the coupling circuit of the first PMOS, capacitor C, and inverter; the second N+ injection region and the third N+ injection region are separated by the gate region of the first NMOS, and the first field oxygen isolation region, the second field oxygen isolation region, the third field oxygen isolation region, the fourth field oxygen isolation region, and the fifth field oxygen isolation region are generated sequentially from left to right between the other injection regions.

2. The GGNMOS electrostatic discharge protection device according to claim 1, characterized in that, The first field oxygen isolation region is located on the left side of the left edge of the P-type substrate, and the right part of the first field oxygen isolation region is located on the left side of the first N+ implantation region. The second field oxygen isolation region is located on the left side of the first N+ implantation region, and the right part of the second field oxygen isolation region is located on the left side of the second N+ implantation region. The third field oxygen isolation region is located on the left side of the third N+ implantation region, and the right part of the third field oxygen isolation region is located on the left side of the first P+ implantation region. The fourth field oxygen isolation region is located on the left side of the first P+ implantation region, and the right part of the fourth field oxygen isolation region is located on the left side of the fourth N+ implantation region. The fifth field oxygen isolation region is located on the left side of the fourth N+ implantation region, and the right part of the fifth field oxygen isolation region is located on the right edge of the P-type substrate.

3. The GGNMOS electrostatic discharge protection device according to claim 1, characterized in that, The inverter includes a second PMOS and a second NMOS; the substrate and source region of the second PMOS are connected to the anode, and the substrate and source region of the second NMOS are connected to the cathode; the drain regions of the second PMOS and the drain regions of the second NMOS are connected as the F terminal of the inverter; the gate regions of the second PMOS and the gate regions of the second NMOS are connected as the E terminal of the inverter.

4. A method for manufacturing a GGNMOS electrostatic discharge protection device, characterized in that, The method includes: Step 1: Form an N-type buried layer in a P-type substrate; Step 2: Generate a first N-type deep well and a second N-type deep well above the N-type buried layer; Step 3: Above the N-type buried layer, at the same depth as the N-type deep well, a first P-well is generated, with the distance between the first P-well and the N-type deep well being zero; Step 4: Generate a first P+ injection, a second N+ injection, and a third N+ injection on the first P-well; generate a first N+ injection on the first N-type deep well; and generate a fourth N+ injection on the third N-type deep well. Step 5: Generate a POLY gate between the second N+ injection and the third N+ injection; Step Six: Generate the first to fifth oxygen isolation zones sequentially from left to right; Step 7: Anneal all injection zones to eliminate the migration of impurities within the injection zones; Step 8: Connect the substrate and source region of the second PMOS together with metal and connect them to the anode of the device; connect the substrate and source region of the second NMOS together and connect them to the cathode of the device; connect the drain region of the second PMOS and the drain region of the second NMOS together with metal and use them as the F terminal of the inverter; connect the gate region of the second PMOS and the gate region of the second NMOS together and use them as the E terminal of the inverter. Step 9: Connect the first P+ injection region and the third N+ injection region together with a metal layer to serve as the cathode of the device. Connect the first N+ injection region, the second N+ injection region, and the fourth N+ injection region together to serve as the anode of the device. Connect the gate terminal to the F terminal of the inverter. Connect a capacitor between the E terminal of the inverter and the cathode. Connect the first PMOS between the E terminal of the inverter and the anode. Connect the gate of the first PMOS to the cathode.

5. The method for manufacturing the GGNMOS electrostatic discharge protection device according to claim 4, characterized in that, The method is preceded by: A silicon dioxide thin film is grown on the P-type substrate, followed by the deposition of a silicon nitride layer; a photoresist layer is spin-coated onto the wafer, and a mask is used to expose and develop it to form a shallow isolation trench; the silicon dioxide, silicon nitride, and shallow isolation trench are etched to remove the photoresist layer, a silicon dioxide layer is deposited, and then chemical polishing is performed until the silicon nitride layer is removed.

Images