Electronic device and method of manufacturing electronic device

Abstract

An electronic device and a method of manufacturing the electronic device. In one example, an electronic device may include a first redistribution structure. A first electronic component may be disposed on a first side of the first redistribution structure. A first passive component may be on a second side of the first redistribution structure, wherein the first redistribution structure is between the first passive component and the first electronic component. A first internal interconnect may be adjacent to a lateral side of the first redistribution structure and coupled to the first redistribution structure. A second internal interconnect may be adjacent a lateral side of the first passive component and coupled to the first redistribution structure. An antenna substrate may be disposed over a first side of the first electronic component. A second redistribution structure may be disposed over a second side of the first electronic component. Other examples and related methods are also disclosed herein.

Description

Technical Field

[0001] The present disclosure relates generally to electronic devices, and more particularly to electronic devices and methods for making electronic devices. Background Art

[0002] Previous electronic packages and methods for forming electronic packages are inadequate, for example resulting in excessive cost, reduced reliability, relatively low performance, or excessive package size. Other limitations and disadvantages of conventional and traditional methods will be apparent to those skilled in the art by comparing such methods with the present disclosure and referring to the drawings. Summary of the invention

[0003] One aspect of the present invention is an electronic device, comprising: a first redistribution structure; a first electronic component located on a first side of the first redistribution structure; a first passive component located on a second side of the first redistribution structure, wherein the first redistribution structure is located between the first passive component and the first electronic component; a first internal interconnection adjacent to a lateral side of the first redistribution structure and coupled to the first redistribution structure; a second internal interconnection adjacent to a lateral side of the first passive component and coupled to the first redistribution structure; an antenna substrate located above the first side of the first electronic component; and a second redistribution structure located above the second side of the first electronic component.

[0004] The electronic device according to an aspect of the present invention further includes a second passive component disposed between the first redistribution structure and the first electronic component.

[0005] The electronic device according to an aspect of the present invention further includes a second passive component adjacent to the first passive component, wherein the first redistribution structure is located between the second passive component and the first electronic component.

[0006] The electronic device according to an aspect of the invention further includes a second passive component coupled to an outer side of the antenna substrate, wherein the antenna substrate is located between the second passive component and the first passive component.

[0007] In the electronic device according to an aspect of the present invention, the first passive component is located between the first redistribution structure and the second redistribution structure.

[0008] In the electronic device according to an aspect of the present invention, the first electronic component is located between the first redistribution structure and the second redistribution structure.

[0009] The electronic device according to aspects of the present invention further includes a die attach material coupling the first electronic component to the antenna substrate.

[0010] The electronic device according to an aspect of the present invention further includes an active side of the first electronic component coupled to the second redistribution structure.

[0011] The electronic device according to an aspect of the present invention further includes an active side of the first electronic component coupled to the first redistribution structure.

[0012] The electronic device according to an aspect of the present invention further comprises a second electronic component, wherein a lateral side of the second electronic component faces the first internal interconnection, and wherein the first internal interconnection is located between the first electronic component and the second electronic component.

[0013] The electronic device according to an aspect of the present invention further includes a first encapsulant disposed around the first internal interconnect, the first electronic component, and the second electronic component.

[0014] The electronic device according to an aspect of the present invention further includes a second encapsulant disposed around the second internal interconnect and the first passive component, wherein the first redistribution structure is located between the first encapsulant and the second encapsulant.

[0015] The electronic device according to an aspect of the present invention further includes a second electronic component coupled to an outer side of the second redistribution structure, wherein the second redistribution structure is located between the second electronic component and the first electronic component.

[0016] Another aspect of the present invention is a method for manufacturing an electronic device, comprising: setting a first substrate; setting a first internal interconnection above the first substrate; setting a first passive component above the first substrate and adjacent to a lateral side of the first internal interconnection; setting a second substrate above the first passive component and the first internal interconnection, wherein the second substrate includes a redistribution structure; setting an electronic component above the second substrate; setting a second internal interconnection adjacent to a lateral side of the electronic component; and setting a third substrate above the electronic component and the second internal interconnection, wherein the third substrate includes an antenna.

[0017] According to another aspect of the invention, the method further includes disposing a second passive component over the second substrate and adjacent to the electronic component.

[0018] According to another aspect of the invention, the method further includes disposing a first encapsulant over the first substrate and around the first passive component and the first internal interconnect.

[0019] According to another aspect of the invention, the method further includes disposing a second encapsulant over the second substrate and around the electronic component and the second internal interconnect.

[0020] In the method according to another aspect of the present invention, disposing the third substrate further includes patterning a conductive layer to form the antenna.

[0021] According to another aspect of the invention, the method further includes disposing a second passive component over the first substrate and adjacent to the first passive component.

[0022] According to another aspect of the present invention, the method further includes disposing a second passive component above the outer side of the third substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 A cross-sectional view of an exemplary electronic device is shown.

[0024] Figures 2A to 2J Example methods for manufacturing electronic devices are presented.

[0025] Figure 3 A cross-sectional view of an exemplary electronic device is shown.

[0026] Figure 4 A cross-sectional view of an exemplary electronic device is shown.

[0027] FIG. 5A to FIG. 5J An exemplary method for manufacturing an electronic device is presented.

[0028] Figure 6 A cross-sectional view of an exemplary electronic device is shown.

[0029] The following discussion provides various examples of electronic devices and methods of making electronic devices. Such examples are non-limiting, and the scope of the appended claims should not be limited to the specific examples disclosed. The detailed description herein is presented for illustrative purposes only and not for limiting purposes. For example, the steps recited in any of the method or process descriptions may be performed in any order and are not necessarily limited to the order presented. In the following discussion, the terms "example" and "for example" are non-limiting.

[0030] The drawings illustrate general construction methods, and descriptions and details of well-known features and techniques may be omitted so as not to unnecessarily obscure the present disclosure. In addition, the elements in the drawings are not necessarily drawn to scale. For example, the dimensions of some elements in the various figures may be exaggerated relative to other elements to help improve the understanding of the examples discussed in the present disclosure. The same reference numerals in different figures represent the same elements.

[0031] The term "or" means any one or more of the items in the list connected by "or". As an example, "x or y" means any one of the three-element set {(x), (y), (x, y)}. As another example, "x, y or z" means any one of the seven-element set {(x), (y), (z), (x, y), (x, z), (y, z), (x, y, z)}.

[0032] The terms “comprises”, “comprising” or “includes”, “including” are “open” terms and specify the presence of stated features but do not preclude the presence or addition of one or more other features.

[0033] The terms "first", "second", etc. may be used herein to describe various elements, but these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Thus, for example, a first element discussed in the present disclosure may be referred to as a second element without departing from the teachings of the present disclosure.

[0034] Unless otherwise specified, the term "coupled" may be used to describe two elements that are in direct contact with each other, or to describe two elements that are indirectly coupled through one or more other elements. For example, if element A is coupled to element B, element A may be in direct contact with element B or indirectly coupled to element B through an intervening element C. Similarly, the terms "over" or "on" may be used to describe two elements that are in direct contact with each other, or to describe two elements that are indirectly coupled by one or more other elements. DETAILED DESCRIPTION

[0035] An exemplary electronic device includes a first redistribution structure. A first electronic component may be disposed on a first side of the first redistribution structure. A first passive component may be located on a second side of the first redistribution structure, wherein the first redistribution structure is located between the first passive component and the first electronic component. A first internal interconnect may be adjacent to a lateral side of the first redistribution structure and coupled to the first redistribution structure. A second internal interconnect may be adjacent to a lateral side of the first passive component and coupled to the first redistribution structure. An antenna substrate may be disposed over the first side of the first electronic component. A second redistribution structure may be disposed over the second side of the first electronic component.

[0036] In various examples, the electronic device may include a second passive component disposed between a first redistribution structure and a first electronic component. The first redistribution structure may be located between the second passive component and the first electronic component. The antenna substrate may be located between the second passive component and the first passive component. The first passive component may be located between the first redistribution structure and the second redistribution structure. The first electronic component may be located between the first redistribution structure and the second redistribution structure. The electronic device may include a die attach material coupling the first electronic component to the antenna substrate. The electronic device may include an active side of the first electronic component coupled to the second redistribution structure. The electronic device may include an active side of the first electronic component coupled to the first redistribution structure. The first internal interconnect may be located between the first electronic component and the second electronic component. The electronic device may include a first encapsulant disposed around the first internal interconnect, the first electronic component, and the second electronic component. The first redistribution structure may be located between the first encapsulant and the second encapsulant. The second redistribution structure may be located between the second electronic component and the first electronic component.

[0037] An exemplary method of manufacturing an electronic device includes the following steps: providing a first substrate; providing a first internal interconnect over the first substrate; and providing a first passive component over the first substrate and adjacent to a lateral side of the first internal interconnect. A second substrate may be provided over the first passive component and the first internal interconnect. The second substrate may include a redistribution structure. An electronic component may be provided over the second substrate. A second internal interconnect may be provided adjacent to a lateral side of the electronic component. A third substrate may be provided over the electronic component and the second internal interconnect. The third substrate may include an antenna.

[0038] Various exemplary methods may include the step of disposing a second passive component over a second substrate and adjacent to the electronic component. The method may include disposing a first encapsulant over the first substrate and around the first passive component and the first internal interconnect. A second encapsulant may be disposed over the second substrate and around the electronic component and the second internal interconnect. Providing a third substrate may further include patterning the conductive layer to form an antenna. A second passive component may be disposed over the first substrate and adjacent to the first passive component. The exemplary method may include disposing a second passive component over an outer side of the third substrate.

[0039] Other examples are included in the present disclosure. Such examples can be found in the drawings, claims, or specification of the present disclosure.

[0040] Figure 1 A cross-sectional view of an exemplary electronic device 100 is shown. Figure 1 In the example shown in , the electronic device 100 may include substrates 112 , 114 , and 116 , an electronic component 120 , an underfill 130 , a passive component 140 , internal interconnects 152 and 154 , encapsulants 162 and 164 , and an external interconnect 170 .

[0041] Some examples of substrates 112, 114, and 116 may include substrate 112, substrate 114, and substrate 116. Substrate 112 may include dielectric structure 112a and conductive structure 112b. Conductive structure 112b may include substrate inward terminal 112b1 and substrate outward terminal 112b2. Substrate 114 may include dielectric structure 114a and conductive structure 114b. Conductive structure 114b may include substrate inward terminal 114b1 and substrate outward terminal 114b2. Substrate 116 may include dielectric structure 116a and conductive structure 116b. Conductive structure 116b may include substrate inward terminal 116b1 and antenna directivity pattern 116b3.

[0042] Some examples of electronic components 120 may include component interconnect 122. Passive component 140 may include passive component interconnect 142. Internal interconnects 152 and 154 may include internal interconnect 152 and internal interconnect 154. Encapsulants 162 and 164 may include encapsulant 162 and encapsulant 164.

[0043] Figures 2A to 2J An exemplary method for manufacturing an electronic device is shown. Figure 2A A cross-sectional view of the electronic device 100 is shown at an early stage of manufacture. Figure 2A In the example shown in FIG. 1 , a substrate 112 may be disposed on a surface of the carrier 10. The substrate 112 may include a dielectric structure 112a and a conductive structure 112b. The conductive structure 112b may include a substrate-inward terminal 112b1 and a substrate-outward terminal 112b2.

[0044] In some examples, a substrate-to-outward terminal 112b2 may be provided on the surface of the carrier 10. The substrate-to-outward terminal 112b2 may have a pattern on the surface of the carrier 10. The substrate-to-outward terminal 112b2 may include or be referred to as a conductor, a conductive material, a pad, a pad, or an under-bump metal (UBM). In some examples, the substrate-to-outward terminal 112b2 may include copper, gold, silver, or nickel. In some examples, the substrate-to-outward terminal 112b2 may be provided by plating. For example, after providing a metal seed layer to cover the upper surface of the carrier 10 and providing a mask pattern to cover the upper surface of the seed layer, the substrate-to-outward terminal 112b2 may be provided by plating to have a pattern by using the seed layer as a seed. For example, the mask pattern may include a photoresist material. The mask pattern may be removed after forming the substrate-to-outward terminal 112b2. In some examples, the thickness of the substrate-to-outward terminal 112b2 may be in the range of approximately 3 μm (micrometer) to 20 μm.

[0045] In some examples, the carrier 10 may be a substantially flat plate. The carrier 10 may include or be referred to as a plate, a single plate, a wafer, a panel, or a strip. For example, the carrier 10 may be made of steel, stainless steel, aluminum, copper, ceramic, glass, or a wafer. In some examples, the thickness of the carrier 10 may be in the range of approximately 300 μm to 2000 μm, and the width of the carrier 10 may be in the range of approximately 100 mm (millimeter) to 300 mm. The carrier 10 is used to achieve overall processing of the components during the process of providing substrates 112, 114, and 116, electronic components 120, bottom fillers 130, passive components 140, internal interconnects 152 and 154, and encapsulants 162 and 164.

[0046] In some examples, the carrier 10 may include a temporary bonding layer disposed on the surface. The substrate outward terminal 112b2 may be disposed on the surface of the temporary bonding layer of the carrier 10. The temporary bonding layer may be formed by performing coating processes such as spin coating, blade coating, casting, brushing, spraying, slit extrusion coating, curtain coating, inclined plate coating or blade coating on the surface of the carrier 10; printing processes such as screen printing, pad printing, gravure printing, elastic printing or lithography; inkjet printing process; intermediate technology between coating and printing; or by direct attachment of an adhesive film or tape. In some examples, the temporary bonding layer may include or be referred to as a temporary adhesive film, a temporary tape or a temporary adhesive coating. For example, the temporary bonding layer may be a thermal release tape (film) film or an optical release tape (film), and the adhesive strength may be weakened or removed by heat or light. In some examples, the temporary bonding layer may have an adhesive strength that is weakened or removed by a physical or chemical external force. The temporary bonding layer may allow the carrier 10 to be separated from the substrate 112 before providing an external interconnect 170 to be described below.

[0047] In some examples, a dielectric structure 112a may be provided on the upper side of the substrate-to-outer terminal 112b2 and the carrier 10. After providing the dielectric structure 112a to cover the substrate-to-outer terminal 112b2 and the carrier 10, an opening exposing the substrate-to-outer terminal 112b2 may be provided. For example, an opening may be formed by forming a mask pattern on the upper side of the dielectric structure 112a and then removing the exposed dielectric structure 112a by etching. In some examples, the opening may be referred to as or include an orifice or a hole. In some examples, the dielectric structure 112a may include or be referred to as a dielectric layer, a coreless layer, or a fillerless layer. For example, the dielectric structure 112a may include an electrically insulating material such as polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), a resin, or an ajinomoto deposited film (ABF). In some examples, the dielectric structure 112a may be formed by spin coating, spray coating, dip coating, or rod coating. In some examples, the thickness of the dielectric structure 112a may be in a range of approximately 5 μm to 30 μm.

[0048] In some examples, a conductive structure 112b may be provided to cover the upper side of the dielectric structure 112a and the substrate-to-outward terminal 112b2. The conductive structure 112b may be provided to have a plurality of patterns, and the corresponding patterns may be electrically connected to the conductive structure 112b. In some examples, the conductive structure 112b may include or be referred to as a conductive layer, a trace, a pad, a TVS, a TGS, a via, a redistribution layer (RDL), a wiring pattern, or a circuit pattern. In some examples, the conductive structure 112b may include copper, gold, silver, or nickel. In some examples, the conductive structure 112b may include corresponding elements, features, materials, or manufacturing methods similar or identical to those previously described for the substrate-to-outward terminal 112b2. The substrate-to-outward terminal 112b2 may be part of the conductive structure 112b. In some examples, the overall thickness of the conductive structure 112b may be in the range of approximately 3 μm to 20 μm. The conductive structure 112 b may be positioned on an upper side of the dielectric structure 112 a and may include or be referred to as a substrate-inward terminal 112 b 1 .

[0049] Despite Figure 2A In the examples of the invention, the completed substrate 112 has been described as including one dielectric structure 112a and two layers of conductive structures 112b, but the number of layers in the substrate 112 may be less than or greater than two. One or more layers or elements of the conductive structure 112b may be interleaved with the dielectric structure 112a. The substrate inward terminals 112b1 and the substrate outward terminals 112b2 may be spaced apart from each other in the row or column direction on opposite sides of the substrate 112. In some examples, the overall thickness of the substrate 112 may be in the range of approximately 5 μm to 30 μm.

[0050] In some examples, substrate 112 may be a redistribution layer ("RDL") substrate or redistribution structure. The RDL substrate may include one or more conductive redistribution layers and one or more dielectric layers, and the RDL substrate may be formed layer by layer above an electronic device to be coupled to the RDL substrate. The RDL substrate may be formed layer by layer above a carrier and may be completely or partially removed after the electronic device is coupled to the RDL substrate. The RDL substrate may be manufactured layer by layer as a wafer-level substrate on a circular wafer with a wafer-level process, or as a panel-level substrate on a rectangular or square panel carrier with a panel-level process. The RDL substrate may be formed by an additive stacking process, and may include one or more dielectric layers alternately stacked with one or more conductive layers, and define corresponding conductive redistribution patterns or traces, which are configured to collectively fan out the electrical traces from the occupied space of the electronic device, or fan the electrical traces into the occupied space of the electronic device. A plating process such as an electroplating process or an electroless plating process may be used to form the conductive pattern. The conductive pattern may include a conductive material such as copper or other plateable metals. The location of the conductive pattern can be made using a photopatterning process such as a photolithography process and a photoresist material to form a photolithography mask. The dielectric layer of the RDL substrate can be patterned using a photopatterning process and can include a photolithography mask through which light is exposed to the desired features of the photopattern, such as through holes in the dielectric layer. The dielectric layer can be made of a photo-definable organic dielectric material such as polyimide (PI), benzocyclobutene (BCB) or polybenzoxazole (PBO). Such dielectric materials can be spin-coated or otherwise applied in liquid form rather than attached in the form of a preformed film. In order to allow the desired photo-defined features to be properly formed, such photo-definable dielectric materials can omit structural reinforcements, or can be filler-free, without strands, woven fabrics or other particles, and can interfere with light from the photopatterning process. In some examples, such filler-free properties of filler-free dielectric materials can allow the thickness of the resulting dielectric layer to be reduced. Although the photo-definable dielectric material described above may be an organic material, in some instances, the dielectric material of the RDL substrate may include one or more inorganic dielectric layers. Some examples of inorganic dielectric layers may include silicon nitride (Si3N4), silicon oxide (SiO2) and / or SiON. The inorganic dielectric layer may be formed by growing the inorganic dielectric layer using an oxidation or nitridation process rather than using a photo-definable organic dielectric material. Such an inorganic dielectric layer may be filler-free, without strands, woven fabrics, or other different inorganic particles. In some instances, the RDL substrate may omit a permanent core structure or carrier, such as a dielectric material including bismaleimide triazine (BT) or FR4, and these types of RDL substrates may include or be referred to as coreless substrates. Other substrates in the present disclosure may also include RDL substrates.

[0051] In some examples, substrate 112 may be a preformed substrate. The preformed substrate may be manufactured before being attached to an electronic device, and may include a dielectric layer between corresponding conductive layers. The conductive layer may include copper and may be formed using an electroplating process. The dielectric layer may be a relatively thick non-photodefinable layer, which may be attached in a preformed film form rather than in a liquid form, and may include a resin with fillers such as strands, woven fabrics and / or other inorganic particles for rigid or structural support. Since the dielectric layer is non-photodefinable, features such as through holes or openings may be formed by using drilling or lasers. In some examples, the dielectric layer may include a prepreg material or an Ajinomoto stacked film (ABF). The preformed substrate may include a permanent core structure or carrier, such as a dielectric material including bismaleimide triazine (BT) or FR4, and the dielectric layer and the conductive layer may be formed on the permanent core structure. In other examples, the preformed substrate may be a coreless substrate and the permanent core structure is omitted, and the dielectric layer and the conductive layer may be formed on a sacrificial carrier that is removed after the dielectric layer and the conductive layer are formed and before being attached to the electronic device. The preformed substrate may be referred to as a printed circuit board (PCB) or a laminate substrate. Such a preformed substrate may be formed by a semi-additive process or a modified semi-additive process. Other substrates in the present disclosure may also include a preformed substrate.

[0052] Figure 2B A cross-sectional view of the electronic device 100 is shown in a later stage of manufacturing. Figure 2B In the example shown in , an internal interconnect 152 may be disposed above the substrate 112. The internal interconnect 152 may be coupled to the substrate inward terminal 112b1. The internal interconnect 152 may be provided by electrolytic plating, electroless plating, sputtering, PVD, CVD, MOCVD, ALD, LPCVD, or PECVD. In some examples, the internal interconnect 152 may be made of copper, gold, silver, palladium, or nickel. The internal interconnect 152 may include a column, a pillar, a vertical wire, a bump, or a solder-coated metal core ball. In some examples, the height of the internal interconnect 152 may be in the range of approximately 3 μm to 200 μm. The internal interconnects 152 may be spaced apart from each other in the row or column direction.

[0053] Figure 2C A cross-sectional view of the electronic device 100 is shown in a later stage of manufacturing. Figure 2C , a passive component 140 may be disposed above the substrate 112. In some examples, the passive component 140 may include a passive component interconnect 142 disposed on the upper side or the lower side. The passive component interconnect 142 is located on a side of the passive component 140 that is oriented toward or away from the substrate 112. The passive component 140 may include, for example, a capacitor, an inductor, or a resistor. In some examples, the passive component 140 may include a passive component interconnect 142 disposed on the upper side or the lower side.

[0054] In some examples, the passive component 140 may include a passive component interconnect 142 disposed on the lower side. The passive component interconnects 142 may be disposed on the lower side of the passive component 140 to be spaced apart from each other in a row or column direction. The passive component interconnects 142 of the passive component 140 may be coupled to the substrate inward terminal 112b1 of the substrate 112. In some examples, a pick-and-place device may pick up the passive component 140 and place it inside the substrate 112. Subsequently, the passive component interconnects 142 of the passive component 140 may be bonded to the substrate inward terminal 112b1 by a reflow or thermocompression bonding process.

[0055] In some examples, the passive component 140 may include a passive component interconnect 142 disposed on the upper side. The lower side of the passive component 140 may be attached to the upper side of the substrate 112 by an adhesive. The passive component 140 may have a lower side attached to the dielectric structure of the substrate 112. In some examples, the adhesive may include or be referred to as a polymer or a dielectric. In some examples, a pick-and-place device may pick up the passive component 140 and place it inside the substrate 112. The passive component 140 may be located on the upper side of the dielectric structure 112a of the substrate 112 and may be attached by an adhesive.

[0056] In some examples, the passive component 140 may include or be referred to as a passive component or a decoupling capacitor. The overall thickness of the passive component 140 may be less than the height of the internal interconnect 152. In some examples, the overall thickness of the passive component 140 may be in the range of approximately 25 μm to 200 μm. In some examples, the passive component 140 may be spaced apart from the internal interconnect 152, wherein the internal interconnect 152 is disposed around the lateral sides of the passive component 140.

[0057] Figure 2D A cross-sectional view of the electronic device 100 is shown in a later stage of manufacturing. Figure 2D In the example shown in , an encapsulant 162 may be provided to cover the inner side of the substrate 112 , the passive components 140 , and the internal interconnects 152 .

[0058] In some examples, the encapsulant 162 may include or be referred to as a body or molding. For example, the encapsulant 162 may include an epoxy molding compound, a resin, a filler-reinforced polymer, a B-stage pressed film, or a gel. For example, the encapsulant 162 may be formed by compression molding, transfer molding, liquid body molding, vacuum lamination, paste printing, or film-assisted molding.

[0059] In some examples, the top portion of the encapsulant 162 may be removed to expose the upper side of the internal interconnects 152 and the upper side of the passive component 140. In some examples, when the passive component interconnects 142 are disposed on the upper side of the passive component 140, the passive component interconnects 142 may be exposed to the upper side of the encapsulant 162. In some examples, when the component interconnects 142 are disposed on the lower side of the passive component 140, the upper side may be exposed to the upper side of the encapsulant 162.

[0060] In some examples, the top portion of the encapsulant 162 may be removed by grinding. In some examples, when the top portion of the encapsulant 162 is removed, the upper side of the internal interconnect 152 may be removed. The upper side of the encapsulant 162 may be coplanar with the upper side of the internal interconnect 152. The thickness of the encapsulant 162 and the height of the internal interconnect 152 may be similar. The encapsulant 162 may contact the inner side of the substrate 112, the sidewalls of the passive component 140, and the sidewalls of the internal interconnect 152. In some examples, the thickness of the encapsulant 162 may be in the range of approximately 13 μm to 210 μm.

[0061] Figure 2E A cross-sectional view of the electronic device 100 is shown in a later stage of manufacturing. Figure 2E In the example shown in FIG. 1 , a substrate 114 may be disposed on an upper side of the encapsulant 162. The substrate 114 may include a dielectric structure 114a and a conductive structure 114b. The conductive structure 114b may include a substrate-inward terminal 114b1 and a substrate-outward terminal 114b2.

[0062] In some examples, substrate-outward terminals 114b2 may be provided on the upper side of encapsulant 162. Substrate-outward terminals 114b2 may be provided with patterns on the upper side of encapsulant 162, the upper side of internal interconnects 152, and the upper side of passive components 140. Substrate-outward terminals 114b2 may be in contact with the upper side of internal interconnects 152. Substrate-outward terminals 114b2 may be in contact with passive component interconnects 142 of passive components 140. Substrate-outward terminals 114b2 may include corresponding elements, features, materials, or manufacturing methods that are similar or identical to those previously described for substrate-outward terminals 112b2 of substrate 112.

[0063] In some examples, a dielectric structure 114a may be provided on the upper side of the substrate-to-outward terminal 114b2 and the encapsulation 162. After providing the dielectric structure 114a to cover the substrate-to-outward terminal 114b2 and the encapsulation 162, an opening exposing the substrate-to-outward terminal 114b2 may be provided. The dielectric structure 114a may include corresponding elements, features, materials, or manufacturing methods that are similar or identical to those previously described for the dielectric structure of the substrate 112. The dielectric structure 114a may include one or more layers.

[0064] Some instances of the conductive structure 114b may be provided to cover the upper side of the dielectric structure 114a and the substrate-outward terminal 114b2. The conductive structure 114b may be provided with a pattern, and the corresponding pattern may be electrically connected to the conductive structure 114b. The conductive structure 114b may include corresponding elements, features, materials, or manufacturing methods similar or identical to those previously described for the conductive structure 112b of the substrate 112. One or more layers or elements of the conductive structure 114b may be interlaced with the dielectric structure 114a.

[0065] In some examples, substrate-outward terminals 114b2 may be part of conductive structures 114b.Conductive structures 114b may be positioned on an upper side of dielectric structures 114a and may include or be referred to as substrate-inward terminals 114b1.

[0066] In some examples, the completed substrate 114 may be a redistribution layer ("RDL") substrate. Although the completed substrate 114 has been shown to include a two-layer dielectric structure 114a and a three-layer conductive structure 114b, the substrate 114 may include any number of layers. The substrate 114 may include or be referred to as an RDL, an interposer, or a redistribution structure. In the depicted example, the substrate inward terminals 114b1 and the substrate outward terminals 114b2 may be arranged in rows or columns and may be located on the lower side or upper side of the substrate 114. In some examples, the overall thickness of the substrate 114 may be in the range of approximately 5μm to 60μm.

[0067] Figure 2F A cross-sectional view of the electronic device 100 is shown in a later stage of manufacturing. Figure 2FIn the example shown in FIG. 1 , an electronic component 120 may be disposed inside the substrate 114. The electronic component 120 may be in contact with or electrically connected to the substrate-outward terminal 114b2 of the substrate 114. In some examples of the electronic component 120, the lower side may include or be referred to as an active side, and the upper side may include or be referred to as an inactive side. The electronic component 120 may include component interconnects 122 on the lower side. The component interconnects 122 may be disposed on the lower side of the electronic component 120 and may be spaced apart from each other in rows or columns. The component interconnects 122 may include or be referred to as bumps, pads, or pillars. The component interconnects 122 may be input / output terminals of the electronic component 120. In some examples, the component interconnects 122 may be disposed on the lower side of the electronic component 120 by electrolytic plating, electroless plating, sputtering, PVD, CVD, MOCVD, ALD, LPCVD, or PECVD. For example, after providing a photoresist pattern that exposes the bonding pads of the electronic components 120, the component interconnects 122 may be disposed in contact with the exposed bonding pads. In some examples, the component interconnects 122 may have a thickness in the range of approximately 10 μm to 100 μm, and a width and pitch in the range of approximately 20 μm to 300 μm.

[0068] In some examples, the pick-and-place device may pick up the electronic component 120 and place it inside the substrate 114. The component interconnect 122 of the electronic component 120 may be located on the upper side of the substrate inward terminal 114b1 of the substrate 114. Subsequently, the component interconnect 122 of the electronic component 120 may be bonded to the substrate inward terminal 114b1 by a reflow or thermocompression bonding process. In some examples, the electronic component 120 may include or be referred to as a bare die, a chip, or a package. The electronic component 120 may be electrically connected to the substrate 112 through the conductive structure 114b of the substrate 114 and the internal interconnect 152. In some examples, the electronic component 120 may be electrically connected to the passive component 140 through the substrate 114. In some examples, the electronic component 120 may be electrically connected to the passive component 140 through the conductive structure 114b of the substrate 114, the internal interconnect 152, and the substrate 112.

[0069] In various examples, the underfill 130 may be positioned between the electronic component 120 and the substrate 114. The underfill 130 may be in contact with the lower side of the electronic component 120 and the inner side of the substrate 114. The underfill 130 may be in contact with the component interconnect 122 of the electronic component 120. The underfill 130 may include or be referred to as a dielectric layer or a non-conductive paste. The underfill 130 may not contain an inorganic filler. In some examples, the underfill 130 may include or be referred to as a CUF, NCP, NCF, ACF, or ACP. In some examples, when the underfill 130 includes a molded underfill (MUF), the underfill 130 may be considered as part of the encapsulant 164. In some examples, the underfill 130 may be cured after being positioned between the electronic component 120 and the substrate 114. In some examples, after providing underfill 130 to cover the inside of substrate 114, component interconnects 122 of electronic component 120 may pass through underfill 130 and be connected to substrate-outward terminals 114b2. Underfill 130 may prevent electronic component 120 from being separated from substrate 114 due to physical or chemical influences.

[0070] Although the electronic component 120 is Figure 2F In the example of , the electronic component 120 is shown with a face-down or flip chip configuration where the component terminals are located on the lower side, but the electronic component 120 may have a face-up or wire-bonded configuration where the component terminals are located on the upper side. For example, in the electronic component 120, the upper side may include or be referred to as the active side, and the lower side may include or be referred to as the inactive side. The inactive side of the electronic component 120 may be bonded to the interior of the substrate 114. In the electronic component 120, the component terminals may be located on the upper side with the active side. The electronic component 120 may include or be referred to as a face-up or wire-bonded component. The component terminals of the electronic component 120 may be electrically connected to the substrate-inward terminals 114b1 of the substrate 114 through component interconnects 122. The component interconnects 122 may include or be referred to as wires. For example, the wires are wires such as gold wires, copper wires, or aluminum wires, and the component terminals of the electronic component 120 may be bonded to the substrate-inward terminals 114b1 of the substrate 114 through wire bonding devices. In some examples, the overall thickness of electronic component 120 may be in the range of approximately 50 μm to 780 μm, or the area may be in the range of approximately 0.3 mm×0.3 mm to 70 mm×70 mm.

[0071] Figure 2G A cross-sectional view of the electronic device 100 is shown in a later stage of manufacturing. Figure 2GIn the example shown in , internal interconnect 154 may be disposed on substrate 114. Internal interconnect 154 may contact or be electrically connected to substrate-inward terminal 114b1 of substrate 114. Internal interconnect 154 may be spaced apart from electronic component 120, wherein internal interconnect 154 is disposed around the lateral side of electronic component 120. Internal interconnect 154 may include corresponding elements, features, materials, or manufacturing methods similar or identical to those previously described for internal interconnect 152. The height of internal interconnect 154 may be greater than the thickness of electronic component 120. In some examples, the thickness of internal interconnect 152 may be in the range of approximately 3 μm to 200 μm.

[0072] Figure 2H A cross-sectional view of the electronic device 100 is shown in a later stage of manufacturing. Figure 2H In the example shown in FIG. 1 , an encapsulant 164 may be provided to cover the interior of the substrate 114, the electronic component 120, and the internal interconnect 154. The encapsulant 164 may contact the interior of the substrate 114, the sidewalls of the internal interconnect 154, and the sidewalls of the electronic component 120. The encapsulant 164 may include corresponding elements, features, materials, or manufacturing methods that are similar or identical to those previously described for the encapsulant 162. In some examples, when the top portion of the encapsulant 164 is removed, the top portion of the internal interconnect 154 may also be removed. The upper side of the encapsulant 164 may be coplanar with the upper side of the internal interconnect 154. The thickness of the encapsulant 164 and the height of the internal interconnect 154 may be similar. In some examples, the thickness of the encapsulant 164 may be in the range of approximately 100 μm to 1200 μm.

[0073] Fig.2I A cross-sectional view of the electronic device 100 is shown in a later stage of manufacturing. Fig.2I In the example shown in , a substrate 116 may be disposed on the upper side of the encapsulant 164. The substrate 116 may include a dielectric structure 116a and a conductive structure 116b. The conductive structure 116b may include a substrate-inward terminal 116b1 and an antenna directivity pattern 116b3. The conductive structure 116b may include or be referred to as a redistribution layer ("RDL").

[0074] In some examples, substrate inward terminals 116b1 may be provided to an upper side of encapsulation 164. Substrate inward terminals 116b1 may have patterns on an upper side of encapsulation 164 and an upper side of internal interconnect 154. Substrate inward terminals 116b1 may be coupled to an upper side of internal interconnect 154. Substrate inward terminals 116b1 may include corresponding elements, features, materials, or manufacturing methods that are similar or identical to those previously described for substrate outward terminals 112b2 of substrate 112.

[0075] Some instances of dielectric structure 116a may be disposed above substrate inward terminals 116b1 and an upper side of encapsulation 164. After providing dielectric structure 116a to cover substrate inward terminals 116b1 and encapsulation 164, an opening exposing substrate inward terminals 116b1 may be provided. Dielectric structure 116a may include corresponding elements, features, materials, or manufacturing methods that are similar or identical to those previously described for dielectric structure 112a of substrate 112. Dielectric structure 116a may include one or more layers.

[0076] In some examples, antenna pattern 116b3 and conductive structure 116b may be provided to cover the upper side of dielectric structure 116a and substrate inward terminal 116b1. Antenna pattern 116b3 may be positioned on the upper side of dielectric structure 116a. Antenna pattern 116b3 may be electrically connected to substrate inward terminal 116b1 through conductive structure 116b, respectively. In some examples, antenna pattern 116b3 may be a dipole antenna, a monopole antenna, a patch antenna, a loop antenna, a beam antenna, a double antenna, a folded antenna, a diamond antenna, or a half-wave antenna. In some examples, antenna pattern 116b3 may include copper, gold, or silver. Since antenna pattern 116b3 is provided as substrate 116 (e.g., a redistribution structure), the size and position of the antenna may be strictly controlled to achieve fine size adjustment.

[0077] In some examples, substrate 116 may be a redistribution layer ("RDL") substrate. Antenna directivity pattern 116b3 may be electrically connected to electronic component 120 via conductive structure 116b, internal interconnect 154, and conductive structure 114b of substrate 114. Although substrate 116 is shown as including two layers of dielectric structure 116a and two layers of conductive structure 116b, the number of these layers may be less than or greater than these layers. Substrate 116 may include or be referred to as an RDL substrate, an interposer, or an antenna substrate. Substrate inward terminals 116b1 may be arranged to be spaced apart from each other in rows or columns. In some examples, the overall thickness of substrate 116 may be in the range of approximately 5μm to 60μm.

[0078] Figure 2J A cross-sectional view of the electronic device 100 is shown in a later stage of manufacturing. Figure 2J In the example shown in , external interconnect 170 may be disposed external to substrate 112 .

[0079] Before the external interconnect 170 is disposed outside the substrate 112, the carrier 10 is separated from the outside of the substrate 112. In some examples, after releasing or reducing the adhesion of the temporary bonding layer inserted between the carrier 10 and the substrate 112 by applying heat, light, a chemical solution, or a physical external force, the carrier 10 may be separated from the underside of the substrate 112. The temporary bonding layer of the carrier 10 may be separated from the substrate 112 while remaining attached to the carrier 10. The carrier 10 may be removed to expose the outside of the substrate 112.

[0080] In some examples, the external interconnect 170 may be coupled to the substrate-outward terminal 112b2 of the substrate 112. In some examples, the external interconnect 170 may include tin (Sn), silver (Ag), lead (Pb), copper (Cu), Sn-Pb, Sn37-Pb, Sn95-Pb, Sn-Pb-Ag, Sn-Cu, Sn-Ag, Sn-Au, Sn-Bi, or Sn-Ag-Cu. For example, after forming a conductive material including solder on the substrate-outward terminal 112b2 by a ball drop process, the external interconnect 170 may be formed by a reflow process. The external interconnect 170 may include or be referred to as a conductive ball (e.g., a solder ball), a conductive pillar (e.g., a copper pillar), or a conductive pillar having a solder cap formed on a copper pillar. In some examples, the external interconnect 170 may be arranged in a ball grid array or a pad grid array outside the substrate 112. In some examples, the size of external interconnect 170 may be in the range of approximately 25 μm to 500 μm. In some examples, external interconnect 170 may be referred to as an external input / output terminal of electronic device 100.

[0081] In some examples, external interconnect 170 can be electrically connected to electronic component 120 through substrate 112, internal interconnect 152, and substrate 114. External interconnect 170 can be coupled to passive component 140 through substrate 112.

[0082] In some examples, singulation may be performed to separate the substrates 112, 114, and 116 and the encapsulants 162 and 164 into individual electronic devices 100. The electronic device 100 may include the substrates 112, 114, and 116, the electronic component 120, the underfill 130, the passive component 140, the internal interconnects 152 and 154, the encapsulants 162 and 164, and the external interconnect 170. In the electronic device 100, in the case where the electronic component 120 and the passive component 140 are stacked through the substrate 114 and the substrate 116 including the patterned antenna, a short electrical path and a miniaturized overall size may be achieved. In some examples, in the electronic device 100, the passive component 140 may be disposed outside the substrate 112 or the substrate 116.

[0083] Figure 3 A cross-sectional view of an exemplary electronic device 100' is shown. Figure 3 In the example shown in , electronic device 100 ′ may include substrates 112 , 114 , and 116 , electronic components 120 and 220 , underfills 130 and 230 , passive components 140 , internal interconnects 152 and 154 , encapsulants 162 and 164 , and external interconnects 170 .

[0084] In some examples, electronic device 100' can be similar to electronic device 100. For example, electronic device 100' can be similar to electronic device 100 with respect to substrates 112, 114, and 116, electronic component 120, underfills 130 and 230, passive component 140, internal interconnects 152 and 154, encapsulants 162 and 164, and external interconnects 170. Electronic device 100' can include electronic component 220 and underfill 230.

[0085] In some examples, the electronic component 220 may include a component interconnect 222. The electronic component 220 may be coupled to the substrate-outward terminal 112b2 of the substrate 112. In some examples of the electronic component 220, the lower side may include or be referred to as an inactive side, and the upper side may include or be referred to as an active side. The electronic component 220 may include an interconnect 222 on the upper side. The component interconnects 222 may be arranged to be spaced apart from each other in a row or column direction on the upper side of the electronic component 220. The component interconnect 222 may include corresponding elements, features, materials, or manufacturing methods that are similar or identical to those previously described for the component interconnect 122 of the electronic component 120.

[0086] Electronic component 220 may include corresponding elements, features, materials, or manufacturing methods that are similar or identical to those previously described for electronic component 120. In some examples, electronic component 220 may be electrically coupled to antenna pattern 116b3 of substrate 116 through substrate 112, internal interconnect 152, substrate 114, and internal interconnect 154. In some examples, electronic component 220 may be electrically connected to passive component 140 or external interconnect 170 through substrate 112. In some examples, electronic component 220 may be electrically connected to passive component 140 or electronic component 120 through substrate 112, internal interconnect 152, and substrate 114.

[0087] In some examples, the bottom filler 230 may be positioned between the exterior of the substrate 112 and the upper side of the electronic component 220. The bottom filler 230 may contact the upper side of the electronic component 220 and the exterior of the substrate 112. The bottom filler 230 may include corresponding elements, features, materials, or manufacturing methods similar or identical to those previously described for the bottom filler 130. When the bottom filler 230 includes a molded bottom filler (MUF), the electronic component 220 may be covered by an encapsulant, and the bottom filler 230 may be considered as part of the encapsulant. The external interconnect 170 may be exposed through the encapsulant. In some examples of the electronic device 100', the bottom filler 230 may be used when the external interconnects 170 are arranged in a pad grid array.

[0088] Figure 4 A cross-sectional view of an exemplary electronic device 300 is shown. Figure 4 In the example shown in , electronic device 300 may include substrates 112 , 114 , and 116 , electronic components 320 , passive components 140 , internal interconnects 152 and 154 , encapsulants 362 and 364 , external interconnects 170 , and die attach material 380 .

[0089] In some examples, electronic device 300 can be similar to electronic device 100. For example, electronic device 300 can be similar to electronic device 100 with respect to substrates 112, 114, and 116, passive components 140, internal interconnects 152 and 154, encapsulant 362, and external interconnect 170. Electronic device 300 can include electronic component 320, encapsulant 364, and die attach material 380. Electronic component 320 can include component interconnect 322.

[0090] FIG. 5A to FIG. 5J An exemplary method for manufacturing an electronic device is shown. Figure 5A A cross-sectional view of an electronic device 300 is shown at an early stage of manufacture. Figure 5AIn the example shown in , a substrate 116 may be disposed on the surface of the carrier 10. The substrate 116 may include a dielectric structure 116a and a conductive structure 116b. The conductive structure 116b may include a substrate inward terminal 116b1 and an antenna directivity pattern 116b3. In the substrate 116, the dielectric structure 116a may be disposed, the conductive structure 116b including the antenna directivity pattern 116b3 may be disposed, the dielectric structure 116a may be disposed, and then the conductive structure 116b including the substrate inward terminal 116b1 may be disposed. The substrate inward terminal 116b1 may be positioned on the upper side of the dielectric structure 116a. Although the substrate 116 is shown as including two layers of dielectric structures 116a and two layers of conductive structures 116b, the substrate 116 may include any number of layers. The carrier 10 and the substrate 116 may include corresponding elements, features, materials, or manufacturing methods that are similar or identical to those previously described for the carrier 10 and the substrate 116.

[0091] Figure 5B A cross-sectional view of an electronic device 300 is shown at a later stage of manufacturing. Figure 5B , an electronic component 320 may be disposed inside the substrate 116. In some examples, the electronic component 320 may include an electronic component interconnect 322 disposed on an upper side. For example, in the electronic component 120, the upper side may include or be referred to as an active side, and the lower side may include or be referred to as an inactive side. The inactive side of the electronic component 120 may be bonded to the interior of the substrate 116. The electronic component 320 may be attached to the interior of the dielectric structure of the substrate 116 by a die attach material 380. In some examples, the die attach material 380 may include an adhesive layer or an adhesive film. In some instances, the die attach material 380 may be provided by performing a coating process on the inner side of the substrate 116, such as spin coating, blade coating, casting, brushing, spraying, slot die coating, curtain coating, bevel coating, or knife edge coating; a printing process such as screen printing, pad printing, gravure printing, flexographic printing, or lithography; an inkjet printing process; an intermediate technology between coating and printing; or by direct attachment of an adhesive film or tape.

[0092] In some examples, the pick-and-place equipment can pick up the electronic component 320 and place it on the upper side of the die attach material 380 inside the dielectric structure 116a of the substrate 116, and then attached to the upper side of the substrate 116 by the die attach material 380. The electronic component 320 can include corresponding elements, features, materials, or manufacturing methods that are similar or the same as those previously described for the electronic component 120 of the electronic device 100. In some examples, the thickness of the electronic component 320 can be in the range of approximately 25 μm to 780 μm.

[0093] Figure 5CA cross-sectional view of an electronic device 300 is shown at a later stage of manufacture, but Figure 5B and Figure 5C The steps can be performed in any order. Figure 5C , an internal interconnect 154 may be disposed over the substrate 116. The internal interconnect 154 may be coupled to the substrate-inward terminal 116b1 of the substrate 116. The height of the internal interconnect 154 may be greater than the overall thickness of the electronic component 320. The internal interconnect 154 may include corresponding elements, features, materials, or manufacturing methods that are similar or identical to those previously described for the internal interconnect 154 of the electronic device 100.

[0094] Figure 5D A cross-sectional view of an electronic device 300 is shown at a later stage of manufacturing. Figure 5D , an encapsulant 364 may be provided to cover the interior of the substrate 116, the internal interconnects 154, and the electronic components 320. The encapsulant 364 may be in contact with the interior of the substrate 116, the sidewalls of the internal interconnects 154, the sidewalls of the electronic components 320, and the sidewalls of the die attach material 380. In some examples, when the top portion of the encapsulant 364 is removed, the top portion of the internal interconnects 154 may also be removed.

[0095] In some examples, component interconnects 322 of electronic component 320 may be exposed to an upper side of encapsulant 364. The upper side of encapsulant 364 may be coplanar with an upper side of internal interconnects 154 and an upper side of component interconnects 322 of electronic component 320. The thickness of encapsulant 364 and the height of internal interconnects 154 may be similar. Encapsulant 364 may include corresponding elements, features, materials, or manufacturing methods that are similar or identical to those previously described for encapsulant 164 of electronic device 100.

[0096] Figure 5E A cross-sectional view of an electronic device 300 is shown at a later stage of manufacturing. Figure 5E In the example shown in FIG. 1 , a substrate 114 may be provided to cover an upper side of the encapsulant 364, an upper side of the interconnect 154, and an upper side of the component interconnect 322 of the electronic component 320. The substrate 114 may include a dielectric structure 114a and a conductive structure 114b. The conductive structure 114b may include a substrate-inward terminal 114b1 and a substrate-outward terminal 114b2. In the substrate 114, the substrate-inward terminal 114b1 may be provided, the dielectric structure 114a and the conductive structure 114b may be provided, the dielectric structure 114a may be provided, and then the conductive structure 114b including the substrate-outward terminal 114b2 may be provided.

[0097] In some examples, substrate-inward terminals 114b1 may be coupled to an upper side of interconnect 154 or an upper side of component interconnect 322 of electronic component 320. Substrate-outward terminals 114b2 may be positioned on an upper side of dielectric structure 114a. Although substrate 114 is shown to include two layers of dielectric structure 114a and three layers of conductive structure 114b, the number of layers may be less than or greater than the number depicted in the examples. In some examples, electronic component 320 may be electrically connected to antenna directivity pattern 116b3 of substrate 116 through conductive structure 114b of substrate 114 and interconnect 154. Substrate 114 may include corresponding elements, features, materials, or manufacturing methods that are similar or identical to those previously described for substrate 114 of electronic device 100.

[0098] Fig. 5F A cross-sectional view of an electronic device 300 is shown at a later stage of manufacturing. Fig. 5F , a passive component 140 may be disposed inside the substrate 114. In some examples, the passive component 140 may include a passive component interconnect 142 disposed on the upper side or the lower side. In some examples, the component interconnect 142 provided to the lower side of the passive component 140 may be coupled to the substrate inward terminal 114b1. In some examples, the passive component 140 may include a component interconnect 142 on the upper side and adhered to the substrate 114 on the lower side. The passive component 140 may include one or more than two passive components. The passive component 140 may include corresponding elements, features, materials, or manufacturing methods that are similar or identical to those previously described for the passive component 140 of the electronic device 100. In some examples, the passive component 140 may be electrically connected to the electronic component 320 through the substrate 114.

[0099] Figure 5G A cross-sectional view of an electronic device 300 is shown at a later stage of manufacturing. Figure 5G , an internal interconnect 152 may be disposed inside the substrate 114. In some examples, the internal interconnect 152 may be coupled to the substrate-inward terminal 114b1 of the substrate 114. The height of the internal interconnect 152 may be greater than the overall thickness of the passive component 140. The internal interconnect 152 may include corresponding elements, features, materials, or manufacturing methods that are similar or identical to those previously described for the internal interconnect 152 of the electronic device 100.

[0100] Figure 5H A cross-sectional view of an electronic device 300 is shown at a later stage of manufacturing. Figure 5HIn the example shown in FIG. 1 , encapsulant 162 may be provided to cover the exterior of substrate 114, internal interconnects 152, and passive components 140. Encapsulant 162 may be in contact with the exterior of substrate 114, the sidewalls of internal interconnects 152, and the sidewalls of passive components 140. In some examples, when the top portion of encapsulant 162 is removed, the top portion of internal interconnects 152 may also be removed.

[0101] In some examples, the passive component interconnects 142 positioned on the upper side of the passive component 140 can be exposed to the encapsulant 162. The upper side of the encapsulant 162 can be coplanar with the upper side of the internal interconnects 152 and the upper side of the electronic component 320. The encapsulant 162 can include corresponding elements, features, materials, or manufacturing methods that are similar or identical to those previously described for the encapsulant 164 of the electronic device 100.

[0102] Fig.5I A cross-sectional view of an electronic device 300 is shown at a later stage of manufacturing. Fig.5I In the example shown in , the substrate 112 may be provided to the upper side of the encapsulant 162 and the upper side of the internal interconnect 152. The substrate 112 may include a dielectric structure 112a and a conductive structure 112b. The conductive structure 112b may include a substrate inward terminal 112b1 and a substrate outward terminal 112b2. In the substrate 112, the substrate inward terminal 112b1 may be provided, the dielectric structure 112a may be provided, and then the conductive structure 112b including the substrate outward terminal 112b2 may be provided. The substrate inward terminal 112b1 may be coupled to the upper side of the interconnect 152 and the upper side of the passive component interconnect 142 of the passive component 140. The substrate outward terminal 112b2 may be positioned on the upper side of the dielectric structure 112a. Although the substrate 112 is shown as including a single-layer dielectric structure 112a and two-layer conductive structures 112b, the number of layers may be less than or greater than these layers. The substrate 112 may include corresponding elements, features, materials, or manufacturing methods that are similar or identical to those previously described with respect to the substrate 112 of the electronic device 100 .

[0103] Figure 5J A cross-sectional view of an electronic device 300 is shown at a later stage of manufacturing. Figure 5J, the external interconnect 170 may be provided to the substrate-outward terminal 112b2 of the substrate 112. The carrier 10 may be removed from the exterior of the substrate 116 before or after providing the external interconnect 170. The external interconnect 170 may include corresponding elements, features, materials, or manufacturing methods that are similar or identical to those previously described for the external interconnect 170 of the electronic device 100. After providing the external interconnect 170, the electronic device 300 may be flipped over so that the external interconnect 170 is positioned at the bottommost side and the substrate 116 is positioned at the topmost side.

[0104] In some examples, electronic device 300 may include substrates 112, 114, and 116, electronic component 320, passive component 140, internal interconnects 152 and 154, encapsulants 362 and 364, external interconnect 170, and die attach material 380. In some examples of electronic device 300, electronic component 220 may be disposed outside of substrate 112. Electronic component 220 may be similar to Figure 3 The electronic component 220 of the electronic device 100' is shown in FIG.

[0105] Figure 6 A cross-sectional view of an exemplary electronic device 400 is shown. Figure 6 In the example shown in , the electronic device 400 may include substrates 112 , 114 , and 416 , an electronic component 420 , an underfill 430 , passive components 440 , 440 a , and 440 b , internal interconnects 452 and 454 , encapsulants 462 and 464 , and an external interconnect 170 .

[0106] Some examples of electronic device 400 may be similar to electronic device 100. For example, electronic device 400 may be similar to electronic device 100 with respect to substrates 112 and 114 and external interconnects 170. Electronic device 400 may include substrate 416, electronic component 420, underfill 430, passive components 440, 440a, and 440b, internal interconnects 452 and 454, and encapsulants 462 and 464.

[0107] In some examples, substrate 416 can be similar to substrate 116 of electronic device 100. Substrate 416 can include a substrate-outward terminal that can include a portion of conductive structure 416b exposed from dielectric structure 116a. Substrate-outward terminal 416b2 can be positioned outside substrate 416 on an outer surface of electronic device 400.

[0108] Some instances of electronic component 420 may be coupled to substrate-inward terminal 112b1 of substrate 112. Underfill 430 may be inserted between the interior of substrate 112 and the underside of electronic component 420. Electronic component 420 and underfill 430 may respectively include corresponding elements, features, materials, or manufacturing methods that are similar or identical to those previously described for electronic component 120 and underfill 130 of electronic device 100.

[0109] In some examples, encapsulant 462 may contact the upper side of electronic component 420 and the sidewalls of internal interconnect 452. Encapsulant 462 may be inserted between the interior of substrate 112 and the exterior of substrate 114. Encapsulant 462 may include corresponding elements, features, materials, or manufacturing methods similar to or identical to those previously described for encapsulant 164 of electronic device 100. Internal interconnect 452 may electrically connect substrate-inward terminal 112b1 of substrate 112 and substrate-outward terminal 114b2 of substrate 114 to each other. In terms of height, internal interconnect 452 is similar to encapsulant 462 covering electronic component 420. Internal interconnect 452 may include corresponding elements, features, materials, or manufacturing methods similar to or identical to those previously described for internal interconnect 154 of electronic device 100.

[0110] In some examples, passive component 440 may be coupled to substrate-inward terminal 114b1 of substrate 114. Passive component 440 may be coupled to substrate-inward terminal 116b1 of substrate 116. Passive component 440 may include corresponding elements, features, materials, or manufacturing methods similar or identical to those previously described for passive component 140 of electronic device 100. In some examples, passive component 440 may be coupled to substrate-outward terminal 112b2 of substrate 112.

[0111] In some examples, encapsulant 464 may contact sidewalls of passive component 440 and sidewalls of internal interconnect 454. Encapsulant 464 may be interposed between the interior of substrate 114 and the interior of substrate 116. Encapsulant 464 may include corresponding elements, features, materials, or manufacturing methods that are similar or identical to those previously described for encapsulant 162 of electronic device 100.

[0112] In some examples, the internal interconnect 452 can electrically connect the substrate-inward terminal 114b1 of the substrate 114 and the substrate-inward terminal 116b1 of the substrate 116 to each other. In terms of height, the internal interconnect 454 can be similar to the encapsulant 464 covering the passive component 440. The internal interconnect 454 can include corresponding elements, features, materials, or manufacturing methods that are similar or identical to those previously described for the internal interconnect 152 of the electronic device 100.

[0113] In various examples, the passive component 440a may be coupled to the substrate-outward terminal 416b2 of the substrate 116. The passive component 440 may be located on the outer side of the substrate 116. The passive component 440a may include passive component interconnects 442a spaced apart from each other in a row or column direction at the lower side. In the passive component 440a, the passive component interconnect 442a may be coupled to the substrate-outward terminal 416b2 of the substrate 116. The passive component 440a may be electrically connected to the electronic component 420 through the substrate 416, the interconnect 454, the substrate 114, the interconnect 452, and the substrate 112. The passive component 440a may include corresponding elements, features, materials, or manufacturing methods that are similar or identical to those previously described for the passive component 140 of the electronic device 100.

[0114] Some examples of passive components 440b may be coupled to substrate-outward terminals 114b2 of substrate 114. The lower side of passive component 440b may contact the upper side of electronic component 420. Passive component 440b may include passive component interconnects 442b disposed on the upper side and may be spaced apart in rows or columns. In passive component 440b, passive component interconnects 442b may be coupled to substrate-outward terminals 114b2 of substrate 114. Passive component 440b may be electrically connected to electronic component 420 through substrate 114, interconnects 452, and substrate 112.

[0115] In some examples, the electronic component 420 may be electrically connected to the antenna directivity pattern 116b3 through the conductive structure 112b of the substrate 112, the internal interconnect 452, the conductive structure 114b of the substrate 114, the internal interconnect 454, and the conductive structure 416b of the substrate 416. In some examples, the passive component 440 may be electrically connected to the electronic component 420 through the conductive structure 114b of the substrate 114, the internal interconnect 452, and the conductive structure 112b of the substrate 112. In some examples, the passive component 440 may be electrically connected to the electronic component 420 through the conductive structure 416b of the substrate 416, the internal interconnect 454, the conductive structure 114b of the substrate 114, the interconnect 452, and the structure 112b of the substrate 112. The external interconnect 170 may be electrically connected to the electronic component 420 through the substrate 112.

[0116] The example devices and methods described above may include a patterned antenna formed in a substrate and vertically stacked passive components and electronic components. The patterned antenna tends to result in improved control of antenna size. The stacked electronic components, passive components, and patterned antenna tend to reduce package size and may result in short electrical paths between the antenna, electronic components, and passive components.

[0117] The present disclosure includes references to certain examples, however, it will be appreciated by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the scope of the present disclosure. In addition, modifications may be made to the disclosed examples without departing from the scope of the present disclosure. Therefore, it is intended that the present disclosure is not limited to the disclosed examples, but that the present disclosure will include all examples within the scope of the appended claims.

Claims

1. An electronic device, characterized in that: include: First redistribution structure; a first electronic component located on a first side of the first redistribution structure; a first passive component located on a second side of the first redistribution structure, wherein the first redistribution structure is located between the first passive component and the first electronic component; a first internal interconnect adjacent to a lateral side of the first redistribution structure and coupled to the first redistribution structure; a second internal interconnect adjacent a lateral side of the first passive component and coupled to the first redistribution structure; an antenna substrate located over the first side of the first electronic component; as well as A second redistribution structure is located above the second side of the first electronic component.

2. The electronic device according to claim 1, characterized in that: Further included is a second passive component disposed between the first redistribution structure and the first electronic component.

3. The electronic device according to claim 1, characterized in that: Further included is a second passive component adjacent to the first passive component, wherein the first redistribution structure is located between the second passive component and the first electronic component.

4. The electronic device according to claim 1, characterized in that: Further included is a second passive component coupled to an outer side of the antenna substrate, wherein the antenna substrate is located between the second passive component and the first passive component.

5. The electronic device according to claim 1, characterized in that: The first passive component is located between the first redistribution structure and the second redistribution structure.

6. The electronic device according to claim 1, characterized in that: The first electronic component is located between the first redistribution structure and the second redistribution structure.

7. The electronic device according to claim 1, characterized in that: Further included is a die attach material coupling the first electronic component to the antenna substrate.

8. The electronic device according to claim 1, characterized in that: Further included is an active side of the first electronic component coupled to the second redistribution structure.

9. The electronic device according to claim 1, characterized in that: Further included is an active side of the first electronic component coupled to the first redistribution structure.

10. The electronic device according to claim 1, characterized in that: Further included is a second electronic component, wherein a lateral side of the second electronic component faces the first internal interconnect, wherein the first internal interconnect is located between the first electronic component and the second electronic component.

11. The electronic device according to claim 10, characterized in that: Further included is a first encapsulant disposed around the first internal interconnect, the first electronic component, and the second electronic component.

12. The electronic device according to claim 11, characterized in that: Further included is a second encapsulant disposed around the second internal interconnect and the first passive component, wherein the first redistribution structure is located between the first encapsulant and the second encapsulant.

13. The electronic device according to claim 1, characterized in that: Further included is a second electronic component coupled to an outer side of the second redistribution structure, wherein the second redistribution structure is located between the second electronic component and the first electronic component.

14. A method for manufacturing an electronic device, characterized in that: include: providing a first substrate; disposing a first internal interconnect over the first substrate; disposing a first passive component over the first substrate and adjacent to a lateral side of the first internal interconnect; disposing a second substrate over the first passive component and the first internal interconnect, wherein the second substrate includes a redistribution structure; disposing an electronic component above the second substrate; disposing a second internal interconnect adjacent to a lateral side of the electronic component; as well as A third substrate is disposed over the electronic component and the second internal interconnect, wherein the third substrate includes an antenna.

15. The method according to claim 14, characterized in that Further included disposing a second passive component over the second substrate and adjacent to the electronic component.

16. The method according to claim 14, characterized in that Further included disposing a first encapsulant over the first substrate and around the first passive component and the first internal interconnect.

17. The method according to claim 16, characterized in that Further included is disposing a second encapsulant over the second substrate and around the electronic component and the second internal interconnect.

18. The method according to claim 14, characterized in that Providing the third substrate further includes patterning a conductive layer to form the antenna.

19. The method according to claim 14, characterized in that Further comprising disposing a second passive component over the first substrate and adjacent to the first passive component.

20. The method according to claim 14, characterized in that Further comprising disposing a second passive component over an outer side of the third substrate.

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