A quantitative evaluation method for load capacity of large-capacity overcapacity system supported by power grid

Abstract

The present invention discloses a method for quantitatively evaluating the load capacity of a large-capacity supercapacitor system for power grid support. An electromagnetic transient simulation program is constructed. The program algorithm is based on the mainstream electromagnetic transient simulation algorithm "trapezoidal integration method". There is no equivalent in the simulation model. Each step length calculation takes into account the internal resistance, capacitance and initial voltage deviation of all supercapacitor monomers in real time, and integrates factors such as over-voltage and under-voltage protection and branch current limiting. The dynamic switching process of the supercapacitor cluster during the charging and discharging process is considered to accurately simulate the charging and discharging process of the supercapacitor system during on-site operation, thereby accurately estimating the charging and discharging time of the supercapacitor system.

Description

Technical Field

[0001] The present invention relates to the technical field of quantitative evaluation of load capacity of a large-capacity supercapacitor system for power grid support, and in particular to a method for quantitative evaluation of load capacity of a large-capacity supercapacitor system for power grid support. Background Art

[0002] Given that there are deviations in the capacitance, internal resistance and initial voltage of supercapacitors in the manufacturing process and actual operation, the above factors are the main factors that affect the accurate estimation and calculation of the charging and discharging time of supercapacitors as energy carriers to provide active support for the power system. At the same time, supercapacitors as energy carriers are usually composed of tens of thousands of supercapacitors in series and parallel. However, the current mainstream electromagnetic transient simulation software such as PSCAD and MATLAB cannot take into account the manufacturing deviations of capacitance and internal resistance between supercapacitors and the deviation of initial voltage during actual operation. The most critical problem is that it is impossible to perform simulation calculations on such a large number of nodes. Summary of the invention

[0003] The purpose of the present invention is to provide a method for quantitatively evaluating the load capacity of a large-capacity supercapacitor system supported by a power grid. The method is based on the mainstream electromagnetic transient simulation algorithm "trapezoidal integration method". There is no equivalent in the simulation model. Each step length calculation takes into account the internal resistance, capacitance and initial voltage deviation of all supercapacitor monomers in real time, and integrates factors such as over-voltage and under-voltage protection and branch current limiting. The dynamic switching process of the supercapacitor cluster during the charging and discharging process is considered, and the charging and discharging process of the supercapacitor system during on-site operation is accurately simulated, so as to accurately estimate the charging and discharging time of the supercapacitor system.

[0004] In order to achieve the above object, the method provided by the present invention comprises the following steps:

[0005] S1: Construct a hardware parameter data set of a supercapacitor system, wherein the supercapacitor system comprises: a plurality of branches, each branch comprises a plurality of clusters, each cluster comprises a plurality of modules, each module comprises a plurality of supercapacitors, and the initial voltage, internal resistance and capacitance of the supercapacitors are assigned according to normal distribution, and the hardware parameter data set comprises supercapacitor parameters corresponding to each branch, each cluster, each module and each supercapacitor of the supercapacitor system, and the supercapacitor parameters comprise: voltage, capacitance and internal resistance;

[0006] S2: updating the hardware parameter data set according to the supercapacitor system discharge time, and real-time statistics of the equivalent open circuit voltage, equivalent capacitance and equivalent internal resistance of the supercapacitor system;

[0007] S3: Combine the real-time parameters of the hardware parameter data set and the supercapacitor system discharge power to calculate the bus voltage of the supercapacitor system, and determine whether the supercapacitor system performs constant power discharge, constant current discharge, or stops discharging, wherein the determination is based on comparing the matching power of the supercapacitor system with the reference power. If the reference power is less than the matching power, the system will discharge at constant power; otherwise, the system will discharge at constant current. If the branch current reaches the upper limit, the system will also switch to constant current discharge, and the reference power will be the set value. When the equivalent open circuit voltage of the supercapacitor system is less than Uoc_min, the discharge will be terminated.

[0008] in,

[0009]

[0010] U bus (t) indicates the bus voltage of the supercapacitor system at time t, and U oc (t) is the equivalent open circuit voltage, P ref is the reference power, ESR is the equivalent internal resistance of the supercapacitor system;

[0011] Matching power

[0012] S4: Based on the electromagnetic transient trapezoidal integration algorithm, the branch current and the open-circuit voltage of the supercapacitor cell of the current step in the supercapacitor system are updated in real time, and the current value I(t) at the current moment is:

[0013]

[0014] Where: I(t) is the current of the current step branch; I(t-dt) is the current value of the previous step branch; ESR is the equivalent internal resistance of the supercapacitor system at the current step, L is the filter inductance of the supercapacitor system, C is the equivalent capacitance of the supercapacitor system at the current step, and U is bus (t) is the bus voltage of the supercapacitor system at the current step length, Uoc(t) is the open circuit voltage of the supercapacitor system at the current step length, and dt is the simulation step length;

[0015] S5: loop S2 to S4, and record the power of the supercapacitor system in real time to calculate the charge and discharge time of the supercapacitor system.

[0016] In one implementation, the hardware parameter data set also includes a supercapacitor cell status flag of each supercapacitor cell, and the supercapacitor cell status flag is used to identify whether the supercapacitor cell is in a cut-off state. The supercapacitor cell status flag is updated in real time in each step and uploaded to the hardware parameter data set at the same time. The supercapacitor cell in the cut-off state does not participate in the discharge process.

[0017] In one implementation, the hardware parameter data set also includes each cluster status flag, and the cluster status flag is used to identify whether the cluster is in a cut-off state, and to determine whether the cluster voltage or the open-circuit voltage of any supercapacitor cell in the cluster exceeds a threshold. If so, the cluster is determined to be in a deleted state. If there is a redundant cluster, any redundant cluster is added to the discharge process.

[0018] In one implementation, the current step size supercapacitor open circuit voltage value U ci (t) is calculated as:

[0019]

[0020] Where U ci (t) is the open circuit voltage of the current step-length supercapacitor; U ci (t-dt) is the open circuit voltage of the supercapacitor cell in the previous step; i represents any supercapacitor cell in the supercapacitor system.

[0021] In one implementation, the method further includes: updating the open circuit voltage of the supercapacitor monomer in real time based on the branch current, and calculating the branch loss, branch stored electric energy, and accumulated charging electric energy in real time;

[0022] Branch loss P1

[0023] P1=I 2 *ESR*dt,

[0024] Among them, I is the branch current, ESR is the equivalent internal resistance of the supercapacitor system at the current step length;

[0025] Branch circuit storage energy W1

[0026] W1=0.5*C*U oc 2

[0027] Where C is the equivalent capacitance of the current step-length supercapacitor system, U oc is the open circuit voltage of the supercapacitor system at the current step length;

[0028] Charging energy for one step

[0029] W2=U bus (t)*I*dt,

[0030] Among them, U bus (t) is the bus voltage of the current step supercapacitor system. The constant power charging and discharging time of the supercapacitor system is calculated as:

[0031] Supercapacitor system constant power charging and discharging time = the time when the supercapacitor system charging and discharging power first exceeds the reference power dead zone - the time when the supercapacitor system charging and discharging power first enters the reference power dead zone;

[0032] The first time the supercapacitor system charging and discharging power exceeds the reference power dead zone is the time when the supercapacitor system charging and discharging power is less than the reference power for the first time, and the first time the supercapacitor system charging and discharging power enters the reference power dead zone is the time when the supercapacitor system charging and discharging power reaches the reference power for the first time.

[0033] The embodiment of the present invention provides a method for quantitatively evaluating the load capacity of a large-capacity supercapacitor system supported by a power grid. By constructing an electromagnetic transient simulation, the method is based on the mainstream electromagnetic transient simulation algorithm "trapezoidal integration method". There is no equivalent in the simulation model. Each step length calculation considers the internal resistance, capacitance and initial voltage deviation of all supercapacitor monomers in real time, and integrates factors such as over-voltage and under-voltage protection and branch current limiting. The dynamic switching process of the supercapacitor cluster during the charging and discharging process is considered, and the charging and discharging process of the supercapacitor system during on-site operation is accurately simulated, thereby accurately estimating the charging and discharging time of the supercapacitor system.

[0034] Therefore, the application of the embodiment of the present invention can solve the problem that the mainstream electromagnetic transient simulation software PSCAD and MATALAB cannot perform such a multi-node simulation;

[0035] The charging and discharging time under different super-capacity system configurations can be calculated through the above steps. At the same time, in order to meet the needs of the power grid, the present invention focuses on explaining the solution process of constant power charging and discharging time. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 It is a schematic diagram of the structure of a supercapacitor system according to an embodiment of the present invention.

[0037] Figure 2 It is a schematic diagram of the calculation principle of the embodiment of the present invention for a supercapacitor system.

[0038] Figure 3 It is a schematic diagram of a method flow of an embodiment of the present invention. DETAILED DESCRIPTION

[0039] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0040] Please refer to the attached drawings. It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner. Therefore, the drawings only show the components related to the present invention rather than the number, shape and size of the components in actual implementation. In actual implementation, the type, quantity and proportion of each component can be changed arbitrarily, and the layout of the components may also be more complicated. Figure 1 As shown in the figure, the supercapacitor system consists of several branches, each branch contains several clusters, each cluster contains several modules, and each module contains several supercapacitor cells. In the program modeling, the initial voltage, internal resistance and capacitance of the supercapacitor cells are assigned according to the normal distribution.

[0041] Combination Figure 1-Figure 3 It should be noted that the overall mathematical modeling of the supercapacitor system charging and discharging process mainly involves the following aspects: first, the open-circuit voltages of all supercapacitor monomers in a branch of a certain step length are added up to calculate the equivalent open-circuit voltage Uoc of the supercapacitor system branch; then, the branch bus voltage of the supercapacitor system charging and discharging process is solved based on the circuit principle; secondly, the key lies in the solution of the branch current during the supercapacitor system charging and discharging process. Because the mathematical model of the transient process of supercapacitor system charging and discharging involves nonlinear algebraic differential equations, it is impossible for the computer to continuously simulate transient phenomena during the calculation process. It can only be solved at discrete time points (step length dt) to obtain the state at the specified time point. The point-by-point solution method leads to cumulative errors step by step. Therefore, in order to accurately estimate the charging and discharging time of the supercapacitor, this simulation program uses the mainstream electromagnetic transient algorithm "trapezoidal integration method" to solve the branch current; finally, based on the above variables and combined with the circuit principle, the open-circuit voltages of all supercapacitor monomers in the branch are updated, and the first step of the step length is returned to the cycle.

[0042] By recording the charging and discharging power during the above process, the time for the supercapacitor system to charge and discharge at a certain rated power can be calculated.

[0043] The specific implementation of the embodiment of the present invention is as follows:

[0044] S1: Construct a hardware parameter data set for a supercapacitor system. The supercapacitor system includes: multiple branches, each branch includes multiple clusters, each cluster includes multiple modules, each module includes multiple supercapacitor cells, and the initial voltage, internal resistance and capacitance of the supercapacitor cells are assigned according to the normal distribution. The hardware parameter data set includes supercapacitor cell parameters corresponding to each branch, each cluster, each module and each supercapacitor cell of the supercapacitor system, and the supercapacitor cell parameters include: voltage, capacitance and internal resistance.

[0045] Modeling of supercapacitor system hardware parameter data set: Establish the actual supercapacitor hardware system on site according to the number of branches, clusters, modules and supercapacitor cells; the internal resistance and capacitance of the supercapacitor cells are assigned according to the normal distribution, and the mean and standard deviation of the parameters can be statistically analyzed based on the actual data of the supercapacitor system leaving the factory.

[0046] It should be noted that S1 of the present invention is to construct a parameter data set based on the supercapacitor system, that is, the modeling process, mainly to be able to consider the deviations of all monomers in the supercapacitor system modeling process, such as internal resistance, capacitance, and initial voltage.

[0047] like Figure 1 As shown, the supercapacitor system is a supercapacitor system composed of supercapacitor monomers; the supercapacitor system is a supercapacitor monomer connected in series and parallel.

[0048] S2: updating the hardware parameter data set according to the supercapacitor system discharge time, and real-time statistics of the equivalent open circuit voltage, equivalent capacitance and equivalent internal resistance of the supercapacitor system.

[0049] It should be noted that the supercapacitor system will have a corresponding parameter data set initialized at the initial moment of discharge, that is, the equivalent open-circuit voltage, equivalent capacitance and equivalent internal resistance of the supercapacitor system at the initial moment are counted. The statistics of the above parameters are the basic circuit principles and will not be repeated here.

[0050] At the next moment after initialization, the parameters such as equivalent open circuit voltage, branch current, and discharge power can be updated and iterated according to the above S2-S4;

[0051] Current step size overcapacity single cell open circuit voltage value:

[0052]

[0053] Where U ci (t) is the open circuit voltage of the current step-length supercapacitor; U ci (t-dt) is the open circuit voltage of the supercapacitor cell in the previous step; the suffix i represents any supercapacitor cell in the supercapacitor system.

[0054] S3: Calculate the bus voltage of the supercapacitor system by combining the real-time parameters of the hardware parameter data set and the discharge power of the supercapacitor system, and determine whether the supercapacitor system performs constant power discharge, constant current discharge, or stops discharging.

[0055] The discharge state is determined by comparing the matching power of the supercapacitor system with the reference power. If the reference power is less than the matching power, the supercapacitor is discharged at a constant power; otherwise, the supercapacitor is discharged at a constant current. If the branch current reaches the upper limit, the supercapacitor is converted to a constant current discharge. The reference power is a value set as required.

[0056] Among them, U bus (t):

[0057]

[0058] U bus (t) indicates the bus voltage of the supercapacitor system at time t, and U oc (t) is the equivalent open circuit voltage, P ref is the reference power, ESR is the equivalent internal resistance of the supercapacitor system;

[0059] Matching power

[0060] It should be noted that the value of the reference power can be set to 10MW, 20MW, 30MW, 40MW, 50MW, 60MW, or 90MW, depending on actual needs, and the present invention does not limit this.

[0061] Judgment of the charging and discharging state of the supercapacitor system (real-time calculation of the dynamic bus voltage of the supercapacitor system): The supercapacitor charging and discharging process includes two processes: constant power discharge and constant current discharge. The judgment basis includes: comparison between the matching power and the discharge power of the supercapacitor system. If the discharge power is less than the matching power, it is discharged at a constant power; otherwise, it is discharged at a constant current; at the same time, the branch current needs to be monitored during the process. If the branch current reaches the upper limit, the state will be converted to constant current discharge.

[0062] Supercapacitor system bus voltage U bus (t):

[0063]

[0064] Uoc(t) is the equivalent open circuit voltage, P ref is the discharge power, and ESR is the equivalent internal resistance of the supercapacitor system.

[0065] The discharge power in this application is: when in constant power discharge state, the reference power P ref That is the discharge power. When in constant current discharge, this value can be obtained by multiplying the bus voltage by the discharge current.

[0066] The update of the supercapacitor system discharge state is related to the maximum current of a single branch and the minimum open circuit voltage that satisfies constant power discharge. As the supercapacitor system's constant power discharge process proceeds, the open circuit voltage drops and the current rises. When the current reaches the limit, the supercapacitor system will not be able to meet the constant power discharge, and will switch to constant current discharge. During the constant current discharge process, the supercapacitor system's open circuit voltage will also drop. When the supercapacitor system's equivalent open circuit voltage is less than Uoc_min, the discharge will be terminated.

[0067] The branch current and the open-circuit voltage of the supercapacitor cell of the current step in the supercapacitor system are updated in real time based on the electromagnetic transient trapezoidal integration algorithm.

[0068] Current value at the current moment:

[0069]

[0070] Where: I(t) is the current of the current step branch; I(t-dt) is the current value of the previous step branch; ESR is the equivalent internal resistance of the supercapacitor system at the current step, L is the filter inductance of the supercapacitor system, C is the equivalent capacitance of the supercapacitor system at the current step, and U is bus (t) is the bus voltage of the supercapacitor system at the current step length, Uoc(t) is the open circuit voltage of the supercapacitor system at the current step length, and dt is the simulation step length.

[0071] S5: loop S2 to S4, and record the power of the supercapacitor system in real time to calculate the charge and discharge time of the supercapacitor system.

[0072] In order to have a more thorough understanding of the changing process of the supercapacitor system's charge and discharge, the following variables are temporarily included in the iterative process of the supercapacitor system's charge and discharge: real-time calculation of branch losses; branch storage energy; and charging energy in one step.

[0073] Branch loss P1

[0074] P1=I 2 *ESR*dt,

[0075] Among them, I is the branch current, ESR is the equivalent internal resistance of the supercapacitor system at the current step length;

[0076] Branch circuit storage energy W1

[0077] W1=0.5*C*U oc 2

[0078] Among them, C is the equivalent capacitance of the current step-length supercapacitor system, and Uoc is the open-circuit voltage of the current step-length supercapacitor system;

[0079] Charging energy for one step

[0080] W2=U bus (t)*I*dt

[0081] Among them, U bus (t) is the bus voltage of the supercapacitor system at the current step size.

[0082] It should be noted that the hardware parameter data set also includes a super-capacitor cell status flag of each super-capacitor cell, and the super-capacitor cell status flag is used to identify whether the super-capacitor cell is in a cut-off state. The flag is updated in real time at each step and uploaded to the hardware parameter data set at the same time. When a cell is in a cut-off state, the cell and the cluster in which it is located will no longer participate in the calculation of the subsequent charge and discharge process.

[0083] As mentioned above, the present invention may also consider the setting of redundant clusters. When the redundant clusters are not put into use, they do not participate in the iterative calculation of the charging and discharging process. When other clusters in the branch are abnormal and the protection trips, the redundant clusters are put into use to participate in the subsequent iterative calculation of the charging and discharging process.

[0084] It should be noted that the redundant cluster is determined during the equipment configuration phase, and redundant cluster configuration can be added as needed; the purpose of the redundant cluster configuration is to compensate for the change in the protection cluster status flag bit that triggers one or some clusters during the dynamic charging and discharging process described above, so that the redundant cluster can be used as a backup. For example, a cluster contains 12 modules, and a module contains 32 supercapacitors. During the charging and discharging process of the supercapacitor system, if the open-circuit voltage of any supercapacitor is higher than 3V, or lower than 0.91V, the entire cluster will trigger protection and be removed. When the redundant cluster is not put into use, it is in the standby stage. The input status of the cluster will be updated in each simulation step of dynamic charging and discharging, and statistics will be kept in real time.

[0085] In the specific implementation, the flag bit can be set to 1 and removed to 0. That is, when calculating the equivalent overcapacitance open circuit voltage, equivalent capacitance and equivalent internal resistance from the overcapacitance monomer parameters, the flag bit judgment is added. If the flag bit of the monomer, module and cluster is 1, the monomer in the cluster is added to the statistics of the equivalent overcapacitance open circuit voltage, equivalent capacitance and equivalent internal resistance.

[0086] Calculation of constant power charging and discharging time of supercapacitor system: Combined with the above process, the power of supercapacitor system is recorded in real time to calculate the charging and discharging time of supercapacitor system;

[0087] The constant power charging and discharging time of the supercapacitor system = the time when the charging and discharging power of the supercapacitor system first exceeds the reference power dead zone - the time when the charging and discharging power of the supercapacitor system first enters the reference power dead zone.

[0088] It should be noted that as long as the actual discharge power reaches the reference power dead zone range, it can be considered that the discharge power at this time reaches the set reference power; the reference power dead zone is generally set to ±1% of the reference power (that is, the value range is (99%*reference power, 101%*reference power)). It can also be changed as needed according to actual conditions, and the present invention does not limit it.

[0089] It should be noted that the constant power discharge time t=t1-t0, t0 is the time when the charge and discharge power first enters the reference power dead zone, and t1 is the time corresponding to the supercapacitor system charge and discharge power first exceeds the reference power dead zone.

[0090] During the discharge process, due to the presence of inductance, the current cannot jump, so the actual power may take a period of time (very short) to reach the set value, which is recorded as the time t0 corresponding to the first entry into the reference power dead zone;

[0091] As the discharge progresses, the equivalent open-circuit voltage Uoc of the supercapacitor system (supercapacitor monomers connected in series) will decrease, and it will be insufficient to discharge the reference power Pref. When the supercapacitor system power is insufficient to discharge the reference power for the first time, it is recorded as the first time that the supercapacitor system charging and discharging power exceeds the reference power dead zone time t1.

[0092] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for quantitatively evaluating the load capacity of a large-capacity overcapacity system supported by a power grid, characterized in that: The method comprises: S1: Construct a hardware parameter data set of a supercapacitor system, wherein the supercapacitor system comprises: a plurality of branches, each branch comprises a plurality of clusters, each cluster comprises a plurality of modules, each module comprises a plurality of supercapacitors, and the initial voltage, internal resistance and capacitance of the supercapacitors are assigned according to normal distribution, and the hardware parameter data set comprises supercapacitor parameters corresponding to each branch, each cluster, each module and each supercapacitor of the supercapacitor system, and the supercapacitor parameters comprise: voltage, capacitance and internal resistance; S2: updating the hardware parameter data set according to the supercapacitor system discharge time, and real-time statistics of the equivalent open circuit voltage, equivalent capacitance and equivalent internal resistance of the supercapacitor system; S3: Combine the real-time parameters of the hardware parameter data set and the supercapacitor system discharge power to calculate the bus voltage of the supercapacitor system, and determine whether the supercapacitor system performs constant power discharge, constant current discharge, or stops discharging, wherein the determination is based on comparing the matching power of the supercapacitor system with the reference power. If the reference power is less than the matching power, the system will discharge at constant power; otherwise, the system will discharge at constant current. If the branch current reaches the upper limit, the system will also switch to constant current discharge, and the reference power will be the set value. When the equivalent open circuit voltage of the supercapacitor system is less than Uoc_min, the discharge will be terminated. in, U bus (t) indicates the bus voltage of the supercapacitor system at time t, and U oc (t) is the equivalent open circuit voltage, P ref is the reference power, ESR is the equivalent internal resistance of the supercapacitor system; Matching power S4: Based on the electromagnetic transient trapezoidal integration algorithm, the branch current and the open-circuit voltage of the supercapacitor cell of the current step in the supercapacitor system are updated in real time; Current value I(t) at the current moment: Where: I(t) is the current of the current step branch; I(t-dt) is the current value of the previous step branch; ESR is the equivalent internal resistance of the supercapacitor system at the current step, L is the filter inductance of the supercapacitor system, C is the equivalent capacitance of the supercapacitor system at the current step, and U is bus (t) is the bus voltage of the supercapacitor system at the current step length, Uoc(t) is the open circuit voltage of the supercapacitor system at the current step length, and dt is the simulation step length; S5: loop S2 to S4, and record the power of the supercapacitor system in real time to calculate the charge and discharge time of the supercapacitor system.

2. The method according to claim 1, characterized in that The hardware parameter data set also includes a supercapacitor state flag of each supercapacitor, and the supercapacitor state flag is used to identify whether the supercapacitor is in a cut-off state. The supercapacitor state flag is updated in real time in each step and uploaded to the hardware parameter data set at the same time. The supercapacitor in the cut-off state does not participate in the discharge process.

3. The method according to claim 1 or 2, characterized in that: The hardware parameter data set also includes each cluster status flag, which is used to identify whether the cluster is in a cut-off state, and to determine whether the cluster voltage or the open-circuit voltage of any supercapacitor cell in the cluster exceeds a threshold. If so, the cluster is determined to be in a deleted state. If there is a redundant cluster, any redundant cluster is added to the discharge process.

4. The method according to claim 1, characterized in that: Current step size overcapacity single cell open circuit voltage value U ci (t) is calculated as: Where U ci (t) is the open circuit voltage of the current step-length supercapacitor; U ci (t-dt) is the open circuit voltage of the supercapacitor cell in the previous step; i represents any supercapacitor cell in the supercapacitor system.

5. The method according to claim 1, characterized in that The method further comprises: updating the open circuit voltage of the supercapacitor monomer in real time based on the branch current, and calculating the branch loss, branch stored electric energy, and accumulated charging electric energy in real time; Branch loss P1 O1=I 2 *ESR*dt, Among them, I is the branch current, ESR is the equivalent internal resistance of the supercapacitor system at the current step length; Branch circuit storage energy W1 W1=0.5*C*U oc 2 Where C is the equivalent capacitance of the current step-length supercapacitor system, U oc is the open circuit voltage of the supercapacitor system at the current step length; Charging energy for one step W2=U bus (t)*I*dt, Among them, U bus (t) is the bus voltage of the supercapacitor system at the current step size.

6. The method according to claim 1, characterized in that The charging and discharging time of the supercapacitor system includes the constant power charging and discharging time of the supercapacitor system, and the constant power charging and discharging time of the supercapacitor system is calculated as follows: the constant power charging and discharging time of the supercapacitor system=the time when the charging and discharging power of the supercapacitor system first exceeds the reference power dead zone-the time when the charging and discharging power of the supercapacitor system first enters the reference power dead zone; The first time the supercapacitor system charging and discharging power exceeds the reference power dead zone is the time when the supercapacitor system charging and discharging power is less than the reference power for the first time, and the first time the supercapacitor system charging and discharging power enters the reference power dead zone is the time when the supercapacitor system charging and discharging power reaches the reference power for the first time.

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