Configurable degenerate readout circuit and detection method for detecting multiple types of biological signals

Abstract

This invention relates to a configurable degenerate readout circuit and detection method for detecting multiple types of biological signals. The invention addresses the problems of high power consumption and poor versatility in existing sensor readout circuits. The circuit includes a data selector, a configurable degenerate readout circuit, and an analog-to-digital converter (ADC). The data selector has a configured input interface, adapts to various sensors, processes four types of sensor signals from the corresponding sensors, and enables the overall circuit to simultaneously measure the outputs of the four sensors. The input and output terminals of the data selector are connected to the output terminals of the front-end sensors. The configurable degenerate readout circuit has output and input terminals, and it is reconfigured into four measurement circuits through switch control. The ADC converts the analog voltage output from the front-end circuit into a digital code output to complete the detection. This invention belongs to the field of biological signal readout circuit technology.

Description

Technical Field

[0001] This invention relates to a configurable degenerate readout circuit and detection method, belonging to the field of biosignal readout circuit technology. Background Technology

[0002] In recent years, with the continuous development of the Internet of Things (IoT) industry, the sensor industry has also developed rapidly. As an indispensable part of the big data information era, sensors have become an emerging high-tech industry with huge development potential. In sensor application systems, the sensor readout circuit is an indispensable part. The function of the sensor is to convert the physical quantity to be measured in the environment into an electrical correlation signal, while the readout circuit is responsible for converting the electrical signal output by the front-end sensor into an analog signal. This includes the analog front-end circuit (AFE) and the analog-to-digital converter (ADC). The converted analog voltage signal is sent to the ADC and the microprocessor, and finally outputs the corresponding digital signal.

[0003] In sensor design, the AFE (Aspect Factor overlay) occupies a small chip area, but its power consumption accounts for half of the overall chip power consumption. Currently, with the continuous development of CMOS technology, transistor sizes are shrinking year by year, but the threshold voltage of MOSFETs cannot decrease proportionally. As feature sizes shrink, problems such as hot carrier injection, leakage current, and speed saturation of short-channel devices become increasingly serious due to low-voltage power supply. Therefore, better solutions should be sought to address these issues in AFE circuits.

[0004] Our daily lives are increasingly reliant on sensing technology. Sensor-enabled devices are ubiquitous and widely used, from environmental monitoring and building safety to personal biomedicine, such as molecular detection and health monitoring. While sensing technology has evolved significantly over the years, greatly improving quality of life, there is still considerable room for improvement. Currently, commercially available sensing devices for health monitoring are typically bulky, expensive, and power-intensive, making them inconvenient for everyday use. However, with the widespread adoption of micro- and nanotechnology, various novel, compact physiological sensor systems have emerged, such as miniature DNA and protein detection chips, implantable blood pressure monitoring microsystems, and continuous glucose sensors. However, most of these can only effectively detect a single health indicator. Furthermore, they may be manufactured using different technologies, producing incompatible output signals, and their data collection processes are more complex. In many real-world applications, such as treating patients with severe heart disease or lung failure, it is necessary to monitor several biomedical signals simultaneously. Therefore, doctors must process different types of monitoring systems in parallel, wasting valuable time and increasing the likelihood of medical errors.

[0005] Most analog front-end circuits can only convert signals from a single type of target sensor, limiting their functionality and application. Meanwhile, developing signal processing and readout circuits for dedicated sensors is time-consuming and costly, significantly restricting system flexibility and scalability. To meet current needs, a configurable degenerate analog front-end circuit suitable for general-purpose sensor platforms should be designed. A configurable degenerate analog front-end can accept different sensor output types and connection configurations, thereby improving circuit design efficiency, reducing costs, and enhancing system flexibility. Summary of the Invention

[0006] To address the problems of high power consumption and poor versatility in existing sensor readout circuits, this invention proposes a configurable degenerate readout circuit and detection method for detecting multiple types of biological signals.

[0007] The technical solution adopted by the present invention to solve the above problems is as follows: the circuit of the present invention includes a data selector, a configurable degenerate readout circuit and an analog-to-digital converter;

[0008] The data selector is configured with an input interface that adapts to various sensors, processes four sensing signals from the corresponding sensors, and enables the overall circuit to simultaneously measure the outputs of the four sensors. The input and output terminals of the data selector are connected to the output terminals of the front-end sensors.

[0009] The configurable degenerate readout circuit has output and input terminals, and it can be reconfigured into four measurement circuits by the control of a switch.

[0010] The analog-to-digital converter converts the analog voltage output from the front-end circuit into a digital code output to complete the detection.

[0011] Furthermore, there are four types of front-end sensors, which are used to measure glucose concentration, protein concentration, pH value and temperature respectively, and have four independent outputs;

[0012] The data selector also includes four clocks, each controlling one of the four switches. It is reconfigured every 500ms, and the time-division multiplexing operation allows the entire circuit to simultaneously measure the outputs of the four front-end sensors.

[0013] Furthermore, the configurable degenerate readout circuitry includes an amplifier, noise storage capacitors CCDS and CCDSC, feedback capacitors CVC and CF, feedback resistors Rf and Rfi, and a switch array S1-S32.

[0014] The non-inverting input of the amplifier is connected to the reference voltage VAMP via switches S22-S26. The non-inverting input of the amplifier is also connected to the feedback capacitor CVC via switches S14 and S15. The feedback capacitor CVC is connected to the output of the front-end data selector via switches S3 and S7. The inverting input of the amplifier is connected to the noise storage capacitors CCDS and CCDSC, as well as five parallel branches.

[0015] Furthermore, the configurable degenerate readout circuit includes four measurement circuits: glucose mode, protein mode, pH mode, and temperature mode.

[0016] Furthermore, the temperature mode circuit includes an amplifier, feedback capacitors CVC and CCDS, and switches S3, S7, S10, S11, S14, S15, S16, S17, S19, S25, S26, S27, and S29. During the storage phase, noise is stored in the noise storage capacitor CCDS. During the acquisition phase, the configurable degenerate readout circuit is configured as a voltage follower with high input impedance characteristics, and the output voltage is obtained through the formula... get.

[0017] Furthermore, the pH mode circuit includes an amplifier, a feedback capacitor CCDS, a feedback resistor RFi, and switches S3, S4, S16, S17, S18, S22, S27, S28, S29, and S31. During the storage phase, noise is stored in the noise storage capacitor CCDS. During the acquisition phase, the configurable degenerate readout circuit is configured as a transimpedance amplifier with low input impedance characteristics. The output voltage is obtained through the formula... get.

[0018] Furthermore, the protein model circuit includes an amplifier, a feedback capacitor CCDS, a feedback resistor RF, and switches S3, S6, S16, S17, S20, S24, S27, S28, and S30. During the storage phase, noise is stored in the noise storage capacitor CCDS. During the acquisition phase, the configurable degenerate readout circuit is configured as a transimpedance amplifier with low input impedance characteristics, and the output voltage is obtained through the formula... get.

[0019] Furthermore, the glucose mode circuit includes an amplifier, a feedback capacitor CCDSC, a feedback capacitor Cf, and switches S1, S2, S3, S5, S16, S17, S21, S23, S27, S28, and S32. During the storage phase, noise is stored in the noise storage capacitor CCDSC. During the acquisition phase, a configurable degenerate readout circuit is configured as a charge amplifier with the same negative feedback structure as the transimpedance amplifier. The output voltage is obtained through the formula... get.

[0020] The steps of the method described in this invention include:

[0021] At time 1, when the data selector clock SWM is high and all other clocks are low, the degenerate readout circuit can be configured to glucose mode via switch control. This mode is a charge amplifier with the same negative feedback structure as the transimpedance amplifier. The circuit detects glucose concentration, and the analog voltage output by the front-end circuit is converted into a digital code output.

[0022] At time 2, when the data selector clock SWF is high and all other clocks are low, the degenerate readout circuit can be configured to protein mode via switch control, i.e., a transimpedance amplifier with low input impedance characteristics. The circuit detects protein concentration, and the analog voltage output by the front-end circuit is converted into digital code output.

[0023] At time 3, when the data selector clock SWI is high and all other clocks are low, the degenerate readout circuit can be configured to pH mode via a switch, i.e., a transimpedance amplifier with low input impedance. The circuit detects the pH value, and the analog voltage output by the front-end circuit is converted into a digital code output.

[0024] At time 4, when the data selector clock SWB is high and all other clocks are low, the degenerate readout circuit can be configured to temperature mode via switch control. This means it is a voltage follower with high input impedance, and the circuit detects the temperature. The analog voltage output from the front-end circuit will be converted into a digital code output.

[0025] At the next moment, the data selector clock returns to moment 1 and continues the above operation to complete the function of simultaneously processing the four sensing signals from the corresponding sensors.

[0026] The beneficial effects of this invention are:

[0027] Compared to other sensor readout circuits, this invention can simultaneously process the output parameters of four front-end sensors, effectively reducing chip area and power consumption. It can be applied to various sensor application systems and has versatility. When the front-end sensor outputs signals of different modes, it can directly switch modes, realizing the intelligence and adaptability of the readout circuit, and has convenience and flexibility.

[0028] This invention can simultaneously process the output parameters of four front sensors, realizing the intelligence and adaptability of the interface circuit, and has the advantages of convenience and flexibility.

[0029] This invention effectively reduces chip area and power consumption by reusing the same amplifier;

[0030] This invention solves the problem that different types of sensors cannot directly reuse the same microsensor readout circuit, and can be applied to various sensor systems, thus having versatility. Attached Figure Description

[0031] Figure 1 This is a schematic diagram of the overall circuit structure of the present invention;

[0032] Figure 2 This is a timing diagram of the four clocks for the data selector;

[0033] Figure 3 This is a schematic diagram of the circuit structure of a configurable degenerate readout circuit;

[0034] Figure 4 This is a schematic diagram of the circuit structure of an analog-to-digital converter;

[0035] Figure 5 is a comparison chart of chip test results. Figure 5(a) is a comparison chart of chip test results when the front end is a temperature sensor, Figure 5(b) is a comparison chart of chip test results when the front end is a protein concentration sensor, Figure 5(c) is a comparison chart of chip test results when the front end is a glucose concentration sensor, and Figure 5(d) is a comparison chart of chip test results when the front end is a pH sensor. Detailed Implementation

[0036] Specific implementation method one: as follows Figure 1 As shown, a configurable degenerate readout circuit for detecting multiple types of biological signals includes three modules: a data selector, a configurable degenerate readout circuit, and a Sigma-Delta analog-to-digital converter.

[0037] The circuit also includes two types of switches: one is a data selector switch, with one switch corresponding to each conversion mode, totaling four modes: glucose mode, protein mode, pH mode, and temperature mode; the other is a switch controlling the storage and sampling modes, switched via two complementary clocks, sw1 and sw2. When clock 1 (sw1) is closed and clock 2 (sw2) is open, it is in storage mode; when clock 1 (sw1) is open and clock 2 (sw2) is closed, it is in sampling mode. The duty cycle of both clock signals is set to 50%. Compared to traditional sensor readout circuits, this invention can be applied to various sensor systems, possessing versatility. It solves the problem that different types of sensors cannot directly reuse the same microsensor readout circuit, effectively reducing chip area and power consumption.

[0038] Specific implementation method two: such as Figure 2As shown, the data selector 101 controls four types of switches: SWM, SWF, SWI, and SWB. The data selector's interface is reconfigured every 500ms, processing the four sensor signals from the corresponding sensors sequentially. It provides time-division multiplexing cyclic operation, allowing the entire circuit to simultaneously measure the outputs of the four sensors. Simultaneously, the input of the data selector is connected to the output of the front-end sensors. The four front-end sensors measure glucose concentration, protein concentration, pH value, and temperature, and each has four independent outputs.

[0039] Specific implementation method three: such as Figure 3 As shown, the configurable degenerate readout circuit 102 includes an amplifier, noise storage capacitors CCDS and CCDSC, feedback capacitors CVC and CF, feedback resistors Rf and Rfi, and a switch array S1-S32. The non-inverting input of the amplifier is connected to a reference voltage VAMP via switches S22-S26. The reference voltage VAMP is used to ensure that the amplifier can operate normally. The non-inverting input of the amplifier is also connected to the feedback capacitor CVC via switches S14 and S15. The feedback capacitor CVC is configured in different circuits under the control of switches S8-S13 and is connected to the output of the front-end data selector via switches S3 and S7. The inverting input of the amplifier is connected to the noise storage capacitors CCDS and CCDSC and five parallel branches. The reference voltage VREF is also connected to this branch via switch S16. The output of the front-end data selector is connected to this branch via switches S3-S6. The feedback capacitors CCDS and CCDSC are configured in different circuits under the control of switches S18-S21. The five parallel branches are switches S28 and S29, series switch S30 and feedback resistor Rf, series switch S31 and feedback resistor Rfi, series switch S32 and feedback capacitor Cf. Switches S17 and S27 are used to control the way noise storage capacitors CCDS and CCDSC are connected to the circuit in different modes. Switches S1 and S2 are used to ground the output capacitor of the front-end data selector to release the charge.

[0040] The noise storage capacitor CCDSC is a capacitor with a fixed capacitance value, with one end connected to the inverting input of the amplifier and the other end connected to switch S21. The feedback capacitor CF is a capacitor with a fixed capacitance value, with one end connected to the output of the amplifier and the other end connected to switch S32. The feedback resistor Rfi is a resistor with a fixed resistance value, with one end connected to the output of the amplifier and the other end connected to switch S31.

[0041] Specific implementation method four: such as Figure 3As shown, the configurable degenerate readout circuit (102) has two operating modes, namely storage mode and sampling mode, controlled by two non-overlapping clocks SW1 and SW2. In storage mode, noise is stored in noise storage capacitors CCDS and CCDSC. In sampling mode, the noise storage capacitors are connected to the circuit, and there is no charge flow path, which can achieve the purpose of reducing noise.

[0042] The configurable degenerate readout circuit (102) includes four measurement circuits, which can be configured as different types of circuits by switching control according to the type of front-end sensor, namely glucose mode, protein mode, pH mode and temperature mode.

[0043] like Figure 3 As shown, when the clock SWM output of the front-end data selector is high and the clock outputs SWF, SWI, and SWB are low, the configurable degenerate readout circuit is configured in glucose mode. The circuit includes an amplifier, noise storage capacitors CCDS and CCDSC, a feedback capacitor CF, and switches S1, S2, S3, S5, S16, S17, S21, S23, S27, S28, and S32. In this mode, the configurable degenerate readout circuit is configured as a charge amplifier with the same negative feedback structure as the transimpedance amplifier. During the storage phase, the noise storage capacitor CCDS is connected to the reference voltage VREF through switches S16 and S21, and the other end is directly connected to the inverting input of the amplifier. Simultaneously, it is connected through switches S27 and S28... The amplifier output is connected to the non-inverting input via switch S23, which is connected to the reference voltage VAMP. This reference voltage ensures proper amplifier operation. At this point, DC offset and low-frequency noise are stored in the noise storage capacitor CCDS. During the sampling phase, the data selector output is connected to the amplifier's inverting input via switches S3, S5, S21, and the noise storage capacitor CCDSC. It is also connected to the amplifier output via switches S3, S5, S17, S32, and the feedback capacitor CF. The non-inverting input is connected to the reference voltage VAMP via switch S23. Changes in charge cause changes in the output voltage. The configurable degenerate readout circuit is configured as a charge amplifier with the same negative feedback structure as the transimpedance amplifier. The output voltage is calculated using the formula... get;.

[0044] like Figure 3As shown, when the clock SWF output of the front-end data selector is high and the clock outputs SWM, SWI, and SWB are low, the configurable degenerate readout circuit is configured in protein mode. The circuit includes an amplifier, a noise storage capacitor CCDS, a feedback resistor Rf, and switches S3, S6, S16, S17, S20, S24, S27, S28, and S30. In this mode, the configurable degenerate readout circuit is configured as a transimpedance amplifier with low input impedance. During the storage phase, the noise storage capacitor CCDS is connected to the reference voltage VREF through switches S16 and S20, and the other end is directly connected to the inverting input of the amplifier. Simultaneously, it is connected to the amplifier's... At the output, the non-inverting input of the amplifier is connected to the reference voltage VAMP via switch S24. The reference voltage ensures normal amplifier operation, and DC offset and low-frequency noise are stored in the noise storage capacitor. During the sampling phase, the output of the data selector is connected to the inverting input of the amplifier via switches S3, S6, S20 and the noise storage capacitor CCDS, and connected to the amplifier output via switches S3, S6, S17, S30 and the feedback resistor Rf. The non-inverting input of the amplifier is connected to the reference voltage VAMP via switch S24. The current generated in the circuit loop will cause a change in the output voltage. The configurable degenerate readout circuit is configured as a transimpedance amplifier with low input impedance characteristics. The output voltage is obtained by formula... get.

[0045] like Figure 3As shown, when the clock SWI output of the front-end data selector is high and the clock outputs SWM, SWF, and SWB are low, the configurable degenerate readout circuit is configured in pH mode. The circuit includes an amplifier, a noise storage capacitor CCDS, a feedback resistor Rfi, and switches S3, S4, S16, S17, S18, S22, S27, S28, and S31. In this mode, the configurable degenerate readout circuit is configured as a transimpedance amplifier with low input impedance. During the storage phase, the noise storage capacitor CCDS is connected to the reference voltage VREF through switches S16 and S18, and the other end is directly connected to the inverting input of the amplifier. Simultaneously, it is connected to the amplifier output through switches S27 and S28, and the non-inverting input of the amplifier is connected through switch S22. The reference voltage VAMP ensures the amplifier operates normally. At this point, DC offset and low-frequency noise are stored in the noise storage capacitor CCDS. During the sampling phase, the output of the data selector is connected to the amplifier's inverting input via switches S3, S4, S18, and the noise storage capacitor CCDS. It is also connected to the amplifier's output via switches S3, S4, S17, S31, and the feedback resistor Rfi. The amplifier's non-inverting input is connected to the reference voltage VAMP via switch S22. At this point, the power supply, feedback resistor, and op-amp output form a closed loop. Changes in the voltage drop across the feedback resistor will cause changes in the output voltage. The configurable degenerate readout circuit is configured as a transimpedance amplifier with low input impedance characteristics. The output voltage is obtained using the formula... get.

[0046] like Figure 3As shown, when the clock SWB output of the front-end data selector is high and the clock outputs SWM, SWF, and SWI are low, the configurable degenerate readout circuit is configured in temperature mode. The circuit includes an amplifier, a feedback capacitor CVC, a noise storage capacitor CCDS, and switches S3, S7, S10, S11, S14, S15, S16, S17, S19, S25, S26, S27, and S29. In this mode, the configurable degenerate readout circuit is configured as a voltage follower with high input impedance. During the storage phase, the feedback capacitor CVC is grounded through switches S10 and S11, releasing its existing charge. The noise storage capacitor CCDS is connected to the reference voltage VREF through switches S16 and S19. The other end is directly connected to the inverting input of the amplifier, and simultaneously connected to the amplifier output via switches S27 and S29. The non-inverting input of the amplifier is connected to the reference voltage VAMP via switches S25 and S26. The reference voltage ensures normal operation of the amplifier. At this time, DC offset and low-frequency noise are stored in the noise storage capacitor CCDS. During the sampling phase, the output of the data selector is connected to the non-inverting input of the amplifier via switches S3 and S7, the feedback capacitor CVC, and switches S14 and S15. The inverting input of the amplifier is connected to the amplifier output via the noise storage capacitor CCDS and switches S19, S17, and S29. At this time, the configurable degenerate readout circuit is configured as a voltage follower with high input impedance characteristics. The output voltage is obtained by formula... get;.

[0047] Specific implementation method five: such as Figure 4 As shown, the analog-to-digital converter 103 circuit includes a two-stage integrator, a comparator, a D flip-flop, a timing generation circuit, and switches. The circuit operates using two clock cycles, clk1 and clk2. The D flip-flop determines the feedback voltage magnitude, Vrefp or Vrefn, through an AND gate logic. Its specific timing sequence is as follows: at the rising edge of clk1, the first stage integrates the value of Vref; at the rising edge of clk2, the first stage samples; at the rising edge of clk1, the second stage samples; at the rising edge of clk2, the second stage integrates the value of Vref; at the rising edge of clk1, the comparator performs a comparison; at the rising edge of clk2, the comparator latches; at the falling edge of clk1, the D flip-flop updates its output value. The feedback signal is delayed for two cycles before being processed by the first-stage input. The D flip-flop operates at the falling edge of clk1 to obtain a stable result after the comparator comparison, while ensuring the second stage receives the correct feedback signal. The Sigma-Delta analog-to-digital converter completes the function of converting the analog voltage output from the front-end circuit into a digital code output.

[0048] Specific implementation method six: such as Figures 1 to 4 As shown, a detection method using a configurable degenerate readout circuit for detecting multiple types of biological signals includes the following steps:

[0049] At time 1, when the data selector clock SWM is high and all other clocks are low, the degenerate readout circuit can be configured to glucose mode via switch control. This mode is a charge amplifier with the same negative feedback structure as the transimpedance amplifier. The circuit detects glucose concentration, and the analog voltage output by the front-end circuit is converted into a digital code output.

[0050] At time 2, when the data selector clock SWF is high and all other clocks are low, the degenerate readout circuit can be configured to protein mode via switch control, i.e., a transimpedance amplifier with low input impedance characteristics. The circuit detects protein concentration, and the analog voltage output by the front-end circuit is converted into digital code output.

[0051] At time 3, when the data selector clock SWI is high and all other clocks are low, the degenerate readout circuit can be configured to pH mode via a switch, i.e., a transimpedance amplifier with low input impedance. The circuit detects the pH value, and the analog voltage output by the front-end circuit is converted into a digital code output.

[0052] At time 4, when the data selector clock SWB is high and all other clocks are low, the degenerate readout circuit can be configured to temperature mode via switch control. This means it is a voltage follower with high input impedance, and the circuit detects the temperature. The analog voltage output from the front-end circuit will be converted into a digital code output.

[0053] At the next moment, the data selector clock returns to moment 1 and continues the above operation to complete the function of simultaneously processing the four sensing signals from the corresponding sensors.

[0054] As shown in Figures 5(a), (b), (c), and (d), the figures illustrate a comparison between the actual test values, circuit simulation values, and theoretical output values ​​of the configurable degenerate readout circuit chip. It can be seen that the chip is working normally and can simultaneously receive the outputs from four front-end sensors. The error between the processed results and the theoretical values ​​does not exceed 3%. This configurable degenerate readout circuit for detecting multiple types of biological signals can simultaneously process data from four biosensors, demonstrating its versatility.

[0055] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent substitutions, and improvements made to the above embodiments without departing from the scope of the present invention, based on the technical essence of the present invention and within the spirit and principles of the present invention, shall still fall within the protection scope of the present invention.

Claims

1. A configurable degenerate readout circuit for detecting multiple types of biological signals, characterized in that, It includes a data selector (101), a configurable degenerate readout circuit (102), and an analog-to-digital converter (103); The data selector (101) is configured with an input interface that adapts to various sensors and processes four sensing signals from the corresponding sensors, enabling the overall circuit to simultaneously measure the outputs of the four sensors. The input and output terminals of the data selector (101) are connected to the output terminals of the front-end sensors. The configurable degenerate readout circuit (102) has an output terminal and an input terminal, and it can be reconfigured into four measurement circuits by the control of a switch; The analog-to-digital converter (103) converts the analog voltage output from the front-end circuit into a digital code output to complete the detection; The configurable degenerate readout circuit (102) includes four measurement circuits: glucose mode, protein mode, pH mode and temperature mode. The configurable degenerate readout circuit (102) includes an amplifier, noise storage capacitors CCDS and CCDSC, feedback capacitors CVC and CF, feedback resistors Rf and Rfi, and switch arrays S1-S32; clock SWF controls switches S6, S20, S24 and S30; clock SWM controls switches S1, S5, S8, S12, S21, S23 and S32; clock SWB controls switches S7, S14, S19, S26 and S29; clock SWI controls switches S4, S18, S22 and S31; clock SW1 controls switches S2, S9, S10, S11, S13, S16, S25, S27 and S28; and clock SW2 controls switches S3, S15 and S17. One end of switch S1 is connected to one end of switch S2, and the other end of switch S2 is grounded. The other end of switch S1 is connected to one end of switch S3 and then connected to the output terminal of the data selector. One end of each of switches S4, S5, S6, and S7 is connected to the other end of switch S3. The other ends of each of switches S4, S5, and S6 are connected to one end of switch S17. The other end of switch S17 is connected to one end of switch S27. One end of each of switches S28, S29, S30, S31, and S32 is connected to the other end of switch S17. The other ends of switches S4, S5, and S6 are connected to the other end of switch S27. The first terminal is connected to the noise storage capacitor CCDSC via switch S21. The other terminals of switches S4, S5, and S6 are also connected to the noise storage capacitor CCDS via switches S18, S19, and S20. The noise storage capacitor CCDS is connected to one end of switch S16 via switches S18, S19, and S20. The other end of switch S16 is connected to the reference voltage VREF. The other end of switch S3 is connected to one end of switch S7. The other end of switch S7 is connected to one end of the feedback capacitor CVC. The other end of the feedback capacitor CVC is connected to the non-inverting input terminal of the amplifier via switches S14 and S15. The other end of switch S7 is connected to one end of switches S8 and S10. The connection is as follows: the other end of switch S8 is grounded through switch S9, the other end of switch S10 is grounded, the other end of feedback capacitor CVC is connected to one end of switch S11 and switch S12, the other end of switch S11 is grounded, and the other end of switch S12 is grounded through switch S13. The non-inverting input of the amplifier is also connected to the reference voltage VAMP through four branches: the non-inverting input of the amplifier is connected to the reference voltage VAMP through switch S22, the non-inverting input of the amplifier is connected to the reference voltage VAMP through switch S23, the non-inverting input of the amplifier is connected to the reference voltage VAMP through switch S24, and the non-inverting input of the amplifier is also connected to the reference voltage VAMP through switches S25 and S26 in sequence. The inverting input of the amplifier... The input terminal is connected to the noise storage capacitor CCDS, the noise storage capacitor CCDSC, and five parallel branches. The five parallel branches are: the inverting input terminal of the amplifier is connected to the output terminal of the amplifier through switch S28; the inverting input terminal of the amplifier is connected to the output terminal of the amplifier through switch S29; the inverting input terminal of the amplifier is connected to the output terminal of the amplifier through switch S30 and feedback resistor Rf in sequence; the inverting input terminal of the amplifier is connected to the output terminal of the amplifier through switch S31 and feedback resistor Rfi in sequence; and the inverting input terminal of the amplifier is connected to the output terminal of the amplifier through switch S32 and feedback resistor CF in sequence. The noise storage capacitor CCDS has a fixed capacitance value, the feedback capacitor CF has a fixed capacitance value, and the feedback resistor Rfi has a fixed resistance value. When the clock SWM output of the front-end data selector is high and the clock SWF, SWI and SWB outputs are low, the configurable degenerate readout circuit is configured in glucose mode. When the clock SWF output of the front-end data selector is high and the clock SWM, SWI and SWB outputs are low, the configurable degenerate readout circuit is configured in protein mode. When the clock SWI output of the front-end data selector is high and the clock SWM, SWF and SWB outputs are low, the configurable degenerate readout circuit is configured in pH mode. When the clock SWB output of the front-end data selector is high and the clock SWM, SWF and SWI outputs are low, the configurable degenerate readout circuit is configured for temperature mode.

2. The configurable degenerate readout circuit for detecting multiple types of biological signals according to claim 1, characterized in that, When the clock SWM output of the front-end data selector is high and the clock outputs SWF, SWI, and SWB are low, the configurable degenerate readout circuit is configured in glucose mode. The circuit includes an amplifier, noise storage capacitors CCDS and CCDSC, a feedback capacitor CF, and switches S1, S2, S3, S5, S16, S17, S21, S23, S27, S28, and S32. In this mode, the configurable degenerate readout circuit is configured as a charge amplifier with the same negative feedback structure as the transimpedance amplifier. During the storage phase, the noise storage capacitor CCDS is connected to the reference voltage VREF through switches S16 and S21, and the other end is directly connected to the inverting input of the amplifier. Simultaneously, it is connected through switches S27 and S28... The amplifier output is connected to the non-inverting input via switch S23, which is connected to the reference voltage VAMP. This reference voltage ensures proper amplifier operation. At this point, DC offset and low-frequency noise are stored in the noise storage capacitor CCDS. During the sampling phase, the data selector output is connected to the amplifier's inverting input via switches S3, S5, S21, and the noise storage capacitor CCDSC. It is also connected to the amplifier output via switches S3, S5, S17, S32, and the feedback capacitor CF. The non-inverting input is connected to the reference voltage VAMP via switch S23. Changes in charge cause changes in the output voltage. The configurable degenerate readout circuit is configured as a charge amplifier with the same negative feedback structure as the transimpedance amplifier. The output voltage is calculated using the formula... get.

3. The configurable degenerate readout circuit for detecting multiple types of biological signals according to claim 1, characterized in that, When the clock SWF output of the front-end data selector is high and the clock SWM, SWI, and SWB outputs are low, the configurable degenerate readout circuit is configured in protein mode. The circuit includes an amplifier, a noise storage capacitor CCDS, a feedback resistor Rf, and switches S3, S6, S16, S17, S20, S24, S27, S28, and S30. At this time, the configurable degenerate readout circuit is configured as a transimpedance amplifier with low input impedance characteristics. During the storage phase, the noise storage capacitor CCDS is connected to the reference voltage VREF through switches S16 and S20, and the other end is directly connected to the inverting input of the amplifier. At the same time, it is connected to the output of the amplifier through switches S27 and S28. The non-inverting input of the amplifier is connected to the reference voltage VAMP through switch S24. The reference voltage ensures that the amplifier works normally. At this time, DC offset and low-frequency noise are stored in the noise storage capacitor. During the sampling phase, the output of the data selector is connected to the inverting input of the amplifier via switches S3, S6, S20 and the noise storage capacitor CCDS, and to the amplifier output via switches S3, S6, S17, S30 and the feedback resistor Rf. The non-inverting input of the amplifier is connected to the reference voltage VAMP via switch S24. The current generated in the circuit loop will cause a change in the output voltage. The configurable degenerate readout circuit is configured as a transimpedance amplifier with low input impedance characteristics. The output voltage is expressed by the formula... get.

4. The configurable degenerate readout circuit for detecting multiple types of biological signals according to claim 1, characterized in that, When the clock SWI output of the front-end data selector is high and the clock SWM, SWF and SWB outputs are low, the configurable degenerate readout circuit is configured in pH mode. The circuit includes an amplifier, a noise storage capacitor CCDS, a feedback resistor Rfi, and switches S3, S4, S16, S17, S18, S22, S27, S28 and S31. At this time, the configurable degenerate readout circuit is configured as a transimpedance amplifier with low input impedance characteristics. During the storage phase, the noise storage capacitor CCDS is connected to the reference voltage VREF via switches S16 and S18, with the other end directly connected to the inverting input of the amplifier. Simultaneously, it is connected to the amplifier output via switches S27 and S28. The non-inverting input of the amplifier is connected to the reference voltage VAMP via switch S22. This reference voltage ensures normal amplifier operation. At this stage, DC offset and low-frequency noise are stored in the noise storage capacitor CCDS. During the sampling phase, the output of the data selector is connected to the inverting input of the amplifier via switches S3, S4, S18, and the noise storage capacitor CCDS. It is connected to the amplifier output via switches S3, S4, S17, S31, and the feedback resistor Rfi. The non-inverting input of the amplifier is connected to the reference voltage VAMP via switch S22. At this time, the power supply, feedback resistor, and operational amplifier output form a closed loop. Changes in the voltage drop across the feedback resistor will cause changes in the output voltage. The configurable degenerate readout circuit is configured as a transimpedance amplifier with low input impedance characteristics. The output voltage is obtained through the formula... get.

5. The configurable degenerate readout circuit for detecting multiple types of biological signals according to claim 1, characterized in that, When the clock SWB output of the front-end data selector is high, and the clock outputs SWM, SWF, and SWI are low, the configurable degenerate readout circuit is configured in temperature mode. The circuit includes an amplifier, a feedback capacitor CVC, a noise storage capacitor CCDS, and switches S3, S7, S10, S11, S14, S15, S16, S17, S19, S25, S26, S27, and S29. In this mode, the configurable degenerate readout circuit is configured as a voltage follower with high input impedance. During the storage phase, the feedback capacitor CVC is grounded through switches S10 and S11, releasing its existing charge. The noise storage capacitor CCDS is connected to the reference voltage VREF through switches S16 and S19. The other end is directly connected to the inverting input of the amplifier, and simultaneously connected to the amplifier output via switches S27 and S29. The non-inverting input of the amplifier is connected to the reference voltage VAMP via switches S25 and S26. The reference voltage ensures normal operation of the amplifier. At this time, DC offset and low-frequency noise are stored in the noise storage capacitor CCDS. During the sampling phase, the output of the data selector is connected to the non-inverting input of the amplifier via switches S3 and S7, the feedback capacitor CVC, and switches S14 and S15. The inverting input of the amplifier is connected to the amplifier output via the noise storage capacitor CCDS and switches S19, S17, and S29. At this time, the configurable degenerate readout circuit is configured as a voltage follower with high input impedance characteristics. The output voltage is obtained by formula... get.

6. The configurable degenerate readout circuit for detecting multiple types of biological signals according to claim 1, characterized in that, There are four types of front-end sensors, which are used to measure glucose concentration, protein concentration, pH value and temperature respectively, and have four independent outputs; The data selector (101) also includes four clocks, which control four types of switches respectively. The clocks are reconfigured every 500ms and the time-division multiplexed operation allows the entire circuit to simultaneously measure the outputs of four front-end sensors.

7. A detection method for detecting multiple types of biological signals using a configurable degenerate readout circuit, characterized in that, Specifically, it includes: At time 1, when the data selector clock SWM is high and all other clocks are low, the degenerate readout circuit can be configured to glucose mode via switch control. This mode is a charge amplifier with the same negative feedback structure as the transimpedance amplifier. The circuit detects glucose concentration, and the analog voltage output by the front-end circuit is converted into a digital code output. At time 2, when the data selector clock SWF is high and all other clocks are low, the degenerate readout circuit can be configured to protein mode via switch control, i.e., a transimpedance amplifier with low input impedance characteristics. The circuit detects protein concentration, and the analog voltage output by the front-end circuit is converted into digital code output. At time 3, when the data selector clock SWI is high and all other clocks are low, the degenerate readout circuit can be configured to pH mode via a switch, i.e., a transimpedance amplifier with low input impedance. The circuit detects the pH value, and the analog voltage output by the front-end circuit is converted into a digital code output. At time 4, when the data selector clock SWB is high and all other clocks are low, the degenerate readout circuit can be configured to temperature mode via switch control. This means it is a voltage follower with high input impedance, and the circuit detects the temperature. The analog voltage output from the front-end circuit will be converted into a digital code output. At the next moment, the data selector clock returns to moment 1 and continues the above operation to complete the function of simultaneously processing the four sensing signals from the corresponding sensors.

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