Continuous-time sigma-delta adc linearity optimization system

Abstract

A continuous-time Σ-Δ ADC linearity optimization system includes: a second-order continuous-time loop filter, an analog-to-digital converter used as a quantizer, first and second digital-to-analog converters, a pre-decision closed-loop feedback module, and first and second high-frequency compensated digital filters. This invention significantly reduces internal signal swing and effectively suppresses nonlinear distortion without changing the loop transfer function through in-loop pre-decision and digital compensation mechanisms, while also being compatible with various quantizer architectures.

Description

Technical Field

[0001] This invention relates to a technology in the field of analog-to-digital conversion, specifically a continuous-time conversion. Analog-to-digital converter (ADC) linearity optimization system. Background Technology

[0002] Because the loop filter, quantizer and feedback DAC used in the existing continuous-time Σ-Δ analog-to-digital conversion (CTΣ-ΔADC) technology all have different degrees of nonlinearity, the output of the loop filter deviates from the ideal linearity and is difficult to completely eliminate through conventional calibration techniques, which has become a key bottleneck restricting the performance improvement of CTΣ-ΔADC. Summary of the Invention

[0003] To address the aforementioned shortcomings of existing technologies, this invention proposes a continuous-time... The ADC linearity optimization system is not only compatible with VCO quantizers but also adaptable to various quantizer architectures, significantly improving the versatility of the solution. Secondly, it successfully achieves stable compatibility with second-order loop filters, with no restrictions on the selection of filter order. Finally, it integrates a pre-decision closed-loop feedback method and a digital filtering circuit into the DAC feedback loop, effectively eliminating high-frequency response distortion during signal reconstruction through real-time residual calculation and frequency response compensation mechanisms.

[0004] This invention is achieved through the following technical solution:

[0005] This invention relates to a continuous time An ADC linearity optimization system includes: a second-order continuous-time loop filter, an analog-to-digital converter (ADC) used as a quantizer, first and second digital-to-analog converters (DACs), a pre-decision closed-loop feedback module, and first and second high-frequency compensation digital filters. The input terminals of the first and second DACs used for feedback are respectively connected to the output terminals of the corresponding first and second high-frequency compensation digital filters. The output terminals of the first and second DACs are connected to the input terminals of the second-order continuous-time loop filter. The input terminal of the first high-frequency compensation digital filter is connected to the output terminal of the linearity optimization system. The input terminal of the second high-frequency compensation digital filter is connected to the output terminal of the pre-decision closed-loop feedback module. The input terminal of the pre-decision closed-loop feedback module is connected to the output terminal of the linearity optimization system. The input signal is first processed by a second-order loop low-pass filter, and the output signal is quantized by the quantizer.

[0006] After two consecutive clock cycles, the pre-decision module extracts the most significant bit from the quantized signal to form a pre-decision digital signal. The optimized system output signal and the pre-decision digital signal are processed by the first and second high-frequency compensation digital filters respectively to obtain the compensated signal. After being converted into an analog voltage by the first and second digital-to-analog converters, the signal is subtracted from the original input in sequence to generate a low-swing residual signal. This residual signal is then processed by a second-order loop low-pass filter and quantized to obtain the residual digital signal. Finally, the residual signal is synthesized with the pre-decision signal in the digital domain to output a complete digital signal.

[0007] Technical effect

[0008] This invention embeds a pre-decision module into the loop, extracting the most significant bit portion of the input signal after it has passed through the loop filter and quantizer; and by introducing high-frequency digital compensation filters into the two DAC feedback paths, it optimizes the pre-decision signal D. pre,out With system main output D out Transfer function correction is performed; a second-order low-pass CIFB topology continuous-time loop filter is adopted, and the final integrator uses a proportional-integral structure to compensate for excessive loop delay. The filter order and bandwidth can be flexibly configured according to system requirements. Compared with existing technologies, this invention does not depend on a specific quantizer type, supporting various quantizer architectures such as VCO, Flash, and SAR. Furthermore, the quantizer bit depth can be adjusted according to system specifications, while the signal swing within the loop is globally reduced, thus significantly suppressing harmonic distortion caused by the nonlinearity of the loop filter and quantizer. Simulation data shows that, compared with traditional structures, the third harmonic HD3 is significantly reduced. Improved to Even after embedding the pre-decision module, it maintains the original signal transfer function and noise shaping characteristics, avoiding stability degradation or frequency response distortion caused by changes in the feedback path, ensuring a stable 40dB / decathlon noise shaping slope across a wide bandwidth; it possesses excellent architectural compatibility and scalability, requiring only a traditional By adding a small amount of digital logic (such as a pre-decision module and a compensation filter), high linearity conversion can be achieved in various quantizer architectures with minimal additional hardware overhead, making it suitable for high-integration, low-power applications. Attached Figure Description

[0009] Figure 1 This is a schematic diagram of the structure of the present invention;

[0010] Figure 2 This is a circuit structure diagram for an example embodiment;

[0011] Figure 3 For traditional continuous time A comparison diagram of the output swing of the loop filter and quantizer of the ADC and the circuit of the embodiment of the present invention.

[0012] Figure 4 For traditional continuous time A comparison diagram of the output PSD of the ADC and the circuit of the embodiment of the present invention. Detailed Implementation

[0013] like Figure 1 As shown, this embodiment involves a continuous time... An ADC linearity optimization system includes: a second-order continuous-time loop filter, an analog-to-digital converter Q1 used as a quantizer, first and second digital-to-analog converters DAC1 and DAC2, a pre-decision closed-loop feedback module, and first and second high-frequency compensation digital filters, wherein: the input terminals D of the first and second digital-to-analog converters DAC1 and DAC2 used for feedback... DAC,in1 D DAC,in2 The output terminals D of the corresponding first and second high-frequency compensation digital filters are respectively connected to the output terminals D. comp,out1 D comp,out2 Connected, the output terminals V of the first and second digital-to-analog converters DAC1 and DAC2 DAC,out1 V DAC,out2 The input terminal D of the first high-frequency compensated digital filter is connected to the input terminal of the second-order continuous-time loop filter. comp,in1 With the output terminal D of the ADC linearity optimization system out Connected, the input terminal D of the second high-frequency compensation digital filter comp,in2 The output terminal D of the pre-decision closed-loop feedback module pre,out Connected to the input terminal D of the pre-decision closed-loop feedback module pre,in With the output terminal D of the ADC linearity optimization system out Connected, input signal V in First, the signal is processed by a second-order loop low-pass filter, and the output signal V is obtained. LP,out The signal is quantized using a 5-bit quantizer. After two consecutive clock cycles, the pre-decision module extracts the most significant bit from the quantized signal to form the pre-decision digital signal D. pre,out Optimize system output signal D out With the pre-decision digital signal D pre,out The signal is processed by the first and second high-frequency compensation digital filters respectively to obtain the compensated signal D. comp,out1 and D comp,out2 Then, it is converted into an analog voltage V by the first and second digital-to-analog converters DAC1 and DAC2. DAC,out1 With V DAC,out2 Then, sequentially, it is compared with the original input V. in Subtraction produces a low-swing residual signal V. LP,in The residual digital signal D is then obtained after further processing and quantization using a second-order loop low-pass filter. q,out Finally, in the digital domain, it is related to the pre-decision signal D. pre,outThe signal is synthesized and output as a complete digital signal D. out .

[0014] like Figure 2 As shown, the second-order continuous-time loop filter is a second-order low-pass CIFB topology, comprising: two sequentially connected sub-filters, wherein: the input terminal V of the first sub-filter... LP1,in Receive input signal V in Or a low-swing residual signal V LP,in Its output terminal V LP1,out Connect to the input terminal V of the second sub-filter LP2,in The output terminal V of the second sub-filter LP2,out Provide loop filter output signal V LP,out .

[0015] The first sub-filter includes: a first resistor R1, a first capacitor C1, and a first operational amplifier OP1, wherein: one end of the first resistor R1 is connected to the input terminal of the first sub-filter, and the other end is connected to the inverting input terminal of the first operational amplifier OP1; the first capacitor C1 is connected in parallel between the inverting input terminal and the output terminal of the first operational amplifier OP1; the non-inverting input terminal of the first operational amplifier OP1 is grounded, and its output terminal serves as the output of the first sub-filter and is connected to the input terminal of the second sub-filter.

[0016] The second sub-filter includes: a second resistor R2, a second capacitor C2, a third resistor R3, and a second operational amplifier OP2. One end of the second resistor R2 is connected to the output of the first sub-filter, and the other end is connected to the inverting input of the second operational amplifier OP2. The third resistor R3 and the second capacitor C2 are connected in series to form a proportional-integral network, which is connected between the inverting input and output of the second operational amplifier OP2. The non-inverting input of the second operational amplifier OP2 is grounded, and its output V... LP2,out As the loop filter output V LP,out .

[0017] like Figure 2 As shown, the pre-decision closed-loop feedback module includes a latch unit and an interpolation unit, which implement the transfer function H. pre [z]=2z –1 –z –2 .

[0018] The latch unit is used to store the digital signals of the first two consecutive sampling clock cycles output by the analog-to-digital converter in the digital domain. It is implemented using, but is not limited to, two-stage D flip-flops, registers, static or dynamic storage units, and other sequential logic circuits.

[0019] The interpolation unit is used to perform linear extrapolation on the two latched historical sample values ​​to generate the most significant bit pre-decision output D at the current moment. pre,out It is implemented using, but not limited to, arithmetic circuits or dedicated processing units, programmable logic devices, or digital processing modules with lookup tables as their core, including but not limited to shift modules, addition modules, and symbolic control logic.

[0020] like Figure 2 As shown, the first high-frequency compensation digital filter H comp1 [z] includes: a latch unit and a shift operation unit, which internally performs signal filtering and implements the transfer function H through shift operations and latch delay. comp1 [z]=4-3z –1 .

[0021] like Figure 2 As shown, the second high-frequency compensation digital filter H comp2 [z] includes two parallel infinite impulse response branches, wherein: the first branch consists of a first-order IIR structure cascaded with a second-order differential unit in the digital domain, and the second branch is another independent IIR branch; the outputs of the two branches are combined by an adder unit to jointly realize the transfer function H. comp2 [z]= .

[0022] The shift, latch, interpolation, differential, and addition units in the high-frequency compensation digital filter can be implemented using digital registers, flip-flops, multipliers, accumulators, programmable logic, or lookup table-based arithmetic modules. Their structure and coefficients can be configured and adjusted according to the actual system frequency response and stability requirements.

[0023] This embodiment is based on the ADC linearity optimization method of the above system, including:

[0024] Step 1, Input signal V in After being processed sequentially by a second-order continuous-time loop filter and a quantizer for two clock cycles, the most significant bit (MSB) of the current signal is extracted by the pre-decision module to obtain the pre-decision digital signal D. pre,out The operational relationship is as follows: .

[0025] Step 2, the pre-decision signal D pre,out With the system's main digital output D out Each signal is input into its corresponding digital compensation filter, and its transfer function is corrected to obtain the compensated signal D. comp,out1 With D comp,out2 .

[0026] Step 3, D comp,out1 With D comp,out2The signal is converted into an analog signal V by a two-way feedback DAC. DAC,out1 and V DAC,out2 The residual signal is then subtracted from the original input signal to generate a residual signal with a significantly reduced swing. This low-swing residual effectively suppresses the nonlinear effect of the loop filter.

[0027] Step four: The residual signal is quantized to obtain D. q,out In the digital domain, with the pre-decision signal D pre,out The components are synthesized to form the final complete system output D. out This completes the entire process of analog-to-digital conversion and linearity optimization.

[0028] Through practical application experiments, the continuous-time Σ-Δ ADC linearity optimization system of this invention was run in a software simulation environment based on Matlab / Simulink. The simulation conditions were set as follows: sampling frequency 204.8MHz, signal bandwidth 1.6MHz, oversampling rate 64, and the nonlinear transfer function of the loop filter and quantizer was set to y=x+0.5x. 3 Compared to traditional continuous-time Σ-Δ modulators, this invention significantly reduces the voltage swing at the output of both the loop filter and the quantizer, decreasing from 2.0V to 0.14V and 0.16V respectively, effectively suppressing the internal signal dynamic range. Further analysis of the output power spectral density reveals that the traditional structure exhibits significant odd-order harmonic distortion, with the third harmonic distortion reaching -52.8dB. In contrast, this invention effectively suppresses all observable harmonics, achieving a signal-to-noise ratio of 84.0dB and a third harmonic distortion of -95.0dB while maintaining a 40dB / decibel band noise shaping slope. This represents a 42.2dB improvement in harmonic suppression capability and a significant improvement in system linearity.

[0029] like Figure 4 As shown, without the pre-decision closed-loop feedback method, the PSD spectrum of the traditional continuous-time Σ-Δ ADC output signal contains a large number of harmonic components caused by nonlinear effects, indicating that it is not in a normal operating state. However, after introducing the pre-decision closed-loop feedback method, the harmonic components in the output PSD spectrum are significantly suppressed. Before processing, the harmonic components HD3 to HD13 were -52.8dB, -55.0dB, -58.0dB, -60.8dB, -64.0dB, and -67.4dB, respectively. After processing with the pre-decision closed-loop feedback method, they decreased to -95.0dB, -90.1dB, -81.6dB, -76.6dB, -75.8dB, and -74.4dB, respectively. These changes clearly demonstrate that the pre-decision closed-loop feedback method can effectively reduce harmonic components, allowing the ADC to recover and maintain its expected operating performance.

[0030] Compared with existing technologies, this invention, through its modular design, is compatible with various quantizers such as VCO, Flash, and SAR, significantly enhancing the architecture's versatility and adaptability to different scenarios. Secondly, by utilizing a second-order low-pass CIFB topology loop filter and combining it with a proportional-integral structure to compensate for excessive loop delay, it supports flexible filter order configuration while ensuring stability, overcoming the bottleneck of stability limitations in traditional solutions. Furthermore, by integrating a pre-decision closed-loop feedback module and a high-frequency compensation digital filter into the DAC feedback loop, it effectively suppresses nonlinear distortion during signal reconstruction through real-time residual calculation and dynamic frequency response correction. Experiments show that the harmonic components HD3-HD... 13 The maximum reduction exceeds 42dB, and the linearity is significantly improved. Finally, this solution introduces only a small number of digital circuits into the traditional structure, which effectively controls the additional area and power consumption while achieving performance improvement, and has both high precision and low power consumption characteristics.

[0031] The above-described specific implementations can be partially adjusted by those skilled in the art in different ways without departing from the principles and purpose of the present invention. The scope of protection of the present invention is defined by the claims and is not limited to the above-described specific implementations. All implementation schemes within the scope of the claims are bound by the present invention.

Claims

1. A continuous time An ADC linearity optimization system is characterized by, include: The system comprises a second-order continuous-time loop filter, an analog-to-digital converter (ADC) used as a quantizer, first and second digital-to-analog converters (DACs), a pre-decision closed-loop feedback module, and first and second high-frequency compensation digital filters. The inputs of the first and second DACs used for feedback are connected to the outputs of their respective first and second high-frequency compensation digital filters. The outputs of the first and second DACs are connected to the input of the second-order continuous-time loop filter. The input of the first high-frequency compensation digital filter is connected to the output of the linearity optimization system. The input of the second high-frequency compensation digital filter is connected to the output of the pre-decision closed-loop feedback module. The input of the pre-decision closed-loop feedback module is connected to the output of the linearity optimization system. The system output is connected to the input terminal. The input signal is first processed by a second-order loop low-pass filter, and the output signal is quantized by a quantizer. After two consecutive clock cycles, the pre-decision module extracts the most significant bit from the quantized signal to form a pre-decision digital signal. The optimized system output signal and the pre-decision digital signal are processed by the first and second high-frequency compensation digital filters respectively. After obtaining the compensated signal, it is converted into an analog voltage by the first and second digital-to-analog converters. Then, it is subtracted from the original input in sequence to generate a low-swing residual signal. After being processed by the second-order loop low-pass filter and quantized again, the residual digital signal is obtained. Finally, it is synthesized with the pre-decision signal in the digital domain to output a complete digital signal.

2. The continuous time as described in claim 1 An ADC linearity optimization system is characterized by, The second-order continuous-time loop filter is a second-order low-pass topology, comprising: two sub-filters connected in sequence, wherein: the input terminal of the first sub-filter receives the input signal or a low-swing residual signal, and its output terminal is connected to the input terminal of the second sub-filter; the output terminal of the second sub-filter provides the loop filter output signal.

3. The continuous time as described in claim 2 An ADC linearity optimization system is characterized by, The first sub-filter includes: a first resistor, a first capacitor, and a first operational amplifier, wherein: one end of the first resistor is connected to the input terminal of the first sub-filter, and the other end is connected to the inverting input terminal of the first operational amplifier; the first capacitor is connected in parallel between the inverting input terminal and the output terminal of the first operational amplifier; the non-inverting input terminal of the first operational amplifier is grounded, and its output terminal serves as the output of the first sub-filter and is connected to the input terminal of the second sub-filter. The second sub-filter includes a second resistor, a second capacitor, a third resistor, and a second operational amplifier. One end of the second resistor is connected to the output of the first sub-filter, and the other end is connected to the inverting input of the second operational amplifier. The third resistor and the second capacitor are connected in series to form a proportional-integral network, which is connected between the inverting input and the output of the second operational amplifier. The non-inverting input of the second operational amplifier is grounded, and its output serves as a loop filter output.

4. The continuous time as described in claim 1 An ADC linearity optimization system is characterized by, The aforementioned pre-decision closed-loop feedback module includes: a latch unit and an interpolation unit, which implement the transfer function H. pre [z]=2z –1 –z –2 .

5. The continuous time as described in claim 1 An ADC linearity optimization system is characterized by, The first high-frequency compensation digital filter includes a latch unit and a shift operation unit, which internally performs signal filtering and implements the transfer function H through shift operations and latch delay. comp1 [z]=4-3z –1 ; The second high-frequency compensated digital filter includes two parallel infinite impulse response branches, wherein the first branch comprises a cascaded first-order IIR structure and a second-order differential unit in the digital domain, and the second branch is another independent IIR branch; the outputs of the two branches are combined by an adder unit to jointly realize the transfer function H. comp2 [z]= .

6. A continuous-time system based on any one of claims 1-5 The ADC linearity optimization method is characterized by, include: Step 1, Input signal V in After being processed sequentially by a second-order continuous-time loop filter and a quantizer for two clock cycles, the most significant bit (MSB) of the current signal is extracted by the pre-decision module to obtain the pre-decision digital signal. ; Step 2, the pre-decision signal D pre,out With the system's main digital output D out Each signal is input into its corresponding digital compensation filter, and its transfer function is corrected to obtain the compensated signal D. comp,out1 With D comp,out2； Step 3, D comp,out1 With D comp,out2 The signal is converted into an analog signal V by a two-way feedback DAC. DAC,out1 and V DAC,out2 Each of these is subtracted from the original input signal to generate a residual signal with a significantly reduced swing. Step four: The residual signal is quantized to obtain D. q,out In the digital domain, with the pre-decision signal D pre,out The components are synthesized to form the final complete system output D. out This completes the entire process of analog-to-digital conversion and linearity optimization.

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