Receiver circuit, semiconductor device, and semiconductor system using same

Abstract

The invention relates to a receiver circuit, a semiconductor device and a semiconductor system using the same. The receiver circuit includes a first amplification stage and a second amplification stage. The first amplification stage is configured to generate a first output signal by differentially amplifying a pair of input signals. The second amplification stage is configured to generate a second output signal by amplifying the first output signal. The receiver circuit is configured to deactivate the second amplification stage and then deactivate the first amplification stage.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority from Korean Application No. 10-2023-0089236 filed on July 10, 2023, in the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to an integrated circuit technology, and more particularly, to a receiver circuit, a semiconductor device, and a semiconductor system using the same. Background Art

[0004] An electronic device may include many electronic components, and among the electronic devices, a computer system may include many semiconductor devices made of semiconductor devices. The semiconductor devices constituting the computer system may communicate with each other by sending and receiving clock signals and data. The semiconductor devices may operate synchronously with the clock signal, and send data synchronously with the clock signal or receive data synchronously with the clock signal.

[0005] Each semiconductor device may include a receiver circuit to receive a clock signal and data. Typically, the receiver circuit may include an amplifier for amplifying a single-ended signal or a differential signal. In order to reduce power consumption, the semiconductor device may activate the receiver circuit only during the period when the operation of the receiver circuit is required, and deactivate the receiver circuit during other periods. However, when the receiver circuit is activated or deactivated, unexpected glitches may occur, which may likely produce abnormal output signals. Specifically, semiconductor devices operating at high frequencies may perform abnormal operations based on abnormal output signals. Summary of the invention

[0006] According to an embodiment, a receiver circuit may include a first amplifier stage, a second amplifier stage, and an enable control circuit. The first amplifier stage may be configured to generate a first output signal by differentially amplifying a first input signal and a second input signal when a first enable signal is enabled. The second amplifier stage may be configured to generate a second output signal by amplifying the first output signal when a second enable signal is enabled. The enable control circuit may be configured to generate a first enable signal and a second enable signal based on the amplified enable signal and disable the first enable signal after disabling the second enable signal.

[0007] According to an embodiment, a receiver circuit may include a first amplifier stage, a second amplifier stage, a third amplifier stage, and an enable control circuit. The first amplifier stage may be configured to generate a first output signal by amplifying an input signal pair. The second amplifier stage may be configured to generate a second output signal by amplifying the first output signal. The third amplifier stage may be configured to generate a third output signal by amplifying the second output signal. The enable control circuit may be configured to activate the first amplifier stage, the second amplifier stage, and the third amplifier stage in sequence, and deactivate the third amplifier stage, the second amplifier stage, and the first amplifier stage in sequence in the reverse order of the order in which the first to third amplifier stages are activated.

[0008] According to an embodiment, a receiver circuit may include a plurality of amplifier stages, the plurality of amplifier stages being sequentially configured such that a first amplifier stage of the plurality of amplifier stages receives an input signal and amplifies the input signal to generate an output signal, wherein each subsequent amplifier stage of the plurality of amplifier stages is configured to amplify the output signal of the previous amplifier stage. The receiver circuit may also include an enable control circuit configured to generate different enable signals to sequentially activate each of the plurality of amplifier stages starting from the first amplifier stage, and to deactivate the amplifier stages in reverse order starting from the last amplifier stage of the plurality of amplifier stages to be activated.

[0009] According to an embodiment, a semiconductor integrated circuit may include an enable control circuit configured to generate a plurality of enable signals that are enabled in sequence. The semiconductor integrated circuit may also include a plurality of amplifier stages connected in series, the plurality of amplifier stages being configured to receive the plurality of enable signals, respectively, and being activated and deactivated in sequence based on the plurality of enable signals. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a diagram showing a configuration of an amplifier according to the embodiment.

[0011] Figure 2A It is shown Figure 1 Timing diagram of the amplifier's operation.

[0012] Figure 2B It is shown Figure 1 Another operation timing diagram of the amplifier is shown in FIG.

[0013] Figure 3 is a diagram showing a configuration of a receiver circuit according to an embodiment.

[0014] Figure 4 is a diagram showing a configuration of a receiver circuit according to an embodiment.

[0015] Figure 5 It is shown Figure 4 A diagram of the configuration of the enable control circuit shown.

[0016] Figure 6 It is shown Figure 5 The timing diagram of the operation of the enable control circuit is shown.

[0017] Figure 7 is a timing diagram illustrating the operation of the receiver circuit according to the embodiment.

[0018] Figure 8 is a diagram illustrating a configuration of a semiconductor system according to an embodiment. DETAILED DESCRIPTION

[0019] Figure 1 is a diagram showing a configuration of an amplifier 100 according to an embodiment of the present disclosure. Figure 1 , the amplifier 100 may be a differential amplifier that receives two input signals and generates one output signal or two output signals. The amplifier 100 may receive a first input signal IN1 and a second input signal IN2 and generate an output signal OUT and a complementary output signal OUTB. The amplifier 100 may perform an amplification operation by receiving a first voltage VH and a second voltage VL. The first voltage VH may have a higher voltage level than the second voltage VL. The amplifier 100 may change the voltage levels of the output signal OUT and the complementary output signal OUTB according to the voltage levels of the first input signal IN1 and the second input signal IN2. When the voltage level of the first input signal IN1 is higher than the voltage level of the second input signal IN2, the amplifier 100 may generate an output signal OUT having a voltage level higher than the voltage level of the complementary output signal OUTB. When the voltage level of the first input signal IN1 is lower than the voltage level of the second input signal IN2, the amplifier 100 may generate an output signal OUT having a voltage level lower than the voltage level of the complementary output signal OUTB. The amplifier 100 may further receive an enable signal EN. The amplifier 100 may be activated based on the enable signal EN. When the enable signal EN is enabled, the amplifier 100 may be activated, and when the enable signal EN is disabled, the amplifier 100 may be deactivated.

[0020] The amplifier 100 may include a first transistor T1, a second transistor T2, a current source CS, a first switch SW1, a second switch SW2, a first resistor R1, and a second resistor R2. The first transistor T1 and the second transistor T2 may be N-channel MOS transistors. The gate of the first transistor T1 may receive a first input signal IN1, and the source of the first transistor T1 may be connected to the current source CS. The gate of the second transistor T2 may receive a second input signal IN2, and the source of the second transistor T2 may be connected to the source of the first transistor T1 and the current source CS. One end of the current source CS may be commonly connected to the sources of the first transistor T1 and the second transistor T2, and the other end of the current source CS may be connected to a terminal to which a second voltage VL is provided. The current source CS may flow a current, or provide a current path from the sources of the first transistor T1 and the second transistor T2 to a terminal to which a second voltage VL is provided. One end of the first switch SW1 may be connected to the drain of the first transistor T1, and the other end of the first switch SW1 may be connected to the first output node ON1. A complementary output signal OUTB may be output from the first output node ON1. The first switch SW1 may receive an enable signal EN as a control signal, and the switch may be opened or closed between the first transistor T1 and the first output node ON1 based on the enable signal EN. One end of the second switch SW2 may be connected to the drain of the second transistor T2, and the other end of the second switch SW2 may be connected to the second output node ON2. The output signal OUT may be output from the second output node ON2. The second switch SW2 may receive an enable signal EN as a control signal, and the switch may be opened or closed between the second transistor T2 and the second output node ON2 based on the enable signal EN. One end of the first resistor R1 may be connected to the first output node ON1, and the other end of the first resistor R1 may be connected to a terminal to which a first voltage VH is provided. One end of the second resistor R2 may be connected to the second output node ON2, and the other end of the second resistor R2 may be connected to a terminal to which a first voltage VH is provided.

[0021] When the enable signal EN is enabled, since the first switch SW1 and the second switch SW2 are turned on (closed) and a current path is formed from the terminal to which the first voltage VH is provided to the terminal to which the second voltage VL is provided, the amplifier 100 may be activated. When the amplifier 100 is activated, the amplifier 100 may generate an output signal OUT and a complementary output signal OUTB by differentially amplifying the voltage levels of the first input signal IN1 and the second input signal IN2. When the enable signal EN is disabled, since the first switch SW1 and the second switch SW2 are turned off (disconnected) and a current path from the terminal to which the first voltage VH is provided to the terminal to which the second voltage VL is provided is blocked, the amplifier 100 may be deactivated. Figure 1The amplifier 100 is shown as an N-type amplifier including N-channel MOS transistors; however, the amplifier 100 may be replaced with a P-type amplifier. The P-type amplifier may include a P-channel MOS transistor that receives the first input signal IN1 and the second input signal IN2.

[0022] Figure 2A It is shown Figure 1 The timing diagram of the operation of the amplifier 100 is shown in FIG. Figure 1 and Figure 2A , the enable signal EN can remain disabled to a low logic level and then be enabled to a high logic level. In this case, it is assumed that the first input signal IN1 has a voltage level corresponding to a high logic level, and the second input signal IN2 has a voltage level corresponding to a low logic level. When the enable signal EN is enabled, the first switch SW1 and the second switch SW2 are turned on (closed), and the first voltage VH is started to be provided from the terminal to which the first voltage VH is provided to the first output node ON1 and the second output node ON2. When the enable signal EN is enabled, the first output node ON1 and the second output node ON2 can be instantaneously charged at the same time, and then the voltage levels of the first output node ON1 and the second output node ON2 can be stabilized to a DC level DC level according to the voltage levels of the first input signal IN1 and the second input signal IN2. Since the amount of current flowing through the first transistor T1 is greater than the amount of current flowing through the second transistor T2, the complementary output signal OUTB of the first output node ON1 can be stabilized to a low logic level, and the output signal OUT of the second output node ON2 can be stabilized to a high logic level. However, when the enable signal EN is enabled, since the first output node ON1 and the second output node ON2 are charged at the same time and the voltage levels of the output signal OUT and the complementary output signal OUTB are inverted, an abnormal glitch g may occur in the output signal OUT and the complementary output signal OUTB. The abnormal glitch may affect the operation of the internal circuit arranged after the amplifier 100, thereby causing abnormal operation of the internal circuit.

[0023] Figure 2B It is shown Figure 1 Another timing diagram of the operation of the amplifier 100 is shown. Figure 1 and Figure 2B, the enable signal EN can remain enabled to a high logic level and then disabled to a low logic level. In this case, it is assumed that the first input signal IN1 has a voltage level corresponding to a high logic level, and the second input signal IN2 has a voltage level corresponding to a low logic level. When the enable signal EN is disabled, the first switch SW1 and the second switch SW2 can be turned off (disconnected), and the first voltage VH provided from the terminal to which the first voltage VH is provided to the first output node ON1 and the second output node ON2 may be blocked. When the enable signal EN is disabled, the first output node ON1 and the second output node ON2 may be floated at the same time. Therefore, because the voltage levels of the first output node ON1 and the second output node ON2 are instantaneously discharged, the voltage level of the complementary output signal OUTB and the voltage level of the output signal OUT may be reduced. When the enable signal EN is disabled, since the first output node ON1 and the second output node ON2 are discharged at the same time and the voltage levels of the first output node ON1 and the second output node ON2 are inverted, abnormal glitches g' may appear in the output signal OUT and the complementary output signal OUTB. The abnormal glitch may affect the operation of an internal circuit arranged after the amplifier 100 , thereby causing abnormal operation of the internal circuit.

[0024] Figure 3 is a diagram showing a configuration of a receiver circuit 200 according to an embodiment of the present disclosure. Figure 3 , the receiver circuit 200 may receive an input signal pair and generate an output signal. The input signal pair may include a first input signal IN1 and a second input signal IN2. The second input signal IN2 may be a complementary signal of the first input signal IN1, and the first input signal IN1 and the second input signal IN2 may be a differential signal pair. In an embodiment, the first input signal IN1 may be a single-ended signal, and the second input signal IN2 may be a reference voltage. The reference voltage may have a voltage level corresponding to an intermediate value of a range of swings of the first input signal IN1. The receiver circuit 200 may include a plurality of amplifier stages. The receiver circuit 200 may generate an output signal by amplifying the first input signal IN1 and the second input signal IN2 through a plurality of amplifier stages. The receiver circuit 200 may set the timing at which the plurality of amplifier stages are deactivated differently. The receiver circuit 200 may control the plurality of amplifier stages to be deactivated in sequence. The receiver circuit 200 may also set the timing at which the plurality of amplifier stages are activated differently. The receiver circuit 200 may control the plurality of amplifier stages to be activated in sequence. For example, the activation and deactivation of the plurality of amplifier stages are staggered in time.

[0025] The receiver circuit 200 may include a first amplifier stage 210 and a second amplifier stage 220 connected in series in sequence. The first amplifier stage 210 may receive a first input signal IN1 and a second input signal IN2, and generate a first output signal OUT1 by differentially amplifying the first input signal IN1 and the second input signal IN2. The second amplifier stage 220 may receive a first output signal OUT1 and generate a second output signal OUT2 by amplifying the first output signal OUT1. The first amplifier stage 210 and the second amplifier stage 220 may each include at least one amplifier. In an embodiment, the first amplifier stage 210 may generate a first output signal OUT1 and a complementary signal of the first output signal OUT1, and the second amplifier stage 220 may generate a second output signal OUT2 by differentially amplifying the first output signal OUT1 and a complementary signal of the first output signal OUT1. In an embodiment, the second amplifier stage 220 may generate a second output signal OUT2 and a complementary signal of the second output signal OUT2.

[0026] The first amplifier stage 210 may receive a first enable signal EN1, and the second amplifier stage 220 may receive a second enable signal EN2. The first amplifier stage 210 may be activated based on the first enable signal EN1. When the first enable signal EN1 is enabled, the first amplifier stage 210 may be activated, and when the first enable signal EN1 is disabled, the first amplifier stage 210 may be disabled. The second amplifier stage 220 may be activated based on the second enable signal EN2. When the second enable signal EN2 is enabled, the second amplifier stage 220 may be activated, and when the second enable signal EN2 is disabled, the second amplifier stage 220 may be disabled. The receiver circuit 200 may disable the first amplifier stage 210 and the second amplifier stage 220 in sequence. The receiver circuit 200 may disable the second enable signal EN2 and then disable the first enable signal EN1. The receiver circuit 200 may activate the first amplifier stage 210 and the second amplifier stage 220 in sequence. The order of activating the first amplifier stage 210 and the second amplifier stage 220 may be opposite to the order of deactivating the first amplifier stage 210 and the second amplifier stage 220. The receiver circuit 200 may enable the first enable signal EN1 and then enable the second enable signal EN2. Therefore, during the period in which the receiver circuit 200 operates, the first amplifier stage 210 may be activated before the second amplifier stage 220 and deactivated after the second amplifier stage 220.

[0027] The receiver circuit 200 may further include an enable control circuit 230. The enable control circuit 230 may receive the amplification enable signal EN and generate a first enable signal EN1 and a second enable signal EN2 based on the amplification enable signal EN. The amplification enable signal EN may be a signal that defines an operation period of the receiver circuit 200. When the amplification enable signal EN is enabled, the enable control circuit 230 may first enable the first enable signal EN1 and then enable the second enable signal EN2. When the amplification enable signal EN is disabled, the enable control circuit 230 may first disable the second enable signal EN2 and then disable the first enable signal EN1.

[0028] Figure 4 is a diagram showing a configuration of a receiver circuit 300 according to an embodiment of the present disclosure. Figure 4 , the receiver circuit 300 may include a first amplifier stage 310, a second amplifier stage 320, a third amplifier stage 330, and an enable control circuit 340. For some embodiments, the plurality of amplifier stages and the enable control circuit may be implemented by a semiconductor integrated circuit. The first amplifier stage 310 may receive a first input signal IN1 and a second input signal IN2, and generate a first output signal OUT1 by differentially amplifying the first input signal IN1 and the second input signal IN2. The first amplifier stage 310 may receive a first enable signal EN1 and be activated based on the first enable signal EN1. When the first enable signal EN1 is enabled, the first amplifier stage 310 may be activated. When the first enable signal EN1 is disabled, the first amplifier stage 310 may be deactivated.

[0029] The second amplifier stage 320 may be cascade-connected to the next stage of the first amplifier stage 310. For example, the first amplifier stage 310 and the second amplifier stage 320 may be electrically connected in series. The second amplifier stage 320 may receive the first output signal OUT1 and generate the second output signal OUT2 by amplifying the first output signal OUT1. The second amplifier stage 320 may receive the second enable signal EN2 and be activated based on the second enable signal EN2. When the second enable signal EN2 is enabled, the second amplifier stage 320 may be activated. When the second enable signal EN2 is disabled, the second amplifier stage 320 may be deactivated. In an embodiment, the first amplifier stage 310 may generate the first output signal OUT1 and a complementary signal of the first output signal OUT1, and the second amplifier stage 320 may generate the second output signal OUT2 by differentially amplifying the first output signal OUT1 and a complementary signal of the first output signal OUT1.

[0030] The third amplifier stage 330 may be cascade-connected to the next stage of the second amplifier stage 320. For example, the second amplifier stage 320 and the third amplifier stage 330 may be electrically connected in series. The third amplifier stage 330 may receive the second output signal OUT2 and generate the third output signal OUT3 by amplifying the second output signal OUT2. The third amplifier stage 330 may receive the third enable signal EN3 and be activated based on the third enable signal EN3. When the third enable signal EN3 is enabled, the third amplifier stage 330 may be activated. When the third enable signal EN3 is disabled, the third amplifier stage 330 may be deactivated. In an embodiment, the second amplifier stage 320 may generate a complementary signal of the second output signal OUT2 and the second output signal OUT2, and the third amplifier stage 330 may generate the third output signal OUT3 by differentially amplifying the complementary signal of the second output signal OUT2 and the second output signal OUT2. The third amplifier stage 330 may also generate the third output signal OUT3 and the complementary signal of the third output signal OUT3.

[0031] The enable control circuit 340 may activate the first to third amplification stages 310, 320, and 330 during an operation period of the receiver circuit 300. When the operation period of the receiver circuit 300 starts, the enable control circuit 340 may activate the first to third amplification stages 310, 320, and 330. When the operation period of the receiver circuit 300 ends, the enable control circuit 340 may sequentially deactivate the activated first to third amplification stages 310, 320, and 330. The enable control circuit 340 may sequentially deactivate the third, second, and first amplification stages 330, 320, and 310. The enable control circuit 340 may first deactivate the third amplification stage 330, deactivate the second amplification stage 320, and then deactivate the first amplification stage 310. The enable control circuit 340 may sequentially activate the first to third amplification stages 310, 320, and 330 in the reverse order of the order in which the first to third amplification stages 310, 320, and 330 are deactivated. The enable control circuit 340 may first activate the first amplification stage 310 , activate the second amplification stage 320 , and then activate the third amplification stage 330 .

[0032] The enable control circuit 340 may receive the amplified enable signal EN and generate a first enable signal EN1, a second enable signal EN2, and a third enable signal EN3 based on the amplified enable signal EN. In an embodiment, the enable control circuit 340 may also generate and output a complementary signal EN2B of the second enable signal EN2. The amplified enable signal EN may be a signal that defines an operation period of the receiver circuit 300. When the amplified enable signal EN is enabled, the receiver circuit 300 may be activated and may receive the first input signal IN1 and the second input signal IN2. When the amplified enable signal EN is disabled, the receiver circuit 300 may be deactivated and may not receive the first input signal IN1 and the second input signal IN2. When the amplified enable signal EN is enabled, the enable control circuit 340 may first enable the first enable signal EN1 and then enable the second enable signal EN2. The enable control circuit 340 may enable the second enable signal EN2 and then enable the third enable signal EN3. When the amplification enable signal EN is disabled, the enable control circuit 340 may first disable the third enable signal EN3 and then disable the second enable signal EN2. The enable control circuit 340 may disable the second enable signal EN2 and then disable the first enable signal EN1.

[0033] The first amplifier stage 310 may include at least one amplifier. The first amplifier stage 310 may include a first amplifier 311, a second amplifier 312, and a third amplifier 313. The first to third amplifiers 311 to 313 may all be differential amplifiers. The first to third amplifiers 311 to 313 may be operated by receiving a first voltage VH and a second voltage VL. The first amplifier 311 may receive a first input signal IN1 and a second input signal IN2, and generate a first intermediate output signal pair by differentially amplifying the first input signal IN1 and the second input signal IN2. The first intermediate output signal pair may include a first intermediate output signal O1 and a complementary signal O1B of the first intermediate output signal O1. The second amplifier 312 may receive a first intermediate output signal O1 and a complementary signal O1B of the first intermediate output signal O1, and generate a second intermediate output signal pair by differentially amplifying the first intermediate output signal O1 and the complementary signal O1B of the first intermediate output signal O1. The second intermediate output signal pair may include a second intermediate output signal O2 and a complementary signal O2B of the second intermediate output signal O2. The third amplifier may receive the second intermediate output signal O2 and the complementary signal O2B of the second intermediate output signal O2, and generate the first output signal OUT1 by differentially amplifying the second intermediate output signal O2 and the complementary signal O2B of the second intermediate output signal O2. Figure 1The first to third amplifiers 311 to 313 may be configured the same or similarly as the amplifiers shown. The first to third amplifiers 311 to 313 may receive the first enable signal EN1 in common. When the first enable signal EN1 is enabled, the first to third amplifiers 311 to 313 may be activated. When the first enable signal EN1 is disabled, the first to third amplifiers 311 to 313 may be deactivated.

[0034] The second amplifier stage 320 may include at least one amplifier. The second amplifier stage 320 may include a fourth amplifier 321. The fourth amplifier 321 may include at least one of an inverter and an inverting amplifier. In an embodiment, the fourth amplifier 321 may also include a buffer or a single-stage amplifier, such as a common-source amplifier, a source follower amplifier, a common-gate amplifier, or a common-source common-gate amplifier. The fourth amplifier 321 may be operated by receiving a first voltage VH and a second voltage VL. The fourth amplifier 321 may receive a first output signal OUT1 and generate a second output signal OUT2 by inverting and amplifying the first output signal OUT1. The second output signal OUT2 may have a voltage level opposite to that of the first output signal OUT1. The fourth amplifier 321 may receive a second enable signal EN2. When the second enable signal EN2 is enabled, the fourth amplifier 321 may be activated. When the second enable signal EN2 is disabled, the fourth amplifier 321 may be deactivated.

[0035] The third amplifier stage 330 may include at least one amplifier. The third amplifier stage 330 may include a fifth amplifier 331. The fifth amplifier 331 may include at least one of an inverter and an inverting amplifier. In an embodiment, the fifth amplifier 331 may also include a buffer or a single-stage amplifier, such as a common-source amplifier, a source follower amplifier, a common-gate amplifier, or a common-source common-gate amplifier. The fifth amplifier 331 may be operated by receiving a first voltage VH and a second voltage VL. The fifth amplifier 331 may receive a second output signal OUT2 and generate a third output signal OUT3 by inverting and amplifying the second output signal OUT2. The third output signal OUT3 may have a voltage level opposite to that of the second output signal OUT2. The fifth amplifier 331 may receive a third enable signal EN3. When the third enable signal EN3 is enabled, the fifth amplifier 331 may be activated. When the third enable signal EN3 is disabled, the fifth amplifier 331 may be deactivated.

[0036] The receiver circuit 300 may further include a first precharge circuit 350. The first precharge circuit 350 may receive a first enable signal EN1 and precharge the first output signal OUT1 to a voltage level of a first voltage VH based on the first enable signal EN1. When the first enable signal EN1 is disabled and the first amplifier stage 310 is disabled, the first precharge circuit 350 may fix the first output signal OUT1 to a voltage level of the first voltage VH. The receiver circuit 300 may further include a discharge circuit 360. The discharge circuit 360 may discharge the second output signal OUT2 to a voltage level of a second voltage VL based on a second enable signal EN2. The discharge circuit 360 may receive a complementary signal EN2B of the second enable signal EN2 and discharge the second output signal OUT2 to a voltage level of a second voltage VL in response to the complementary signal EN2B of the second enable signal EN2. When the second enable signal EN2 is disabled and the second amplifier stage 320 is disabled, the discharge circuit 360 may fix the second output signal OUT2 to a voltage level of the second voltage VL. The receiver circuit 300 may further include a second precharge circuit 370. The second precharge circuit 370 may receive the third enable signal EN3 and precharge the third output signal OUT3 to the voltage level of the first voltage VH based on the third enable signal EN3. When the third enable signal EN3 is disabled and the third amplifier stage 330 is deactivated, the second precharge circuit 370 may fix the third output signal OUT3 to the voltage level of the first voltage VH.

[0037] The first precharge circuit 350 may include a first transistor 351. The first transistor 351 may be a P-channel MOS transistor. The gate of the first transistor 351 may receive a first enable signal EN1, the source of the first transistor 351 may receive a first voltage VH, and the drain of the first transistor 351 may be connected to a first output signal OUT1. The discharge circuit 360 may include a second transistor 361. The second transistor 361 may be an N-channel MOS transistor. The gate of the second transistor 361 may receive a complementary signal EN2B of the second enable signal EN2, the drain of the second transistor 361 may be connected to the second output signal OUT2, and the source of the second transistor 361 may receive a second voltage VL. The second precharge circuit 370 may include a third transistor 371. The third transistor 371 may be a P-channel MOS transistor. The gate of the third transistor 371 may receive a third enable signal EN3, the source of the third transistor 371 may receive the first voltage VH, and the drain of the third transistor 371 may be connected to a third output signal OUT3.

[0038] Figure 5 It is shown Figure 4 FIG. 3 is a diagram showing a configuration of the enable control circuit 340. Figure 5, the enable control circuit 340 may include a delay circuit 410, a first gating circuit 420, a second gating circuit 430, and a third gating circuit 440. The delay circuit 410 may receive the amplification enable signal EN, and generate a first delay signal END1 and a second delay signal END2 by sequentially delaying the amplification enable signal EN. The delay circuit 410 may generate a first delay signal END1 by delaying the amplification enable signal EN by a unit delay time, and generate a second delay signal END2 by delaying the first delay signal END1 by a unit delay time. The unit delay time may be an arbitrarily set delay time. For example, the unit delay time may correspond to the minimum time required for the voltage level of the first output signal OUT1 to stabilize from the time when the first amplifier stage 310 is activated or deactivated. Alternatively, the unit delay time may correspond to the minimum time required for the abnormal burr appearing in the first output signal OUT1 to disappear as the first amplifier stage 310 is activated or deactivated. The delay circuit 410 may include a first delay device DLY1 and a second delay device DLY2. The delay time of the first delay device DLY1 and the second delay device DLY2 may be substantially equal to the unit delay time. The first delay device DLY1 may receive the amplification enable signal EN and generate a first delay signal END1 by delaying the amplification enable signal EN. The second delay device DLY2 may receive the first delay signal END1 and generate a second delay signal END2 by delaying the first delay signal END1.

[0039] The first gating circuit 420 may receive the amplified enable signal EN and the second delayed signal END2. The first gating circuit 420 may generate the first enable signal EN1 based on the amplified enable signal EN and the second delayed signal END2. When at least one of the amplified enable signal EN and the second delayed signal END2 is enabled, the first gating circuit 420 may enable the first enable signal EN1. When both the amplified enable signal EN and the second delayed signal END2 are disabled, the first gating circuit 420 may disable the first enable signal EN1. When the amplified enable signal EN is enabled, the first gating circuit 420 may enable the first enable signal EN1, and when the second delayed signal END2 is disabled, the first gating circuit 420 may disable the first enable signal EN1. The first gating circuit 420 may include an OR gate OR. A first input terminal of the OR gate OR may receive the amplified enable signal EN, a second input terminal of the OR gate OR may receive the second delayed signal END2, and the first enable signal EN1 may be output from an output terminal of the OR gate OR.

[0040] The second gating circuit 430 may receive the first delay signal END1. The second gating circuit 430 may provide the first delay signal END1 as the second enable signal EN2. When the first delay signal END1 is enabled, the second gating circuit 430 may enable the second enable signal EN2, and when the first delay signal END1 is disabled, the second gating circuit 430 may disable the second enable signal EN2. The second gating circuit 430 may include a first AND gate AND1 and an inverter IV. The first input terminal of the first AND gate AND1 may receive the first delay signal END1, the second input terminal of the first AND gate AND1 may receive the first voltage VH, and the second enable signal EN2 may be output from the output terminal of the first AND gate AND1. The input terminal of the inverter IV may receive the second enable signal EN2, and the complementary signal EN2B of the second enable signal EN2 may be output from the output terminal of the inverter IV.

[0041] The third gating circuit 440 may receive the amplified enable signal EN and the second delayed signal END2. The third gating circuit 440 may generate a third enable signal EN3 based on the amplified enable signal EN and the second delayed signal END2. When both the amplified enable signal EN and the second delayed signal END2 are enabled, the third gating circuit 440 may enable the third enable signal EN3. When at least one of the amplified enable signal EN and the second delayed signal END2 is disabled, the third gating circuit 440 may disable the third enable signal EN3. When the second delayed signal END2 is enabled, the third gating circuit 440 may enable the third enable signal EN3, and when the amplified enable signal EN is disabled, the third gating circuit 440 may disable the third enable signal EN3. The third gating circuit 440 may include a second AND gate AND2. A first input terminal of the second AND gate AND2 may receive the amplified enable signal EN, a second input terminal of the second AND gate AND2 may receive the second delayed signal END2, and the third enable signal EN3 may be output from an output terminal of the second AND gate AND2.

[0042] Figure 6 It is shown Figure 5 The timing diagram of the operation of the enable control circuit 340 is shown in FIG. Figure 5 and Figure 6, the delay circuit 410 may generate the first delay signal END1 and the second delay signal END2 by sequentially delaying the amplification enable signal EN. The amplification enable signal EN may be enabled first, and then the first delay signal END1 and the second delay signal END2 may be enabled sequentially. The first gating circuit 420 may enable the first enable signal EN1 to a high logic level when the amplification enable signal EN is enabled. When the first delay signal END1 is enabled to a high logic level, the second gating circuit 430 may enable the second enable signal EN2 to a high logic level. When the second delay signal END2 is enabled to a high logic level, the third gating circuit 440 may enable the third enable signal EN3 to a high logic level. When the amplification enable signal EN is disabled to a low logic level, the delay circuit 410 may disable the first delay signal END1 and the second delay signal END2 to a low logic level in sequence. When the amplification enable signal EN is disabled, the third gating circuit 440 may disable the third enable signal EN3 to a low logic level. When the first delay signal END1 is disabled, the second gating circuit 430 may disable the second enable signal EN2 to a low logic level. When the second delay signal END2 is disabled, the first gating circuit 420 may disable the first enable signal EN1 to a low logic level. Therefore, the first enable signal EN1 may be enabled first, and then the second enable signal EN2 and the third enable signal EN3 may be enabled in sequence. Conversely, the third enable signal EN3 may be disabled first, and then the second enable signal EN2 and the first enable signal EN1 may be disabled in sequence. The enable period of the first enable signal EN1 may be the longest, the enable period of the second enable signal EN2 may be shorter than the enable period of the first enable signal EN1, and the enable period of the third enable signal EN3 may be the shortest. In this way, the order of enabling is to enable EN1 first, then enable EN2, and finally enable EN3. The order of disabling is the opposite, that is, to disable EN3 first, then disable EN2, and finally disable EN1.

[0043] Figure 7 is a timing diagram showing the operation of the receiver circuit 300 according to an embodiment of the present disclosure. Figure 4 , Figure 6 and Figure 7The operation of the receiver circuit 300 is described. When the amplification enable signal EN is in a disabled state, the first precharge circuit 350 may precharge the first output signal OUT1 to a high logic level, the discharge circuit 360 may discharge the second output signal OUT2 to a low logic level, and the second precharge circuit 370 may precharge the third output signal OUT3 to a high logic level. The amplification enable signal EN may be enabled so that the period in which the first input signal IN1 and the second input signal IN2 are input may be covered. When the amplification enable signal EN is enabled, the first enable signal EN1 may be enabled, the first precharge circuit 350 may be turned off, and the first amplifier stage 310 may be activated. After the first enable signal EN1 is enabled, the second enable signal EN2 and the third enable signal EN3 may be enabled in sequence. When the second enable signal EN2 and the third enable signal EN3 are enabled, the discharge circuit 360 and the second precharge circuit 370 may be turned off, and the second amplifier stage 320 and the third amplifier stage 330 may be activated in sequence. After the first to third enable signals EN1 to EN3 are enabled, the preamble PRA, the body BD and the postamble PSA of the first input signal IN1 and the second input signal IN2 can be input in sequence. By differentially amplifying the first input signal IN1 and the second input signal IN2, the first amplifier stage 310 can generate a first output signal OUT1 that changes substantially the same as the first input signal IN1. By amplifying the first output signal OUT1, the second amplifier stage 320 can generate a second output signal OUT2 that changes complementarily to the first output signal OUT1. The third amplifier stage 330 can amplify the second output signal OUT2 and generate a third output signal OUT3 that changes complementarily to the second output signal OUT2. After sending the postamble PSA of the first input signal IN1 and the second input signal IN2, the amplification enable signal EN can be disabled. When the amplification enable signal EN is disabled, the third enable signal EN3 can be disabled first, and the third amplifier stage 330 can be deactivated. The second precharge circuit 370 can precharge the voltage level of the third output signal OUT3 to the voltage level of the first voltage VH. After the third enable signal EN3 is disabled, the second enable signal EN2 and the first enable signal EN1 may be disabled in sequence. When the second enable signal EN2 and the first enable signal EN1 are disabled, the second amplifier stage 320 and the first amplifier stage 310 may be deactivated in sequence. The discharge circuit 360 may discharge the second output signal OUT2 to a voltage level of the second voltage VL, and the first precharge circuit 350 may precharge the first output signal OUT1 to a voltage level of the first voltage VH.

[0044] When the first enable signal EN1 is enabled, the output nodes of the first to third amplifiers 311 to 313 constituting the first amplification stage 310 may be charged at the same time, and an abnormal glitch EAG may appear in the first output signal OUT1. Since the second enable signal EN2 and the third enable signal EN3 are enabled later than the first enable signal EN1, the second enable signal EN2 and the third enable signal EN3 may not be affected by the abnormal glitch EAG even if the second amplification stage 320 and the third amplification stage 330 are activated. In other words, the second amplification stage 320 may not amplify the abnormal glitch EAG, and the voltage levels of the second output signal OUT2 and the third output signal OUT3 may not be affected. When the first enable signal EN1 is disabled, the output nodes of the first to third amplifiers 311 to 313 constituting the first amplification stage 310 may be discharged at the same time, and an abnormal glitch DAG may appear in the first output signal OUT1. Since the second enable signal EN2 and the third enable signal EN3 are in a disabled state before the first enable signal EN1, and the second amplification stage 320 and the third amplification stage 330 are also in a disabled state, the abnormal glitch DAG of the first output signal OUT1 may not affect the voltage levels of the second output signal OUT2 and the third output signal OUT3.

[0045] Figure 8 is a diagram showing a configuration of a semiconductor system 500 according to an embodiment of the present disclosure. Figure 8 , the semiconductor system 500 may include a first semiconductor device 510 and a second semiconductor device 520. The first semiconductor device 510 may be a master device that provides various control signals required for the operation of the second semiconductor device 520. The second semiconductor device 520 may be a slave device that performs various operations under the control of the first semiconductor device 510. The first semiconductor device 510 may include various types of host devices. For example, the first semiconductor device 510 may include a central processing unit (CPU), a graphics processing unit (GPU), a multimedia processor (MMP), a digital signal processor, an application processor (AP), a memory controller, etc. For example, the second semiconductor device 520 may be a memory device, and the memory device may include a volatile memory and a non-volatile memory. The volatile memory may include a static RAM (SRAM), a dynamic RAM (DRAM), and a synchronous DRAM (SDRAM). The non-volatile memory may include a read-only memory (ROM), a programmable ROM (PROM), an electrically erasable programmable ROM (EEPROM), an erasable PROM (EPROM), a flash memory, a phase change RAM (PRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), a ferroelectric RAM (FRAM), etc.

[0046] The second semiconductor device 520 may be connected to the first semiconductor device 510 through a plurality of buses. The plurality of buses may be signal transmission paths, links or channels for transmitting signals. The plurality of buses may include a clock bus 501 and a data bus 502. The clock bus 501 and the data bus 502 may be bidirectional buses. The second semiconductor device 520 may be connected to the first semiconductor device 510 through the clock bus 501, and may transmit the clock signal pair CKT / CKC to the first semiconductor device 510 or receive the clock signal pair CKT / CKC transmitted from the first semiconductor device 510 through the clock bus 501. The second semiconductor device 520 may be connected to the first semiconductor device 510 through the data bus 502, and may transmit the data DQ to the first semiconductor device 510 or receive the data DQ transmitted from the first semiconductor device 510 through the data bus 502. The clock signal pair CKT / CKC may be synchronized with the data DQ, and the data DQ may be aligned with the edge of the clock signal pair CKT / CKC and transmitted through the data bus 501. In an embodiment, the clock bus 501 may be a data strobe bus, and the clock signal pair CKT / CKC may be a data strobe signal pair.

[0047] The first semiconductor device 510 may include a clock transmitter 511, a clock receiver 512, a data transmitter 513, and a data receiver 514. The clock transmitter 511 may generate a clock signal pair CKT / CKC based on an internal clock signal INCK1 of the first semiconductor device 510, and transmit the clock signal pair CKT / CKC to the second semiconductor device 520 through the clock bus 501. The clock receiver 512 may receive the clock signal pair CKT / CKC transmitted from the second semiconductor device 520 through the clock bus 501, and generate an internal clock signal INCK1 of the first semiconductor device 510. Figure 3 and Figure 4 Any one of the receiver circuits 200 and 300 respectively shown in Figure 5 may be used as the clock receiver 512. The data transmitter 513 may generate data DQ according to the internal data IND1 of the first semiconductor device 510, and transmit the data DQ to the second semiconductor device 520 through the data bus 502. The data transmitter 513 may receive the internal clock signal INCK1 and transmit the data DQ by synchronizing the internal data IND1 with the internal clock signal INCK1. The data receiver 514 may receive the data DQ transmitted from the second semiconductor device 520 through the data bus 502, and generate the internal data IND1 of the first semiconductor device 510. The data receiver 514 may receive the internal clock signal INCK1 and receive the data DQ in synchronization with the internal clock signal INCK1, thereby generating the internal data IND1.

[0048] The second semiconductor device 520 may include a clock transmitter 521, a clock receiver 522, a data transmitter 523, and a data receiver 524. The clock transmitter 521 may generate a clock signal pair CKT / CKC based on an internal clock signal INCK2 of the second semiconductor device 520, and transmit the clock signal pair CKT / CKC to the first semiconductor device 510 through the clock bus 501. The clock receiver 522 may receive the clock signal pair CKT / CKC transmitted from the first semiconductor device 510 through the clock bus 501, and generate an internal clock signal INCK2 of the second semiconductor device 520. Figure 3 and Figure 4 Any one of the receiver circuits 200 and 300 respectively shown in Figure 5 may be used as the clock receiver 522. The data transmitter 523 may generate data DQ according to the internal data IND2 of the second semiconductor device 520, and transmit the data DQ to the first semiconductor device 510 through the data bus 502. The data transmitter 523 may receive the internal clock signal INCK2 and transmit the data DQ by synchronizing the internal data IND2 with the internal clock signal INCK2. The data receiver 524 may receive the data DQ transmitted from the first semiconductor device 510 through the data bus 502, and generate the internal data IND2 of the second semiconductor device 520. The data receiver 524 may receive the internal clock signal INCK2 and receive the data DQ in synchronization with the internal clock signal INCK2, thereby generating the internal data IND2.

[0049] Those skilled in the art to which the present disclosure belongs will understand that the present disclosure can be implemented in other specific forms without changing its technical spirit or basic features. Therefore, it should be understood that the above-mentioned embodiments are exemplary in all aspects and not restrictive. The scope of the present disclosure is defined by the attached claims rather than the detailed description, and it should be understood that all changes or modifications obtained according to the meaning and scope of the claims and their equivalent concepts are included in the scope of the present disclosure.

Claims

1. A receiver circuit comprising: a first amplifier stage that generates a first output signal by differentially amplifying a first input signal and a second input signal when a first enable signal is enabled; a second amplifier stage, generating a second output signal by amplifying the first output signal when a second enable signal is enabled; as well as The enable control circuit generates the first enable signal and the second enable signal based on the amplified enable signal, and disables the first enable signal after disabling the second enable signal.

2. The receiver circuit according to claim 1, wherein: The enable control circuit enables the second enable signal after enabling the first enable signal.

3. The receiver circuit according to claim 1, wherein: The second input signal is a complementary signal of the first input signal.

4. The receiver circuit according to claim 1, wherein: The first amplifier stage comprises: a first amplifier that outputs an intermediate output signal pair by differentially amplifying the first input signal and the second input signal when the first enable signal is enabled; and A third amplifier generates the first output signal by differentially amplifying the intermediate output signal pair when the first enable signal is enabled.

5. The receiver circuit of claim 4, further comprising: The first precharge circuit precharges the first output signal to a voltage level of a first voltage based on the first enable signal.

6. The receiver circuit of claim 5, further comprising: The discharge circuit discharges the second output signal to a voltage level of a second voltage based on the second enable signal.

7. The receiver circuit of claim 1 , further comprising: The third amplifier stage generates a third output signal by amplifying the second output signal when a third enable signal is enabled.

8. The receiver circuit of claim 7, wherein: The enable control circuit further generates the third enable signal based on the amplified enable signal, enables the third enable signal after enabling the second enable signal, and disables the second enable signal after disabling the third enable signal.

9. The receiver circuit of claim 7, further comprising: The second precharge circuit precharges the third output signal to a voltage level of the first voltage based on the third enable signal.

10. A receiver circuit comprising: a first amplifier stage for generating a first output signal by amplifying an input signal pair; a second amplifier stage, generating a second output signal by amplifying the first output signal; a third amplifier stage, generating a third output signal by amplifying the second output signal; as well as The enable control circuit sequentially activates the first amplifier stage, the second amplifier stage, and the third amplifier stage, and sequentially deactivates the third amplifier stage, the second amplifier stage, and the first amplifier stage in a reverse order to the order in which the first to third amplifier stages are activated.

11. The receiver circuit of claim 10, wherein: The enable control circuit generates a first enable signal, a second enable signal, and a third enable signal based on the amplified enable signal, enables the first enable signal, the second enable signal, and the third enable signal in sequence, and disables the third enable signal, the second enable signal, and the first enable signal in sequence in the reverse order of the order in which the first enable signal to the third enable signal are enabled.

12. The receiver circuit of claim 11, wherein: The first amplifier stage generates the first output signal by differentially amplifying the input signal pair when the first enable signal is enabled.

13. The receiver circuit of claim 11, wherein: The second amplification stage generates the second output signal by amplifying the first output signal when the second enable signal is enabled.

14. The receiver circuit of claim 11, wherein: The third amplification stage generates the third output signal by amplifying the second output signal when the third enable signal is enabled.

15. The receiver circuit of claim 11, further comprising: The first precharge circuit precharges the first output signal to a voltage level of a first voltage based on the first enable signal.

16. The receiver circuit of claim 11, further comprising: The discharge circuit discharges the second output signal to a voltage level of a second voltage based on the second enable signal.

17. The receiver circuit of claim 11, further comprising: The second precharge circuit precharges the third output signal to a voltage level of the first voltage based on the third enable signal.

18. The receiver circuit of claim 11, wherein: The enabling control circuit comprises: a delay circuit, generating a first delayed signal and a second delayed signal by sequentially delaying the amplification enable signal; a first gating circuit that enables the first enable signal when the amplification enable signal is enabled, and disables the first enable signal when the second delay signal is disabled; a second gating circuit, providing the first delayed signal as the second enable signal; and The third gating circuit enables the third enable signal when the second delay signal is enabled, and disables the third enable signal when the amplification enable signal is disabled.

19. A semiconductor integrated circuit comprising: an enable control circuit that generates a plurality of enable signals and sequentially disables the plurality of enable signals; as well as A plurality of amplifier stages are connected in series and respectively receive the plurality of enable signals and are sequentially disabled based on the plurality of enable signals.

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