Semiconductor device and preparation method thereof, and storage system

Abstract

The invention provides a semiconductor device, a preparation method and a storage system, and the method comprises the steps: forming a first dielectric stacking structure, forming a first step structure in the first dielectric stacking structure, and forming a first contact hole which penetrates through the first step structure in the stacking direction; a second dielectric stack structure is formed on the first dielectric stack structure, a second step structure is formed in the second dielectric stack structure, a second contact hole is formed, and the second contact hole penetrates through the first step structure in the stacking direction and extends to the first contact hole to form a contact hole.

Description

Technical Field

[0001] The present application relates to the field of semiconductor design and manufacturing, and more specifically, to a semiconductor device, a method for preparing a semiconductor device, and a storage system. Background Art

[0002] In the semiconductor field, in order to overcome the limitations of two-dimensional semiconductor devices, the industry has developed and mass-produced semiconductor devices with three-dimensional structures. Three-dimensional semiconductor devices can improve integration density by arranging, for example, memory cells in three dimensions. Three-dimensional semiconductor devices such as 3D NAND flash memory may include a storage array area and a step area, wherein the storage array area is used to form a plurality of storage strings, each storage string may include a plurality of storage cells; the step area is used to lead out a contact structure from each layer of word lines connected to the storage cell, and is connected to a controller through the contact structure, so that the storage cell can be controlled to perform operations such as programming, reading, and erasing.

[0003] However, as the number of stacked layers in semiconductor devices continues to increase, the number of contact structures further increases, and the spacing between adjacent contact structures continues to decrease, which not only increases the difficulty of the manufacturing process, but also increases the risk of short circuits between adjacent contact structures. Summary of the invention

[0004] The present application provides a semiconductor device, a manufacturing method and a storage system that can at least partially solve the above-mentioned problems existing in the related art or other problems in the art.

[0005] On the one hand, the present application provides a method for preparing a semiconductor device, the method comprising: forming a first dielectric stacking structure, forming a first step structure in the first dielectric stacking structure, and forming a first contact hole penetrating the first step structure along a stacking direction; and forming a second dielectric stacking structure on the first dielectric stacking structure, forming a second step structure in the second dielectric stacking structure, and forming a second contact hole, wherein the second contact hole penetrates the first step structure along the stacking direction and extends to the first contact hole to form a contact hole.

[0006] In one embodiment of the present application, a radial dimension of the second contact hole close to the bottom of the first contact hole is greater than a radial dimension of the first contact hole close to the top of the second contact hole.

[0007] In one embodiment of the present application, forming a first dielectric stacking structure includes alternately stacking a first dielectric layer and a second dielectric layer along the stacking direction; and forming a second dielectric stacking structure on the first dielectric stacking structure includes alternately stacking a third dielectric layer and a fourth dielectric layer along the stacking direction on the first dielectric stacking structure, wherein after forming the contact hole, the method further includes: filling the contact hole with a first dielectric filling material layer to form a virtual channel structure; and removing the second dielectric layer and the fourth dielectric layer to form a sacrificial gap, and forming a gate conductor layer in the sacrificial gap.

[0008] In one embodiment of the present application, the method also includes forming a channel hole to accommodate the channel structure, the channel hole includes a first channel hole and a second channel hole connected to each other along the stacking direction, and the formation of the channel hole includes: in the process of forming the first contact hole, forming a first channel hole extending in the first dielectric stacking structure along the stacking direction.

[0009] In one embodiment of the present application, forming the channel hole further comprises: in the process of forming the second contact hole, forming a second channel hole extending along the stacking direction in the second dielectric stack structure and extending to the first channel hole.

[0010] In one embodiment of the present application, the first contact hole and the first channel hole are formed by using the same mask; and / or the second contact hole and the second channel hole are formed by using the same mask.

[0011] In one embodiment of the present application, after forming the gate conductor layer, the method also includes forming a contact structure connected to the corresponding gate conductor layer, and forming the contact structure includes: removing the first dielectric filling material layer to expose the contact hole; and expanding the aperture of the contact hole so that the radial dimension of the first part of the contact hole is larger than the radial dimension of the second part of the contact hole, wherein the first part is the part of the contact hole extending from top to bottom along the stacking direction to the corresponding gate conductor layer; and the second part is different from the first part.

[0012] In one embodiment of the present application, after expanding the aperture of the contact hole, the method for forming the contact structure further includes: forming a first electrical connection portion of the contact structure in the first portion, and forming a second electrical connection portion of the contact structure in the second portion, wherein the first electrical connection portion extends to the corresponding portion of the upper surface of the gate conductor layer and extends in a plane perpendicular to the stacking direction, and contacts the upper surface.

[0013] On the other hand, the present application provides a semiconductor device, which includes: a stacked structure, including a first stacked structure and at least one second stacked structure arranged on the first stacked structure, wherein the stacked structure defines a storage area and a step area in a plane perpendicular to the stacking direction; a channel structure, which runs through the storage area and includes a first channel structure located in the first stacked structure and a second channel structure located in the second stacked structure, wherein the first channel structure has a first upper end close to the second channel structure, and the second channel structure has a second upper end away from the first channel structure; and a contact structure, which runs through the step area and is connected to the corresponding gate conductor layer in the stacked structure, wherein the contact structure includes a second contact structure connected to the gate conductor layer of the second stacked structure, and the second contact structure includes a first sub-portion located in the first stacked structure and a second sub-portion located in the second stacked structure, wherein a first top end of the first sub-portion close to the second sub-portion is flush with a first top end of the first channel structure; and / or a second top end of the second sub-portion away from the first sub-portion is flush with a second top end of the second channel structure.

[0014] In one embodiment of the present application, the contact structure also includes a first contact structure connected to the gate conductor layer of the first stacked structure, wherein the first contact structure includes a third top end and a third bottom end opposite to each other in the stacking direction, and the third top end, the second top end of the second sub-portion, and the second upper end of the second channel structure are flush.

[0015] In one embodiment of the present application, the first sub-portion has a first bottom end away from the second sub-portion, wherein the first lower end of the first channel structure away from the second channel structure, the first bottom end of the first sub-portion and the third bottom end of the first contact structure are flush.

[0016] In one embodiment of the present application, the step region includes a plurality of step steps and a covering dielectric layer covering the plurality of step steps; and the contact structure includes a first electrical connection portion and a second electrical connection portion, the first electrical connection portion penetrates the covering dielectric layer along the stacking direction, extends to the upper surface of the corresponding gate conductor layer, and is connected to the upper surface, and the second electrical connection portion is connected to the first electrical connection portion and penetrates the step steps along the stacking direction.

[0017] In one embodiment of the present application, the semiconductor device further includes a peripheral circuit, wherein the corresponding gate conductor layer is electrically connected to the peripheral circuit through the first electrical connection portion or the second electrical connection portion of the contact structure.

[0018] In one embodiment of the present application, the peripheral circuit includes a first peripheral circuit and a second peripheral circuit arranged opposite to each other along the stacking direction; the corresponding gate conductor layer is electrically connected to the first peripheral circuit through the first electrical connection portion, or is electrically connected to the second peripheral circuit through the second electrical connection portion.

[0019] In one embodiment of the present application, each of the storage areas corresponds to at least one step area, and at least one step area is located in the middle of the corresponding storage area to divide the corresponding storage area into at least two sub-storage areas.

[0020] In one embodiment of the present application, each of the storage areas corresponds to at least one step area, and at least one step area is located at an edge of the corresponding storage area.

[0021] In one embodiment of the present application, the contact structure includes a conductive core layer, an adhesive layer and a barrier layer in order from the inside to the outside, wherein the barrier layer includes a first layer and a second layer spaced apart in the stacking direction.

[0022] In one embodiment of the present application, a radial dimension of the first top end of the first sub-section is smaller than a radial dimension of the second bottom end of the second sub-section, wherein the second bottom end and the second top end of the second sub-section are opposite to each other in the stacking direction.

[0023] In one embodiment of the present application, a radial dimension of the first top end of the first sub-section is greater than a radial dimension of the first bottom end of the first sub-section, wherein the first bottom end and the first top end of the first sub-section are opposite to each other in the stacking direction.

[0024] In one embodiment of the present application, a radial dimension of the second lower end of the second channel structure close to the first channel structure is smaller than a radial dimension of the first upper end of the first channel structure.

[0025] Another aspect of the present application provides a storage system, which includes: a controller and a semiconductor device as described in any one of the other aspects of the present application, wherein the controller is coupled to the semiconductor device and is used to control the semiconductor device to store data.

[0026] In one embodiment of the present application, the semiconductor device includes at least one of a three-dimensional NAND memory and a three-dimensional NOR memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Other features, purposes and advantages of the present application will become more apparent by reading the detailed description of non-limiting embodiments made with reference to the following drawings. In the drawings:

[0028] Figure 1is a flow chart of a method for preparing a semiconductor device according to one embodiment of the present application;

[0029] FIG. 2A to FIG. 6B They are respectively process schematic diagrams of a method for preparing a semiconductor device according to an embodiment of the present application;

[0030] Figure 6C yes Figure 6B A schematic enlarged cross-sectional view of the intermediate structure at A after forming a dummy channel structure is shown;

[0031] FIG. 7A to FIG. 7B They are respectively process schematic diagrams of a method for preparing a semiconductor device according to an embodiment of the present application;

[0032] Figure 7C yes Figure 7B A schematic enlarged cross-sectional view of the intermediate structure at position B after the gate composite layer is formed is shown;

[0033] Fig. 8A is a schematic top view of a semiconductor device according to one embodiment of the present application;

[0034] Figure 8B is a cross-sectional schematic diagram of a semiconductor device according to one embodiment of the present application;

[0035] Figure 8C yes Figure 8B The semiconductor device is shown as an enlarged schematic cross-sectional view at position C, with only the contact hole remaining;

[0036] Fig.8D yes Figure 8B A schematic enlarged cross-sectional view of a semiconductor device at position C is shown; and

[0037] Fig. 9 It is a schematic diagram of the storage system structure according to one embodiment of the present application.

[0038] Specific method

[0039] The present application will be described in detail below in conjunction with the accompanying drawings. The exemplary embodiments mentioned herein are only used to explain the present application and are not used to limit the scope of the present application. Throughout the specification, the same reference numerals refer to the same elements.

[0040] In the drawings, the thickness, size and shape of the components have been slightly adjusted for ease of illustration. The drawings are for illustration only and are not drawn strictly to scale. As used herein, the terms "substantially," "approximately," and similar terms are used to indicate approximation, not degree, and are intended to account for the inherent deviations in measurements or calculations that would be recognized by one of ordinary skill in the art.

[0041] It should also be understood that the expression "and / or" includes any and all combinations of one or more of the associated listed items. Expressions such as "including", "including", "having", "having" and / or "having" are open rather than closed expressions in this specification, which indicate the presence of the stated features, elements and / or parts, but do not exclude the presence or addition of one or more other features, elements, parts and / or combinations thereof. In addition, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features rather than just the individual elements in the list. When describing embodiments of the present application, "may" is used to mean "one or more embodiments of the present application". And, the term "exemplary" is intended to refer to an example or illustration.

[0042] In addition, when the expressions “connected”, “covered” and / or “formed on” are used in the present application, it may indicate that the corresponding components are in direct contact or indirect contact, unless otherwise clearly defined or inferred from the context.

[0043] Unless otherwise specified, all words (including technical terms and scientific terms) used in this article have the same meaning as those commonly understood by ordinary technicians in the field to which this application belongs. In addition, unless clearly stated in this application, words defined in common dictionaries should be interpreted as having the same meaning as their meaning in the context of the relevant technology, and should not be interpreted in an idealized or overly formal sense.

[0044] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments in this application can be combined with each other. In addition, unless explicitly limited or contradictory to the context, the specific steps in the method described in this application are not necessarily limited to the order described, but can be performed in any order or in parallel. The application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0045] Figure 1 is a flow chart of a method 1000 for preparing a semiconductor device according to one embodiment of the present application. FIG. 2A to FIG. 8B They are respectively process schematic diagrams of a method 1000 for preparing a semiconductor device according to an embodiment of the present application.

[0046] like Figure 1 As shown, the method 1000 for preparing a semiconductor device may include:

[0047] S1, forming a first dielectric stacking structure, forming a first step structure in the first dielectric stacking structure, and forming a first contact hole penetrating the first step structure along a stacking direction.

[0048] S2, forming a second dielectric stacking structure on the first dielectric stacking structure, forming a second step structure in the second dielectric stacking structure, and forming a second contact hole, wherein the second contact hole penetrates the first step structure along the stacking direction and extends to the first contact hole to form a contact hole.

[0049] According to at least one embodiment of the present application, after forming each individual sub-stack structure, a corresponding sub-step structure and a sub-contact hole may be formed therein first, and then the remaining sub-stack structures may be formed on the individual sub-stack structure. Considering that the number of stacking layers of each individual sub-stack structure is limited, the method for preparing a semiconductor device provided by the present application can avoid the step of forming contact holes by a deep hole etching process after forming all the sub-stack structures, thereby simplifying the method for preparing a semiconductor device, reducing the preparation cost of the semiconductor device, and improving the reliability of the contact structure accommodated in the contact hole.

[0050] The following will be combined Figures 1 to 8B The specific process of each step of the above-mentioned preparation method 1000 in one embodiment of the present application is described in detail.

[0051] Step S1

[0052] Figure 2A It is a schematic top view of a structure formed after forming the first contact hole 411 according to an embodiment of the present application. Figure 2B It is a schematic cross-sectional view of a structure formed after forming the first contact hole 411 according to an embodiment of the present application.

[0053] like Figures 1 to 2B As shown, step S1 forms a first dielectric stacking structure, forms a first step structure in the first dielectric stacking structure, and forms a first contact hole that penetrates the first step structure along the stacking direction, which may, for example, include: providing a substrate 100'; alternately stacking a first dielectric layer 210 and a second dielectric layer 220 on the substrate 100' to form a first dielectric stacking structure 201'; forming a first step structure 021 in a step region 02 of the first dielectric stacking structure 201'; and forming a first contact hole 411 that penetrates the first step structure 021 along the stacking direction.

[0054] Specifically, in one embodiment of the present application, the substrate 100' can be made of any suitable semiconductor material, such as single crystal silicon (Si), single crystal germanium (Ge), silicon germanium (GeSi), silicon carbide (SiC), silicon on insulator (SOI), germanium on insulator (GOI) or III-V compounds such as gallium arsenide. Further, the substrate 100' can be made of single crystal silicon.

[0055] In one embodiment of the present application, the substrate 100' may be, for example, a composite substrate for supporting a device structure thereon. The substrate 100' may be formed by sequentially depositing a plurality of layers made of different materials through a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0056] In addition, the substrate 100' may also include a substrate sacrificial layer (not shown) for subsequently forming a semiconductor connection layer for connecting the channel structure. The substrate sacrificial layer may include a single layer, a multilayer or a suitable composite layer. For example, the substrate sacrificial layer may include any one or more of a silicon oxide layer, a silicon nitride layer and a silicon oxynitride layer. As an option, the substrate sacrificial layer may be a high dielectric constant dielectric layer. As another option, the substrate sacrificial layer may include a first dielectric layer (not shown), a sacrificial layer (not shown) and a second dielectric layer (not shown) arranged in sequence, wherein the first dielectric layer and the second dielectric layer may be silicon nitride layers, and the sacrificial layer may be a silicon oxide layer. Optionally, the sacrificial layer may also be single crystal silicon or polycrystalline silicon. Specifically, in one embodiment of the present application, an exemplary material for forming the sacrificial layer may be polycrystalline silicon. As another option, the substrate sacrificial layer may include any one or more of a dielectric material, a semiconductor material and a conductive material.

[0057] In addition, a part of the substrate 100' may also form a well region doped with an N-type or P-type dopant via an ion implantation or diffusion process. The dopant may include any one or a combination of phosphorus (P), arsenic (As) and antimony (Sb). In some embodiments of the present application, the well region may be prepared with the same dopant or with different dopants. Furthermore, the doping concentration of the well region may be the same or different, which is not limited in the present application.

[0058] The substrate 100' may include a first surface and a second surface opposite to each other. After forming the substrate 100', the first dielectric layer 210 and the second dielectric layer 220 may be alternately stacked on the first surface along the stacking direction (z direction) by one or more thin film deposition processes to form a first dielectric stack structure 201', wherein the thin film deposition process may include but is not limited to CVD, PVD, ALD or any combination thereof or any combination thereof, which is not limited in the present application.

[0059] The substrate 100' may define at least one preset storage region and at least one preset step region adjacent to each other in a plane (xy plane) perpendicular to the stacking direction. The first dielectric stack structure 201' defines a storage region 01 opposite to the preset storage region and a step region 02 opposite to the preset step region in the xy plane.

[0060] The first dielectric stack structure 201' may include a plurality of pairs of first dielectric layers 210 and second dielectric layers 220. For example, the first dielectric stack structure 201' may include 64 pairs, 128 pairs, or more than 128 pairs of first dielectric layers 210 and second dielectric layers 220.

[0061] In other words, the first dielectric stack structure 201' may include a plurality of dielectric layer pairs formed by a first dielectric layer 210 and a second dielectric layer 220 stacked in the z direction. In some embodiments, the first dielectric layer 210 and the second dielectric layer 220 may include a first dielectric material and a second dielectric material different from the first dielectric material, respectively. Exemplary materials for forming the first dielectric layer 210 and the second dielectric layer 220 may include silicon oxide and silicon nitride, respectively. The silicon oxide layer may be used as an isolation stack layer, and the silicon nitride layer may be used as a sacrificial stack layer. The sacrificial stack layer may then be removed and replaced with a gate layer including a conductive material.

[0062] After forming the first dielectric stacking structure 201', a first step structure 021 including a plurality of stair steps may be formed in the step region 02 of the first dielectric stacking structure 201'. This may be achieved by performing a plurality of "trim-etch" cycles on, for example, the first dielectric stacking structure 201'. By performing a plurality of "trim-etch" cycles, the first dielectric stacking structure 201' may have one or more inclined edges and a top (away from the substrate 100') dielectric layer pair that is shorter than a bottom (close to the substrate 100') dielectric layer pair. Any suitable etching process (including any one or combination of a dry etching process and a wet etching process) may be used in the stair step formation process, and the present application does not limit this.

[0063] After forming the first step structure 021, a first contact hole 411 may be formed in the step region 02 by, for example, a dry etching process or a combination of dry and wet etching processes; other manufacturing processes, such as a patterning process including photolithography, cleaning, and chemical mechanical polishing, may also be performed. The first contact hole 411 has a cylindrical or columnar shape (e.g., Figure 2B shown).

[0064] Optionally, before forming the first contact hole 411, a first cover layer 022 may be formed on a side of the first dielectric stack structure 201' away from the substrate 100' by one or more thin film deposition processes, and the first cover layer 022 at least covers the first step structure 021, wherein the thin film deposition process may include but is not limited to CVD, PVD, ALD or any combination thereof, or any combination thereof, which is not limited in the present application. In addition, a planarization process such as chemical mechanical polishing may be performed to provide the first cover layer 022 with a relatively flat surface. After forming the first cover layer 022, a first contact hole 411 may be formed that penetrates the first cover layer 022, the first dielectric stack structure 201', and extends to the substrate 100' along the z direction.

[0065] In addition, in one embodiment of the present application, in order to simplify the manufacturing process of the semiconductor device and save production costs, a first channel hole 311 extending along the z direction in the first dielectric stack structure 201' can be formed in the process of forming the first contact hole 411. The first channel hole 311 has a cylindrical or columnar shape (e.g. Figure 2B shown).

[0066] As an option, the same mask plate may be used and the first contact hole 411 and the first channel hole 311 may be formed in the same process. For example, a photoresist mask layer (not shown) is formed on the surface of the first cover layer 022; a first contact hole pattern (not shown) and a first channel hole pattern (not shown) are formed in the photoresist mask layer through the same mask plate; the first dielectric stack structure 201' is etched through the first contact hole pattern and the first channel hole pattern to form the first contact hole 411 and the first channel hole 311 respectively. The above etching process may include a dry etching process or a combination of dry and wet etching processes; and may also include other manufacturing processes, such as cleaning and chemical mechanical polishing.

[0067] Optionally, the first channel hole 311 and the first contact hole 411 may have the same depth in the z direction. It should be noted that the number and position of the first channel holes and the first contact holes in the drawings are only examples given for illustration and are not intended to limit actual situations.

[0068] Figure 3A It is a schematic top view of a structure formed after forming a sacrificial filling material layer 431 according to an embodiment of the present application. Figure 3B It is a schematic cross-sectional view of a structure formed after forming a sacrificial filling material layer 431 according to an embodiment of the present application.

[0069] like Figure 3A and 3BAs shown, before executing step S2 , the method 1000 for preparing a semiconductor device may further include filling the first contact hole 411 with a sacrificial filling material layer 431 .

[0070] Specifically, a sacrificial filling material layer 431 may be formed in the first channel hole 311 and the first contact hole 411 by a thin film deposition process such as CVD, PVD, ALD or any combination thereof. The sacrificial filling material layer 431 may be formed of a material having a high deposition rate to facilitate rapid filling of the first channel hole 311 and the first contact hole 411, and the sacrificial filling layer 431 should be any material having a high dry etching selectivity relative to the first dielectric layer 210 and the second dielectric layer 220 to facilitate removal in subsequent steps.

[0071] In one embodiment of the present application, the sacrificial filling layer 431 may include an oxide dielectric layer, and may also be a semiconductor layer, such as a polysilicon layer, etc. In addition, during the filling process, a plurality of gaps may be formed in the sacrificial filling layer 431 by controlling the channel filling process to relieve structural stress, so as to facilitate the subsequent formation of a second dielectric stack structure on the first dielectric stack structure 201 ′ having the first channel hole 311 and the first contact hole 411.

[0072] In addition, after forming the sacrificial filling layer 431, a planarization process may be performed on the sacrificial filling layer 431. For example, a planarization process such as a chemical mechanical polishing process with a low grinding rate may be performed on the exposed surface of the sacrificial filling layer 431. The planarization process can more easily make the sacrificial filling layer 431 flush with the surface of the first cover layer 022, thereby facilitating the formation of the dielectric spacer 432 on the flush surface.

[0073] Optionally, a dielectric spacer 432 is formed on the above-mentioned flush surface by a thin film deposition process such as CVD, PVD, ALD or any combination thereof. The dielectric spacer 432 may include a dielectric material, such as oxide.

[0074] Step S2

[0075] Figure 4A It is a schematic top view of a structure formed after forming a second dielectric stack structure 202 ′ according to an embodiment of the present application. Figure 4B It is a schematic cross-sectional view of a structure formed after forming a second dielectric stack structure 202 ′ according to an embodiment of the present application. Figure 5A It is a schematic top view of a structure formed after forming the second contact hole 412 according to an embodiment of the present application. Figure 5B It is a schematic cross-sectional view of a structure formed after forming the second contact hole 412 according to an embodiment of the present application.

[0076] like FIG. 2A to FIG. 5B As shown, step S2 forms a second dielectric stacking structure on the first dielectric stacking structure, forms a second step structure in the second dielectric stacking structure, and forms a second contact hole, wherein the second contact hole penetrates the first step structure along the stacking direction and extends to the first contact hole. The contact hole formed may, for example, include: forming a second dielectric stacking structure 202'; forming a second step structure 023 in the step area 02 of the second dielectric stacking structure 202'; and forming a second contact hole 412 penetrating the second step structure 023 along the z direction.

[0077] Specifically, refer to Figures 2A to 4B In one embodiment of the present application, the third dielectric layer 230 and the fourth dielectric layer 240 can be alternately stacked along the z direction on the surface of the dielectric spacer layer 432 by one or more thin film deposition processes to form a second dielectric stack structure 202', wherein the thin film deposition process may include but is not limited to CVD, PVD, ALD or any combination thereof, and the present application is not limited to this.

[0078] In some embodiments, the third dielectric layer 230 and the fourth dielectric layer 240 may include a third dielectric material and a fourth dielectric material different from the third dielectric material, respectively. In other embodiments, the third dielectric layer 230 may be made of the same material as the first dielectric layer 210; the fourth dielectric layer 240 may be made of the same material as the second dielectric layer 220. Exemplary materials for forming the first dielectric layer 210 and the third dielectric layer 230 may include silicon oxide, and exemplary materials for forming the second dielectric layer 220 and the fourth dielectric layer 240 may include silicon nitride. The silicon oxide layer may be used as an isolation stack layer, and the silicon nitride layer may be used as a sacrificial stack layer. The sacrificial stack layer may then be removed and replaced with a gate layer including a conductive material.

[0079] In the xy plane, the second dielectric stacking structure 202' includes a storage region opposite to the storage region 01 and a step region opposite to the step region 02. After the second dielectric stacking structure 202' is formed, the "trim-etch" process described above can be used to form a second step structure 023 including a plurality of step steps in the step region of the second dielectric stacking structure 202', which is not described in detail in this application.

[0080] like FIG. 4A to FIG. 5BAs shown, after forming the second step structure 023, a second contact hole 412 may be formed in the step region of the second dielectric stack structure 202' by, for example, a dry etching process or a combination of dry and wet etching processes; other manufacturing processes, such as a patterning process including photolithography, cleaning, and chemical mechanical polishing, may also be performed. The second contact hole 412 has a cylindrical or columnar shape (such as a cylindrical shape) that passes through the second dielectric stack structure 202'. Figure 5B shown).

[0081] Optionally, the process of forming the “first contact hole 411 ” described above may be used to form the second cover layer 024 and the second contact hole 412 , which will not be described in detail in this application. The second contact hole 412 penetrates the second step structure 023 along the z direction and extends to the first contact hole 411 .

[0082] refer to Figure 3B and Figure 5B After forming the second contact hole 412, the sacrificial filling material layer 431 in the first contact hole 411 can be removed through the second contact hole 412, and the first contact hole 411 and the second contact hole 412 are connected to form the contact hole 410. Optionally, the sacrificial filling material layer 431 can be removed by an etching process, and the etching process can include a dry etching process or a combination of dry and wet etching processes; it can also include other manufacturing processes, such as cleaning and chemical mechanical polishing.

[0083] Optionally, refer to Figure 5B , the radial dimension D2 of the second contact hole 412 near the bottom of the first contact hole 411 is larger than the radial dimension D1 of the first contact hole 411 near the top of the second contact hole 412. By making the aperture size of the second contact hole at the top larger than the aperture size of the first contact hole at the bottom, the process window for forming a contact structure in the contact hole can be effectively increased, and the stability of the contact structure can be improved.

[0084] In addition, refer again Figure 5B Due to the limitation of the deep hole etching process, the first contact hole 411 and the second contact hole 412 often have a tapered groove morphology with a larger top and a smaller bottom. Therefore, the bottom aperture size of the first contact hole 411 away from the second contact hole 412 is the minimum aperture size of the contact hole 410, and the top aperture size of the second contact hole 412 away from the first contact hole 411 is the maximum aperture size of the contact hole 410. In order to improve the conductivity and stability of the contact structure subsequently formed in the contact hole, the minimum aperture size of the contact hole can be limited to 120nm-180nm. In addition, the contact structure formed in the contact hole needs to be set on the corresponding step step. Considering the limited surface width of the step step, the maximum aperture size of the contact hole can be limited to 250nm-350nm.

[0085] In addition, in one embodiment of the present application, in order to simplify the manufacturing process of the semiconductor device and save production costs, a second channel hole 312 extending in the second dielectric stack structure 202' along the z direction may be formed in the process of forming the second contact hole 412. Optionally, the second channel hole 312 has a cylindrical or columnar shape that penetrates the second dielectric stack structure 202' along the z direction and extends to the first channel hole 311.

[0086] For example, the same mask plate may be used to form the second contact hole 412 and the second channel hole 312 in the same process. For example, the second contact hole 412 and the second channel hole 312 are formed by the process of "using the same mask plate to form the first contact hole 411 and the first channel hole 311" described above, which is not described in detail in this application.

[0087] In addition, the radial dimension D4 of the second channel hole 312 near the bottom of the first channel hole 311 is smaller than the radial dimension D3 of the first channel hole 311 near the top of the second channel hole 312. By setting the diameter of the hole at the bottom of the second channel hole to be smaller than the diameter of the top of the first channel hole, the interval between adjacent channel structures in the subsequently formed channel structure can be effectively reduced, the storage density per unit area of ​​the semiconductor device can be greatly improved, and the price of the unit storage unit can be reduced.

[0088] In addition, as an option, in order to simplify the manufacturing process of the semiconductor device, the sacrificial filling material layer 431 formed in the first channel hole 311 can be removed in the process of removing the sacrificial filling material layer 431 formed in the first contact hole 411. The second channel hole 312 and the first channel hole 311 are connected to form a channel hole 310, and the channel hole 310 is used to accommodate the channel structure formed in the subsequent steps.

[0089] After removing the sacrificial filling material layer 431 formed in the first contact hole 411 and the sacrificial filling material layer 431 formed in the first channel hole 311 in the same process, the channel hole 310 and the contact hole 410 can be separately covered in different subsequent steps to form a channel structure and a virtual channel structure, respectively.

[0090] As another option, the sacrificial filling material layer 431 formed in the first channel hole 311 and the sacrificial filling material layer 431 formed in the first contact hole 411 may be removed separately in different processes as needed.

[0091] For example, a shielding layer (not shown) may be formed on the top surface of the second dielectric stack structure 202' away from the substrate 100', and the sacrificial filling material layer 431 formed in the first channel hole 311 may be covered by the shielding layer, and the sacrificial filling material layer 431 formed in the first contact hole 411 that is not covered by the shielding layer may be removed. Afterwards, in a subsequent step, a dummy channel structure may be formed in the contact hole 410 after the sacrificial filling material layer 431 is removed; after the dummy channel structure is formed, the shielding layer and the sacrificial filling material layer 431 under the shielding layer may be removed to form a channel structure in the channel hole 310 after the sacrificial filling material layer 431 is removed.

[0092] Alternatively, a shielding layer (not shown) may be formed on the top surface of the second dielectric stack structure 202' away from the substrate 100', and the shielding layer may be used to cover the sacrificial filling material layer 431 formed in the first contact hole 411, and the sacrificial filling material layer 431 not covered by the shielding layer and formed in the first channel hole 311 is removed. Afterwards, in a subsequent step, a channel structure may be formed in the channel hole 310 after the sacrificial filling material layer 431 is removed; after the channel structure is formed, the shielding layer and the sacrificial filling material layer 431 under the shielding layer are removed to form a dummy channel structure in the contact hole 410 after the sacrificial filling material layer 431 is removed.

[0093] In addition, the preparation method of the upper and lower sub-dielectric stacking structures (the first dielectric stacking structure and the second dielectric stacking structure) is described above. In fact, with the continuous increase in the storage demand of semiconductor devices, the storage stack gradually increases. In order to break through the limitations of process limits, multi-stack technology can also be used to form a dielectric stacking structure by stacking a plurality of sub-dielectric stacking structures stacked in sequence in the stacking direction. Among them, each sub-dielectric stacking structure can include a plurality of stacked dielectric layer pairs. The number of layers of each sub-dielectric stacking structure may be the same or different. Since the content, structure and technical effects involved in the preparation process of the two sub-dielectric stacking structures described above can be fully or partially applied to the dielectric stacking structure formed by a plurality of sub-dielectric stacking structures described here, the content related or similar thereto will not be repeated. However, it can be understood by those skilled in the art that subsequent preparation processes can be carried out on the basis of a plurality of sub-dielectric stacking structures or two sub-dielectric stacking structures.

[0094] In other words, the above steps can be repeated according to the actual needs of the semiconductor device to form a dielectric stack structure including multiple sub-dielectric stack structures, and corresponding sub-step structures and sub-contact holes can be formed in the multiple sub-dielectric stack structures respectively. After each individual sub-stack structure is formed, a corresponding sub-step structure and sub-contact hole can be formed therein first, and then the remaining sub-stack structures are formed on the individual sub-stack structure. Considering that the number of stacking layers of each individual sub-stack structure is limited, the method for preparing a semiconductor device provided in at least one embodiment of the present application can avoid the step of forming contact holes by a deep hole etching process after forming all the sub-stack structures, thereby simplifying the method for preparing the semiconductor device, reducing the preparation cost of the semiconductor device, and improving the reliability of the contact structure.

[0095] Fig. 6A It is a schematic top view of a structure formed after forming a dummy channel structure according to an embodiment of the present application. Figure 6B It is a schematic cross-sectional view of a structure formed after forming a dummy channel structure according to an embodiment of the present application. Figure 6C yes Figure 6B The cross-sectional schematic enlarged view of the intermediate structure at A after the dummy channel structure is formed is shown. Fig. 7A It is a schematic top view of a structure formed after forming a gate conductor layer according to one embodiment of the present application.

[0096] Figure 7B It is a schematic cross-sectional view of a structure formed after forming a gate conductor layer according to one embodiment of the present application. Figure 7C yes Figure 7B The cross-sectional schematic enlarged view of the intermediate structure at B after the gate composite layer 250 is formed is shown.

[0097] like Figures 5A to 7C As shown, after forming the channel hole 310 and the contact hole 410 , the method 1000 for preparing a semiconductor device may further include forming a channel structure 300 , a dummy channel structure and a gate conductor layer.

[0098] Specifically, the dummy channel structure may be formed before the channel structure 300 is formed; or the dummy channel structure may be formed after the channel structure 300 is formed. Figures 5A to 6C Taking the example of forming the channel structure 300 first and then forming the dummy channel structure, the specific process of each step of forming the channel structure 300 and the dummy channel structure in one embodiment of the present application is described in detail. However, those skilled in the art should understand that the present application does not limit this.

[0099] As described above, in order to simplify the preparation process of semiconductor devices and save production costs, the same mask can be used to form the channel hole 310 and the contact hole 410 in the same process. Therefore, in the process of forming the channel structure 300, the formed contact hole 410 needs to be shielded.

[0100] Forming the channel structure 300 includes sequentially forming a functional layer 320 and a channel layer 330 on the inner wall of the channel hole 310 by one or more thin film deposition processes such as CVD, PVD, ALD or any combination thereof.

[0101] Specifically, the functional layer 320 may include a blocking layer (not shown) formed on the inner wall of the channel hole 310 to block the outflow of charges; a charge capture layer (not shown) formed on the surface of the blocking layer to store charges during the operation of the three-dimensional memory; and a tunneling layer (not shown) formed on the surface of the charge capture layer.

[0102] In some embodiments, the functional layer 320 may include an oxide-nitride-oxide (ONO) structure. However, in some other embodiments, the functional layer 320 may also have a structure different from the ONO configuration. The channel layer 330 can be used to transport the required charges (electrons or holes). However, it should be understood by those skilled in the art that the channel structure 300 may be set according to different three-dimensional memory architectures without departing from the teachings of the present application, and the present application does not limit this.

[0103] For example, as an option, the functional layer 320 may be formed on the sidewall and bottom of the channel hole 310 , and the channel layer 330 may be formed on the surface of the tunnel layer in the functional layer 320 by a thin film deposition process such as CVD, PVD, ALD or any combination thereof.

[0104] As another option, the functional layer 320 may be formed only on the sidewalls of the channel hole 310, and the channel layer 330 may be formed on the surface of the tunneling layer of the functional layer 320 and, for example, on the surface of an epitaxial layer (not shown) subsequently formed on the bottom surface of the channel hole 310 by a thin film deposition process such as CVD, PVD, ALD or any combination thereof.

[0105] Specifically, an epitaxial layer may be formed at the bottom of the channel hole 310 by an epitaxial growth process, wherein the manufacturing process for epitaxially growing the epitaxial layer may include but is not limited to: vapor phase epitaxy (VPE), liquid phase epitaxy (LPE), molecular beam epitaxy (MPE) or any combination thereof. The epitaxial layer may be at least one of epitaxial silicon, silicon germanium, germanium, III-V compound materials, II-VI compound materials, organic semiconductor materials and other suitable semiconductor materials. After the epitaxial layer is formed, an initial functional layer (not shown) may be formed on the inner wall of the channel hole 310 and the surface of the epitaxial layer by a thin film deposition process such as CVD, PVD, ALD or any combination thereof, and then, for example, a dry etching process or a combination of dry and wet etching processes may be used; other manufacturing processes may also be performed, such as a patterning process including photolithography, cleaning and chemical mechanical polishing, etc., to remove the portion of the initial functional layer located on the surface of the epitaxial layer and expose a portion of the surface of the epitaxial layer. It can be understood that this embodiment forms the functional layer 320 only on the sidewall of the channel hole 310. After forming the functional layer 320 , a channel layer 330 connected to the epitaxial layer may be formed on the surface of the tunnel layer of the functional layer 320 and the exposed epitaxial layer surface by a thin film deposition process such as CVD, PVD, ALD or any combination thereof.

[0106] In some embodiments, the channel layer 330 may include silicon, such as polysilicon or monocrystalline silicon. The material of the channel layer 330 may include, but is not limited to, N-type doped polysilicon. Similar to the channel hole 310, the channel layer 330 may also have a cylindrical or columnar shape extending in the z direction. As an option, the channel layer 330 may also extend into the substrate 100' in the z direction.

[0107] In addition, the channel structure 300 also includes a channel plug (not shown) formed at one end of the channel hole 310 away from the substrate 100' (which can be understood as the top of the channel structure 300). Specifically, after the channel layer 330 is formed, a channel hole filling dielectric layer (not shown) can be used to fill the remaining portion of the channel hole 310. The channel hole filling dielectric layer may include an oxidized dielectric layer, such as silicon oxide, etc. Further, during the filling process, a plurality of insulating gaps can be formed in the channel hole filling dielectric layer by controlling the channel filling process to reduce structural stress. Then, a channel plug is formed in the portion of the channel hole filling dielectric layer located at the top of the channel hole 310. The material of the channel plug can be prepared from the same material as the channel layer 330, such as N-type doped polysilicon, etc. The channel plug is electrically connected to the channel layer 330.

[0108] Reference again FIG. 5A to FIG. 6BThe formation of the virtual channel structure includes: filling the contact hole 410 with a first dielectric filling material layer 433 through one or more thin film deposition processes such as CVD, PVD, ALD or any combination thereof to form a virtual channel structure. Optionally, the first dielectric filling material layer 433 may be a composite structure or a single-layer structure, which is not limited in the present application.

[0109] In the method for forming a semiconductor device, the second dielectric layer and the fourth dielectric layer can be removed through the gate line gap formed subsequently, and the gate composite layer is formed by the gate back process. However, after removing the second dielectric layer and the fourth dielectric layer, the dielectric stack structure formed by the plurality of sub-dielectric stack structures is prone to collapse, and a virtual channel structure is usually required to provide support for the dielectric stack structure. As semiconductor devices continue to develop towards high-density and high-layer numbers, the number of virtual channel structures is increasing, and the proportion of virtual channel structures in the effective storage area of ​​semiconductor devices is increasing. In addition, one or more virtual channel structures are usually arranged around the contact structure in the step area. In the process of preparing the semiconductor device, due to internal stress distribution and other reasons, the critical size of the gate line gap in the plane perpendicular to the stacking direction may be enlarged, thereby squeezing the virtual channel hole accommodating the virtual channel toward the direction of the contact hole accommodating the contact structure, resulting in the contact hole overlapping the virtual channel hole. This high overlap risk will cause leakage current problems, thereby affecting the electrical performance of the semiconductor device finally formed and degrading its reliability.

[0110] In the method for preparing a semiconductor device provided in at least one embodiment of the present application, a virtual channel hole and a virtual channel structure are not separately provided, but a first dielectric filling material layer is used to fill a pre-prepared contact hole to form a temporary virtual channel structure, so as to provide support for the dielectric stacking structure in the subsequent process of forming a gate composite layer. After forming the gate composite layer, the first dielectric filling material layer in the contact hole can also be removed to form a contact structure in the contact hole. Therefore, in the process of preparing the semiconductor device, while providing support for the dielectric stacking structure, the storage density per unit area of ​​the semiconductor device can be increased, and the electrical performance and reliability of the semiconductor device can be improved.

[0111] Optionally, the first dielectric filling material layer 433 may include a semiconductor material layer, such as a polysilicon material layer. The use of a semiconductor material layer to form a virtual channel structure can reduce the stress deformation of the dielectric stack structure caused by thermal effects in the subsequent preparation process of the semiconductor device. In addition, the first dielectric filling material layer 433 may be a single layer, a multilayer or a suitable composite layer. Optionally, during the filling process, a plurality of gaps can be formed in the virtual channel structure by controlling the channel filling process to reduce structural stress. It can be understood by those skilled in the art that the material, structure and preparation process of the virtual channel structure can be selected according to actual needs, and the present application does not limit the material and preparation process for forming the virtual channel structure.

[0112] In addition, a covering sacrificial layer 434 may be formed on the top surface of the second dielectric stack structure 202 ′ by one or more thin film deposition processes such as CVD, PVD, ALD or any combination thereof.

[0113] In addition, a planarization process may be performed on the covering sacrificial layer 434. For example, a planarization process such as a chemical mechanical polishing process with a low grinding rate may be performed on the surface of the covering sacrificial layer 434. The planarization process can more easily make the covering sacrificial layer 434 have a planarized surface, thereby facilitating the execution of the subsequent step of forming a contact structure.

[0114] Combination Fig. 6A , Figure 6B , FIG. 7A to FIG. 7C , forming a gate composite layer 250 including a gate conductor layer may, for example, include: forming a gate line gap 510; removing the second dielectric layer 220 and the fourth dielectric layer 240 through the gate line gap 510 to form a sacrificial gap (not shown); and forming a gate composite layer 250 including a gate conductor layer in the sacrificial gap.

[0115] In one embodiment of the present application, Fig. 6A and Fig. 7A As shown, the gate line gap 510 can be formed by, for example, a dry etching process or a combination of dry and wet etching processes; other manufacturing processes, such as a patterning process including photolithography, cleaning, and chemical mechanical polishing, can also be performed.

[0116] As an option, the gate line gap 510 may extend through the storage area 01 and the step area 02 in the x direction. As another option, the gate line gap 410 may also extend intermittently in the x direction. As another option, some of the gate line gaps 410 in the plurality of gate line gaps 410 may only extend through the storage area 01 in the x direction; some of the gate line gaps 410 in the plurality of gate line gaps 410 may also only extend through the step area 02 in the x direction.

[0117] like Figure 6B , FIG. 7A to FIG. 7C As shown, the gate line gap 510 can be used as a passage (process window) for providing an etchant and a chemical precursor, and the second dielectric layer 220 and the fourth dielectric layer 240 are removed by a process such as wet etching to form a sacrificial gap for accommodating the gate layer. In addition, the sacrificial gap can also be filled through the gate line gap 510 to form a gate composite layer 250.

[0118] Optionally, the gate composite layer 250 may include an inter-wall dielectric layer 251, an adhesive layer 252, and a gate metal layer 253, wherein the adhesive layer 252 and the gate metal layer 253 may be understood as gate conductor layers. The inter-wall dielectric layer 251 may be located between the first dielectric layer 210 (or the third dielectric layer 230) and the gate metal layer 253, and as an option, the inter-wall dielectric layer 251 may be a high dielectric constant dielectric layer. The adhesive layer 252 may be located between the first dielectric layer 210 and the gate metal layer 253, or between the inter-wall dielectric layer 251 and the gate metal layer 253, and the adhesive layer 252 may be, for example, a titanium nitride (TiN) layer.

[0119] An initial inter-wall dielectric layer (not shown), an initial adhesive layer (not shown) and an initial gate conductor layer (not shown) may be sequentially formed in the gate line gap 510 and the sacrificial gap by a thin film deposition process such as CVD, PVD, ALD or any combination thereof. Afterwards, by multiple times, for example, dry etching process or a combination of dry and wet etching processes; other manufacturing processes may also be performed, such as a patterning process including photolithography, cleaning and chemical mechanical polishing, etc., to sequentially remove the initial gate conductor layer, the initial adhesive layer and the initial inter-wall dielectric layer located in the gate line gap 510, thereby forming a gate composite layer 250.

[0120] refer to Figure 2B and Figure 7B After forming the gate composite layer 250 , the first dielectric stack structure 201 ′ and the second dielectric stack structure 202 ′ are formed into a stacked structure 200 .

[0121] Fig. 8A is a schematic top view of a semiconductor device 2000 according to an embodiment of the present application. Figure 8B is a schematic cross-sectional view of a semiconductor device 2000 according to an embodiment of the present application. Figure 8C yes Figure 8B The semiconductor device 2000 is shown as an enlarged schematic cross-sectional view at C, where only the contact hole 410 is retained. Fig.8D yes Figure 8B The illustrated schematic enlarged cross-sectional view of the semiconductor device 2000 at C is shown.

[0122] like 7A to 8DAs shown, after forming the channel structure 300 and the gate conductor layer, the method 1000 for manufacturing a semiconductor device may further include forming a gate line gap structure 500 and a contact structure 400 .

[0123] like 7A to 8A As shown, after forming the gate composite layer 250 , the gate line gap 510 may be filled by a thin film deposition process such as CVD, PVD, ALD or any combination thereof to form a gate line gap structure 500 .

[0124] Optionally, insulating dielectric materials such as silicon oxide, silicon nitride and silicon oxynitride may be used, and semiconductor materials such as polysilicon may be used to fill the gate line gap 510, which is not limited in the present application.

[0125] like 7A to 8D As shown, before forming the contact structure 400 , the method 1000 for preparing a semiconductor device may further include enlarging a hole size of a portion of the contact hole 410 .

[0126] Specifically, refer to Figure 7C and Figure 8C After forming the gate composite layer 250, the virtual channel structure formed above can be removed by removing the first dielectric filling material layer 433, and the contact hole 410 can be exposed. The first dielectric filling material layer 433 can be removed by, for example, a dry etching process or a combination of dry and wet etching processes; other manufacturing processes can also be performed, such as a patterning process including photolithography, cleaning, and chemical mechanical polishing.

[0127] After exposing the contact hole 410, the aperture of the contact hole 410 can be enlarged so that the radial dimension of the first portion 410-1 of the contact hole 410 is larger than the radial dimension of the second portion 410-2 of the contact hole 410, wherein the first portion 410-1 is the portion of the contact hole 410 extending from top to bottom along the z direction to the corresponding gate conductor layer; and the second portion 410-2 is the portion of the contact hole 410 that is different from the first portion 410-1.

[0128] Specifically, refer to Figure 7B , Figure 7C and Figure 8C Through the exposed contact hole 410 , a portion of the third dielectric layer 230 in the step region 02 and the second covering layer 024 filling the step steps, and a portion of the first dielectric layer 210 in the step region 02 and the first covering layer 022 filling the step steps can be removed.

[0129] Optionally, by, for example, a dry etching process or a combination of dry and wet etching processes; other manufacturing processes, such as a patterning process including photolithography, cleaning and chemical mechanical polishing, etc., may also be performed, and by adjusting parameters such as the type, concentration, etching time and etching speed of the etchant, the etching rate of the first covering layer 022 and the second covering layer 024 in the above-mentioned etching process can be greater than the etching rate of the first dielectric layer 210 and the third dielectric layer 230, thereby allowing the process of enlarging the aperture of the contact hole 410 to stop above each step step, thereby enlarging the radial size of the first portion 410-1 of the contact hole 410.

[0130] refer to FIG. 8B to FIG. 8D After the aperture of the contact hole 410 is enlarged, the contact structure 400 is formed, including: forming a first electrical connection portion 400-1 of the contact structure 400 in the first portion 410-1, and forming a second electrical connection portion 400-2 of the contact structure 400 in the second portion 410-2, wherein the portion of the first electrical connection portion 400-1 extending to the corresponding upper surface of the gate conductor layer extends in the xy plane and contacts the upper surface. In the case where the gate composite layer 250 includes the inter-wall dielectric layer 251, the adhesive layer 252, and the gate metal layer 253, it can be understood that the gate conductor layer includes the adhesive layer 252 and the gate metal layer 253, and the upper surface of the gate conductor layer can be understood as the upper surface of the adhesive layer 252. In the case where the gate composite layer 250 includes the inter-wall dielectric layer 251 and the gate metal layer 253, it can be understood that the gate conductor layer is the gate metal layer 253, and the upper surface of the gate conductor layer can be understood as the upper surface of the gate metal layer 253.

[0131] Optionally, the contact structure 400 includes a conductive core layer 440, an adhesive layer 430 and a barrier layer 420 in order from the inside to the outside, wherein the barrier layer 420 includes a first layer 420-1 and a second layer 420-2 having a gap in the z direction. Specifically, after the aperture of the contact hole 410 is enlarged, an initial barrier layer (not shown) may be formed on the sidewall of the enlarged contact hole 410 by a thin film deposition process such as CVD, PVD, ALD or any combination thereof. Optionally, the initial barrier layer may be a high dielectric constant dielectric layer. Thereafter, the initial barrier layer formed at the portion where the first portion 410-1 and the second portion 410-2 are connected may be removed by, for example, a deep hole etching process. In other words, the portion of the initial barrier layer located in the xy plane is removed so that the barrier layer 420 formed after the process is divided into a first layer 420-1 and a second layer 420-2 having a gap in the z direction. After forming the barrier layer 420 , an adhesion layer 430 and a conductive core layer 440 may be sequentially formed in the expanded contact hole 410 by a thin film deposition process such as one or more CVD, PVD, ALD or any combination thereof.

[0132] The barrier layer 420 is divided into two parts with a gap in the z direction, which can ensure that the part of the first electrical connection part 400-1 extending to the upper surface of the gate conductor layer extends in the xy plane and achieves effective contact with the upper surface; in addition, the barrier layer 420 can also ensure that each contact structure 400 is only electrically connected to the corresponding gate conductor layer.

[0133] In addition, if Figure 7B and 8B As shown, after the contact structure 400 is formed, the covering sacrificial layer 434 may be removed by, for example, a dry etching process or a combination of dry and wet etching processes; other manufacturing processes may also be performed, such as a patterning process including photolithography, cleaning, and chemical mechanical polishing.

[0134] According to at least one embodiment of the present application, after forming each individual sub-stack structure, a corresponding sub-step structure and a sub-contact hole may be formed therein first, and then the remaining sub-stack structures may be formed on the individual sub-stack structure. Considering that the number of stacking layers of each individual sub-stack structure is limited, the method for preparing a semiconductor device provided by the present application can avoid the step of forming contact holes by a deep hole etching process after forming all the sub-stack structures, thereby simplifying the method for preparing a semiconductor device, reducing the preparation cost of the semiconductor device, and improving the reliability of the contact structure accommodated in the contact hole.

[0135] In addition, the gate conductor layer can selectively be electrically connected to a first peripheral circuit located on the front side of the semiconductor device through a first portion of a corresponding contact structure, or can be electrically connected to a second peripheral circuit located on the back side of the semiconductor device through a second portion of a corresponding second contact structure, thereby providing an implementation basis for combining multiple peripheral circuit wafers with a storage array wafer, further reducing the characteristic size of the system including the semiconductor device, and improving the system's integration and overall performance.

[0136] In addition, the dummy channel structure is only a temporary transitional structure in the preparation process, and provides support for the dielectric stack structure in the process of forming the gate layer. After the gate composite layer is formed, the dummy channel structure in the contact hole can be removed, and a contact structure can be formed in the contact hole, thereby providing support for the dielectric stack structure while increasing the storage density per unit area of ​​the semiconductor device, and improving the electrical performance and reliability of the semiconductor device.

[0137] In addition, if Figures 8A to 8DAs shown, the present application also provides a semiconductor device 2000. The semiconductor device 2000 includes: a stacked structure 200, a channel structure 300 and a contact structure 400. The stacked structure 200 includes a first stacked structure 201 and at least one second stacked structure 202 disposed on the first stacked structure 201, wherein the stacked structure 200 defines a storage area 01 and a step area 02 in a plane (xy plane) perpendicular to the stacking direction (z direction). The channel structure 300 penetrates the storage area 01 along the z direction, and includes a first channel structure 301 located in the first stacked structure 201 and a second channel structure 302 located in the second stacked structure 202, wherein the first channel structure 301 has a first upper end 22 close to the second channel structure 302, and the second channel structure 302 has a second upper end 44 away from the first channel structure 301. The contact structure 400 penetrates the step region 02 along the z direction and is connected to the corresponding gate conductor layer in the stacked structure 200, wherein the contact structure 400 includes a second contact structure 402 connected to the gate conductor layer of the second stacked structure 202, and the second contact structure 402 includes a first sub-portion 402-1 located in the first stacked structure 201 and a second sub-portion 402-2 located in the second stacked structure 202. The first top 77 of the first sub-portion 402-1 close to the second sub-portion 402-2 is flush with the first upper end 22 of the first channel structure 301; and / or the second top 88 of the second sub-portion 402-2 away from the first sub-portion 402-1 is flush with the second upper end 44 of the second channel structure 302. Those skilled in the art should understand that the term "flush" should be understood as completely flush, and slightly flush or substantially flush or approximately flush within the range of process or measurement errors.

[0138] For example, taking a three-dimensional memory as an example, the three-dimensional memory may include a memory array and a peripheral circuit for controlling signals entering and exiting the memory array. The peripheral circuit may include a high-voltage circuit, a low-voltage circuit, and an ultra-low-voltage circuit. Usually, the memory array and the peripheral circuit may be formed on two different wafers, and then the peripheral circuit wafer is bonded to the memory array wafer through a process such as bonding to connect the peripheral circuit and the memory array together.

[0139] As three-dimensional memory continues to develop towards high-layer count and high-density, the size of the peripheral circuit wafer is becoming more and more a key factor in determining the size of the entire chip. However, the peripheral circuit wafer is often unable to be further reduced due to the size of the high-voltage circuit on it. Therefore, in order to improve the storage density and integrability of three-dimensional memory, low-voltage circuits and ultra-low-voltage circuits can be integrated on one peripheral circuit wafer, and high-voltage circuits can be integrated on another peripheral circuit wafer.

[0140] The semiconductor device provided by at least one embodiment of the present application has a contact structure that penetrates the stacked structure, which can realize the integration of peripheral circuits on the front and back sides of the semiconductor device, thereby improving the integration and overall performance of the system including the semiconductor device.

[0141] Specifically, Figure 8B and Fig.8D As shown, the semiconductor device 2000 may include a stacked structure 200 formed by alternatingly stacking a gate composite layer 250 and a first dielectric layer 210 (or a third dielectric layer 230), wherein the first dielectric layer 210 (or the third dielectric layer 230) may be used as an isolation stacking layer, and the gate composite layer 250 may be formed by, for example, a gate-last process.

[0142] The gate composite layer 250 may include a gate metal layer 253, which may be made of a conductive material, such as any one or a combination of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), doped crystalline silicon or silicide. In addition, the gate composite layer 250 may also include an inter-wall dielectric layer 251 located between the first dielectric layer 210 (or the third dielectric layer 230) and the gate metal layer 253. As an option, the inter-wall dielectric layer 251 may be a high dielectric constant dielectric layer. Further, the gate composite layer 250 may also include an adhesion layer 252 located between the first dielectric layer 210 (or the third dielectric layer 230) and the gate metal layer 253, or located between the inter-wall dielectric layer 251 and the gate metal layer 253, such as a titanium nitride TiN layer.

[0143] Optionally, when the gate composite layer 250 includes the inter-wall dielectric layer 251, the adhesive layer 252 and the gate metal layer 253, the adhesive layer 252 and the gate metal layer 253 can be understood as a gate conductor layer. Optionally, when the gate composite layer 250 includes the inter-wall dielectric layer 251 and the gate metal layer 253, the gate metal layer 253 can be understood as a gate conductor layer.

[0144] In addition, the number of layers of the stacked structure 200 is not limited to the number of layers shown in the figure, and can be set separately as needed, such as 32 layers, 64 layers, 128 layers, etc. In addition, with the increasing demand for the storage capacity of semiconductor devices, the above-mentioned storage stacking layers are gradually increasing. The stacked structure 200 may include a plurality of sub-stacked structures (for example, a first stacked structure 201 and at least one second stacked structure 202 disposed on the first stacked structure 201) formed by a double stacking technology or a multi-stacked technology. A plurality of sub-stacked structures may be stacked in sequence in the z direction to form a stacked structure 200. The number of layers of each sub-stacked structure may be the same or different. The content of a single stacked structure described below may be fully or partially applicable to a stacked structure formed by a plurality of sub-stacked structures, and therefore the content related or similar thereto will not be repeated.

[0145] like Fig. 8A and 8B As shown, the stacked structure 200 may include a storage region 01 and a step region 02 distributed along the x direction, wherein the storage region 01 includes a channel structure 300 penetrating the stacked structure 200 along the z direction, and the step region 02 includes a contact structure 400. Figure 6C , the channel structure 300 may include a functional layer 320 and a channel layer 330 sequentially formed on the inner wall of the channel hole 310. The functional layer 320 may include a barrier layer (not shown), a charge trapping layer (not shown) and a tunneling layer (not shown) sequentially arranged on the inner wall of the channel hole 310. As an option, the channel hole 310 may have a cylindrical or columnar shape passing through the stacked structure 200 along the z direction. The channel layer 330 may include silicon, such as amorphous silicon, polycrystalline silicon or single crystal silicon. The material of the channel layer 330 includes but is not limited to N-type (or P-type) doped polycrystalline silicon. Similar to the channel hole 310, the functional layer 320 and the channel layer 330 may also have a cylindrical or columnar shape passing through the stacked structure 200. The channel structure 300 and the plurality of gate composite layers 250 may be configured in series to form a stack of memory cells in the semiconductor device 2000.

[0146] As an option, in one embodiment of the present application, each storage area 01 corresponds to at least one step area 02, and at least one step area 02 is located in the middle of the corresponding storage area 01, so as to divide the corresponding storage area 01 into at least two sub-storage areas, and multiple channel structures 300 are respectively arranged in the sub-storage areas. The step area 02 may include multiple step steps and a first covering layer 022 and a second covering layer 024 covering the multiple step steps. The contact structure 400 electrically connected to the gate conductor layer of the gate composite layer 250 passes through the step area 02 and is respectively arranged on each step step.

[0147] As another option, in one embodiment of the present application, each storage area 01 corresponds to at least one step area 02, and at least one step area 02 is located at the periphery of the corresponding storage area 01. The step area 02 includes a plurality of step steps and a first covering layer 022 and a second covering layer 024 covering the plurality of step steps, and a contact structure 400 electrically connected to the gate conductor layer of the gate composite layer 250 penetrates the step area 02 and is respectively disposed on each step step.

[0148] In other words, the stacked structure may include other layers or parts in addition to the gate core layer and the first dielectric layer (or the third dielectric layer) along the z direction, such as the first cover layer and the second cover layer. In the present application, the contact structure "penetrating the step region of the stacked structure" means that the contact structure penetrates all the layers or parts included in the stacked structure at the location thereof, so as to extend to or beyond the two opposite surfaces of the stacked structure along the z direction.

[0149] In addition, refer again Figure 8B In one embodiment of the present application, the contact structure 400 further includes a first contact structure 401 connected to the gate conductor layer of the first stacked structure 201. The first contact structure 401 includes a third top 66 and a third bottom 55 opposite to each other in the z direction, and the third top 55, the second top 88 of the second sub-portion 402-2, and the second upper end 44 of the second channel structure 302 are flush. Setting the tops of the contact structure and the channel structure to be flush is conducive to realizing that the contact structure and the channel structure are simultaneously combined with peripheral circuits on the front side of the semiconductor device, thereby improving the integration and overall performance of the system including the semiconductor device.

[0150] Optionally, in one embodiment of the present application, the first sub-portion 402-1 has a first bottom end 99 away from the second sub-portion 402-2, and the first lower end 11 of the first channel structure 301 away from the second channel structure 302, the first bottom end 99 of the first sub-portion 402-1, and the third bottom end 55 of the first contact structure 401 are flush. Setting the bottom ends of the contact structure and the channel structure to be flush is conducive to realizing that the contact structure and the channel structure are simultaneously combined with a peripheral circuit on the reverse side of the semiconductor device, thereby improving the integration and overall performance of the system including the semiconductor device.

[0151] refer to Figure 8B and Fig.8D The contact structure 400 includes a first electrical connection portion 400-1 and a second electrical connection portion 400-2. The first electrical connection portion 400-1 penetrates the first covering layer 022 (or the second covering layer 024) along the z direction, extends to the upper surface of the corresponding gate conductor layer, and is electrically connected to the upper surface. The second electrical connection portion 400-2 is connected to the first electrical connection portion 400-1 and penetrates the step along the z direction.

[0152] Optionally, the portion of the first electrical connection 400-1 extending to the upper surface of the gate conductor layer extends in a plane perpendicular to the z-direction and contacts the upper surface. In other words, in the xy plane, the radial dimension of the portion of the first electrical connection 400-1 adjacent to the upper surface is greater than the radial dimension of the second electrical connection 400-2. The first electrical connection 400-1 and the second electrical connection 400-2 of the contact structure 400 can both be electrically connected to the corresponding gate conductor layer. Therefore, each gate conductor layer can be electrically connected to a peripheral circuit (not shown) through the first electrical connection 400-1 or the second electrical connection 400-2 of the contact structure 400 corresponding to it.

[0153] Specifically, the peripheral circuit may include a first peripheral circuit (not shown) and a second peripheral circuit (not shown) arranged opposite to each other along the z direction. Each gate conductor layer may be electrically connected to the first peripheral circuit through the first electrical connection portion 400-1 (or the second electrical connection portion 400-2) of the contact structure 400 corresponding thereto, or may be electrically connected to the second peripheral circuit through the second electrical connection portion 400-2 (or the first electrical connection portion 400-1) of the contact structure 400 corresponding thereto.

[0154] In this embodiment, the gate conductor layer can be selectively electrically connected to a first peripheral circuit located on the front side of the semiconductor device through a first electrical connection portion of a corresponding contact structure, or electrically connected to a second peripheral circuit located on the back side of the semiconductor device through a second electrical connection portion of a corresponding contact structure, thereby providing an implementation basis for combining multiple peripheral circuit wafers with a storage array wafer, further reducing the characteristic size of the system including the semiconductor device, and improving the system's integration and overall performance.

[0155] Optionally, in one embodiment of the present application, the contact structure 400 includes a conductive core layer 440, an adhesive layer 430 and a barrier layer 420 in order from the inside to the outside, wherein the barrier layer 420 includes a first layer 420-1 and a second layer 420-2 spaced apart in the z direction. The barrier layer 420 is divided into two spaced apart parts in the z direction, which can ensure that the portion of the first electrical connection portion 400-1 extending to the upper surface of the gate conductor layer extends in the xy plane and achieves effective contact with the upper surface; in addition, the barrier layer 420 can also ensure that each contact structure 400 is only electrically connected to the corresponding gate conductor layer.

[0156] In addition, refer again Figure 8B In one embodiment of the present application, the radial dimension of the first top 77 of the first sub-portion 402-1 of the second contact structure 402 is smaller than the radial dimension of the second bottom end of the second sub-portion 402-2 opposite to the second top 88 in the z direction. Optionally, the radial dimension of the first top 77 of the first sub-portion 402-1 of the second contact structure 402 is larger than the radial dimension of the first bottom end of the first sub-portion 402-1 opposite to the first top 77 in the z direction. As described in the above semiconductor device manufacturing method 1000, the aperture size of the second contact hole located at the top and accommodating the second sub-portion 402-2 is larger than the aperture size of the first contact hole located at the bottom and accommodating the first sub-portion 402-1, which can effectively increase the process window for forming the contact structure in the contact hole and improve the stability of the contact structure.

[0157] In addition, in one embodiment of the present application, the radial dimension of the second lower end 33 of the second channel structure 302 close to the first channel structure 301 is smaller than the radial dimension of the first upper end 22 of the first channel structure 301. By setting the diameter of the lower end of the second channel structure to be smaller than the aperture size of the upper end of the first channel structure, the interval between adjacent channel structures can be effectively reduced, the storage density per unit area of ​​the semiconductor device can be greatly improved, and the price of the unit storage unit can be reduced.

[0158] Fig. 9 It is a schematic diagram of the structure of a storage system 30000 according to one embodiment of the present application.

[0159] like Fig. 9 As shown, at least one embodiment of another aspect of the present application further provides a storage system 30000. The storage system 30000 may include a semiconductor device 20000 and a controller 32000. The semiconductor device 20000 may be the same as the semiconductor device described in any embodiment above, and the present application will not repeat it.

[0160] Optionally, the semiconductor device 20000 may be a memory array wafer or a memory including a peripheral circuit. Specifically, the semiconductor device 20000 may include at least one of a two-dimensional memory or a three-dimensional memory. As an option, the three-dimensional memory may include at least one of a three-dimensional NAND memory and a three-dimensional NOR memory.

[0161] Specifically, the storage system 30000 may include a semiconductor device 20000 and a controller 32000. The semiconductor device 20000 may be the same as the semiconductor device described in any of the above embodiments, and this application will not repeat them. The controller 32000 may control the semiconductor device 20000 through a channel CH, and the semiconductor device 20000 may perform operations based on the control of the controller 32000 in response to a request from a host 31000. The semiconductor device 20000 may receive a command CMD and an address ADDR from the controller 32000 through the channel CH and access an area selected from a storage cell array in response to the address. In other words, the semiconductor device 20000 may perform an internal operation corresponding to the command on the area selected by the address.

[0162] In some embodiments, the storage system may be implemented as a universal flash storage (UFS) device, a solid state drive (SSD), a multimedia card in the form of MMC, eMMC, RS-MMC and micro MMC, a secure digital card in the form of SD, mini SD and micro SD, a storage device of the Personal Computer Memory Card International Association (PCMCIA) card type, a storage device of the peripheral component interconnect (PCI) type, a storage device of the high-speed PCI (PCI-E) type, a compact flash (CF) card, a smart media card or a memory stick, etc. The storage system provided in the present application has the same beneficial effects as the semiconductor device provided in the present application because the semiconductor device provided in the present application is provided, and no further description is given here.

[0163] The above description is only a preferred embodiment of the present application and an explanation of the technical principles used. Those skilled in the art should understand that the scope of protection involved in the present application is not limited to the technical solution formed by the selected combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the technical concept. For example, the above features are replaced with the technical features with similar functions disclosed in this application (but not limited to) by each other to form a technical solution.

Claims

1. A method for preparing a semiconductor device, characterized in that: include: forming a first dielectric stacking structure, forming a first step structure in the first dielectric stacking structure, and forming a first contact hole penetrating the first step structure along a stacking direction; as well as forming a second dielectric stacking structure on the first dielectric stacking structure, forming a second step structure in the second dielectric stacking structure, and forming a second contact hole, The second contact hole penetrates the first step structure along the stacking direction and extends to the first contact hole to form a contact hole.

2. The method according to claim 1, wherein: A radial dimension of the second contact hole near a bottom of the first contact hole is greater than a radial dimension of the first contact hole near a top of the second contact hole.

3. The method according to claim 1, wherein: Forming a first dielectric stack structure includes alternately stacking a first dielectric layer and a second dielectric layer along the stacking direction; and forming a second dielectric stack structure on the first dielectric stack structure includes alternately stacking a third dielectric layer and a fourth dielectric layer along the stacking direction on the first dielectric stack structure, Wherein, after forming the contact hole, the method further comprises: Filling the contact hole with a first dielectric filling material layer to form a dummy channel structure; and The second dielectric layer and the fourth dielectric layer are removed to form a sacrificial gap, and a gate conductor layer is formed in the sacrificial gap.

4. The method according to claim 1, wherein: The method further includes forming a channel hole accommodating the channel structure, the channel hole including a first channel hole and a second channel hole connected to each other along the stacking direction, and forming the channel hole includes: In the process of forming the first contact hole, a first channel hole extending in the first dielectric stack structure along the stacking direction is formed.

5. The method according to claim 4, wherein: Forming the channel hole further includes: In the process of forming the second contact hole, a second channel hole is formed extending in the second dielectric stack structure along the stacking direction and extending to the first channel hole.

6. The method according to claim 5, wherein: The first contact hole and the first channel hole are formed by using the same mask; and / or The second contact hole and the second channel hole are formed by using the same mask.

7. The method according to claim 3, wherein: After forming the gate conductor layer, the method further includes forming a contact structure connected to the corresponding gate conductor layer, and forming the contact structure includes: removing the first dielectric filling material layer to expose the contact hole; and enlarging the aperture of the contact hole so that the radial dimension of the first portion of the contact hole is larger than the radial dimension of the second portion of the contact hole, The first portion is a portion of the contact hole extending from top to bottom along the stacking direction to the corresponding gate conductor layer; and the second portion is different from the first portion.

8. The method according to claim 7, wherein: After enlarging the diameter of the contact hole, the method for forming the contact structure further includes: forming a first electrical connection of the contact structure in the first portion and forming a second electrical connection of the contact structure in the second portion, The portion of the first electrical connection portion extending to the corresponding upper surface of the gate conductor layer extends in a plane perpendicular to the stacking direction and contacts the upper surface.

9. A semiconductor device, characterized in that: include: A stacked structure, comprising a first stacked structure and at least one second stacked structure disposed on the first stacked structure, wherein the stacked structure defines a storage area and a step area in a plane perpendicular to a stacking direction; a channel structure, which runs through the storage area and includes a first channel structure located in the first stacked structure and a second channel structure located in the second stacked structure, wherein the first channel structure has a first upper end close to the second channel structure, and the second channel structure has a second upper end far from the first channel structure; as well as a contact structure that penetrates the step region and is connected to the corresponding gate conductor layer in the stacked structure, wherein the contact structure includes a second contact structure connected to the gate conductor layer of the second stacked structure, and the second contact structure includes a first sub-portion located in the first stacked structure and a second sub-portion located in the second stacked structure, Wherein, a first top end of the first sub-portion close to the second sub-portion is flush with a first upper end of the first channel structure; and / or A second top end of the second sub-portion away from the first sub-portion is flush with a second upper end of the second channel structure.

10. The semiconductor device according to claim 9, wherein The contact structure further includes a first contact structure connected to the gate conductor layer of the first stacked structure. The first contact structure includes a third top end and a third bottom end opposite to each other in the stacking direction, and the third top end, the second top end of the second sub-portion, and the second upper end of the second channel structure are flush.

11. The semiconductor device according to claim 10, wherein: The first sub-section has a first bottom end away from the second sub-section, The first channel structure is away from the first lower end of the second channel structure, the first bottom end of the first sub-portion, and the third bottom end of the first contact structure and is flush.

12. The semiconductor device according to claim 9, wherein The step region includes a plurality of step steps and a covering dielectric layer covering the plurality of step steps; and The contact structure includes a first electrical connection portion and a second electrical connection portion, wherein the first electrical connection portion penetrates the covering dielectric layer along the stacking direction, extends to the upper surface of the corresponding gate conductor layer, and is connected to the upper surface, and the second electrical connection portion is connected to the first electrical connection portion and penetrates the step along the stacking direction.

13. The semiconductor device according to claim 12, wherein: The semiconductor device further includes a peripheral circuit, Wherein, the corresponding gate conductor layer is electrically connected to the peripheral circuit through the first electrical connection portion or the second electrical connection portion of the contact structure.

14. The semiconductor device according to claim 12, wherein: The peripheral circuit comprises a first peripheral circuit and a second peripheral circuit arranged opposite to each other along the stacking direction; The corresponding gate conductor layer is electrically connected to the first peripheral circuit through the first electrical connection portion, or is electrically connected to the second peripheral circuit through the second electrical connection portion.

15. The semiconductor device according to claim 11, wherein Each of the storage areas corresponds to at least one step area, and at least one step area is located in the middle of the corresponding storage area, so as to divide the corresponding storage area into at least two sub-storage areas.

16. The semiconductor device according to claim 11, wherein Each of the storage areas corresponds to at least one step area, and at least one step area is located at an edge of the corresponding storage area.

17. The semiconductor device according to claim 12, wherein: The contact structure comprises a conductive core layer, an adhesive layer and a barrier layer in sequence from the inside to the outside, wherein the barrier layer comprises a first layer and a second layer spaced apart in the stacking direction.

18. The semiconductor device according to claim 9, wherein: The radial dimension of the first top end of the first sub-section is smaller than the radial dimension of the second bottom end of the second sub-section, The second bottom end and the second top end of the second sub-section are opposite to each other in the stacking direction.

19. The semiconductor device according to claim 9, wherein: The radial dimension of the first top end of the first sub-section is greater than the radial dimension of the first bottom end of the first sub-section, Wherein, the first bottom end and the first top end of the first sub-section are opposite to each other in the stacking direction.

20. The semiconductor device according to claim 9, wherein A radial dimension of a second lower end of the second channel structure close to the first channel structure is smaller than a radial dimension of a first upper end of the first channel structure.

21. A storage system, characterized in that: The storage system comprises: a controller and the semiconductor device according to any one of claims 9 to 20, wherein the controller is coupled to the semiconductor device and is used to control the semiconductor device to store data.

Images