Ferroelectric memory and manufacturing method thereof

Abstract

The invention relates to the technical field of semiconductor manufacturing, in particular to a ferroelectric memory and a manufacturing method thereof. The manufacturing method of the ferroelectric memory comprises the following steps of forming a substrate, wherein the substrate comprises a first dielectric layer, a storage hole penetrating through the first dielectric layer and a storage structure covering the inner wall of the storage hole and the top surface of the first dielectric layer; forming a conductive filling layer which fills the storage hole and covers the storage structure; removing the conductive filling layer and the storage structure above the first dielectric layer by adopting a grinding process; and forming a second dielectric layer covering the substrate and a first lead-out structure which penetrates through the second dielectric layer and is electrically connected with the remaining conductive filling layer in the storage hole. According to the invention, the manufacturing cost of the ferroelectric memory is saved, the manufacturing process of the ferroelectric memory is simplified, and the integration level of the ferroelectric memory is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a ferroelectric memory and a manufacturing method thereof. Background Art

[0002] Ferroelectric RAM (FeRAM) is a device that integrates memory cells in the back-end of line (BEOL), which is a structure in which the memory cell is inserted between two adjacent metal layers. The memory cell is generally composed of an upper and lower electrode layer and a ferroelectric memory layer in the middle. The storage performance of the ferroelectric memory is proportional to the effective area of ​​the ferroelectric memory layer and the electrode layer in the memory cell. The material of the ferroelectric memory layer in the memory cell of the traditional ferroelectric memory is usually phase change material or ferroelectric material, and the traditional memory cell is a three-dimensional structure.

[0003] In the manufacturing process of the traditional ferroelectric memory, after depositing the lower electrode layer, storage layer, upper electrode layer and contact structure in the capacitor hole in the dielectric layer, it is necessary to form a mask layer above the dielectric layer and pattern the mask layer to remove the lower electrode layer, storage layer and upper electrode layer covering the top surface of the dielectric layer to separate adjacent memory cells. However, the above-mentioned steps of separating adjacent memory cells are not only costly, but also prone to leakage problems between adjacent memory cells due to incomplete separation, which is not conducive to the improvement and enhancement of the performance of the ferroelectric memory. In addition, the above-mentioned process of separating adjacent memory cells requires a large spacing between adjacent memory cells so that there are sufficient lithography windows, which is not conducive to further improvement of the integration of the ferroelectric memory.

[0004] Therefore, how to simplify the manufacturing process of ferroelectric memory, reduce the manufacturing cost of ferroelectric memory, improve the integration of ferroelectric memory, and improve the performance of ferroelectric memory is a technical problem that needs to be solved urgently. Summary of the invention

[0005] The ferroelectric memory and the manufacturing method thereof provided by the present invention are used to simplify the manufacturing process of the ferroelectric memory, reduce the manufacturing cost of the ferroelectric memory, and at the same time improve the integration of the ferroelectric memory and improve the performance of the ferroelectric memory.

[0006] According to some embodiments, the present invention provides a method for manufacturing a ferroelectric memory, comprising the following steps:

[0007] forming a substrate, the substrate comprising a first dielectric layer, a storage hole penetrating the first dielectric layer along a first direction, and a storage structure covering an inner wall of the storage hole and a top surface of the first dielectric layer, the first dielectric layer comprising a top surface and a bottom surface that are relatively distributed, and the first direction intersects the top surface of the first dielectric layer perpendicularly;

[0008] forming a conductive filling layer that fills the storage hole and covers the storage structure;

[0009] Using a grinding process to remove the conductive filling layer and the storage structure located above the first dielectric layer;

[0010] A second dielectric layer covering the substrate and a first lead-out structure penetrating the second dielectric layer and electrically connected to the remaining conductive filling layer in the storage hole are formed.

[0011] In some embodiments, the specific steps of forming the substrate include:

[0012] forming a first dielectric layer;

[0013] Etching the first dielectric layer to form the storage hole penetrating the first dielectric layer along a first direction;

[0014] forming a lower electrode layer covering the inner wall of the storage hole and the top surface of the first dielectric layer;

[0015] forming a storage layer covering the lower electrode layer;

[0016] An upper electrode layer covering the storage layer is formed, and the lower electrode layer, the storage layer and the upper electrode layer together constitute the storage structure.

[0017] In some embodiments, the specific steps of forming a conductive filling layer that fills the storage hole and covers the storage structure include:

[0018] Metal tungsten is deposited on the substrate to form the conductive filling layer that continuously covers the upper electrode layer in the storage hole and the upper electrode layer on the top surface of the first dielectric layer.

[0019] In some embodiments, the specific steps of removing the conductive filling layer and the storage structure located above the first dielectric layer by a grinding process include:

[0020] Using a first grinding process to remove at least the conductive filling layer and the upper electrode layer located on the top surface of the first dielectric layer;

[0021] A second grinding process is used to remove at least the storage layer and the lower electrode layer located on the top surface of the first dielectric layer.

[0022] In some embodiments, the specific steps of removing at least the conductive filling layer and the upper electrode layer located on the top surface of the first dielectric layer by using the first grinding process include:

[0023] The conductive filling layer and the upper electrode layer located on the top surface of the first dielectric layer are removed by adopting a first grinding process and using the storage layer as a grinding cut-off layer.

[0024] In some embodiments, the specific steps of removing at least the storage layer and the lower electrode layer located on the top surface of the first dielectric layer by using the second grinding process include:

[0025] The storage layer and the lower electrode layer located on the top surface of the first dielectric layer are completely removed by adopting a second grinding process and adjusting the grinding time.

[0026] In some embodiments, the specific steps of forming the substrate include:

[0027] forming a first dielectric layer;

[0028] Etching the first dielectric layer to form the storage hole penetrating the first dielectric layer along a first direction;

[0029] forming a lower electrode layer covering the inner wall of the storage hole and the top surface of the first dielectric layer;

[0030] Etching back part of the lower electrode layer to completely remove the lower electrode layer on the top surface of the first dielectric layer and part of the lower electrode layer in the storage hole, wherein the top surface of the remaining lower electrode layer in the storage hole is lower than the top surface of the first dielectric layer;

[0031] forming a storage layer that continuously covers the top surface of the first dielectric layer, the inner wall of the storage hole, and the surface of the lower electrode layer;

[0032] An upper electrode layer covering the storage layer is formed, and the lower electrode layer, the storage layer and the upper electrode layer together constitute the storage structure.

[0033] In some embodiments, the specific steps of etching back part of the lower electrode layer include:

[0034] A portion of the lower electrode layer in the storage hole is etched by multiple lateral etching processes to reduce the inclination angle of the top surface of the lower electrode layer.

[0035] In some embodiments, the specific steps of removing the conductive filling layer and the storage structure located above the first dielectric layer by a grinding process include:

[0036] Using a first grinding process to remove at least the conductive filling layer and the upper electrode layer located on the top surface of the first dielectric layer;

[0037] A third grinding process is used to remove at least the storage layer located on the top surface of the first dielectric layer.

[0038] In some embodiments, the specific steps of forming a second dielectric layer covering the substrate and a first lead-out structure penetrating the second dielectric layer and electrically connected to the remaining conductive filling layer in the storage hole include:

[0039] forming a third dielectric layer covering the substrate, the storage structure and the conductive filling layer;

[0040] forming the second dielectric layer covering the third dielectric layer;

[0041] Forming a first lead-out hole that continuously penetrates the second dielectric layer and the third dielectric layer and exposes the conductive filling layer;

[0042] Filling the first lead-out hole with a conductive material to form the first lead-out structure electrically connected to the conductive filling layer.

[0043] According to some other embodiments, the present invention further provides a ferroelectric memory, comprising:

[0044] A substrate, the substrate comprising a first dielectric layer and a storage hole penetrating the first dielectric layer along a first direction, the first dielectric layer comprising a top surface and a bottom surface that are relatively distributed, and the first direction perpendicularly intersects with the top surface of the first dielectric layer;

[0045] A storage structure, covering the inner wall of the storage hole, wherein the top surface of the storage structure is lower than or flush with the top surface of the first dielectric layer;

[0046] A conductive filling layer, which fills the storage hole and covers the surface of the storage structure, and the top surface of the conductive filling layer is flush with the top surface of the storage structure;

[0047] A second dielectric layer covering the substrate;

[0048] The first lead-out structure penetrates the second dielectric layer along the first direction and is electrically connected to the conductive filling layer.

[0049] In some embodiments, the storage structure includes a lower electrode layer, a storage layer covering a surface of the lower electrode layer, and an upper electrode layer covering a surface of the storage layer;

[0050] The conductive filling layer covers the surface of the upper electrode layer and is in contact with and electrically connected to the upper electrode layer.

[0051] In some embodiments, a top surface of the lower electrode layer, a top surface of the storage layer, a top surface of the upper electrode layer, and a top surface of the conductive filling layer are flush.

[0052] In some embodiments, the top surface of the lower electrode layer is lower than the top surface of the first dielectric layer, and the storage layer continuously covers the sidewall of the storage hole and the surface of the lower electrode layer away from the sidewall of the storage hole;

[0053] The top surface of the storage layer, the top surface of the upper electrode layer and the top surface of the conductive filling layer are flush.

[0054] The ferroelectric memory and its manufacturing method provided by the present invention, after forming a conductive filling layer that fills the storage hole and covers the storage structure, adopts a grinding process to remove the conductive filling layer and the storage structure located above the first dielectric layer, so that not only can the adjacent storage structures be fully separated to improve the electrical performance of the ferroelectric memory, but also no photomask is required, saving the manufacturing cost of the ferroelectric memory and simplifying the manufacturing process of the ferroelectric memory. Moreover, the storage structure and the conductive filling layer on the top surface of the first dielectric layer can be fully removed by the grinding process, which helps to reduce the distance between adjacent storage structures, thereby increasing the number of storage structures to improve the integration of the ferroelectric memory. At the same time, the present invention etches the deposited lower electrode layer back before depositing the storage layer in the storage structure, so that the lower electrode layer and the upper electrode layer in the storage structure can be fully isolated by the subsequently deposited storage layer, avoiding the leakage problem between the lower electrode layer and the upper electrode layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] Figure 1 is a flow chart of a method for manufacturing a ferroelectric memory in a specific embodiment of the present invention;

[0056] Figure 2 is a schematic structural diagram of a substrate in a specific embodiment of the present invention;

[0057] Figure 3 is a structural schematic diagram after a storage structure is formed in a storage hole in a specific embodiment of the present invention;

[0058] Figure 4 is a schematic diagram of a structure after a conductive filling layer is formed in a specific embodiment of the present invention;

[0059] Figure 5 is a structural schematic diagram after the conductive filling layer and the storage structure on the top surface of the first dielectric layer are removed by a grinding process in a specific embodiment of the present invention;

[0060] Figure 6 is a schematic diagram of a structure after forming a second dielectric layer in a specific embodiment of the present invention;

[0061] Figure 7 is a structural schematic diagram after the first lead-out structure is formed in a specific embodiment of the present invention;

[0062] Figure 8 is another structural schematic diagram after a lower electrode layer is formed in a storage hole in a specific embodiment of the present invention;

[0063] Fig. 9 is another structural schematic diagram after the lower electrode layer is etched back in a specific embodiment of the present invention;

[0064] Fig.10 is another structural schematic diagram after a storage structure and a conductive filling layer are formed in a storage hole in a specific embodiment of the present invention;

[0065] Fig.11 is another structural schematic diagram after the conductive filling layer and the storage structure on the top surface of the first dielectric layer are removed by a grinding process in a specific embodiment of the present invention;

[0066] Fig.12 It is another structural schematic diagram after the first lead-out structure is formed in a specific implementation manner of the present invention. DETAILED DESCRIPTION

[0067] The specific implementation manner of the ferroelectric memory and the manufacturing method thereof provided by the present invention is described in detail below with reference to the accompanying drawings.

[0068] This specific embodiment provides a method for manufacturing a ferroelectric memory. Figure 1 FIG. 1 is a flow chart of a method for manufacturing a ferroelectric memory in a specific embodiment of the present invention. Figure 1 As shown, the manufacturing method of the ferroelectric memory comprises the following steps:

[0069] Step S11, forming a substrate, the substrate comprising a first dielectric layer, a storage hole penetrating the first dielectric layer along a first direction, and a storage structure covering an inner wall of the storage hole and a top surface of the first dielectric layer, the first dielectric layer comprising a top surface and a bottom surface that are relatively distributed, and the first direction intersects the top surface of the first dielectric layer perpendicularly;

[0070] Step S12, forming a conductive filling layer that fills the storage hole and covers the storage structure;

[0071] Step S13, removing the conductive filling layer and the storage structure located above the first dielectric layer by a grinding process;

[0072] Step S14, forming a second dielectric layer covering the substrate and a first lead-out structure penetrating the second dielectric layer and electrically connected to the remaining conductive filling layer in the storage hole.

[0073] Figure 2 is a schematic structural diagram of a substrate in a specific embodiment of the present invention, Figure 3 FIG. 1 is a schematic diagram of a structure after a storage structure is formed in a storage hole in a specific embodiment of the present invention. Figure 2 and Figure 3 As shown, the specific steps of forming the substrate include:

[0074] forming a first dielectric layer 21;

[0075] Etching the first dielectric layer 21 to form the storage hole 22 penetrating the first dielectric layer 21 along the first direction D1;

[0076] forming a lower electrode layer 31 covering the inner wall of the storage hole 22 and the top surface of the first dielectric layer 21;

[0077] forming a storage layer 32 covering the lower electrode layer 31;

[0078] An upper electrode layer 33 is formed to cover the storage layer 32 . The lower electrode layer 31 , the storage layer 32 and the upper electrode layer 33 together constitute the storage structure.

[0079] For example, the base includes a substrate, an isolation layer 20 located above the substrate, and the first dielectric layer 21 covering the isolation layer 20. The substrate includes an active region, and the active region includes a channel region and a source region and a drain region distributed on opposite sides of the channel region along a second direction D2, and the second direction D2 is parallel to the top surface of the first dielectric layer 21. The isolation layer 20 has a first contact structure 23 electrically connected to the drain region and penetrating the isolation layer 20 along the first direction D1, and a second contact structure 24 electrically connected to the source region and penetrating the isolation layer 20 along the first direction D1. In another example, the base also includes a gate electrode located above the substrate and corresponding to the channel region, the isolation layer 20 covers the gate electrode, and the isolation layer 20 has a first contact structure 23 electrically connected to the drain region and penetrating the isolation layer 20 along the first direction D1, and a second contact structure 24 electrically connected to the gate electrode and penetrating the isolation layer 20 along the first direction D1.

[0080] The substrate further includes a fourth dielectric layer 25 located between the first dielectric layer 21 and the isolation layer 20. The materials of the first dielectric layer 21 and the isolation layer 20 may both be oxide materials, such as silicon dioxide; and the material of the fourth dielectric layer 25 may be nitride materials, such as silicon nitride. The first dielectric layer 21 is etched to form the storage hole 22 that penetrates the first dielectric layer 21 and the fourth dielectric layer 25 along the first direction D1 and exposes the first contact structure 23. In an example, the substrate includes at least a plurality of active regions arranged at intervals along the second direction D2 and the first contact structure 23 and the second contact structure 24 located above each active region. By etching the first dielectric layer 21, a plurality of storage holes 22 that are arranged at intervals along the second direction D2 and correspond to the plurality of first contact structures 23 are formed. A conductive material such as TiN is deposited on the substrate to form the lower electrode layer 31 that continuously covers the inner wall of the storage hole 22 and the top surface of the first dielectric layer 21. A ferroelectric material (such as HZO (hafnium zirconium oxide)) is deposited on the substrate to form the storage layer 32 covering the lower electrode layer 31. Then, a conductive material such as TiN is deposited on the substrate to form the upper electrode layer 33 covering the storage layer 32, so that the lower electrode layer 31, the storage layer 32 and the upper electrode layer 33 together constitute the storage structure.

[0081] Figure 4 is a schematic diagram of a structure after forming a conductive filling layer in a specific embodiment of the present invention. Figure 4 As shown, the specific steps of forming a conductive filling layer that fills the storage hole and covers the storage structure include:

[0082] Metal tungsten is deposited on the substrate to form the conductive filling layer 40 that continuously covers the upper electrode layer 33 in the storage hole 22 and the upper electrode layer 33 on the top surface of the first dielectric layer 21 .

[0083] Specifically, an atomic layer deposition process may be used to deposit metal tungsten onto the substrate to form the conductive filling layer 40 that continuously covers the upper electrode layer 33 in the storage hole 22 and the upper electrode layer 33 on the top surface of the first dielectric layer 21. The conductive filling layer 40 is in electrical contact with the upper electrode layer 33 to lead out the signal of the upper electrode layer 33.

[0084] Figure 5 is a schematic diagram of a structure after the conductive filling layer and the storage structure on the top surface of the first dielectric layer are removed by a grinding process in a specific embodiment of the present invention. Figure 5As shown, the specific steps of removing the conductive filling layer 40 and the storage structure located above the first dielectric layer 21 by a grinding process include:

[0085] Using a first grinding process to remove at least the conductive filling layer 40 and the upper electrode layer 33 located on the top surface of the first dielectric layer 21;

[0086] A second grinding process is used to remove at least the storage layer 32 and the lower electrode layer 31 located on the top surface of the first dielectric layer 21 .

[0087] In some embodiments, the specific steps of removing at least the conductive filling layer 40 and the upper electrode layer 33 located on the top surface of the first dielectric layer 21 by using the first grinding process include:

[0088] The conductive filling layer 40 and the upper electrode layer 33 located on the top surface of the first dielectric layer 21 are removed by adopting a first grinding process and using the storage layer 32 as a grinding stop layer.

[0089] In some embodiments, the specific steps of using the second grinding process to remove at least the storage layer 32 and the lower electrode layer 31 located on the top surface of the first dielectric layer 21 include:

[0090] The storage layer 32 and the lower electrode layer 31 located on the top surface of the first dielectric layer 21 are completely removed by adopting a second grinding process and adjusting the grinding time.

[0091] For example, the first grinding process is a first chemical mechanical grinding process. The first chemical mechanical grinding process is used to completely remove the conductive filling layer 40 and the upper electrode layer 33 located on the top surface of the first dielectric layer 21 with the storage layer 32 as the grinding cut-off layer, and the conductive filling layer 40 and the upper electrode layer 33 above the storage hole 22 are removed at the same time to expose the storage layer 32. In one example, the sum of the thickness of the conductive filling layer 40 and the thickness of the upper electrode layer 33 removed by the first grinding process is The second grinding process is a second chemical mechanical grinding process. The second chemical mechanical grinding process is adopted and the first dielectric layer 21 is used as a grinding cut-off layer to remove the storage layer 32 and the lower electrode layer 31 located on the top surface of the first dielectric layer 21. By adjusting the grinding time of the second chemical mechanical grinding process, the storage layer 32 and the lower electrode layer 31 located on the top surface of the first dielectric layer 21 can be completely removed while avoiding damage to the first dielectric layer 21. In an example, after the first grinding process and the second grinding process are completed, the storage structure and the conductive filling layer 40 on the top surface of the first dielectric layer 21 are completely removed, and the top surface of the lower electrode layer 31, the top surface of the storage layer 32, the top surface of the upper electrode layer 33, and the top surface of the conductive filling layer 40 remaining in the storage hole 22 are all flush with the top surface of the first dielectric layer 21. This specific embodiment adopts a two-step grinding process (i.e., the first grinding process and the second grinding process), which can not only further ensure the complete removal of the conductive filling layer 40 and the storage structure on the top surface of the first dielectric layer 21, but also avoid damage to the first dielectric layer 21 and the storage structure and the conductive filling layer 40 in the storage hole 22, thereby further improving the performance of the ferroelectric memory.

[0092] Figure 6 is a schematic diagram of a structure after forming a second dielectric layer in a specific embodiment of the present invention, Figure 7: is a schematic diagram of a structure after the first lead-out structure is formed in a specific embodiment of the present invention. Specifically, after removing the conductive filling layer 40 and the storage structure on the top surface of the first dielectric layer 21, an insulating material such as silicon dioxide is deposited on the substrate to form the second dielectric layer 60 that continuously covers the remaining storage structure and the conductive filling layer in the storage hole 22, as well as the top surface of the first dielectric layer 21. Afterwards, the second dielectric layer 60 can be planarized by chemical mechanical polishing or other methods. During the planarization process, the thickness of the remaining second dielectric layer 60 after polishing can be controlled by controlling the polishing time to fully protect the storage structure. Next, a mask layer 70 is formed on the second dielectric layer 60, and a patterned photoresist layer 71 is formed on the mask layer 70, wherein the photoresist layer 71 has a first etching window 72 and a second etching window 73 that expose the mask layer 70. The mask layer 70 and the second dielectric layer 60 are etched downward along the first etching window 72, and the mask layer 70, the second dielectric layer 60, the first dielectric layer 21 and the fourth dielectric layer 25 are etched downward along the second etching window 73 to form a first lead-out hole exposing the conductive filling layer 40 and a second lead-out hole exposing the second contact structure 24. At the same time, a conductive material such as metal tungsten is filled into the first lead-out hole and the second lead-out hole to form the first lead-out structure 80 electrically connected to the conductive filling layer 40 and the second lead-out structure 81 electrically connected to the second contact structure 24.

[0093] Figure 8 is another structural schematic diagram after a lower electrode layer is formed in a storage hole in a specific embodiment of the present invention, Fig. 9 is another structural schematic diagram after the lower electrode layer is etched back in a specific embodiment of the present invention, Fig.10 FIG. 1 is another schematic diagram of a structure after a storage structure and a conductive filling layer are formed in a storage hole in a specific embodiment of the present invention. Figure 8 , Fig. 9 and Fig.10 As shown, the specific steps of forming the substrate include:

[0094] forming a first dielectric layer 21;

[0095] Etching the first dielectric layer 21 to form the storage hole 22 penetrating the first dielectric layer 21 along the first direction D1;

[0096] forming a lower electrode layer 31 covering the inner wall of the storage hole 22 and the top surface of the first dielectric layer 21;

[0097] Etch back part of the lower electrode layer 31, completely remove the lower electrode layer 31 on the top surface of the first dielectric layer 21 and part of the lower electrode layer 31 in the storage hole 22, and the top surface of the remaining lower electrode layer 31 in the storage hole 22 is lower than the top surface of the first dielectric layer 21;

[0098] forming a storage layer 32 that continuously covers the top surface of the first dielectric layer 21, the inner wall of the storage hole 22, and the surface of the lower electrode layer 31;

[0099] An upper electrode layer 33 is formed to cover the storage layer 32 . The lower electrode layer 31 , the storage layer 32 and the upper electrode layer 33 together constitute the storage structure.

[0100] Specifically, by etching back the lower electrode layer 31 after depositing the lower electrode layer 31 and before depositing the storage layer 32, not only can the connection between the lower electrode layers 31 in adjacent storage structures be fully cut off, but the lower electrode layer 31 and the upper electrode layer 33 in the same storage structure can also be isolated through the subsequently deposited storage layer 32, thereby fully avoiding the leakage problem between the lower electrode layer 31 and the upper electrode layer 33 in the same storage structure.

[0101] In some other embodiments, the specific steps of etching back part of the lower electrode layer 31 include:

[0102] The portion of the lower electrode layer 31 in the storage hole 22 is etched through multiple lateral etching processes to reduce the inclination angle of the top surface of the lower electrode layer 31 .

[0103] Specifically, by etching the portion of the lower electrode layer 31 in the storage hole 22 through multiple lateral etching processes, the inclination angle of the top surface of the lower electrode layer 31 is reduced, which can reduce the tip discharge effect of the lower electrode layer 31, thereby further improving the performance of the ferroelectric memory. The multiple times mentioned in this specific embodiment refers to more than twice.

[0104] Fig.11 is another structural schematic diagram of a specific embodiment of the present invention after the conductive filling layer and the storage structure on the top surface of the first dielectric layer are removed by a grinding process. Fig.11 As shown, the specific steps of removing the conductive filling layer 40 and the storage structure located above the first dielectric layer 21 by a grinding process include:

[0105] Using a first grinding process to remove at least the conductive filling layer 40 and the upper electrode layer 33 located on the top surface of the first dielectric layer 21;

[0106] The third grinding process is used to remove at least the storage layer 32 located on the top surface of the first dielectric layer 21 .

[0107] For example, the first grinding process is a first chemical mechanical grinding process. The first chemical mechanical grinding process is used to completely remove the conductive filling layer 40 and the upper electrode layer 33 located on the top surface of the first dielectric layer 21 with the storage layer 32 as the grinding cut-off layer, and the conductive filling layer 40 and the upper electrode layer 33 above the storage hole 22 are removed at the same time to expose the storage layer 32. The third grinding process is a third chemical mechanical grinding process. The third chemical mechanical grinding process is used to remove the storage layer 32 located on the top surface of the first dielectric layer 21 with the first dielectric layer 21 as the grinding cut-off layer. By adjusting the grinding time of the third chemical mechanical grinding process, it is possible to completely remove the storage layer 32 located on the top surface of the first dielectric layer 21 while avoiding damage to the first dielectric layer 21. In one example, after the first grinding process and the third grinding process are completed, the storage structure and the conductive filling layer 40 on the top surface of the first dielectric layer 21 are completely removed, and the top surface of the storage layer 32, the top surface of the upper electrode layer 33, and the top surface of the conductive filling layer 40 remaining in the storage hole 22 are all flush with the top surface of the first dielectric layer 21.

[0108] Fig.12 is another structural schematic diagram after the first lead-out structure is formed in a specific embodiment of the present invention. In other embodiments, such as Fig.12 As shown, the specific steps of forming the second dielectric layer 60 covering the substrate and the first lead-out structure 80 penetrating the second dielectric layer 60 and electrically connected to the remaining conductive filling layer 40 in the storage hole 22 include:

[0109] forming a third dielectric layer 120 covering the substrate, the storage structure and the conductive filling layer 40;

[0110] forming the second dielectric layer 60 covering the third dielectric layer 120;

[0111] Forming a first lead-out hole that continuously penetrates the second dielectric layer 60 and the third dielectric layer 120 and exposes the conductive filling layer 40;

[0112] A conductive material is filled into the first lead-out hole to form the first lead-out structure 80 electrically connected to the conductive filling layer 40 .

[0113] For example, after removing the conductive filling layer 40 and the storage structure on the top surface of the first dielectric layer 21, a silicon nitride material is first deposited on the substrate to form the third dielectric layer 120 that continuously covers the remaining storage structure and the conductive filling layer in the storage hole 22, as well as the top surface of the first dielectric layer 21. Then, silicon dioxide is deposited on the third dielectric layer 120 to form the second dielectric layer 60. Then, a first lead-out hole is formed through the second dielectric layer 60 and the third dielectric layer 120 and exposes the conductive filling layer 40 by an etching process, and a second lead-out hole is formed through the second dielectric layer 60, the third dielectric layer 120, the first dielectric layer 21 and the fourth dielectric layer 25 and exposes the second contact structure 24. At the same time, a conductive material such as metal tungsten is filled into the first lead-out hole and the second lead-out hole to form the first lead-out structure 80 electrically connected to the conductive filling layer 40 and the second lead-out structure 81 electrically connected to the second contact structure 24.

[0114] This specific embodiment also provides a ferroelectric memory. The ferroelectric memory provided in this specific embodiment can be used as follows Figure 1-Figure 12 The ferroelectric memory is formed by the manufacturing method shown in FIG. The structural schematic diagram of the ferroelectric memory can be seen in FIG. Figure 7 and Fig.12 .like Figure 1-Figure 12 As shown, the ferroelectric memory comprises:

[0115] A substrate, the substrate comprising a first dielectric layer 21 and a storage hole 22 penetrating the first dielectric layer 21 along a first direction D1, the first dielectric layer 21 comprising a top surface and a bottom surface that are relatively distributed, and the first direction D1 intersects the top surface of the first dielectric layer 21 perpendicularly;

[0116] A storage structure, covering the inner wall of the storage hole 22, and the top surface of the storage structure is lower than or flush with the top surface of the first dielectric layer 21;

[0117] A conductive filling layer 40, which fills the storage hole 22 and covers the surface of the storage structure, and the top surface of the conductive filling layer 40 is flush with the top surface of the storage structure;

[0118] A second dielectric layer 60, covering the substrate;

[0119] The first lead-out structure 80 penetrates the second dielectric layer 60 along the first direction D1 and is electrically connected to the conductive filling layer 40 .

[0120] Specifically, by making the top surface of the storage structure lower than or flush with the top surface of the first dielectric layer 21, the adjacent storage structures can be fully isolated, thereby improving the electrical performance of the ferroelectric memory. Moreover, the storage structure and the conductive filling layer on the top surface of the first dielectric layer can be fully removed by the grinding process, which helps to reduce the distance between adjacent storage structures, thereby increasing the number of storage structures to improve the integration of the ferroelectric memory. The top surface of the storage structure described in this specific embodiment is lower than or flush with the top surface of the first dielectric layer 21, which means that at least part of the top surface of the storage structure is lower than or flush with the top surface of the first dielectric layer 21.

[0121] In some embodiments, the storage structure includes a lower electrode layer 31, a storage layer 32 covering a surface of the lower electrode layer 31, and an upper electrode layer 33 covering a surface of the storage layer 32;

[0122] The conductive filling layer 40 covers the surface of the upper electrode layer 33 and is in contact with and electrically connected to the upper electrode layer 33 .

[0123] In some embodiments, the top surface of the lower electrode layer 31, the top surface of the storage layer 32, the top surface of the upper electrode layer 33 and the top surface of the conductive filling layer 40 are flush with each other. Figure 7 shown.

[0124] In some embodiments, the top surface of the lower electrode layer 31 is lower than the top surface of the first dielectric layer 21, and the storage layer 32 continuously covers the side wall of the storage hole 22 and the surface of the lower electrode layer 31 away from the side wall of the storage hole 22;

[0125] The top surface of the storage layer 32, the top surface of the upper electrode layer 33 and the top surface of the conductive filling layer 40 are flush. With the above structure, the lower electrode layer 31 and the upper electrode layer 33 in the storage structure can be fully isolated by the second dielectric layer 60, so as to avoid leakage inside the storage structure, thereby further improving the performance of the ferroelectric memory.

[0126] The ferroelectric memory and its manufacturing method provided in this specific embodiment, after forming a conductive filling layer that fills the storage hole and covers the storage structure, uses a grinding process to remove the conductive filling layer and the storage structure located above the first dielectric layer, so that not only can the adjacent storage structures be fully separated to improve the electrical performance of the ferroelectric memory, but also no photomask is required, saving the manufacturing cost of the ferroelectric memory and simplifying the manufacturing process of the ferroelectric memory. Moreover, the storage structure and the conductive filling layer on the top surface of the first dielectric layer can be fully removed by the grinding process, which helps to reduce the distance between adjacent storage structures, thereby increasing the number of storage structures and improving the integration of the ferroelectric memory. At the same time, this specific embodiment, by etching back the deposited lower electrode layer before depositing the storage layer in the storage structure, can fully isolate the lower electrode layer and the upper electrode layer in the storage structure through the subsequently deposited storage layer, thereby avoiding the leakage problem between the lower electrode layer and the upper electrode layer.

[0127] The above is only a preferred embodiment of the present invention. It should be pointed out that ordinary technicians in this technical field can make several improvements and modifications without departing from the principle of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A method for manufacturing a ferroelectric memory, characterized in that: The steps include: forming a substrate, the substrate comprising a first dielectric layer, a storage hole penetrating the first dielectric layer along a first direction, and a storage structure covering an inner wall of the storage hole and a top surface of the first dielectric layer, the first dielectric layer comprising a top surface and a bottom surface that are relatively distributed, and the first direction intersects the top surface of the first dielectric layer perpendicularly; forming a conductive filling layer that fills the storage hole and covers the storage structure; Using a grinding process to remove the conductive filling layer and the storage structure located above the first dielectric layer; A second dielectric layer covering the substrate and a first lead-out structure penetrating the second dielectric layer and electrically connected to the remaining conductive filling layer in the storage hole are formed.

2. The method for manufacturing a ferroelectric memory according to claim 1, characterized in that: The specific steps of forming the substrate include: forming a first dielectric layer; Etching the first dielectric layer to form the storage hole penetrating the first dielectric layer along a first direction; forming a lower electrode layer covering the inner wall of the storage hole and the top surface of the first dielectric layer; forming a storage layer covering the lower electrode layer; An upper electrode layer covering the storage layer is formed, and the lower electrode layer, the storage layer and the upper electrode layer together constitute the storage structure.

3. The method for manufacturing a ferroelectric memory according to claim 2, wherein: The specific steps of forming a conductive filling layer that fills the storage hole and covers the storage structure include: Metal tungsten is deposited on the substrate to form the conductive filling layer that continuously covers the upper electrode layer in the storage hole and the upper electrode layer on the top surface of the first dielectric layer.

4. The method for manufacturing a ferroelectric memory according to claim 2, wherein: The specific steps of removing the conductive filling layer and the storage structure located above the first dielectric layer by a grinding process include: Using a first grinding process to remove at least the conductive filling layer and the upper electrode layer located on the top surface of the first dielectric layer; A second grinding process is used to remove at least the storage layer and the lower electrode layer located on the top surface of the first dielectric layer.

5. The method for manufacturing a ferroelectric memory according to claim 4, characterized in that: The specific steps of removing at least the conductive filling layer and the upper electrode layer located on the top surface of the first dielectric layer by using the first grinding process include: The conductive filling layer and the upper electrode layer located on the top surface of the first dielectric layer are removed by adopting a first grinding process and using the storage layer as a grinding cut-off layer.

6. The method for manufacturing a ferroelectric memory according to claim 4, characterized in that: The specific steps of removing at least the storage layer and the lower electrode layer located on the top surface of the first dielectric layer by using the second grinding process include: The storage layer and the lower electrode layer located on the top surface of the first dielectric layer are completely removed by adopting a second grinding process and adjusting the grinding time.

7. The method for manufacturing a ferroelectric memory according to claim 1, characterized in that: The specific steps of forming the substrate include: forming a first dielectric layer; Etching the first dielectric layer to form the storage hole penetrating the first dielectric layer along a first direction; forming a lower electrode layer covering the inner wall of the storage hole and the top surface of the first dielectric layer; Etching back part of the lower electrode layer to completely remove the lower electrode layer on the top surface of the first dielectric layer and part of the lower electrode layer in the storage hole, wherein the top surface of the remaining lower electrode layer in the storage hole is lower than the top surface of the first dielectric layer; forming a storage layer that continuously covers the top surface of the first dielectric layer, the inner wall of the storage hole, and the surface of the lower electrode layer; An upper electrode layer covering the storage layer is formed, and the lower electrode layer, the storage layer and the upper electrode layer together constitute the storage structure.

8. The method for manufacturing a ferroelectric memory according to claim 7, characterized in that: The specific steps of etching back part of the lower electrode layer include: A portion of the lower electrode layer in the storage hole is etched by multiple lateral etching processes to reduce the inclination angle of the top surface of the lower electrode layer.

9. The method for manufacturing a ferroelectric memory according to claim 7, characterized in that: The specific steps of removing the conductive filling layer and the storage structure located above the first dielectric layer by a grinding process include: Using a first grinding process to remove at least the conductive filling layer and the upper electrode layer located on the top surface of the first dielectric layer; A third grinding process is used to remove at least the storage layer located on the top surface of the first dielectric layer.

10. The method for manufacturing a ferroelectric memory according to claim 1, characterized in that: The specific steps of forming a second dielectric layer covering the substrate and a first lead-out structure penetrating the second dielectric layer and electrically connected to the remaining conductive filling layer in the storage hole include: forming a third dielectric layer covering the substrate, the storage structure and the conductive filling layer; forming the second dielectric layer covering the third dielectric layer; Forming a first lead-out hole that continuously penetrates the second dielectric layer and the third dielectric layer and exposes the conductive filling layer; Filling the first lead-out hole with a conductive material to form the first lead-out structure electrically connected to the conductive filling layer.

11. A ferroelectric memory, characterized in that: include: The substrate comprises a first dielectric layer and a storage hole penetrating the first dielectric layer along a first direction, the first dielectric layer comprises a top surface and a bottom surface that are relatively distributed, and the first direction is parallel to the first dielectric layer. The top surface of the first dielectric layer intersects vertically; A storage structure, covering the inner wall of the storage hole, wherein the top surface of the storage structure is lower than or flush with the top surface of the first dielectric layer; A conductive filling layer, which fills the storage hole and covers the surface of the storage structure, and the top surface of the conductive filling layer is flush with the top surface of the storage structure; A second dielectric layer covering the substrate; The first lead-out structure penetrates the second dielectric layer along the first direction and is electrically connected to the conductive filling layer.

12. The ferroelectric memory according to claim 11, characterized in that: The storage structure includes a lower electrode layer, a storage layer covering a surface of the lower electrode layer, and an upper electrode layer covering a surface of the storage layer; The conductive filling layer covers the surface of the upper electrode layer and is in contact with and electrically connected to the upper electrode layer.

13. The ferroelectric memory according to claim 12, characterized in that: The top surface of the lower electrode layer, the top surface of the storage layer, the top surface of the upper electrode layer and the top surface of the conductive filling layer are flush.

14. The ferroelectric memory according to claim 12, wherein: The top surface of the lower electrode layer is lower than the top surface of the first dielectric layer, and the storage layer continuously covers the side wall of the storage hole and the surface of the lower electrode layer away from the side wall of the storage hole; The top surface of the storage layer, the top surface of the upper electrode layer and the top surface of the conductive filling layer are flush.

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