Processing method of ultra-low VF plane Schottky diode
By using specific steps such as propulsion oxidation and barrier cleaning during the processing of Schottky diodes, the problem of high forward voltage drop at high current density is solved. Achieve lower circuit conduction loss and is suitable for low power applications.
Patent Information
- Application Number
- CN202411754310.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-02
- Publication Date
- 2025-01-10
AI Technical Summary
The current 30V Schottky diode cannot be at a current density of 450A/cm2, which leads to high circuit conduction loss and is difficult to meet the needs of low-power applications.
Using an ultra-low VF plane Schottky diode processing method, including preparing an N-epitaxial layer and a silica oxide layer on an N+ substrate, forming a protective ring and an active region through photolithography, and injecting B elements And the propulsion oxidation process was carried out, barrier cleaning was performed using 3# liquid, HF and hydrofluoric acid mist to form a Ti-Si barrier, and then barrier sputtering, depositing the front metal TiNiAl, and was carried out through multiple photolithography. Metal corrosion, eventually thinning and depositing the alloy on the back.
It realizes the forward voltage drop to 400-450mV at a current density of 450A/cm2, effectively reducing circuit conduction loss, and is suitable for low-power applications.
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Figure CN119300369A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for processing an ultra-low VF planar Schottky diode. Background Art
[0002] Schottky diodes, also known as Schottky barrier diodes (SBD for short), are low-power, ultra-high-speed semiconductor devices. The most notable feature is that the reverse recovery time is extremely short (can be as short as a few nanoseconds), and the forward conduction voltage drop is only about 0.4V. They are mostly used as high-frequency, low-voltage, high-current rectifier diodes, freewheeling diodes, and protection diodes. They are also used as rectifier diodes and small-signal detector diodes in microwave communication circuits. They are more common in communication power supplies, inverters, etc.
[0003] At present, most planar process Schottky diode products use Ni, NiPt, Pt and other barrier metals. Such barrier Schottky diode products have moderate forward and reverse characteristics and are suitable for systems with medium and high operating temperatures. However, the forward VF of the 30V Schottky diode currently produced is 500mV at a current density of 450 A / cm2. For products that focus on forward applications, the VF needs to be as low as possible, which can reduce the power consumption of the product. Summary of the invention
[0004] In view of the above problems, the present invention provides a method for 2 A processing method for an ultra-low VF planar Schottky diode with a forward voltage drop of 400-450mV, which effectively reduces the conduction loss of the circuit.
[0005] The technical solution of the present invention is: A method for processing an ultra-low VF planar Schottky diode comprises the following steps: Step 1, sequentially preparing an N- epitaxial layer and a silicon dioxide oxide layer on an N+ substrate; Step 2, forming a protection ring on the silicon dioxide oxide layer by etching a pattern using a photoresist; Step 3, injecting B element into the guard ring and performing a push oxidation process; Step 4, etching the silicon dioxide oxide layer through a second photoresist pattern to form an active area; and Step 5: Use 3# liquid, HF and hydrofluoric acid mist to clean the barrier; 3# liquid includes H2SO4 solution and H2O2 solution, and the ratio is H2SO4:H2O2=5:1~2:1; Liquid 3# removes organic matter, HF removes the natural oxide layer, and hydrofluoric acid mist removes the tiny water droplets left by cleaning to obtain a clean Si interface; Among them, the reason for residual water stains: during barrier cleaning, the suspended silicon atoms will react with water to form amorphous soluble silica gel. After the residual water droplets evaporate, silica gel and SiO2 will be left on the silicon surface. Si+O2->SiO2 SiO2+H2O->H2SiO3 H2SiO3->H + +HSiO3 - When using hydrofluoric acid mist, SiO2+HF in the water stain will continue to react to generate SiF4 gas and water, and H2SO3 and HF will react to generate an easily decomposable substance, which is also a gas after decomposition; Step six, barrier sputtering to form a Ti-Si barrier; Step 7, depositing front metal TiNiAl; Step eight, using the three patterns of the photomask to perform metal etching on the front side; Step nine, using the photomask four pattern to perform barrier metal etching; Step 10, back side thinning, deposition and alloying.
[0006] Specifically, in step three, the B element injection energy is 60KEV, and the injection dose is 2E14-4E14.
[0007] Specifically, the oxidation process in step 3 includes: A. Send the ion-implanted wafer to an oxidation furnace tube at a temperature of 750°C, introduce oxygen, then raise the temperature to 950°C, introduce hydrogen to grow a silicon dioxide oxide film; B. Raise the temperature to 1050°C and continue for 145 minutes; C. Cool down to 950°C, introduce hydrogen and oxygen, and superimpose with step a to form a 4KÅ silicon dioxide oxide film; D. Cool down to 750℃ and take out of the furnace.
[0008] Specifically, step four includes: The silicon dioxide layer is coated, exposed and developed to form a photoresist pattern on the photoresist. The thickness of the photoresist is 14000Å. The silicon dioxide is etched by wet etching process to form an active area, and then the photoresist is removed. The silicon dioxide is removed by BOE etching solution, and the photoresist is removed by concentrated sulfuric acid.
[0009] Specifically, the ratio of the BOE etching solution is: 6 Vol NH4F (40%): 1 Vol HF (49%).
[0010] BOE: Buffered oxide film etchant, the commonly used ratio is 6Vol NH4F (40%): 1Vol HF (49%), mainly using NH4F to buffer and stabilize the etching rate of HF: 6HF+SiO2→ H2SiF6+2H2O SiO2+4HF+2NH4F → (NH4)2SiF6+ 2H2O Specifically, step six includes depositing a Ti barrier metal layer with a thickness of 500Å on the wafer, and then performing rapid annealing at 620-700°C for 60s in a nitrogen atmosphere by RTP to form a Ti-Si barrier.
[0011] Specifically, in the sputtering process, Ti is rapidly annealed at a temperature of 620-700°C.
[0012] Specifically, step nine includes: Four-pass photolithography: The metal is coated, exposed and developed to form four photoresist patterns on the photoresist, and the thickness of the photoresist is 30,000Å; Barrier metal etching: TiN and Ti metal are etched by wet method, followed by organic stripping.
[0013] Specifically, the TiN is corroded by using SC1 solution; and the Ti metal is removed by using PBE solution.
[0014] Specifically, the SC1 solution includes NH4OH:H2O2:H20=1:2:7, and the reaction equation is as follows: TiN+3H2O+H2O2->TiO ++ +3OH - +NH4OH; The PBE solution includes 8.9% HNO3, 3.7% CH3COOH, and 2.02% HF, and the reaction equation is as follows: Ti+6HF=H2TIF6+2H2 Ti+4H++6HF2-=(TIF6)2-+2H2+6HF; Planar Schottky Ti barrier currently uses Ti silicide as the barrier contact layer. The silicide barrier layer with uniform thickness and consistent composition is the key to determining product parameter performance and reliability. The present invention adopts 3# (sulfuric acid and hydrogen peroxide) + HF + HFFUME cleaning method to clean the contact interface between Ti and Si, and adopts a rapid annealing process with precise temperature and time to make the thickness uniformity of the barrier silicide good. BRIEF DESCRIPTION OF THE DRAWINGS
[0015] Figure 1 is a schematic diagram of the structure of the wafer after oxidation in step 1; Figure 2This is a schematic diagram of the structure of the wafer after the first photolithography step in step 2 is completed; Figure 3 This is a schematic diagram of the structure of the wafer after one-time etching and degumming in step 2; Figure 4 This is a schematic diagram of the structure of the wafer after ion implantation in step three; Figure 5 Schematic diagram of the structure of the wafer after push-in oxidation in step three; Figure 6 This is a schematic diagram of the structure after the second photolithography step of the wafer in step 4 is completed; Figure 7 This is a schematic diagram of the structure of the wafer after secondary etching and degumming in step 4; Figure 8 It is a schematic diagram of the structure after the wafer is sputtered and the barrier alloy is formed in step six; Fig. 9 is a schematic diagram of the structure after metal deposition on the front side of the wafer in step seven; Fig.10 This is a schematic diagram of the structure of the wafer after three photolithography steps in step eight are completed; Fig.11 This is a schematic diagram of the structure after the metal corrosion and debonding of the front side of the wafer in step eight; Fig.12 This is a schematic diagram of the structure of the wafer after four photolithography steps in step nine; Fig.13 1 is a schematic diagram of the structure after the wafer barrier metal is corroded and stripped in step nine; Fig.14 is a schematic diagram of the structure after the back side of the wafer is thinned in step ten; Fig.15 It is a schematic diagram of the structure of the wafer back gold deposition and alloy in step ten. DETAILED DESCRIPTION
[0016] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and cannot be understood as limiting the present invention.
[0017] Reference below Figure 1-15 describe the invention; A method for processing an ultra-low VF planar Schottky diode comprises the following steps: Step 1: Prepare an N-epitaxial layer and a silicon dioxide oxide layer on an N+ substrate in sequence; Figure 1 As shown; Specifically, the preparation of the silicon dioxide oxide film is a primary oxidation: the wafer is sent to a 1000°C oxidation furnace tube to form a 6-7KÅ silicon dioxide oxide film on the epitaxial layer; Step 2: forming a protection ring on the silicon dioxide oxide layer by etching a pattern using a photoresist; Figure 2-3 As shown; Specifically, one-step photolithography: coating, exposing, and developing on the silicon dioxide layer to form a photoresist pattern on the photoresist; One-step etching and photoresist removal: Use a wet etching process to etch silicon dioxide to form a guard ring, and then remove the photoresist.
[0018] Step 3: injecting B element into the guard ring and performing a push oxidation process; Figure 4-5 As shown; Specifically, the B element implantation energy is 60KEV, and the implantation dose is 2E14-4E14.
[0019] The advanced oxidation process includes: A. Send the ion-implanted wafer to an oxidation furnace tube at a temperature of 750°C, introduce oxygen, then raise the temperature to 950°C, introduce hydrogen to grow a silicon dioxide oxide film; B. Raise the temperature to 1050°C and continue for 145 minutes; C. Cool down to 950°C, introduce hydrogen and oxygen, and superimpose with step a to form a 4KÅ silicon dioxide oxide film; D. Cool down to 750℃ and take out of the furnace.
[0020] Step 4, etching the silicon dioxide oxide layer through a second photoresist pattern to form an active area; Specific: Secondary photolithography: The second photolithography pattern is formed on the photoresist by coating, exposing and developing on the silicon dioxide layer. The thickness of the photoresist is 14000Å. Figure 6 As shown; Secondary etching and de-gumming: Use wet etching process to etch silicon dioxide to form active area, then remove photoresist, remove silicon dioxide through BOE (main components are NH4F and HF), and remove photoresist with concentrated sulfuric acid, refer to Figure 7 As shown; Step 5: Use 3# liquid + HF + hydrofluoric acid mist to clean the barrier; Liquid 3# removes organic matter, HF removes the natural oxide layer, and hydrofluoric acid mist removes the tiny water droplets left by cleaning to obtain a clean Si interface.
[0021] The ratio of 3# liquid is: H2SO4:H2O2=5:1-2:1; Reasons for residual water stains: During barrier cleaning, the suspended silicon atoms react with water to form amorphous soluble silica gel. After the residual water droplets evaporate, silica gel and SiO2 will be left on the silicon surface. Si+O2->SiO2 SiO2+H2O->H2SiO3 H2SiO3->H + +HSiO3 - Using hydrofluoric acid mist, SiO2+HF in the water stains will continue to react to generate SiF4 gas and water, and H2SO3 and HF will react to generate an easily decomposable substance, which is also a gas after decomposition.
[0022] Step six, barrier sputtering to form a Ti-Si barrier; Specifically, a Ti barrier metal layer with a thickness of 500Å was deposited on the wafer by a sputtering process, and then a rapid annealing at 620-700°C for 60s was performed in a nitrogen atmosphere by RTP to form a Ti-Si barrier; Sputtering: Argon gas is glow-discharged in a vacuum chamber to generate positive ions (Ar+). Ar+ is attracted to the cathode of the target material and bombards the target material at high speed, causing the target atoms to be sputtered out and deposited on the surface of the wafer. RTP annealing: Annealing temperature is a key parameter that affects the performance of ohmic contacts. Appropriate annealing temperature can reduce the specific contact resistivity between the metal electrode and the semiconductor. Using 620~700℃ for Ti can obtain a lower potential barrier than Ni, thereby reducing VF. Figure 8 As shown; Step 7, depositing front metal TiNiAl; By metal evaporation, a 3.9um thick front metal TiNiAl is deposited on the front of the wafer to facilitate packaging and protect the barrier metal. Fig. 9 As shown; Step eight, using the three patterns of the photomask to perform metal etching on the front side; Specific: Three-stage photolithography: The three patterns of the photoresist are formed on the metal by coating, exposing and developing. The thickness of the photoresist is 30000Å. Fig.10 As shown; Front metal corrosion: wet etching of AlNiTi metal, followed by organic degumming; The etching solution mainly uses Al etching solution (80% phosphoric acid, 5% acetic acid, 5% nitric acid, and 10% water) to remove Al and Ni; PBE (3.7% glacial acetic acid, 2% nitric acid and 8.9% hydrofluoric acid) was used to remove Ti metal, and EDTA was used to remove free metal ions. Fig.11 As shown; Step nine, using the photomask four pattern to perform barrier metal etching; Specific: Four-pass photolithography: The four-pass photolithography pattern is formed on the photoresist by coating, exposing and developing on the metal. The thickness of the photoresist is 30000Å. Fig.12 As shown; Barrier metal corrosion: TiN and Ti metal are corroded by wet method, and then organic degumming is performed. TiN is mainly corroded by SC1 (ammonia and hydrogen peroxide), and PBE (3.7% glacial acetic acid, 2% nitric acid, 8.9% hydrofluoric acid) is used to remove Ti metal. Fig.13 As shown; Step 10, back side thinning, deposition and alloying.
[0023] Specifically include: Back thinning: The required product thickness is obtained by laminating and mechanical grinding, and then stress is relieved. Stress relief mainly uses Si etching solution (a mixed solution of nitric acid, acetic acid and hydrofluoric acid) to form a relatively smooth surface. Fig.14 As shown; Back gold deposition and alloy: back gold cleaning, film removal, deposition of back metal Au 1.2um, vacuum alloying, forming Au-Si alloy, alloy temperature 400℃-5min, the process is completed.
[0024] The parameters of Ti and Ni barriers and the RTP temperature were experimentally verified using 13mil30V products: As shown in the table above, from the RTP temperature deviation results, the average values of VF@1mA and IR@10V at 620℃-700℃ are 155-155.2mV, 8.9-9.0uA fluctuations, so the formed barrier height is relatively stable, and the Ni barrier is 450A / cm higher than the Ti barrier. 2 Under current density, VF can be as low as about 100mV. For applications with a high forward conduction ratio, this type of device can effectively reduce the conduction loss in the circuit.
[0025] Regarding the contents disclosed in this case, there are a few points that need to be explained: (1) The drawings of the embodiments disclosed in this case only involve the structures involved in the embodiments disclosed in this case. Other structures can refer to the general design; (2) In the absence of conflict, the embodiments and features of the embodiments disclosed in this case may be combined with each other to obtain new embodiments; The above are only specific implementation methods disclosed in this case, but the protection scope of the present disclosure is not limited thereto. The protection scope disclosed in this case should be based on the protection scope of the claims.
Claims
1. A method for processing an ultra-low VF planar Schottky diode, characterized in that: The following steps are involved: Step 1, sequentially preparing an N- epitaxial layer and a silicon dioxide oxide layer on an N+ substrate; Step 2, forming a protection ring on the silicon dioxide oxide layer by etching a pattern using a photoresist; Step 3, injecting B element into the guard ring and performing a push oxidation process; Step 4, etching the silicon dioxide oxide layer through a second photoresist pattern to form an active area; and Step 5: Use 3# liquid, HF and hydrofluoric acid mist to clean the barrier; 3# liquid includes H2SO4 solution and H2O2 solution, and the ratio is H2SO4:H2O2=5:1~2:1; Step six, barrier sputtering to form a Ti-Si barrier; Step 7, depositing front metal TiNiAl; Step eight, using the three patterns of the photomask to perform metal etching on the front side; Step nine, using the photomask four pattern to perform barrier metal etching; Step 10, back side thinning, deposition and alloying.
2. The method for processing an ultra-low VF planar Schottky diode according to claim 1, characterized in that: In step 3, the injection energy of element B is 60KEV, and the injection dose is 2E14-4E14.
3. The method for processing an ultra-low VF planar Schottky diode according to claim 1, characterized in that: The oxidation process in step 3 includes: A. Send the ion-implanted wafer to an oxidation furnace tube at a temperature of 750°C, introduce oxygen, then raise the temperature to 950°C, introduce hydrogen to grow a silicon dioxide oxide film; B. Raise the temperature to 1050°C and continue for 145 minutes; C. Cool down to 950°C, introduce hydrogen and oxygen, and superimpose with step a to form a 4KÅ silicon dioxide oxide film; D. Cool down to 750℃ and take out of the furnace.
4. The method for processing an ultra-low VF planar Schottky diode according to claim 1, characterized in that: Step 4 includes: The silicon dioxide layer is coated, exposed and developed to form a photoresist pattern on the photoresist. The thickness of the photoresist is 14000Å. The silicon dioxide is etched by wet etching process to form an active area, and then the photoresist is removed. The silicon dioxide is removed by BOE etching solution, and the photoresist is removed by concentrated sulfuric acid.
5. The method for processing an ultra-low VF planar Schottky diode according to claim 4, characterized in that: The ratio of the BOE etching solution is: 6Vol NH4F (40%): 1Vol HF (49%).
6. The method for processing an ultra-low VF planar Schottky diode according to claim 1, characterized in that: Step six includes depositing a Ti barrier metal layer with a thickness of 500Å on the wafer, and then performing rapid annealing at 620~700℃ for 60s in a nitrogen atmosphere by RTP to form a Ti-Si barrier.
7. The method for processing an ultra-low VF planar Schottky diode according to claim 6, characterized in that: In the sputtering process, Ti is rapidly annealed at a temperature of 620~700℃.
8. The method for processing an ultra-low VF planar Schottky diode according to claim 1, characterized in that: Step nine includes: Four-pass photolithography: The metal is coated, exposed and developed to form four photoresist patterns on the photoresist, and the thickness of the photoresist is 30,000Å; Barrier metal etching: TiN and Ti metal are etched by wet method, followed by organic stripping.
9. The method for processing an ultra-low VF planar Schottky diode according to claim 8, characterized in that: The TiN is corroded by using SC1 solution; the Ti metal is removed by using PBE solution.
10. The method for processing an ultra-low VF planar Schottky diode according to claim 9, characterized in that: The ratio of the SC1 solution is NH4OH:H2O2:H20=1:2:7.