Manufacturing method of heterojunction transistor

Abstract

The invention discloses a manufacturing method of a heterojunction transistor, and the method comprises the steps: S1, providing a substrate, forming shallow trench isolation in the substrate to define an active region, and forming a first dielectric layer and a second dielectric layer on the surface of the substrate; s2, forming a laminated structure; s3, forming a fifth dielectric layer; s4, removing the fifth dielectric layer and the fourth dielectric layer which are higher than the epitaxial layer; s5, growing an outer base region polycrystalline silicon layer on the remaining fifth dielectric layer, and forming a sixth dielectric layer; s6, removing the third dielectric layer and the sixth dielectric layer on the top of the third dielectric layer to form a second opening; s7, forming a side wall structure; s8, growing a second polycrystalline silicon layer through an epitaxial process, and removing part of the second polycrystalline silicon layer and the sixth dielectric layer to form an emitter; and S9, removing part of the outer base region polycrystalline silicon layer, the fifth dielectric layer, the second dielectric layer and the first dielectric layer to form an HBT device pattern. According to the scheme, the heterojunction transistor can be efficiently manufactured.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor manufacturing, and in particular to a method for manufacturing a heterojunction transistor. Background Art

[0002] Heterojunction Bipolar Transistor (HBT) is a type of bipolar transistor. Its emitter and base regions use different semiconductor materials, so that the emitter junction (i.e., the PN junction between the emitter and base regions) forms a heterojunction. Heterojunction bipolar transistors have better high-frequency signal characteristics and base region emission efficiency than general bipolar transistors, and can operate at signals up to hundreds of GHz.

[0003] SiGe HBT introduces Ge into the base region to form a heterojunction transistor with a wide-bandgap Si emitter region, a narrow-bandgap SiGe base region, and a wide-bandgap Si collector region. Compared with traditional Si BJT, SiGe HBT has higher frequency characteristics, so it has great potential to work in a high-frequency state. Compared with GaAs-based devices, it has the advantages of low cost, good thermal conductivity, and good mechanical properties of the substrate. In particular, it is compatible with mature silicon integration technology and CMOS technology, and has more flexibility in production. Therefore, researchers have been committed to exploring the structure of SiGe HBT. Summary of the invention

[0004] In order to solve the above problems, the present application provides a method for manufacturing a heterojunction transistor.

[0005] The present application provides a method for manufacturing a heterojunction transistor, comprising: S1: providing a substrate, wherein shallow trench isolation is formed in the substrate to define an active area, a first dielectric layer and a second dielectric layer are sequentially formed on the surface of the substrate from bottom to top, and a first opening located above the active area is formed in the first dielectric layer and the second dielectric layer; S2: forming a stacked structure on the first opening, the stacked structure comprising, from bottom to top, an epitaxial layer, a silicon germanium layer, a third dielectric layer and a fourth dielectric layer, the epitaxial layer is used to form a collector, and the silicon germanium layer is used to form a base region; S3: forming a fifth dielectric layer, wherein the fifth dielectric layer covers the stacked structure and the second dielectric layer; S4: etching and removing the fifth dielectric layer and the fourth dielectric layer which are higher than the epitaxial layer; S5: growing an external base region polysilicon layer on the remaining fifth dielectric layer, and forming a sixth dielectric layer on the external base region polysilicon layer and the remaining third dielectric layer; S6: etching and removing the third dielectric layer and the sixth dielectric layer located on the top thereof to form a second opening, wherein the second opening is located above the germanium silicon layer; S7: forming two side wall structures arranged at a relative interval in the second opening; S8: growing a second polysilicon layer by an epitaxial process, and removing a portion of the second polysilicon layer and the sixth dielectric layer by a photolithography and etching process to form an emitter; S9: removing a portion of the external base polysilicon layer, the fifth dielectric layer, the second dielectric layer and the first dielectric layer through photolithography and etching processes to form an HBT device pattern.

[0006] In some embodiments, before S1, the method further includes: S01: providing the substrate, and sequentially growing a first dielectric layer and a second dielectric layer on the surface of the substrate; S02: etching the second dielectric layer by photolithography and etching processes; S03: Etching the first dielectric layer by a wet etching process to form the first opening.

[0007] In some embodiments, the S2 includes: S21: forming an epitaxial layer and a germanium silicon layer in sequence through a one-step epitaxial process; S22: sequentially forming a third dielectric layer and a fourth dielectric layer on the germanium silicon layer; S23: etching the fourth dielectric layer, the third dielectric layer, the germanium silicon layer and the epitaxial layer through photolithography and etching processes to form a stacked structure located above the active area.

[0008] In some embodiments, the S4 includes: S41: Processing the top of the fifth dielectric layer by a chemical mechanical polishing process; S42: etching the top of the fifth dielectric layer and the fourth dielectric layer by a dry etching process; S43: Processing the surface of the remaining fifth dielectric layer by a wet etching process until all the fifth dielectric layers higher than the epitaxial layer are removed.

[0009] In some embodiments, the S6 includes: S61: removing the sixth dielectric layer on the top of the third dielectric layer by photolithography and etching processes; S62: removing the third dielectric layer by a wet etching process to form a second opening.

[0010] In some embodiments, the S7 includes: S71: sequentially forming a seventh dielectric layer and a first polysilicon layer on the silicon germanium layer and the sixth dielectric layer; S72: etching the first polysilicon layer to form a third opening; S73: using the first polysilicon layer as a mask, etching and removing the seventh dielectric layer above the sixth dielectric layer and the seventh dielectric layer below the third opening, and the remaining seventh dielectric layer forms a sidewall structure.

[0011] In some embodiments, the first dielectric layer, the fourth dielectric layer, the fifth dielectric layer, and the sixth dielectric layer are silicon oxide layers, and the second dielectric layer, the third dielectric layer, and the seventh dielectric layer are silicon nitride layers.

[0012] In some embodiments, the epitaxial layer is a phosphorus-doped silicon layer.

[0013] In some embodiments, the extrinsic base polysilicon layer is a polysilicon layer in-situ doped with boron.

[0014] The technical solution of this application has at least the following advantages: 1. A method for efficiently manufacturing a heterojunction transistor is provided, and in this process, the collector and the base region are manufactured by a one-step epitaxial process, and both the collector and the base region are self-aligned with the emitter. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0016] Figure 1 is a flow chart of a method for manufacturing a heterojunction transistor provided by an exemplary embodiment of the present application; Figure 2-14 It is a schematic diagram of the semiconductor structure in each process step of a method for manufacturing a heterojunction transistor provided by an exemplary embodiment of the present application.

[0017] Description of reference numerals: 1, substrate; 101, shallow trench isolation; 2, first dielectric layer; 3, second dielectric layer; 4, epitaxial layer; 5, germanium silicon layer; 6, third dielectric layer; 7, fourth dielectric layer; 8, fifth dielectric layer; 9, external base region polysilicon layer; 10, sixth dielectric layer; 11, seventh dielectric layer; 12, first polysilicon layer; 13, second polysilicon layer; A1, first opening; A2, second opening; A3, third opening. DETAILED DESCRIPTION

[0018] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in this application. Obviously, the described embodiments are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0019] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0020] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, it can also be the internal connection of two components, it can be a wireless connection, or it can be a wired connection. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0021] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0022] The present application provides a method for manufacturing a heterojunction transistor. Referring to the figure, the method mainly comprises the following steps: S1: providing a substrate, in which shallow trench isolation is formed to define an active area, a first dielectric layer and a second dielectric layer are sequentially formed on the surface of the substrate from bottom to top, and a first opening located above the active area is formed in the first dielectric layer and the second dielectric layer.

[0023] S2: forming a stacked structure on the first opening, the stacked structure including an epitaxial layer, a germanium silicon layer, a third dielectric layer and a fourth dielectric layer from bottom to top, the epitaxial layer is used to form a collector, and the germanium silicon layer is used to form a base region.

[0024] S3: forming a fifth dielectric layer, wherein the fifth dielectric layer covers the stacked structure and the second dielectric layer.

[0025] S4: etching and removing the fifth dielectric layer and the fourth dielectric layer which are higher than the epitaxial layer.

[0026] S5: growing an external base polysilicon layer on the remaining fifth dielectric layer, and forming a sixth dielectric layer on the external base polysilicon layer and the remaining third dielectric layer.

[0027] S6: etching and removing the third dielectric layer and the sixth dielectric layer located on the top thereof to form a second opening, wherein the second opening is located above the germanium silicon layer.

[0028] S7: forming two sidewall structures arranged at a relative interval in the second opening.

[0029] S8: growing a second polysilicon layer by an epitaxial process, and removing a portion of the second polysilicon layer and the sixth dielectric layer by photolithography and etching processes to form an emitter.

[0030] S9: removing a portion of the external base polysilicon layer, the fifth dielectric layer, the second dielectric layer and the first dielectric layer through photolithography and etching processes to form an HBT device pattern.

[0031] Specifically, refer to Figure 2~Figure 13 , Figure 2-Figure 13 1 is a schematic diagram of the semiconductor structure in each process step of the method for manufacturing a heterojunction transistor provided in an embodiment of the present application. Next, the method for manufacturing a germanium-silicon heterojunction transistor provided in an embodiment of the present application is described in detail.

[0032] First, execute S1, refer to Figure 2 A substrate 1 is provided, in which a shallow trench isolation 101 is formed, and the area between two shallow trench isolations 101 is defined as an active area. A first dielectric layer 2 and a second dielectric layer 3 are sequentially formed on the surface of the substrate 1 from bottom to top, and a first opening A1 located above the active area is formed in the first dielectric layer 2 and the second dielectric layer 3.

[0033] Preferably, the material of the first dielectric layer 2 is a silicon oxide layer, and the material of the second dielectric layer 3 is a silicon nitride layer.

[0034] Preferably, the following steps may be included before S1 to form the structure in S1: S01: providing a substrate 1, and sequentially growing a first dielectric layer 2 and a second dielectric layer 3 on a surface of the substrate 1.

[0035] Exemplarily, a substrate 1 is provided with a shallow trench isolation 101, and the shallow trench isolation 101 structure defines an active area. Afterwards, a first dielectric layer 2 can be grown on the surface of the substrate 1 by a HDP (High-Density Plasma) process, and then a second dielectric layer 3 can be grown on the first dielectric layer 2 by a FUR process, i.e., a furnace tube growth film layer.

[0036] S02: Etching the second dielectric layer 3 by photolithography and etching processes.

[0037] Exemplarily, the second dielectric layer 3 in a predetermined area is etched by photolithography and etching processes, and the etching stops at the surface of the first dielectric layer 2 .

[0038] S03: Etching the first dielectric layer 2 by a wet etching process to form a first opening A1.

[0039] Exemplarily, the exposed first dielectric layer 2 is etched by a wet etching process, and the etching stays on the surface of the substrate 1, thereby forming Figure 2 The first opening A1 in.

[0040] Afterwards, execute S2, such as Figure 5 As shown, a stacked structure is formed on the first opening A1, and the stacked structure includes an epitaxial layer 4, a germanium silicon layer 5, a third dielectric layer 6 and a fourth dielectric layer 7 from bottom to top. The epitaxial layer 4 is used to form a collector, and the germanium silicon layer 5 is used to form a base region.

[0041] Preferably, the epitaxial layer 4 is made of a silicon layer doped with phosphorus, the third dielectric layer 6 is made of silicon nitride, and the fourth dielectric layer 7 is made of silicon oxide.

[0042] Further, S2 may include the following steps: S21: forming an epitaxial layer 4 and a germanium silicon layer 5 in sequence through a one-step epitaxial process.

[0043] For example, Figure 3 As shown, through a one-step epitaxial process, an N-EPI process, i.e., an N-type epitaxial growth process, is first used to grow an epitaxial layer 4 on the structure formed after S1, and then a No selective EPI process, i.e., a non-selective epitaxial growth process, is used to form a germanium silicon layer 5 on the epitaxial layer 4.

[0044] S22 : forming a third dielectric layer 6 and a fourth dielectric layer 7 in sequence on the silicon germanium layer 5 .

[0045] For example, Figure 4 As shown, the third dielectric layer 6 can be grown on the germanium silicon layer 5 by the FUR process, and then the fourth dielectric layer 7 can be grown on the third dielectric layer 6 by the HDP process.

[0046] S23: etching the fourth dielectric layer 7, the third dielectric layer 6, the germanium silicon layer 5 and the epitaxial layer 4 through photolithography and etching processes to form a stacked structure located above the active area.

[0047] Exemplarily, the fourth dielectric layer 7, the third dielectric layer 6, the germanium silicon layer 5 and the epitaxial layer 4 in the designated area are etched by photolithography and dry etching processes, and the etching stops on the second dielectric layer 3, thereby forming Figure 5 The stacked structure shown in FIG. 1 is a stacked structure. Since the germanium silicon layer 5 and the epitaxial layer 4 are etched in the same step, the subsequent collector and base region are self-aligned. Since there is no second dielectric layer 3 blocking above the first opening A1, the substrate 1 located in the designated area and below the first opening A1 will be over-etched, thereby forming Figure 5 There are two grooves located in the substrate 1.

[0048] After that, execute S3, refer to Figure 6 A fifth dielectric layer 8 is formed on the structure formed after S2 , and the fifth dielectric layer 8 covers the stacked structure and the second dielectric layer 3 .

[0049] Preferably, the fifth dielectric layer 8 is made of silicon oxide, and the fifth dielectric layer 8 can be grown by a HDP process.

[0050] After that, execute S4, refer to Figure 7 , the fifth dielectric layer 8 and the fourth dielectric layer 7 which are higher than the epitaxial layer 4 are etched away.

[0051] Further, S4 may include the following steps: S41: processing the top of the fifth dielectric layer 8 by a chemical mechanical polishing process.

[0052] Exemplarily, the top of the fifth dielectric layer 8 is firstly polished by a chemical mechanical polishing process.

[0053] S42: etching the top of the fifth dielectric layer 8 and the fourth dielectric layer 7 by a dry etching process.

[0054] Exemplarily, the top of the fifth dielectric layer 8 is etched by a dry etching process until the remaining fifth dielectric layer 8 is slightly higher than the top of the epitaxial layer 4, or is flush with the top of the epitaxial layer 4. During this process, the fourth dielectric layer 7 located above the third dielectric layer 6 is also removed.

[0055] S43 : treating the surface of the remaining fifth dielectric layer 8 by a wet etching process until all the fifth dielectric layer 8 higher than the epitaxial layer 4 is removed.

[0056] Exemplarily, the surface of the remaining fifth dielectric layer 8 is processed by a wet etching process, so as to facilitate the growth of the external base region polysilicon layer 9 in a subsequent process.

[0057] After that, execute S5, refer to Figure 8, an external base region polysilicon layer 9 is grown on the remaining fifth dielectric layer 8 , and a sixth dielectric layer 10 is formed on the external base region polysilicon layer 9 and the remaining third dielectric layer 6 .

[0058] Preferably, the material of the external base polysilicon layer 9 may be polysilicon in-situ doped with boron, and the external base polysilicon layer 9 may be grown on the remaining fifth dielectric layer 8 by a selective EPI, i.e., a selective epitaxial growth process. The material of the sixth dielectric layer 10 may be a silicon oxide layer, and the sixth dielectric layer 10 may be grown on the external base polysilicon layer 9 and the remaining third dielectric layer 6 by a HDP process.

[0059] After that, execute S6, refer to Fig. 9 , the third dielectric layer 6 and the sixth dielectric layer 10 located on the top thereof are etched away to form a second opening A2 , and the second opening A2 is located above the germanium silicon layer 5 .

[0060] Further, S6 may include the following steps: S61: removing the sixth dielectric layer 10 on the top of the third dielectric layer 6 by photolithography and etching processes.

[0061] Exemplarily, the sixth dielectric layer 10 located on the top of the third dielectric layer 6 may be removed by photolithography and dry etching processes.

[0062] S62: removing the third dielectric layer 6 by a wet etching process to form a second opening A2.

[0063] Exemplarily, the third dielectric layer 6 is removed by a wet etching process to form Fig. 9 The second opening A2 is shown.

[0064] After that, execute S7, refer to Fig.11 , two sidewall structures arranged at a relative interval are formed in the second opening A2.

[0065] Exemplarily, S7 may include the following steps: S71 : forming a seventh dielectric layer 11 and a first polysilicon layer 12 in sequence on the silicon germanium layer 5 and the sixth dielectric layer 10 .

[0066] Preferably, the seventh dielectric layer 11 is made of silicon nitride layer.

[0067] For example, Fig.10 As shown, the seventh dielectric layer 11 can be grown on the silicon germanium layer 5 and the remaining sixth dielectric layer 10 by a PECVD (Plasma-Enhanced Chemical Vapor Deposition) process. Thereafter, a first polysilicon layer 12 is formed on the seventh dielectric layer 11 .

[0068] S72: etching the first polysilicon layer 12 to form a third opening A3.

[0069] Exemplarily, a dry etching process is used to remove part of the first polysilicon layer 12, and the etching stops at the surface of the seventh dielectric layer 11, forming Fig.10 The third opening A3 is shown.

[0070] S73: using the first polysilicon layer 12 as a mask, etching and removing the seventh dielectric layer 11 above the sixth dielectric layer 10 and the seventh dielectric layer 11 below the third opening, and the remaining seventh dielectric layer 11 forms a sidewall structure.

[0071] Illustratively, the remaining first polysilicon layer 12 is used as a mask and the seventh dielectric layer 11 above the sixth dielectric layer 10 and the seventh dielectric layer 11 below the third opening are removed by a wet etching process, and the remaining seventh dielectric layer 11 constitutes a sidewall structure.

[0072] After that, execute S8, refer to Fig.11 and Fig.12 , a second polysilicon layer 13 is grown by an epitaxial process, and a portion of the second polysilicon layer 13 and the sixth dielectric layer 10 is removed by photolithography and etching processes to form an emitter.

[0073] Exemplarily, the second polysilicon layer 13 is grown by an epitaxial process, and then a portion of the second polysilicon layer 13 and the sixth dielectric layer 10 are removed by photolithography and dry etching processes, and only the second polysilicon layer 13 and the sixth dielectric layer 10 in a predetermined area are retained, and the remaining first polysilicon layer 12 and second polysilicon layer 13 constitute the emitter. The range of the predetermined area is larger than the third opening and smaller than the first opening A1. Since the collector is located within the range of the first opening A1 and the base region is located within the range of the second opening A2, self-alignment of the collector and the base region with the emitter is achieved.

[0074] After that, execute S9, refer to Fig.13 , a portion of the external base polysilicon layer 9, the fifth dielectric layer 8, the second dielectric layer 3 and the first dielectric layer 2 are removed by photolithography and etching processes to form a HBT device pattern.

[0075] Exemplarily, by photolithography and etching processes, a portion of the external base polysilicon layer 9, the fifth dielectric layer 8, the second dielectric layer 3 and the first dielectric layer 2 are removed, and the etching stops on the surface of the substrate 1, and only the external base polysilicon layer 9, the fifth dielectric layer 8, the second dielectric layer 3 and the first dielectric layer 2 in the predetermined area are retained, thereby forming Fig.13 The HBT device diagram shown in FIG. The boundary of the predetermined area in this step is located above the shallow trench isolation 101 .

[0076] The manufacturing method of the heterojunction transistor provided in the embodiment of the present application can complete the production of the collector and the base region through a one-step epitaxial process by sequentially executing the above steps, and the collector and the base region are self-aligned with the emitter, so that the heterojunction transistor can be efficiently manufactured.

[0077] Obviously, the above embodiments are merely examples for the purpose of clear explanation, and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived therefrom are still within the scope of protection created by this application.

Claims

1. A method for manufacturing a heterojunction transistor, characterized in that: include: S1: providing a substrate, wherein shallow trench isolation is formed in the substrate to define an active area, a first dielectric layer and a second dielectric layer are sequentially formed on the surface of the substrate from bottom to top, and a first opening located above the active area is formed in the first dielectric layer and the second dielectric layer; S2: forming a stacked structure on the first opening, the stacked structure comprising, from bottom to top, an epitaxial layer, a silicon germanium layer, a third dielectric layer and a fourth dielectric layer, the epitaxial layer is used to form a collector, and the silicon germanium layer is used to form a base region; S3: forming a fifth dielectric layer, wherein the fifth dielectric layer covers the stacked structure and the second dielectric layer; S4: etching and removing the fifth dielectric layer and the fourth dielectric layer which are higher than the epitaxial layer; S5: growing an external base region polysilicon layer on the remaining fifth dielectric layer, and forming a sixth dielectric layer on the external base region polysilicon layer and the remaining third dielectric layer; S6: etching and removing the third dielectric layer and the sixth dielectric layer located on the top thereof to form a second opening, wherein the second opening is located above the germanium silicon layer; S7: forming two side wall structures arranged at a relative interval in the second opening; S8: growing a second polysilicon layer by an epitaxial process, and removing a portion of the second polysilicon layer and the sixth dielectric layer by a photolithography and etching process to form an emitter; S9: removing a portion of the external base polysilicon layer, the fifth dielectric layer, the second dielectric layer and the first dielectric layer through photolithography and etching processes to form an HBT device pattern.

2. The method for manufacturing a heterojunction transistor according to claim 1, characterized in that: Before the S1, it also includes: S01: providing the substrate, and sequentially growing a first dielectric layer and a second dielectric layer on the surface of the substrate; S02: etching the second dielectric layer by photolithography and etching processes; S03: Etching the first dielectric layer by a wet etching process to form the first opening.

3. The method for manufacturing a heterojunction transistor according to claim 1, characterized in that: The S2 includes: S21: forming an epitaxial layer and a germanium silicon layer in sequence through a one-step epitaxial process; S22: sequentially forming a third dielectric layer and a fourth dielectric layer on the germanium silicon layer; S23: etching the fourth dielectric layer, the third dielectric layer, the germanium silicon layer and the epitaxial layer through photolithography and etching processes to form a stacked structure located above the active area.

4. The method for manufacturing a heterojunction transistor according to claim 1, characterized in that: The S4 includes: S41: Processing the top of the fifth dielectric layer by a chemical mechanical polishing process; S42: etching the top of the fifth dielectric layer and the fourth dielectric layer by a dry etching process; S43: Processing the surface of the remaining fifth dielectric layer by a wet etching process until all the fifth dielectric layers higher than the epitaxial layer are removed.

5. The method for manufacturing a heterojunction transistor according to claim 1, characterized in that: The S6 includes: S61: removing the sixth dielectric layer on the top of the third dielectric layer by photolithography and etching processes; S62: removing the third dielectric layer by a wet etching process to form a second opening.

6. The method for manufacturing a heterojunction transistor according to claim 1, characterized in that: The S7 includes: S71: sequentially forming a seventh dielectric layer and a first polysilicon layer on the silicon germanium layer and the sixth dielectric layer; S72: etching the first polysilicon layer to form a third opening; S73: using the first polysilicon layer as a mask, etching and removing the seventh dielectric layer above the sixth dielectric layer and the seventh dielectric layer below the third opening, and the remaining seventh dielectric layer forms a sidewall structure.

7. The method for manufacturing a heterojunction transistor according to claim 1, characterized in that: The first dielectric layer, the fourth dielectric layer, the fifth dielectric layer, and the sixth dielectric layer are silicon oxide layers, and the second dielectric layer, the third dielectric layer, and the seventh dielectric layer are silicon nitride layers.

8. The method for manufacturing a heterojunction transistor according to claim 1, characterized in that: The epitaxial layer is a phosphorus-doped silicon layer.

9. The method for manufacturing a heterojunction transistor according to claim 1, characterized in that: The external base region polysilicon layer is a polysilicon layer in-situ doped with boron.

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