A method for manufacturing a heterojunction transistor

Abstract

This application discloses a method for manufacturing a heterojunction transistor, comprising: S1: providing a substrate having shallow trench isolation formed therein to define an active area, and forming a first dielectric layer and a second dielectric layer on the substrate surface; S2: forming a stacked structure; S3: forming a fifth dielectric layer; S4: removing the fifth dielectric layer and the fourth dielectric layer above the epitaxial layer; S5: growing an extrinsic base polysilicon layer on the remaining fifth dielectric layer and forming a sixth dielectric layer; S6: removing the third dielectric layer and the sixth dielectric layer located on top thereof to form a second opening; S7: forming a sidewall structure; S8: growing a second polysilicon layer through an epitaxial process, removing a portion of the second polysilicon layer and the sixth dielectric layer to form an emitter; S9: removing a portion of the extrinsic base polysilicon layer, the fifth dielectric layer, the second dielectric layer, and the first dielectric layer to form an HBT device pattern. Through the above-described scheme, this application can efficiently manufacture heterojunction transistors.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor manufacturing, and in particular to a method for manufacturing a heterojunction transistor. Background Art

[0002] A heterojunction bipolar transistor (HBT) is a type of bipolar transistor. Its emitter and base regions use different semiconductor materials, creating a heterojunction at the emitter junction (i.e., the PN junction between the emitter and base regions). Compared to conventional bipolar transistors, HBTs offer improved high-frequency signal characteristics and base region emission efficiency, enabling operation at signals up to hundreds of GHz.

[0003] By introducing Ge into the base region, the SiGe HBT forms a heterojunction transistor with a wide-bandgap Si emitter region, a narrow-bandgap SiGe base region, and a wide-bandgap Si collector region. Compared to traditional Si BJTs, SiGe HBTs have higher frequency characteristics and thus have great potential for high-frequency operation. Compared to GaAs-based devices, they offer advantages such as low cost, good thermal conductivity, and superior substrate mechanical properties. In particular, they are compatible with mature silicon integration and CMOS technologies, offering greater production flexibility. Consequently, researchers have been dedicated to exploring the SiGe HBT structure. Summary of the Invention

[0004] In order to solve the above problems, the present application provides a method for manufacturing a heterojunction transistor.

[0005] The present invention provides a method for manufacturing a heterojunction transistor, comprising:

[0006] S1: Providing a substrate, wherein shallow trench isolation is formed in the substrate to define an active area, and a first dielectric layer and a second dielectric layer are sequentially formed on the surface of the substrate from bottom to top, wherein a first opening is formed in the first dielectric layer and the second dielectric layer and is located above the active area;

[0007] S2: forming a stacked structure on the first opening, the stacked structure comprising, from bottom to top, an epitaxial layer, a silicon-germanium layer, a third dielectric layer, and a fourth dielectric layer, the epitaxial layer being used to form a collector, and the silicon-germanium layer being used to form a base region;

[0008] S3: forming a fifth dielectric layer, wherein the fifth dielectric layer covers the stacked structure and the second dielectric layer;

[0009] S4: etching and removing the fifth dielectric layer and the fourth dielectric layer that are higher than the epitaxial layer;

[0010] S5: growing an external base polysilicon layer on the remaining fifth dielectric layer, and forming a sixth dielectric layer on the external base polysilicon layer and the remaining third dielectric layer;

[0011] S6: etching and removing the third dielectric layer and the sixth dielectric layer located on top of the third dielectric layer to form a second opening, wherein the second opening is located above the silicon germanium layer;

[0012] S7: forming two sidewall structures with a relative spacing in the second opening;

[0013] S8: growing a second polysilicon layer by an epitaxial process, and removing a portion of the second polysilicon layer and the sixth dielectric layer by photolithography and etching processes to form an emitter;

[0014] S9: removing a portion of the external base polysilicon layer, the fifth dielectric layer, the second dielectric layer and the first dielectric layer through photolithography and etching processes to form an HBT device pattern.

[0015] In some embodiments, before S1, the method further includes:

[0016] S01: providing the substrate, and sequentially growing a first dielectric layer and a second dielectric layer on the surface of the substrate;

[0017] S02: etching the second dielectric layer by photolithography and etching processes;

[0018] S03: Etching the first dielectric layer through a wet etching process to form the first opening.

[0019] In some embodiments, the S2 includes:

[0020] S21: forming an epitaxial layer and a silicon germanium layer in sequence through a one-step epitaxial process;

[0021] S22: forming a third dielectric layer and a fourth dielectric layer in sequence on the silicon germanium layer;

[0022] S23: etching the fourth dielectric layer, the third dielectric layer, the silicon germanium layer and the epitaxial layer through photolithography and etching processes to form a stacked structure located above the active area.

[0023] In some embodiments, the S4 includes:

[0024] S41: Processing the top of the fifth dielectric layer by a chemical mechanical polishing process;

[0025] S42: etching the top of the fifth dielectric layer and the fourth dielectric layer by a dry etching process;

[0026] S43: Processing the remaining surface of the fifth dielectric layer by a wet etching process until all the fifth dielectric layers higher than the epitaxial layer are removed.

[0027] In some embodiments, the S6 includes:

[0028] S61: removing the sixth dielectric layer on top of the third dielectric layer by photolithography and etching processes;

[0029] S62: removing the third dielectric layer by a wet etching process to form a second opening.

[0030] In some embodiments, the S7 includes:

[0031] S71: forming a seventh dielectric layer and a first polysilicon layer in sequence on the silicon germanium layer and the sixth dielectric layer;

[0032] S72: etching the first polysilicon layer to form a third opening;

[0033] S73: using the first polysilicon layer as a mask, etching and removing the seventh dielectric layer above the sixth dielectric layer and the seventh dielectric layer below the third opening, and the remaining seventh dielectric layer forms a sidewall structure.

[0034] In some embodiments, the first dielectric layer, the fourth dielectric layer, the fifth dielectric layer, and the sixth dielectric layer are silicon oxide layers, and the second dielectric layer, the third dielectric layer, and the seventh dielectric layer are silicon nitride layers.

[0035] In some embodiments, the epitaxial layer is a phosphorus-doped silicon layer.

[0036] In some embodiments, the extrinsic base polysilicon layer is a polysilicon layer in-situ doped with boron.

[0037] The technical solution of this application has at least the following advantages:

[0038] 1. A method for efficiently manufacturing a heterojunction transistor is provided, in which the collector and base regions are manufactured by a one-step epitaxial process, and both the collector and base regions are self-aligned with the emitter. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the following is a brief introduction to the drawings required for use in the specific implementation methods or the description of the prior art. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0040] Figure 1is a flow chart of a method for manufacturing a heterojunction transistor provided by an exemplary embodiment of the present application;

[0041] Figure 2-14 It is a schematic diagram of the semiconductor structure in each process step of a method for manufacturing a heterojunction transistor provided by an exemplary embodiment of the present application.

[0042] DESCRIPTION OF NUMERALS: 1. substrate; 101. shallow trench isolation; 2. first dielectric layer; 3. second dielectric layer; 4. epitaxial layer; 5. silicon-germanium layer; 6. third dielectric layer; 7. fourth dielectric layer; 8. fifth dielectric layer; 9. extrinsic base polysilicon layer; 10. sixth dielectric layer; 11. seventh dielectric layer; 12. first polysilicon layer; 13. second polysilicon layer;

[0043] A1, first opening; A2, second opening; A3, third opening. DETAILED DESCRIPTION

[0044] The following is a clear and complete description of the technical solutions in this application in conjunction with the accompanying drawings. Obviously, the embodiments described are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of this application.

[0045] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate the description of this application and simplify the description. They do not indicate or imply that the devices or components referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0046] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "installed," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; they can refer to internal connections between two components; they can refer to wireless connections or wired connections. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.

[0047] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0048] The present application provides a method for manufacturing a heterojunction transistor. Referring to the figures, the method mainly includes the following steps:

[0049] S1: A substrate is provided, in which shallow trench isolation is formed to define an active area, a first dielectric layer and a second dielectric layer are sequentially formed on the surface of the substrate from bottom to top, and a first opening is formed in the first dielectric layer and the second dielectric layer and is located above the active area.

[0050] S2: forming a stacked structure on the first opening, the stacked structure including, from bottom to top, an epitaxial layer, a silicon germanium layer, a third dielectric layer, and a fourth dielectric layer, the epitaxial layer is used to form a collector, and the silicon germanium layer is used to form a base region.

[0051] S3: forming a fifth dielectric layer, where the fifth dielectric layer covers the stacked structure and the second dielectric layer.

[0052] S4: etching and removing the fifth dielectric layer and the fourth dielectric layer that are higher than the epitaxial layer.

[0053] S5: growing an external base polysilicon layer on the remaining fifth dielectric layer, and forming a sixth dielectric layer on the external base polysilicon layer and the remaining third dielectric layer.

[0054] S6: etching and removing the third dielectric layer and the sixth dielectric layer located on top of the third dielectric layer to form a second opening, wherein the second opening is located above the silicon germanium layer.

[0055] S7: forming two sidewall structures with a relative interval in the second opening.

[0056] S8: growing a second polysilicon layer through an epitaxial process, and removing a portion of the second polysilicon layer and the sixth dielectric layer through a photolithography and etching process to form an emitter.

[0057] S9: removing a portion of the external base polysilicon layer, the fifth dielectric layer, the second dielectric layer, and the first dielectric layer through photolithography and etching processes to form an HBT device pattern.

[0058] Specifically, refer to Figures 2 to 13 , Figure 2-13 This is a schematic diagram of the semiconductor structure in each process step of the manufacturing method of the heterojunction transistor provided in the embodiment of the present application. Next, the manufacturing method of the germanium-silicon heterojunction transistor provided in the embodiment of the present application is described in detail.

[0059] First, execute S1, refer to Figure 2A substrate 1 is provided. Shallow trench isolations 101 are formed in the substrate 1. The area between two shallow trench isolations 101 is defined as an active area. A first dielectric layer 2 and a second dielectric layer 3 are sequentially formed on the surface of the substrate 1 from bottom to top. A first opening A1 is formed in each of the first and second dielectric layers 2 and 3 above the active area.

[0060] Preferably, the material of the first dielectric layer 2 is a silicon oxide layer, and the material of the second dielectric layer 3 is a silicon nitride layer.

[0061] Preferably, the following steps may be included before S1 to form the structure in S1:

[0062] S01: providing a substrate 1, and sequentially growing a first dielectric layer 2 and a second dielectric layer 3 on the surface of the substrate 1.

[0063] For example, a substrate 1 is provided with shallow trench isolation 101 formed therein, where the shallow trench isolation 101 structure defines an active area. A first dielectric layer 2 is then grown on the surface of the substrate 1 using a high-density plasma (HDP) process. A second dielectric layer 3 is then grown on the first dielectric layer 2 using a furnace-grown film process (FUR).

[0064] S02: Etching the second dielectric layer 3 by photolithography and etching processes.

[0065] Exemplarily, the second dielectric layer 3 in a predetermined area is etched by photolithography and etching processes, and the etching stops at the surface of the first dielectric layer 2 .

[0066] S03: Etching the first dielectric layer 2 by a wet etching process to form a first opening A1.

[0067] Exemplarily, the exposed first dielectric layer 2 is etched by a wet etching process, and the etching stops at the surface of the substrate 1, thereby forming Figure 2 The first opening A1 in.

[0068] Afterwards, execute S2, such as Figure 5 As shown, a stacked structure is formed on the first opening A1, which includes an epitaxial layer 4, a germanium silicon layer 5, a third dielectric layer 6 and a fourth dielectric layer 7 from bottom to top. The epitaxial layer 4 is used to form a collector, and the germanium silicon layer 5 is used to form a base region.

[0069] Preferably, the epitaxial layer 4 is made of a silicon layer doped with phosphorus, the third dielectric layer 6 is made of silicon nitride, and the fourth dielectric layer 7 is made of silicon oxide.

[0070] Furthermore, S2 may include the following steps:

[0071] S21: forming an epitaxial layer 4 and a silicon-germanium layer 5 in sequence through a one-step epitaxial process.

[0072] For example, Figure 3 As shown, through a one-step epitaxial process, an N-EPI process, i.e., an N-type epitaxial growth process, is first used to grow an epitaxial layer 4 on the structure formed after S1, and then a No selective EPI process, i.e., a non-selective epitaxial growth process is used to form a germanium silicon layer 5 on the epitaxial layer 4.

[0073] S22 : forming a third dielectric layer 6 and a fourth dielectric layer 7 in sequence on the silicon germanium layer 5 .

[0074] For example, Figure 4 As shown, a third dielectric layer 6 may be grown on the germanium silicon layer 5 by a FUR process, and then a fourth dielectric layer 7 may be grown on the third dielectric layer 6 by a HDP process.

[0075] S23: etching the fourth dielectric layer 7, the third dielectric layer 6, the silicon germanium layer 5 and the epitaxial layer 4 through photolithography and etching processes to form a stacked structure located above the active area.

[0076] Exemplarily, the fourth dielectric layer 7, the third dielectric layer 6, the germanium silicon layer 5 and the epitaxial layer 4 in the designated area are etched by photolithography and dry etching processes, and the etching stops on the second dielectric layer 3, thereby forming Figure 5 As shown in the stacked structure. Since the SiGe layer 5 and the epitaxial layer 4 are etched in the same step, the subsequent collector and base regions are self-aligned. Since there is no second dielectric layer 3 blocking above the first opening A1, the substrate 1 located in the designated area and below the first opening A1 will be over-etched, thereby forming Figure 5 There are two grooves located in the substrate 1.

[0077] After that, execute S3, refer to Figure 6 A fifth dielectric layer 8 is formed on the structure formed after S2 , and the fifth dielectric layer 8 covers the stacked structure and the second dielectric layer 3 .

[0078] Preferably, the fifth dielectric layer 8 is made of silicon oxide, and the fifth dielectric layer 8 can be grown by a HDP process.

[0079] After that, execute S4, refer to Figure 7 , the fifth dielectric layer 8 and the fourth dielectric layer 7 that are higher than the epitaxial layer 4 are etched away.

[0080] Furthermore, S4 may include the following steps:

[0081] S41 : processing the top of the fifth dielectric layer 8 by a chemical mechanical polishing process.

[0082] Exemplarily, the top of the fifth dielectric layer 8 is first polished by a chemical mechanical polishing process.

[0083] S42 : etching the top of the fifth dielectric layer 8 and the fourth dielectric layer 7 by a dry etching process.

[0084] Illustratively, the top of the fifth dielectric layer 8 is etched by a dry etching process until the remaining fifth dielectric layer 8 is slightly higher than the top of the epitaxial layer 4 or is flush with the top of the epitaxial layer 4. During this process, the fourth dielectric layer 7 located above the third dielectric layer 6 is also removed.

[0085] S43 : treating the surface of the remaining fifth dielectric layer 8 by a wet etching process until all the fifth dielectric layer 8 higher than the epitaxial layer 4 is removed.

[0086] Exemplarily, a wet etching process is used to process the surface of the remaining fifth dielectric layer 8 , thereby facilitating the growth of the external base region polysilicon layer 9 in a subsequent process.

[0087] After that, execute S5, refer to Figure 8 , an external base polysilicon layer 9 is grown on the remaining fifth dielectric layer 8 , and a sixth dielectric layer 10 is formed on the external base polysilicon layer 9 and the remaining third dielectric layer 6 .

[0088] Preferably, the material of the extrinsic base polysilicon layer 9 can be polysilicon in-situ doped with boron, and the extrinsic base polysilicon layer 9 can be grown on the remaining fifth dielectric layer 8 through a selective EPI (selective epitaxial growth) process. The material of the sixth dielectric layer 10 can be a silicon oxide layer, and the sixth dielectric layer 10 can be grown on the extrinsic base polysilicon layer 9 and the remaining third dielectric layer 6 through a HDP process.

[0089] After that, execute S6, refer to Figure 9 , the third dielectric layer 6 and the sixth dielectric layer 10 located on top thereof are etched away to form a second opening A2 . The second opening A2 is located above the silicon germanium layer 5 .

[0090] Furthermore, S6 may include the following steps:

[0091] S61 : removing the sixth dielectric layer 10 on the top of the third dielectric layer 6 by photolithography and etching processes.

[0092] For example, the sixth dielectric layer 10 located on the top of the third dielectric layer 6 may be removed by photolithography and dry etching processes.

[0093] S62 : removing the third dielectric layer 6 by a wet etching process to form a second opening A2 .

[0094] Exemplarily, the third dielectric layer 6 is removed by a wet etching process to form Figure 9 The second opening A2 is shown.

[0095] After that, execute S7, refer to Figure 11 , two sidewall structures are formed in the second opening A2 with a relative interval.

[0096] Exemplarily, S7 may include the following steps:

[0097] S71 : forming a seventh dielectric layer 11 and a first polysilicon layer 12 in sequence on the silicon germanium layer 5 and the sixth dielectric layer 10 .

[0098] Preferably, the seventh dielectric layer 11 is made of silicon nitride.

[0099] For example, Figure 10 As shown, a seventh dielectric layer 11 may be grown on the silicon germanium layer 5 and the remaining sixth dielectric layer 10 by a PECVD (Plasma-Enhanced Chemical Vapor Deposition) process. Thereafter, a first polysilicon layer 12 is formed on the seventh dielectric layer 11 .

[0100] S72 : etching the first polysilicon layer 12 to form a third opening A3 .

[0101] Exemplarily, a dry etching process is used to remove part of the first polysilicon layer 12, and the etching stops at the surface of the seventh dielectric layer 11, forming the following Figure 10 The third opening A3 is shown.

[0102] S73 : using the first polysilicon layer 12 as a mask, etching away the seventh dielectric layer 11 above the sixth dielectric layer 10 and the seventh dielectric layer 11 below the third opening, and the remaining seventh dielectric layer 11 forms a sidewall structure.

[0103] Illustratively, the remaining first polysilicon layer 12 is used as a mask to remove the seventh dielectric layer 11 above the sixth dielectric layer 10 and the seventh dielectric layer 11 below the third opening through a wet etching process, and the remaining seventh dielectric layer 11 constitutes a sidewall structure.

[0104] After that, execute S8, refer to Figure 11 and Figure 12 , a second polysilicon layer 13 is grown by an epitaxial process, and a portion of the second polysilicon layer 13 and the sixth dielectric layer 10 is removed by photolithography and etching processes to form an emitter.

[0105] Exemplarily, the second polysilicon layer 13 is grown via an epitaxial process. Subsequently, portions of the second polysilicon layer 13 and the sixth dielectric layer 10 are removed via photolithography and dry etching, leaving only the second polysilicon layer 13 and the sixth dielectric layer 10 in a predetermined region. The remaining first polysilicon layer 12 and second polysilicon layer 13 constitute the emitter. The predetermined region is larger than the third opening and smaller than the first opening A1. Because the collector is within the first opening A1 and the base is within the second opening A2, self-alignment of the collector and base with the emitter is achieved.

[0106] After that, execute S9, refer to Figure 13 , a portion of the external base polysilicon layer 9, the fifth dielectric layer 8, the second dielectric layer 3 and the first dielectric layer 2 are removed by photolithography and etching processes to form an HBT device pattern.

[0107] For example, a portion of the external base polysilicon layer 9, the fifth dielectric layer 8, the second dielectric layer 3 and the first dielectric layer 2 is removed by photolithography and etching processes, and the etching stops at the surface of the substrate 1, and only the external base polysilicon layer 9, the fifth dielectric layer 8, the second dielectric layer 3 and the first dielectric layer 2 in the predetermined area are retained, thereby forming the following: Figure 13 The HBT device pattern shown in FIG. The boundary of the predetermined area in this step is located above the shallow trench isolation 101 .

[0108] The manufacturing method of the heterojunction transistor provided in the embodiment of the present application can complete the production of the collector and the base region through a one-step epitaxial process by sequentially executing the above steps, and both the collector and the base region are self-aligned with the emitter, thereby efficiently producing a heterojunction transistor.

[0109] Obviously, the above embodiments are merely examples for clarity of explanation and are not intended to limit the implementation methods. Those skilled in the art will appreciate that other variations or modifications can be made based on the above description. It is not necessary and impossible to enumerate all implementation methods here. Obvious variations or modifications arising therefrom remain within the scope of protection of this application.

Claims

1. A method for manufacturing a heterojunction transistor, characterized in that: include: S1: Providing a substrate, wherein shallow trench isolation is formed in the substrate to define an active area, and a first dielectric layer and a second dielectric layer are sequentially formed on the surface of the substrate from bottom to top, wherein a first opening is formed in the first dielectric layer and the second dielectric layer and is located above the active area; S2: forming a stacked structure on the first opening, the stacked structure comprising, from bottom to top, an epitaxial layer, a silicon-germanium layer, a third dielectric layer, and a fourth dielectric layer, the epitaxial layer being used to form a collector, and the silicon-germanium layer being used to form a base region; S3: forming a fifth dielectric layer, wherein the fifth dielectric layer covers the stacked structure and the second dielectric layer; S4: etching and removing the fifth dielectric layer and the fourth dielectric layer that are higher than the epitaxial layer; S5: growing an external base polysilicon layer on the remaining fifth dielectric layer, and forming a sixth dielectric layer on the external base polysilicon layer and the remaining third dielectric layer; S6: etching and removing the third dielectric layer and the sixth dielectric layer located on top of the third dielectric layer to form a second opening, wherein the second opening is located above the silicon germanium layer; S7: forming two sidewall structures with a relative spacing in the second opening; S8: growing a second polysilicon layer by an epitaxial process, and removing a portion of the second polysilicon layer and the sixth dielectric layer by photolithography and etching processes to form an emitter; S9: removing a portion of the external base polysilicon layer, the fifth dielectric layer, the second dielectric layer and the first dielectric layer through photolithography and etching processes to form an HBT device pattern.

2. The method for manufacturing a heterojunction transistor according to claim 1, wherein: Before the S1, it also includes: S01: providing the substrate, and sequentially growing a first dielectric layer and a second dielectric layer on the surface of the substrate; S02: etching the second dielectric layer by photolithography and etching processes; S03: Etching the first dielectric layer through a wet etching process to form the first opening.

3. The method for manufacturing a heterojunction transistor according to claim 1, wherein: The S2 includes: S21: forming an epitaxial layer and a silicon germanium layer in sequence through a one-step epitaxial process; S22: forming a third dielectric layer and a fourth dielectric layer in sequence on the silicon germanium layer; S23: etching the fourth dielectric layer, the third dielectric layer, the silicon germanium layer and the epitaxial layer through photolithography and etching processes to form a stacked structure located above the active area.

4. The method for manufacturing a heterojunction transistor according to claim 1, wherein: The S4 includes: S41: Processing the top of the fifth dielectric layer by a chemical mechanical polishing process; S42: etching the top of the fifth dielectric layer and the fourth dielectric layer by a dry etching process; S43: Processing the remaining surface of the fifth dielectric layer by a wet etching process until all the fifth dielectric layers higher than the epitaxial layer are removed.

5. The method for manufacturing a heterojunction transistor according to claim 1, wherein: The S6 includes: S61: removing the sixth dielectric layer on top of the third dielectric layer by photolithography and etching processes; S62: removing the third dielectric layer by a wet etching process to form a second opening.

6. The method for manufacturing a heterojunction transistor according to claim 1, wherein: The S7 includes: S71: forming a seventh dielectric layer and a first polysilicon layer in sequence on the silicon germanium layer and the sixth dielectric layer; S72: etching the first polysilicon layer to form a third opening; S73: using the first polysilicon layer as a mask, etching and removing the seventh dielectric layer above the sixth dielectric layer and the seventh dielectric layer below the third opening, and the remaining seventh dielectric layer forms a sidewall structure.

7. The method for manufacturing a heterojunction transistor according to claim 1, wherein: The first dielectric layer, the fourth dielectric layer, the fifth dielectric layer, and the sixth dielectric layer are silicon oxide layers, and the second dielectric layer, the third dielectric layer, and the seventh dielectric layer are silicon nitride layers.

8. The method for manufacturing a heterojunction transistor according to claim 1, wherein: The epitaxial layer is a phosphorus-doped silicon layer.

9. The method for manufacturing a heterojunction transistor according to claim 1, wherein: The external base region polysilicon layer is a polysilicon layer in-situ doped with boron.

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