SiC finfet device and method of manufacturing the same

Abstract

The application discloses a SiC FinFET device, comprising: a fin body, at least two first shielding areas are formed in a first SiC epitaxial layer at the bottom of the fin body. The first shielding area also extends to the bottom of the gate structure on both sides of the fin body and covers the gate dielectric layer of each gate structure from the bottom. A first current spreading layer is formed between two adjacent first shielding areas and has a first interval. A second shielding area is formed in the fin body at the top of each first shielding area. Two adjacent second shielding areas have a second interval greater than the first interval. A second current spreading layer, a well area and a source area are formed in the fin body between two adjacent second shielding areas. The application also discloses a manufacturing method of the SiC FinFET device. The application can increase the channel carrier mobility by using the fin body, and also can protect the gate dielectric layer well and make the device have a lower specific on-resistance.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor integrated circuit manufacturing, and particularly relates to a SiC FinFET device; the present application also relates to a manufacturing method of the SiC FinFET device. BACKGROUND

[0002] With more and more applications putting forward higher requirements for the withstand voltage and power consumption of power devices, the performance of power devices is facing greater and greater challenges. Silicon carbide material has the advantages of high thermal conductivity, wide band gap, high critical breakdown voltage and the like, and the semiconductor device taking silicon carbide as the material has increasingly obvious advantages in high-voltage and high-power applications. Silicon carbide MOSFET has the characteristics of high breakdown voltage, low specific on-resistance and low switching loss, and has advantages in various application scenarios such as new energy vehicles. However, due to the limitation of gate oxide process, there are a large number of interface traps in the interface of the silicon carbide MOSFET, which makes the silicon carbide MOSFET have a lower channel mobility, thereby increasing the specific on-resistance of the silicon carbide MOSFET.

[0003] In order to reduce the specific on-resistance of the silicon carbide MOSFET, researchers have proposed a trench-type silicon carbide MOSFET. The trench-type silicon carbide MOSFET has a small cell size and thus a larger channel density, and the interface trap of the channel is less, so the specific on-resistance of the trench-type silicon carbide MOSFET is smaller than that of the planar-type silicon carbide MOSFET. However, the gate oxide reliability of the trench-type silicon carbide MOSFET is poor, and in order to protect the gate oxide, the trench-type silicon carbide MOSFET often introduces a P-type shielding region, which increases the specific on-resistance of the trench-type silicon carbide MOSFET. At the same time, the channel mobility of the trench-type silicon carbide MOSFET is still much lower than the body mobility of the MOSFET, so a device structure for increasing the channel mobility is needed.

[0004] In order to further reduce the specific on-resistance of the device on the basis of the trench-type silicon carbide MOSFET, researchers have proposed a silicon carbide FinFET. When the Fin width is small enough, the carriers inside the channel are affected by the gate voltage on both sides of the Fin, so they are distributed in a wider channel, and the device mobility is thus increased. At the same time, the silicon carbide FinFET has a smaller cell size than the trench-type silicon carbide MOSFET, and thus has a larger channel density. The above mechanism makes the silicon carbide FinFET have a much lower specific on-resistance than the trench-type silicon carbide MOSFET. However, the gate oxide layer electric field of the above-mentioned silicon carbide FinFET is high under high drain-source voltage, which exceeds the safe working field strength of 3 MV / cm of silicon dioxide.

[0005] Therefore, it is necessary to propose a silicon carbide FinFET with a gate oxide protection structure, which can reduce the gate oxide layer electric field while still having a low specific on-resistance. SUMMARY

[0006] The technical problem solved by the present application is to provide a SiC FinFET device that can increase channel carrier mobility by using a fin body, while also protecting the gate dielectric layer and reducing the specific on-resistance of the device. To this end, the present application also provides a manufacturing method for a SiC FinFET device.

[0007] To solve the above technical problem, the SiC FinFET device provided by the present application comprises:

[0008] At least two first trenches are formed in the first SiC epitaxial layer, and the first SiC epitaxial layer between two adjacent first trenches constitutes a fin body; the length direction of the fin body is a first direction, and the width direction of the fin body is a second direction.

[0009] A gate structure is formed in each of the first trenches on both sides of the fin body, and the gate structure comprises a gate dielectric layer formed on the inner side surface of the first trench and a gate conductive material layer filled in the first trench.

[0010] At least two first shielding regions of a second conductivity type are formed in the first SiC epitaxial layer at the bottom of the fin body.

[0011] In the second direction, the first shielding regions also extend to the bottom of the gate structures on both sides of the fin body and thereby cover the gate dielectric layers of the gate structures from the bottom.

[0012] In the first direction, the first SiC epitaxial layer between two adjacent first shielding regions has a first spacing, and a first current spreading layer of a first conductivity type is formed in the first SiC epitaxial layer between the two adjacent first shielding regions.

[0013] A second shielding region of a second conductivity type is formed in the fin body on top of each first shielding region, and the second shielding region is in contact with the first shielding region at the bottom.

[0014] In the first direction, the second spacing between two adjacent second shielding regions is greater than the first spacing.

[0015] A second current spreading layer of a first conductivity type, a well region of a second conductivity type, and a source region of a first conductivity type that are heavily doped are formed in the fin body between two adjacent second shielding regions.

[0016] The bottom surface of the second current spreading layer is in contact with the first current spreading layer, the well region is formed in the top region of the second current spreading layer, and the source region is formed in the top region of the well region.

[0017] The surface of the well region covered by the gate structure is used to form a conductive channel.

[0018] A first lead-out region of a second conductivity type is formed in the top region of the second shielding region.

[0019] The drift region of the first conductivity type is composed of the first SiC epitaxial layer located at the bottom of the first shielding region and the first current spreading layer.

[0020] Both the source region and the first lead-out region are connected to a source electrode composed of a front metal layer.

[0021] A further improvement is that the first SiC epitaxial layer adopts a 4H crystal form.

[0022] A further improvement is that the side surface of the first trench is a crystal face.

[0023] A further improvement is that the included angle between the side surface of the first trench and the normal line of the top surface of the first SiC epitaxial layer is 3.5°.

[0024] A further improvement is that the SiC FinFET device is a MOSFET; a drain region of the first conductivity type is formed on the back of the drift region.

[0025] A further improvement is that a buffer layer of the first conductivity type is further formed between the drain region and the drift region.

[0026] The doping concentration of the buffer layer is greater than the doping concentration of the drift region.

[0027] The doping concentration of the first current spreading layer is greater than the doping concentration of the drift region.

[0028] The doping concentration of the second current spreading layer is greater than the doping concentration of the drift region.

[0029] A drain electrode composed of a back metal layer is formed on the back of the drain region.

[0030] A further improvement is that the drain region is composed of a SiC substrate of the first conductivity type.

[0031] The buffer layer is composed of a zeroth SiC epitaxial layer formed on the surface of the SiC substrate.

[0032] Further improvement is that the first SiC epitaxial layer is composed of a first SiC epitaxial sub-layer and a second SiC epitaxial sub-layer, and the second SiC epitaxial sub-layer is formed on the top surface of the first SiC epitaxial sub-layer.

[0033] The first shielding region is composed of ion implantation regions of the second conductive type formed in the first SiC epitaxial sub-layer.

[0034] The second shielding region is composed of ion implantation regions of the second conductive type formed in the second SiC epitaxial sub-layer.

[0035] The first conductive type doping impurities of the first current spreading layer are composed of in-situ doping impurities of the first SiC epitaxial sub-layer plus ion implantation impurities of the first conductive type.

[0036] The first conductive type doping impurities of the second current spreading layer are composed of in-situ doping impurities of the second SiC epitaxial sub-layer.

[0037] Further improvement is that the SiC FinFET device is an N-type device, the first conductive type is N-type, and the second conductive type is P-type; or, the SiC FinFET device is a P-type device, the first conductive type is P-type, and the second conductive type is N-type.

[0038] To solve the above technical problems, the manufacturing method of the SiC FinFET device provided by the application comprises the following steps:

[0039] An epitaxial growth forms a first SiC epitaxial sub-layer of the first conductive type and light doping.

[0040] A first conductive type ion implantation is performed to form a first current spreading layer in the top region of the first SiC epitaxial sub-layer.

[0041] A second conductive type ion implantation is performed to form a first shielding region in the selected region of the first current spreading layer; a drift region is composed of the first shielding region and the first SiC epitaxial sub-layer at the bottom of the first current spreading layer, the bottom surface of the first shielding region is in contact with the drift region; there is a first spacing between two adjacent first shielding regions, and the first current spreading layer is reserved between the two adjacent first shielding regions.

[0042] A second SiC epitaxial sub-layer of the second conductive type doping is formed on the surface of the first SiC epitaxial sub-layer, and a first SiC epitaxial layer is composed of the first SiC epitaxial sub-layer and the second SiC epitaxial sub-layer.

[0043] forming a second shielding region in the second SiC epitaxial sub-layer on top of each of the first shielding regions by a second conductive type ion implantation; the bottom surface of the second shielding region is in contact with the first shielding region; the second distance between two adjacent second shielding regions is greater than the first distance.

[0044] forming a first lead-out region in the top region of each of the first shielding regions by a second conductive type heavily doped ion implantation.

[0045] forming a well region in the top region of the second SiC epitaxial sub-layer between each of the second shielding regions by a second conductive type ion implantation; the second current spreading layer is composed of the second SiC epitaxial sub-layer at the bottom of the well region.

[0046] forming a source region in the top region of the well region by a first conductive type heavily doped ion implantation.

[0047] forming at least two first trenches by a patterned etching; a fin is composed of the first SiC epitaxial layer between two adjacent first trenches; the length direction of the fin is the first direction, and the width direction of the fin is the second direction; the first shielding region is located at the bottom of the fin, and in the second direction, the first shielding region also extends to the bottom of the first trench on both sides of the fin and is in contact with the bottom surface of the first trench; two adjacent first shielding regions are arranged along the first direction.

[0048] forming a gate dielectric layer on the inner side surface of the first trench.

[0049] filling a gate conductive material layer in the first trench.

[0050] forming a front metal layer and patterning the front metal layer to form a source electrode; the source region and the first lead-out region are both connected to the source electrode.

[0051] Further improvement is that the first SiC epitaxial layer adopts 4H crystal form.

[0052] Further improvement is that the side surface of the first trench is crystal face.

[0053] Further improvement is that the angle between the side surface of the first trench and the normal of the top surface of the first SiC epitaxial layer is 3.5°.

[0054] Further improvement is that the SiC FinFET device is MOSFET.

[0055] Before forming the first SiC epitaxial sub-layer, further comprising:

[0056] The first conductive type heavily doped SiC substrate is formed on the top surface of the first conductive type heavily doped SiC substrate and the buffer layer is composed of the first conductive type heavily doped SiC epitaxial layer.

[0057] The doping concentration of the buffer layer is greater than the doping concentration of the drift region.

[0058] The doping concentration of the first current spreading layer is greater than the doping concentration of the drift region.

[0059] The doping concentration of the second current spreading layer is greater than the doping concentration of the drift region.

[0060] The drain region is composed of the SiC substrate.

[0061] After the front surface process is completed, the method further comprises:

[0062] The back surface metal layer is formed on the back surface of the drain region and the drain electrode is composed of the back surface metal layer.

[0063] Further improvement is that the SiC FinFET device is an N-type device, the first conductive type is N-type and the second conductive type is P-type; or, the SiC FinFET device is a P-type device, the first conductive type is P-type and the second conductive type is N-type.

[0064] The SiC FinFET device of the application adopts a fin body, since the fin body has the feature of narrow width, the channel carriers formed in the well region in the fin body are simultaneously affected by the gate voltage on both sides and thus are distributed in a wider channel, so that the channel carriers are less hindered in the migration process and thus the channel carrier mobility of the device is increased.

[0065] Meanwhile, in view of the feature that the gate dielectric layer such as gate oxide layer of the SiC FinFET device such as MOSFET is easily affected by high electric field intensity under high source-drain voltage, the application sets the first shielding region and the second shielding region to protect the gate dielectric layer, wherein the first shielding region extends to the bottom of the gate dielectric layer, since the first shielding region is connected to the source electrode through the second shielding region and the first lead-out region, in the case of N-type MOSFET, the voltage of the first shielding region is less than the gate conductive material layer, the electric lines formed by the high source-drain voltage are preferentially concentrated in the first shielding region, so that the electric lines are prevented from being concentrated in the gate dielectric layer, thus the gate dielectric layer is protected, so the application can well protect the gate dielectric layer.

[0066] In addition, the present application further sets the pattern structure of the first shielding area and the second shielding area, wherein the first interval between two adjacent first shielding areas is reduced, so that the first shielding area can cover more gate dielectric layer, thereby improving the protection of the gate dielectric layer; meanwhile, the second interval between two adjacent second shielding areas located at the top is larger than the first interval, since the channel width is determined by the length of the well region along the length direction of the fin body, i.e. the first direction, and the well region is located between two adjacent second shielding areas, so that the channel width can be increased by increasing the second interval, and therefore the channel density can be increased and the specific on-resistance of the device can be reduced.

[0067] Therefore, the present application can increase the channel carrier mobility by using the fin body, and can also protect the gate dielectric layer well and make the device have a lower specific on-resistance. BRIEF DESCRIPTION OF DRAWINGS

[0068] The present application will be further described in detail below in combination with the drawings and specific embodiments:

[0069] Figure 1 is a perspective view of a SiC FinFET device according to an embodiment of the present application;

[0070] Figure 2 is a cross-sectional structure view along the line AA1 of Figure 1

[0071] Figure 3 is a cross-sectional structure view along the line BB1 of Figure 1

[0072] Figure 4 is a top view of Figure 1

[0073] Figure 5 is a cross-sectional structure view along the line AA2 of Figure 1

[0074] Figure 6 is a cross-sectional structure view along the line BB2 of Figure 1

[0075] Figure 7 is a top view of Figure 1

[0076] Figure 8-18 is a device structure diagram in each step of the manufacturing method of the SiC FinFET device according to an embodiment of the present application;

[0077] Figure 19A is an electric field line distribution diagram in a SiC FinFET device according to the prior art;

[0078] Figure 19B ​​​​​​is a distribution of electric field lines in the SiC FinFET device of the embodiment of the present application. DETAILED DESCRIPTION

[0079] As Figure 1 shown, is a perspective view of the SiC FinFET device of the embodiment of the present application. Figure 2 is a cross-sectional structure view along the line AA1 of Figure 1 . Figure 3 is a cross-sectional structure view along the line BB1 of Figure 1 . Figure 4 is a top view of Figure 1 . Figure 5 is a cross-sectional structure view along the line AA2 of Figure 1 . Figure 6 is a cross-sectional structure view along the line BB2 of Figure 1 . Figure 7 is a top view of Figure 1 after removing the metal of the source 11. The SiC FinFET device of the embodiment of the present application comprises:

[0080] At least two first trenches are formed in the first SiC epitaxial layer 103, and the first SiC epitaxial layer 103 between two adjacent first trenches forms a fin. The structure of the first SiC epitaxial layer 103 is shown in Figure 5 .

[0081] The length direction of the fin is the first direction, and the width direction of the fin is the second direction. Figure 1 In order to better illustrate the structure of the embodiment of the present application, a coordinate system is also used for illustration, Figure 1 in which the first direction is the Y direction, and the second direction is the X direction. The Z direction is the direction perpendicular to the top surface of the fin and upward.

[0082] One gate structure is formed in each of the first trenches on both sides of the fin, and the gate structure comprises a gate dielectric layer 10 formed on the inner side surface of the first trench and a gate conductive material layer 3 filled in the first trench.

[0083] In some embodiments, the gate dielectric layer 10 is a gate oxide layer, and the gate conductive material layer 3 is a polysilicon gate. Figure 1 In some embodiments, the gate conductive material layer 3 is also represented by polysilicon.

[0084] At least two first shielding regions 4a of the second conductive type are formed in the first SiC epitaxial layer 103 at the bottom of the fin. Figure 1 Two first shielding regions 4a are shown in

[0085] In the second direction, the first shielding region 4a also extends to the bottom of the gate structure on both sides of the fin and thereby covers the gate dielectric layer 10 of each gate structure from the bottom.

[0086] In the first direction, there is a first distance d1 between two adjacent first shielding regions 4a and a first current spreading layer 9a doped with the first conductive type is formed in the first SiC epitaxial layer 103 between the two adjacent first shielding regions 4a. Figure 5 shown.

[0087] A second shielding region 4b doped with the second conductive type is formed in the fin at the top of each first shielding region 4a. The second shielding region 4b is in contact with the first shielding region 4a at the bottom.

[0088] In the first direction, there is a second distance d2 between two adjacent second shielding areas 4b, and the second distance d2 is greater than the first distance d1. Figure 5 shown.

[0089] A second current spreading layer 9 b doped with the first conductivity type, a well region 8 doped with the second conductivity type, and a source region 2 heavily doped with the first conductivity type are formed in the fin between two adjacent second shielding regions 4 b.

[0090] The bottom surface of the second current spreading layer 9 b contacts the first current spreading layer 9 a , the well region 8 is formed in the top region of the second current spreading layer 9 b , and the source region 2 is formed in the top region of the well region 8 .

[0091] The surface of the well region 8 covered by the side surface of the gate structure is used to form a conductive channel.

[0092] A first lead-out region 1 heavily doped with the second conductivity type is formed in the top region of the second shielding region 4 b.

[0093] The first conductivity type lightly doped drift region 5 is composed of a first SiC epitaxial layer 103 located at the bottom of the first shielding region 4 a and the first current spreading layer 9 a.

[0094] The source region 2 and the first lead-out region 1 are both connected to a source electrode 11 formed by a front metal layer. Figure 1 In FIG, the source 11 is also represented by source metal.

[0095] The source region 2 and the first lead-out region 1 are both heavily doped, and thus form an ohmic contact with the source electrode 11. The first lead-out region 1 connects the first shielding region 4a, the second shielding region 4b and the well region 8 to the source electrode 11.

[0096] In the embodiment of the present invention, the first SiC epitaxial layer 103 adopts 4H crystal type. Preferably, the side surface of the first trench is (1 _ 100) crystal plane.

[0097] Generally, the (0001) crystal plane and the top surface of the first SiC epitaxial layer 103 have a certain angle, such as an angle of 3.5°. At this time, the angle between the side surface of the first trench and the normal line of the top surface of the first SiC epitaxial layer 103 needs to be set to 3.5°. That is, the side surface of the first trench needs to have an angle of 3.5° with the side surface perpendicular to the top surface, so that the side surface of the first trench is a (1 _ 100) crystal plane.

[0098] In the embodiment of the present application, the SiC FinFET device is a MOSFET; a drain region of the first conductive type with heavy doping is formed on the back surface of the drift region 5. The drain region is composed of the SiC substrate 7 with heavy doping of the first conductive type.

[0099] In some preferable embodiments, a buffer layer 6 with heavy doping of the first conductive type is further formed between the drain region and the drift region 5.

[0100] The buffer layer 6 is composed of a zeroth SiC epitaxial layer formed on the surface of the SiC substrate 7.

[0101] The doping concentration of the buffer layer 6 is greater than the doping concentration of the drift region 5.

[0102] The doping concentration of the first current spreading layer 9a is greater than the doping concentration of the drift region 5.

[0103] The doping concentration of the second current spreading layer 9b is greater than the doping concentration of the drift region 5.

[0104] A drain electrode 12 composed of a back surface metal layer is formed on the back surface of the drain region. Figure 1 In the embodiment, the drain electrode 12 is also indicated by a drain metal.

[0105] Please refer to Figure 5 In the embodiment of the present application, the first SiC epitaxial layer 103 is composed of a first SiC epitaxial sub-layer 101 and a second SiC epitaxial sub-layer 102, and the second SiC epitaxial sub-layer 102 is formed on the top surface of the first SiC epitaxial sub-layer 101.

[0106] The first shielding region 4a is composed of an ion implantation region of the second conductive type formed in the first SiC epitaxial sub-layer 101.

[0107] The second shielding region 4b is composed of an ion implantation region of the second conductive type formed in the second SiC epitaxial sub-layer 102.

[0108] The first conductive type doping impurities of the first current spreading layer 9a are composed of in-situ doping impurities formed in the first SiC epitaxial sub-layer 101 plus ion implantation impurities of the first conductive type.

[0109] The first conductive type doping impurity of the second current spreading layer 9b is composed of in-situ doping impurities formed in the second SiC epitaxial sub-layer 102.

[0110] In the embodiment of the present application, the SiC FinFET device is an N-type device, the first conductive type is N-type, and the second conductive type is P-type. As shown in the figure, the first current spreading layer 9a and the second current spreading layer 9b are represented by CLS layers, the well region 8 is represented by Pwell, and the source region 2 is represented by N+; the first shielding region 4a and the second shielding region 4b are both represented by P; the first lead-out region 1 is represented by P+; the drift region 5 is represented by N-drift region, the buffer layer 6 is represented by N+ buffer layer, and the SiC substrate 7 is represented by N+ substrate. Figure 5 In other embodiments, the SiC FinFET device can also be a P-type device, the first conductive type is P-type, and the second conductive type is N-type.

[0111] The SiC FinFET device in the embodiment of the present application adopts a fin body. Since the fin body has the characteristic of a narrow width, the channel carriers formed in the well region 8 in the fin body are simultaneously affected by the gate voltages on both sides and thus are distributed in a wider channel. As a result, the channel carriers are less hindered in the migration process, and thus the channel carrier mobility of the device is increased.

[0112] Meanwhile, in view of the characteristic that the gate dielectric layer 10 such as a gate oxide layer of the SiC FinFET device such as a MOSFET is easily affected by a high electric field strength under a high source-drain voltage, the embodiment of the present application sets the first shielding region 4a and the second shielding region 4b to protect the gate dielectric layer 10. The first shielding region 4a extends to the bottom of the gate dielectric layer 10. Since the first shielding region 4a is connected to the source electrode 11 through the second shielding region 4b and the first lead-out region 1, the voltage of the first shielding region 4a is lower than that of the gate electrode material layer 3 in the case of an N-type MOSFET. The electric lines formed by the high source-drain voltage are preferentially concentrated in the first shielding region 4a, so that the electric lines are prevented from being concentrated in the gate dielectric layer 10. Thus, the gate dielectric layer 10 is protected, and the embodiment of the present application can well protect the gate dielectric layer 10.

[0113]

[0114] ​In addition, the embodiment of the present invention further arranges the graphic structure of the first shielding area 4a and the second shielding area 4b, wherein the first spacing d1 between the two adjacent first shielding areas 4a is reduced, so that the first shielding area 4a can cover more gate dielectric layer 10, thereby improving the protection of the gate dielectric layer 10; at the same time, the second spacing d2 between the two adjacent second shielding areas 4b located at the top is larger and greater than the first spacing d1. Since the channel width is determined by the length of the well area 8 along the length direction of the fin body, that is, the first direction, and the well area 8 is located between the two adjacent second shielding areas 4b, the channel width can be increased by increasing the second spacing d2. Therefore, the channel density can be increased and the device's specific on-resistance can be reduced.

[0115] Therefore, the embodiment of the present invention can use the fin to increase the channel carrier mobility, while also providing good protection for the gate dielectric layer 10 and enabling the device to have a lower specific on-resistance.

[0116] like Figure 19A FIG. 1 shows the electric field line distribution diagram in an existing SiC FinFET device. Figure 19A The difference between the existing SiC FinFET device and the SiC FinFET device of the embodiment of the present invention is that: Figure 19A The first shielding region 4a and the second shielding region 4b are not provided in an existing SiCFinFET device, so the current spreading layer 9 is not divided into the first current spreading layer 9a and the second current spreading layer 9b of the embodiment of the present invention, and other identical structures are also represented by the same marks. Figure 19A The cross-sectional position can be similar to that of the embodiment of the present invention Figure 1 From the cross-sectional position corresponding to line BB1 ​​or line BB2 in FIG, it can be seen that when the source-drain voltage is large, electric lines of force, i.e., electric field lines converge, as indicated by arrow lines 301, are likely to be generated at the bottom corner of the first trench. Since the higher the density of electric lines, the greater the electric field intensity, the gate dielectric layer 10 at the bottom corner of the first trench will be subjected to a large electric field, and thus the gate dielectric layer 10 is easily damaged.

[0117] like Figure 19B , which is a diagram of the electric field line distribution in the SiC FinFET device according to an embodiment of the present invention; Figure 19B The device cross-sectional structure is Figure 2 The corresponding cross-sectional structure, Figure 19B The power lines shown by arrow lines 302 are added to Figure 19B As shown, since the first shielding area 4a is at the bottom of the gate dielectric layer 10 and the potential of the first shielding area 4a is lower, that is, connected to the source potential, the electric lines will converge in the first shielding area 4a. Therefore, no electric line convergence will occur in the gate dielectric layer 10, so the gate dielectric layer 10 is protected.

[0118] As Figure 8 to 18 shown, is the device structure schematic diagram in each step of the manufacturing method of the SiC FinFET device of the embodiment of the present application; the manufacturing method of the SiC FinFET device of the embodiment of the present application comprises the following steps:

[0119] Step one, as Figure 8 shown, epitaxial growth forms a first conductive type lightly doped first SiC epitaxial sub-layer 101.

[0120] The drift region 5 is composed of the first SiC epitaxial sub-layer 101, so the first SiC epitaxial sub-layer 101 is grown according to the doping needs of the drift region 5.

[0121] In the method of the embodiment of the present application, the SiC FinFET device is a MOSFET.

[0122] Before forming the first SiC epitaxial sub-layer 101, it further comprises:

[0123] Epitaxial growth forms a first conductive type heavily doped zeroth SiC epitaxial layer on the top surface of the first conductive type heavily doped SiC substrate 7 and forms a buffer layer 6 from the zeroth SiC epitaxial layer.

[0124] The doping concentration of the buffer layer 6 is greater than the doping concentration of the first SiC epitaxial sub-layer 101.

[0125] In the method of the embodiment of the present application, the SiC FinFET device is an N-type device, the first conductive type is N-type, and the second conductive type is P-type. In other embodiments, the SiC FinFET device can also be a P-type device, the first conductive type is P-type, and the second conductive type is N-type.

[0126] Step two, as Figure 9 shown, first conductive type ion implantation 201 is performed to form a first current spreading layer 9a in the top region of the first SiC epitaxial sub-layer 101.

[0127] Since the embodiment of the present application is an N-type device, the first conductive type ion implantation 201 in step two is N-type ion implantation, and the impurity generally uses nitrogen (N), Figure 2 The first conductive type ion implantation 201 in the middle also uses N ion implantation to represent.

[0128] Step three, as Figure 10 shown, second conductive type ion implantation 202 is performed to form a first shielding region 4a in the selected region of the first current spreading layer 9a. Figure 10 The corresponding cross section can correspond to Figure 1 the AA2 line in the middle, which is a YZ plane, and the subsequent Figure 11 to 15 cross section position and Figure 10 are the same.

[0129] In the embodiment of the present application, the second-conductivity-type ion implantation 202 is P-type ion implantation, and the implanted impurity is generally aluminum (Al), Figure 10 In the embodiment of the present application, the second-conductivity-type ion implantation 202 is P-type ion implantation, and the implanted impurity is generally aluminum (Al),

[0130] Before the second-conductivity-type ion implantation 202 is performed, a mask layer 203 needs to be defined by using a photolithography process. The mask layer 203 is generally a photoresist pattern formed directly by using the photolithography process.

[0131] The drift region 5 is composed of the first shielding region 4a and the first SiC epitaxial sub-layer 101 at the bottom of the first current spreading layer 9a, and the bottom surface of the first shielding region 4a is in contact with the drift region 5. The first current spreading layer 9a is reserved between two adjacent first shielding regions 4a, and the first spacing d1 is provided between the two adjacent first shielding regions 4a.

[0132] Step four, as shown in the figure, a second SiC epitaxial sub-layer 102 doped with the second-conductivity-type is formed on the surface of the first SiC epitaxial sub-layer 101, and the first SiC epitaxial layer 103 is composed of the first SiC epitaxial sub-layer 101 and the second SiC epitaxial sub-layer 102. Figure 11 Step five, as shown in the figure, the second-conductivity-type ion implantation 204 is performed to form the second shielding region 4b in the second SiC epitaxial sub-layer 102 on the top of each first shielding region 4a; the bottom surface of the second shielding region 4b is in contact with the first shielding region 4a; the second spacing d2 is provided between two adjacent second shielding regions 4b, and the second spacing d2 is greater than the first spacing d1.

[0133] Figure 12 In the embodiment of the present application, the second-conductivity-type ion implantation 204 is P-type ion implantation, and the implanted impurity is generally aluminum (Al), In the embodiment of the present application, the second-conductivity-type ion implantation 204 is P-type ion implantation, and the implanted impurity is generally aluminum (Al),

[0134] Figure 12 Before the second-conductivity-type ion implantation 204 is performed, a mask layer 204 needs to be defined by using a photolithography process. The mask layer 204 is generally a photoresist pattern formed directly by using the photolithography process.

[0135] Step six, as shown in the figure, the second-conductivity-type heavy-doping ion implantation 206 is performed to form the first lead-out region 1 in the top region of each first shielding region 4a.

[0136] Step six, as shown in the figure, the second-conductivity-type heavy-doping ion implantation 206 is performed to form the first lead-out region 1 in the top region of each first shielding region 4a. Figure 13

[0137] Figure 13 ​​The second-conductivity-type ion implantation 206 is also represented by Al ion implantation. Before the second-conductivity-type ion implantation 206 is performed, a mask layer 207 needs to be defined by a photolithography process. In some embodiments, the mask layer 207 is directly adopted from the mask layer 204 in the step 2. Figure 12

[0138] Step 7, as shown in FIG. 8, a second-conductivity-type ion implantation 208 is performed to form well regions 8 in the top regions of the second SiC epitaxial sub-layer 102 between the second shielding regions 4b; the second current spreading layer 9b is composed of the second SiC epitaxial sub-layer 102 at the bottom of the well regions 8. Figure 14

[0139] In the embodiments of the present application, the doping concentration of the first current spreading layer 9a is greater than the doping concentration of the drift region 5.

[0140] The doping concentration of the second current spreading layer 9b is greater than the doping concentration of the drift region 5.

[0141] Figure 14 The second-conductivity-type ion implantation 208 is also represented by Al ion implantation. Before the second-conductivity-type ion implantation 208 is performed, a mask layer 208 needs to be defined by a photolithography process. As can be seen, the regions opened by the mask layers 208 and 204 are just opposite, i.e. complementary regions.

[0142] Step 8, as shown in FIG. 9, a first-conductivity-type heavy doping ion implantation 210 is performed to form source regions 2 in the top regions of the well regions 8. Figure 15

[0143] The first-conductivity-type heavy doping ion implantation 210 is represented by N ion implantation, i.e. the implanted impurity is nitrogen. Before the first-conductivity-type heavy doping ion implantation 210 is performed, a mask layer 211 needs to be defined by a photolithography process. In the embodiments of the present application, the mask layer 211 is directly adopted from the mask layer 208 in the step 6. Figure 15 Figure 14 Step 9, as shown in FIG. 10, a patterned etching is performed to form at least two first trenches.

[0144] Figure 16 The corresponding cross section can correspond to the cross section at the line BB2 in FIG. 6, which is an XZ plane, and the cross section positions and the cross section positions in the subsequent steps are the same. Figure 16 Figure 1 Figure 17 to 18 Figure 16

[0145] ​​​​​​​​The fin body is composed of a first SiC epitaxial layer 103 located between two adjacent first trenches; the length direction of the fin body is the first direction, and the width direction of the fin body is the second direction; the first shielding region 4a is located at the bottom of the fin body, and in the second direction, the first shielding region 4a also extends to the bottom of the first trenches on both sides of the fin body and contacts the bottom surface of the first trench; two adjacent first shielding regions 4a are arranged along the first direction.

[0146] In the embodiment of the present invention, the first SiC epitaxial layer 103 adopts 4H crystal type, which is a hexagonal crystal structure.

[0147] The side surface of the first groove is (1 _ In some embodiments, the top surface of the first SiC epitaxial layer 103 is not the (0001) crystal plane, but there is an angle between the two. Therefore, the (1 _ 100) crystal plane, but it is necessary to set the angle between the side of the first trench and the normal line of the top surface of the first SiC epitaxial layer 103 to 3.5° to obtain (1 _ 100) crystal plane.

[0148] Step 10: Figure 17 As shown, a gate dielectric layer 10 is formed on the inner surface of the first trench.

[0149] In the method of the embodiment of the present invention, the gate dielectric layer 10 is a gate oxide layer, which is formed by performing a thermal oxidation process on Si.

[0150] Step 11: Figure 18 As shown, the gate conductive material layer 3 is filled in the first trench.

[0151] In the method of the embodiment of the present invention, the gate conductive material layer 3 is made of polysilicon gate.

[0152] Step 12: Figure 18 As shown, a front metal layer is formed and patterned to form a source electrode 11 , and both the source region 2 and the first lead-out region 1 are connected to the source electrode 11 .

[0153] The drain region is composed of SiC substrate 7 .

[0154] After the front process is completed, it also includes:

[0155] A back metal layer is formed on the back side of the drain region and the drain electrode 12 is formed by the back metal layer.

[0156] The present invention has been described in detail above by means of specific embodiments, but these do not constitute limitations of the present invention. Without departing from the principles of the present invention, those skilled in the art may make many variations and improvements, which should also be considered as the scope of protection of the present invention.

Claims

1. A SiC FinFET device, characterized in that: include: At least two first trenches are formed in the first SiC epitaxial layer, and the first SiC epitaxial layer located between two adjacent first trenches constitutes a fin; the length direction of the fin is a first direction, and the width direction of the fin is a second direction; A gate structure is formed in each of the first trenches on both sides of the fin, wherein the gate structure includes a gate dielectric layer formed on the inner surface of the first trench and a gate conductive material layer filled in the first trench; At least two first shielding regions doped with a second conductivity type are formed in the first SiC epitaxial layer at the bottom of the fin body; In the second direction, the first shielding region further extends to the bottom of the gate structures on both sides of the fin body and thus covers the gate dielectric layer of each gate structure; In the first direction, a first distance is provided between two adjacent first shielding regions, and a first current spreading layer doped with a first conductive type is formed in the first SiC epitaxial layer between the two adjacent first shielding regions; A second shielding region doped with a second conductive type is formed in the fin body at the top of each first shielding region, wherein the second shielding region is in contact with the first shielding region at the bottom; In the first direction, there is a second distance between two adjacent second shielding areas, and the second distance is greater than the first distance; A second current spreading layer doped with the first conductivity type, a well region doped with the second conductivity type, and a source region heavily doped with the first conductivity type are formed in the fin body between two adjacent second shielding regions; The bottom surface of the second current spreading layer contacts the first current spreading layer, the well region is formed in a top region of the second current spreading layer, and the source region is formed in the top region of the well region; The surface of the well region covered by the side surface of the gate structure is used to form a conductive channel; A first lead-out region heavily doped with a second conductivity type is formed in a top region of the second shielding region; A drift region lightly doped with a first conductivity type is composed of the first SiC epitaxial layer located at the bottom of the first shielding region and the first current spreading layer; The source region and the first lead-out region are both connected to a source electrode formed by a front metal layer.

2. The SiC FinFET device according to claim 1, wherein: The first SiC epitaxial layer adopts 4H crystal type.

3. The SiC FinFET device according to claim 2, wherein: The side surface of the first trench is a (1-100) crystal plane.

4. The SiC FinFET device according to claim 3, wherein: An angle between a side surface of the first trench and a normal to a top surface of the first SiC epitaxial layer is 3.5°.

5. The SiC FinFET device according to claim 1, wherein: The SiC FinFET device is a MOSFET; a drain region heavily doped with a first conductivity type is formed on the back side of the drift region.

6. The SiC FinFET device according to claim 5, wherein: A buffer layer heavily doped with the first conductivity type is further formed between the drain region and the drift region; The doping concentration of the buffer layer is greater than the doping concentration of the drift region; The doping concentration of the first current spreading layer is greater than the doping concentration of the drift region; The doping concentration of the second current spreading layer is greater than the doping concentration of the drift region; A drain electrode composed of a back metal layer is formed on the back side of the drain region.

7. The SiC FinFET device according to claim 6, wherein: The drain region is composed of a SiC substrate heavily doped with a first conductivity type; The buffer layer is composed of a zeroth SiC epitaxial layer formed on the surface of the SiC substrate.

8. The SiC FinFET device according to claim 1, wherein: The first SiC epitaxial layer is composed of a first SiC epitaxial sublayer and a second SiC epitaxial sublayer, wherein the second SiC epitaxial sublayer is formed on a top surface of the first SiC epitaxial sublayer; The first shielding region is composed of an ion implantation region of the second conductivity type formed in the first SiC epitaxial sublayer; The second shielding region is composed of an ion implantation region of the second conductivity type formed in the second SiC epitaxial sublayer; The first conductivity type dopant impurities of the first current spreading layer are composed of in-situ dopant impurities formed in the first SiC epitaxial sublayer plus ion implanted impurities of the first conductivity type; The first conductivity type dopant impurities of the second current spreading layer are composed of in-situ dopant impurities formed in the second SiC epitaxial sub-layer.

9. The SiC FinFET device according to any one of claims 1 to 8, wherein: The SiC FinFET device is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type; or, the SiC FinFET device is a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.

10. A method for manufacturing a SiC FinFET device, characterized in that: The steps include: Epitaxially growing a first SiC epitaxial sublayer lightly doped with a first conductivity type; Performing first conductive type ion implantation to form a first current spreading layer in a top region of the first SiC epitaxial sublayer; Performing second conductive type ion implantation to form a first shielding region in a selected area of ​​the first current spreading layer; a drift region consisting of the first shielding region and the first SiC epitaxial sublayer at the bottom of the first current spreading layer, wherein the bottom surface of the first shielding region contacts the drift region; a first spacing is provided between two adjacent first shielding regions, and the first current spreading layer is retained between the two adjacent first shielding regions; forming a second SiC epitaxial sublayer doped with a second conductivity type on a surface of the first SiC epitaxial sublayer, wherein the first SiC epitaxial sublayer and the second SiC epitaxial sublayer constitute a first SiC epitaxial layer; Performing second conductive type ion implantation to form a second shielding region in the second SiC epitaxial sublayer on top of each first shielding region; the bottom surface of the second shielding region contacts the first shielding region; a second spacing is provided between two adjacent second shielding regions, and the second spacing is greater than the first spacing; Performing second conductivity type heavily doped ion implantation to form a first lead-out region in a top region of each of the first shielding regions; Performing second conductive type ion implantation to form a well region in the top region of the second SiC epitaxial sublayer between the second shielding regions; forming a second current spreading layer by the second SiC epitaxial sublayer at the bottom of the well region; Performing first conductivity type heavily doped ion implantation to form a source region in a top region of the well region; Performing patterned etching to form at least two first trenches, wherein the first SiC epitaxial layer located between two adjacent first trenches forms a fin body; the length direction of the fin body is a first direction, and the width direction of the fin body is a second direction; the first shielding region is located at the bottom of the fin body, and in the second direction, the first shielding region also extends to the bottom of the first trenches on both sides of the fin body and contacts the bottom surface of the first trench; two adjacent first shielding regions are arranged along the first direction; forming a gate dielectric layer on the inner surface of the first trench; filling a gate conductive material layer in the first trench; A front metal layer is formed and patterned to form a source electrode, wherein both the source region and the first lead-out region are connected to the source electrode.

11. The method for manufacturing a SiC FinFET device according to claim 10, wherein: The first SiC epitaxial layer adopts 4H crystal type.

12. The method for manufacturing a SiC FinFET device according to claim 11, wherein: The side surface of the first trench is a (1-100) crystal plane.

13. The method for manufacturing a SiC FinFET device according to claim 12, wherein: An angle between a side surface of the first trench and a normal to a top surface of the first SiC epitaxial layer is 3.5°.

14. The method for manufacturing a SiC FinFET device according to claim 10, wherein: SiC FinFET devices are MOSFETs; Before forming the first SiC epitaxial sub-layer, the method further includes: Epitaxially growing a zeroth SiC epitaxial layer heavily doped with the first conductivity type on the top surface of the SiC substrate heavily doped with the first conductivity type, and forming a buffer layer with the zeroth SiC epitaxial layer; The doping concentration of the buffer layer is greater than the doping concentration of the drift region; The doping concentration of the first current spreading layer is greater than the doping concentration of the drift region; The doping concentration of the second current spreading layer is greater than the doping concentration of the drift region; The drain region is composed of the SiC substrate; After the front process is completed, it also includes: A back metal layer is formed on the back side of the drain region and the back metal layer constitutes a drain electrode.

15. The method for manufacturing a SiC FinFET device according to any one of claims 10 to 14, wherein: The SiC FinFET device is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type; or, the SiC FinFET device is a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.

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